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From: Michael Ellerman <mpe@ellerman.id.au>
To: Kim Phillips <kim.phillips@amd.com>, maddy <maddy@linux.ibm.com>,
	Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Cc: Stephane Eranian <eranian@google.com>,
	Peter Zijlstra <peterz@infradead.org>,
	linuxppc-dev@lists.ozlabs.org,
	LKML <linux-kernel@vger.kernel.org>,
	Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Andi Kleen <ak@linux.intel.com>, "Liang\,
	Kan" <kan.liang@linux.intel.com>,
	Alexey Budankov <alexey.budankov@linux.intel.com>,
	yao.jin@linux.intel.com, Robert Richter <robert.richter@amd.com>
Subject: Re: [RFC 00/11] perf: Enhancing perf to export processor hazard information
Date: Thu, 19 Mar 2020 22:22:03 +1100	[thread overview]
Message-ID: <87o8ssd1yc.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <8803550e-5d6d-2eda-39f5-e4594052188c@amd.com>

Kim Phillips <kim.phillips@amd.com> writes:
> On 3/17/20 1:50 AM, maddy wrote:
>> On 3/13/20 4:08 AM, Kim Phillips wrote:
>>> On 3/11/20 11:00 AM, Ravi Bangoria wrote:
>>>
>>>> information on each sample using PMI at periodic intervals. Hence proposing
>>>> PERF_SAMPLE_PIPELINE_HAZ.
>>>
>>> And that's fine for any extra bits that POWER9 has to convey
>>> to its users beyond things already represented by other sample
>>> types like PERF_SAMPLE_DATA_SRC, but the capturing of both POWER9
>>> and other vendor e.g., AMD IBS data can be made vendor-independent
>>> at record time by using SAMPLE_AUX, or SAMPLE_RAW even, which is
>>> what IBS currently uses.
>> 
>> My bad. Not sure what you mean by this. We are trying to abstract
>> as much vendor specific data as possible with this (like perf-mem).
>
> Perhaps if I say it this way: instead of doing all the 
> isa207_get_phazard_data() work past the mfspr(SPRN_SIER)
> in patch 4/11, rather/instead just put the raw sier value in a 
> PERF_SAMPLE_RAW or _AUX event, and call perf_event_update_userpage.
> Specific SIER capabilities can be written as part of the perf.data
> header.  Then synthesize the true pipe events from the raw SIER
> values later, and in userspace.

In the past the perf maintainers have wanted the perf API to abstract
over the specific CPU details, rather than just pushing raw register
values out to userspace.

But maybe that's no longer the case and we should just use
PERF_SAMPLE_AUX?

cheers

WARNING: multiple messages have this Message-ID (diff)
From: Michael Ellerman <mpe@ellerman.id.au>
To: Kim Phillips <kim.phillips@amd.com>, maddy <maddy@linux.ibm.com>,
	Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Andi Kleen <ak@linux.intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Jiri Olsa <jolsa@redhat.com>,
	Alexey Budankov <alexey.budankov@linux.intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	Stephane Eranian <eranian@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	yao.jin@linux.intel.com, Ingo Molnar <mingo@redhat.com>,
	Paul Mackerras <paulus@samba.org>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Robert Richter <robert.richter@amd.com>,
	Namhyung Kim <namhyung@kernel.org>,
	linuxppc-dev@lists.ozlabs.org, "Liang,
	Kan" <kan.liang@linux.intel.com>
Subject: Re: [RFC 00/11] perf: Enhancing perf to export processor hazard information
Date: Thu, 19 Mar 2020 22:22:03 +1100	[thread overview]
Message-ID: <87o8ssd1yc.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <8803550e-5d6d-2eda-39f5-e4594052188c@amd.com>

Kim Phillips <kim.phillips@amd.com> writes:
> On 3/17/20 1:50 AM, maddy wrote:
>> On 3/13/20 4:08 AM, Kim Phillips wrote:
>>> On 3/11/20 11:00 AM, Ravi Bangoria wrote:
>>>
>>>> information on each sample using PMI at periodic intervals. Hence proposing
>>>> PERF_SAMPLE_PIPELINE_HAZ.
>>>
>>> And that's fine for any extra bits that POWER9 has to convey
>>> to its users beyond things already represented by other sample
>>> types like PERF_SAMPLE_DATA_SRC, but the capturing of both POWER9
>>> and other vendor e.g., AMD IBS data can be made vendor-independent
>>> at record time by using SAMPLE_AUX, or SAMPLE_RAW even, which is
>>> what IBS currently uses.
>> 
>> My bad. Not sure what you mean by this. We are trying to abstract
>> as much vendor specific data as possible with this (like perf-mem).
>
> Perhaps if I say it this way: instead of doing all the 
> isa207_get_phazard_data() work past the mfspr(SPRN_SIER)
> in patch 4/11, rather/instead just put the raw sier value in a 
> PERF_SAMPLE_RAW or _AUX event, and call perf_event_update_userpage.
> Specific SIER capabilities can be written as part of the perf.data
> header.  Then synthesize the true pipe events from the raw SIER
> values later, and in userspace.

In the past the perf maintainers have wanted the perf API to abstract
over the specific CPU details, rather than just pushing raw register
values out to userspace.

But maybe that's no longer the case and we should just use
PERF_SAMPLE_AUX?

cheers

  reply	other threads:[~2020-03-19 11:22 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-02  5:23 [RFC 00/11] perf: Enhancing perf to export processor hazard information Ravi Bangoria
2020-03-02  5:23 ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 01/11] powerpc/perf: Simplify ISA207_SIER macros Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 02/11] perf/core: Data structure to present hazard data Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  9:55   ` Peter Zijlstra
2020-03-02  9:55     ` Peter Zijlstra
2020-03-02 14:23     ` maddy
2020-03-02 14:23       ` maddy
2020-03-02 14:48   ` Mark Rutland
2020-03-02 14:48     ` Mark Rutland
2020-03-03 14:32     ` Ravi Bangoria
2020-03-03 14:32       ` Ravi Bangoria
2020-03-02 14:54   ` Mark Rutland
2020-03-02 14:54     ` Mark Rutland
2020-03-03 14:31     ` Ravi Bangoria
2020-03-03 14:31       ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 03/11] powerpc/perf: Arch specific definitions for pipeline Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 04/11] powerpc/perf: Arch support to expose Hazard data Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 05/11] perf tools: Enable record and script to record and show hazard data Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 06/11] perf hists: Make a room for hazard info in struct hist_entry Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 07/11] perf hazard: Functions to convert generic hazard data to arch specific string Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 08/11] perf report: Enable hazard mode Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 09/11] perf annotate: Introduce type for annotation_line Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 10/11] perf annotate: Preparation for hazard Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02  5:23 ` [RFC 11/11] perf annotate: Show hazard data in tui mode Ravi Bangoria
2020-03-02  5:23   ` Ravi Bangoria
2020-03-02 10:13 ` [RFC 00/11] perf: Enhancing perf to export processor hazard information Peter Zijlstra
2020-03-02 10:13   ` Peter Zijlstra
2020-03-02 20:21   ` Stephane Eranian
2020-03-02 20:21     ` Stephane Eranian
2020-03-02 22:25     ` Kim Phillips
2020-03-02 22:25       ` Kim Phillips
2020-03-05  4:46       ` Ravi Bangoria
2020-03-05  4:46         ` Ravi Bangoria
2020-03-05 22:06         ` Kim Phillips
2020-03-05 22:06           ` Kim Phillips
2020-03-11 16:00           ` Ravi Bangoria
2020-03-12 22:38             ` Kim Phillips
2020-03-12 22:38               ` Kim Phillips
2020-03-17  6:50               ` maddy
2020-03-17  6:50                 ` maddy
2020-03-18 17:35                 ` Kim Phillips
2020-03-18 17:35                   ` Kim Phillips
2020-03-19 11:22                   ` Michael Ellerman [this message]
2020-03-19 11:22                     ` Michael Ellerman
2020-03-26 10:19                   ` maddy
2020-03-26 10:19                     ` maddy
2020-03-26 19:48                     ` Kim Phillips
2020-03-26 19:48                       ` Kim Phillips
2020-04-20  7:09                       ` Madhavan Srinivasan
2020-04-20  7:09                         ` Madhavan Srinivasan
2020-04-27  7:18                         ` Madhavan Srinivasan
2020-04-27  7:18                           ` Madhavan Srinivasan
2020-03-05  4:28     ` maddy
2020-03-05  4:28       ` maddy
2020-03-03  1:33   ` Andi Kleen
2020-03-03  1:33     ` Andi Kleen
2020-03-05  5:06     ` Ravi Bangoria
2020-03-05  5:06       ` Ravi Bangoria
2020-03-02 21:08 ` Paul Clarke
2020-03-02 21:08   ` Paul Clarke
2020-03-05  5:06   ` Ravi Bangoria
2020-03-05  5:06     ` Ravi Bangoria

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