From: maddy <maddy@linux.ibm.com> To: Stephane Eranian <eranian@google.com>, Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@linux.ibm.com>, linuxppc-dev@lists.ozlabs.org, LKML <linux-kernel@vger.kernel.org>, Michael Ellerman <mpe@ellerman.id.au>, Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>, Adrian Hunter <adrian.hunter@intel.com>, Andi Kleen <ak@linux.intel.com>, "Liang, Kan" <kan.liang@linux.intel.com>, Alexey Budankov <alexey.budankov@linux.intel.com>, yao.jin@linux.intel.com, Robert Richter <robert.richter@amd.com>, "Phillips, Kim" <kim.phillips@amd.com> Subject: Re: [RFC 00/11] perf: Enhancing perf to export processor hazard information Date: Thu, 5 Mar 2020 09:58:57 +0530 [thread overview] Message-ID: <feb5e5b1-b1d4-1db4-cd25-c9b1829725f9@linux.ibm.com> (raw) In-Reply-To: <CABPqkBSzwpR6p7UZs7g1vWGCJRLsh565mRMGc6m0Enn1SnkC4w@mail.gmail.com> On 3/3/20 1:51 AM, Stephane Eranian wrote: > On Mon, Mar 2, 2020 at 2:13 AM Peter Zijlstra <peterz@infradead.org> wrote: >> On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote: >>> Modern processors export such hazard data in Performance >>> Monitoring Unit (PMU) registers. Ex, 'Sampled Instruction Event >>> Register' on IBM PowerPC[1][2] and 'Instruction-Based Sampling' on >>> AMD[3] provides similar information. >>> >>> Implementation detail: >>> >>> A new sample_type called PERF_SAMPLE_PIPELINE_HAZ is introduced. >>> If it's set, kernel converts arch specific hazard information >>> into generic format: >>> >>> struct perf_pipeline_haz_data { >>> /* Instruction/Opcode type: Load, Store, Branch .... */ >>> __u8 itype; >>> /* Instruction Cache source */ >>> __u8 icache; >>> /* Instruction suffered hazard in pipeline stage */ >>> __u8 hazard_stage; >>> /* Hazard reason */ >>> __u8 hazard_reason; >>> /* Instruction suffered stall in pipeline stage */ >>> __u8 stall_stage; >>> /* Stall reason */ >>> __u8 stall_reason; >>> __u16 pad; >>> }; >> Kim, does this format indeed work for AMD IBS? > > Personally, I don't like the term hazard. This is too IBM Power > specific. We need to find a better term, maybe stall or penalty. Yes, names can be reworked and thinking more on it, how about these as "pipeline" data instead of "hazard" data. > Also worth considering is the support of ARM SPE (Statistical > Profiling Extension) which is their version of IBS. > Whatever gets added need to cover all three with no limitations. Thanks for pointing this out. We looked at the ARM SPE spec and it does provides information like issue latency, translation latency so on. And AMD IBS provides data like fetch latency, tag to retire latency, completion to retire latency and so on when using Fetch sampling. So yes, will rework the struct definition to include data from ARM SPE and AMD IBS also. Will post out a newer version soon. Thanks for the comments Maddy
WARNING: multiple messages have this Message-ID (diff)
From: maddy <maddy@linux.ibm.com> To: Stephane Eranian <eranian@google.com>, Peter Zijlstra <peterz@infradead.org> Cc: Mark Rutland <mark.rutland@arm.com>, Ravi Bangoria <ravi.bangoria@linux.ibm.com>, Andi Kleen <ak@linux.intel.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@redhat.com>, LKML <linux-kernel@vger.kernel.org>, Arnaldo Carvalho de Melo <acme@kernel.org>, Adrian Hunter <adrian.hunter@intel.com>, Robert Richter <robert.richter@amd.com>, yao.jin@linux.intel.com, Ingo Molnar <mingo@redhat.com>, Paul Mackerras <paulus@samba.org>, Namhyung Kim <namhyung@kernel.org>, "Phillips, Kim" <kim.phillips@amd.com>, linuxppc-dev@lists.ozlabs.org, Alexey Budankov <alexey.budankov@linux.intel.com>, "Liang, Kan" <kan.liang@linux.intel.com> Subject: Re: [RFC 00/11] perf: Enhancing perf to export processor hazard information Date: Thu, 5 Mar 2020 09:58:57 +0530 [thread overview] Message-ID: <feb5e5b1-b1d4-1db4-cd25-c9b1829725f9@linux.ibm.com> (raw) In-Reply-To: <CABPqkBSzwpR6p7UZs7g1vWGCJRLsh565mRMGc6m0Enn1SnkC4w@mail.gmail.com> On 3/3/20 1:51 AM, Stephane Eranian wrote: > On Mon, Mar 2, 2020 at 2:13 AM Peter Zijlstra <peterz@infradead.org> wrote: >> On Mon, Mar 02, 2020 at 10:53:44AM +0530, Ravi Bangoria wrote: >>> Modern processors export such hazard data in Performance >>> Monitoring Unit (PMU) registers. Ex, 'Sampled Instruction Event >>> Register' on IBM PowerPC[1][2] and 'Instruction-Based Sampling' on >>> AMD[3] provides similar information. >>> >>> Implementation detail: >>> >>> A new sample_type called PERF_SAMPLE_PIPELINE_HAZ is introduced. >>> If it's set, kernel converts arch specific hazard information >>> into generic format: >>> >>> struct perf_pipeline_haz_data { >>> /* Instruction/Opcode type: Load, Store, Branch .... */ >>> __u8 itype; >>> /* Instruction Cache source */ >>> __u8 icache; >>> /* Instruction suffered hazard in pipeline stage */ >>> __u8 hazard_stage; >>> /* Hazard reason */ >>> __u8 hazard_reason; >>> /* Instruction suffered stall in pipeline stage */ >>> __u8 stall_stage; >>> /* Stall reason */ >>> __u8 stall_reason; >>> __u16 pad; >>> }; >> Kim, does this format indeed work for AMD IBS? > > Personally, I don't like the term hazard. This is too IBM Power > specific. We need to find a better term, maybe stall or penalty. Yes, names can be reworked and thinking more on it, how about these as "pipeline" data instead of "hazard" data. > Also worth considering is the support of ARM SPE (Statistical > Profiling Extension) which is their version of IBS. > Whatever gets added need to cover all three with no limitations. Thanks for pointing this out. We looked at the ARM SPE spec and it does provides information like issue latency, translation latency so on. And AMD IBS provides data like fetch latency, tag to retire latency, completion to retire latency and so on when using Fetch sampling. So yes, will rework the struct definition to include data from ARM SPE and AMD IBS also. Will post out a newer version soon. Thanks for the comments Maddy
next prev parent reply other threads:[~2020-03-05 4:29 UTC|newest] Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-02 5:23 [RFC 00/11] perf: Enhancing perf to export processor hazard information Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 01/11] powerpc/perf: Simplify ISA207_SIER macros Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 02/11] perf/core: Data structure to present hazard data Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 9:55 ` Peter Zijlstra 2020-03-02 9:55 ` Peter Zijlstra 2020-03-02 14:23 ` maddy 2020-03-02 14:23 ` maddy 2020-03-02 14:48 ` Mark Rutland 2020-03-02 14:48 ` Mark Rutland 2020-03-03 14:32 ` Ravi Bangoria 2020-03-03 14:32 ` Ravi Bangoria 2020-03-02 14:54 ` Mark Rutland 2020-03-02 14:54 ` Mark Rutland 2020-03-03 14:31 ` Ravi Bangoria 2020-03-03 14:31 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 03/11] powerpc/perf: Arch specific definitions for pipeline Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 04/11] powerpc/perf: Arch support to expose Hazard data Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 05/11] perf tools: Enable record and script to record and show hazard data Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 06/11] perf hists: Make a room for hazard info in struct hist_entry Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 07/11] perf hazard: Functions to convert generic hazard data to arch specific string Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 08/11] perf report: Enable hazard mode Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 09/11] perf annotate: Introduce type for annotation_line Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 10/11] perf annotate: Preparation for hazard Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 5:23 ` [RFC 11/11] perf annotate: Show hazard data in tui mode Ravi Bangoria 2020-03-02 5:23 ` Ravi Bangoria 2020-03-02 10:13 ` [RFC 00/11] perf: Enhancing perf to export processor hazard information Peter Zijlstra 2020-03-02 10:13 ` Peter Zijlstra 2020-03-02 20:21 ` Stephane Eranian 2020-03-02 20:21 ` Stephane Eranian 2020-03-02 22:25 ` Kim Phillips 2020-03-02 22:25 ` Kim Phillips 2020-03-05 4:46 ` Ravi Bangoria 2020-03-05 4:46 ` Ravi Bangoria 2020-03-05 22:06 ` Kim Phillips 2020-03-05 22:06 ` Kim Phillips 2020-03-11 16:00 ` Ravi Bangoria 2020-03-12 22:38 ` Kim Phillips 2020-03-12 22:38 ` Kim Phillips 2020-03-17 6:50 ` maddy 2020-03-17 6:50 ` maddy 2020-03-18 17:35 ` Kim Phillips 2020-03-18 17:35 ` Kim Phillips 2020-03-19 11:22 ` Michael Ellerman 2020-03-19 11:22 ` Michael Ellerman 2020-03-26 10:19 ` maddy 2020-03-26 10:19 ` maddy 2020-03-26 19:48 ` Kim Phillips 2020-03-26 19:48 ` Kim Phillips 2020-04-20 7:09 ` Madhavan Srinivasan 2020-04-20 7:09 ` Madhavan Srinivasan 2020-04-27 7:18 ` Madhavan Srinivasan 2020-04-27 7:18 ` Madhavan Srinivasan 2020-03-05 4:28 ` maddy [this message] 2020-03-05 4:28 ` maddy 2020-03-03 1:33 ` Andi Kleen 2020-03-03 1:33 ` Andi Kleen 2020-03-05 5:06 ` Ravi Bangoria 2020-03-05 5:06 ` Ravi Bangoria 2020-03-02 21:08 ` Paul Clarke 2020-03-02 21:08 ` Paul Clarke 2020-03-05 5:06 ` Ravi Bangoria 2020-03-05 5:06 ` Ravi Bangoria
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