* [Intel-gfx] [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
Rename picture parameter set (it's a long packet, not a long write) and
compression mode (it's not a DCS command) enumerations according to the
DSI specification. Order the types according to the spec. Use tabs
instead of spaces for indentation. Use all lower case for hex.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
include/video/mipi_display.h | 10 +++++-----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index bd2498bbd74a..f237d80828c3 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_V_SYNC_END:
case MIPI_DSI_H_SYNC_START:
case MIPI_DSI_H_SYNC_END:
+ case MIPI_DSI_COMPRESSION_MODE:
case MIPI_DSI_END_OF_TRANSMISSION:
case MIPI_DSI_COLOR_MODE_OFF:
case MIPI_DSI_COLOR_MODE_ON:
@@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
- case MIPI_DSI_DCS_COMPRESSION_MODE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
bool mipi_dsi_packet_format_is_long(u8 type)
{
switch (type) {
- case MIPI_DSI_PPS_LONG_WRITE:
case MIPI_DSI_NULL_PACKET:
case MIPI_DSI_BLANKING_PACKET:
case MIPI_DSI_GENERIC_LONG_WRITE:
case MIPI_DSI_DCS_LONG_WRITE:
+ case MIPI_DSI_PICTURE_PARAMETER_SET:
case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index cba57a678daf..79fd71cf4934 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -17,6 +17,9 @@ enum {
MIPI_DSI_H_SYNC_START = 0x21,
MIPI_DSI_H_SYNC_END = 0x31,
+ MIPI_DSI_COMPRESSION_MODE = 0x07,
+ MIPI_DSI_END_OF_TRANSMISSION = 0x08,
+
MIPI_DSI_COLOR_MODE_OFF = 0x02,
MIPI_DSI_COLOR_MODE_ON = 0x12,
MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
@@ -35,18 +38,15 @@ enum {
MIPI_DSI_DCS_READ = 0x06,
- MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
- MIPI_DSI_PPS_LONG_WRITE = 0x0A,
-
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
- MIPI_DSI_END_OF_TRANSMISSION = 0x08,
-
MIPI_DSI_NULL_PACKET = 0x09,
MIPI_DSI_BLANKING_PACKET = 0x19,
MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
MIPI_DSI_DCS_LONG_WRITE = 0x39,
+ MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
+
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, Vandita Kulkarni, intel-gfx
Rename picture parameter set (it's a long packet, not a long write) and
compression mode (it's not a DCS command) enumerations according to the
DSI specification. Order the types according to the spec. Use tabs
instead of spaces for indentation. Use all lower case for hex.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
include/video/mipi_display.h | 10 +++++-----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index bd2498bbd74a..f237d80828c3 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_V_SYNC_END:
case MIPI_DSI_H_SYNC_START:
case MIPI_DSI_H_SYNC_END:
+ case MIPI_DSI_COMPRESSION_MODE:
case MIPI_DSI_END_OF_TRANSMISSION:
case MIPI_DSI_COLOR_MODE_OFF:
case MIPI_DSI_COLOR_MODE_ON:
@@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
- case MIPI_DSI_DCS_COMPRESSION_MODE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
bool mipi_dsi_packet_format_is_long(u8 type)
{
switch (type) {
- case MIPI_DSI_PPS_LONG_WRITE:
case MIPI_DSI_NULL_PACKET:
case MIPI_DSI_BLANKING_PACKET:
case MIPI_DSI_GENERIC_LONG_WRITE:
case MIPI_DSI_DCS_LONG_WRITE:
+ case MIPI_DSI_PICTURE_PARAMETER_SET:
case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index cba57a678daf..79fd71cf4934 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -17,6 +17,9 @@ enum {
MIPI_DSI_H_SYNC_START = 0x21,
MIPI_DSI_H_SYNC_END = 0x31,
+ MIPI_DSI_COMPRESSION_MODE = 0x07,
+ MIPI_DSI_END_OF_TRANSMISSION = 0x08,
+
MIPI_DSI_COLOR_MODE_OFF = 0x02,
MIPI_DSI_COLOR_MODE_ON = 0x12,
MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
@@ -35,18 +38,15 @@ enum {
MIPI_DSI_DCS_READ = 0x06,
- MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
- MIPI_DSI_PPS_LONG_WRITE = 0x0A,
-
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
- MIPI_DSI_END_OF_TRANSMISSION = 0x08,
-
MIPI_DSI_NULL_PACKET = 0x09,
MIPI_DSI_BLANKING_PACKET = 0x19,
MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
MIPI_DSI_DCS_LONG_WRITE = 0x39,
+ MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
+
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
--
2.20.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH v2 2/5] drm/dsi: add missing DSI data types
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, Vandita Kulkarni, intel-gfx
Add execute queue and compressed pixel stream packet data types for
completeness.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
include/video/mipi_display.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index f237d80828c3..3f33f02571fd 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
+ case MIPI_DSI_EXECUTE_QUEUE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
case MIPI_DSI_GENERIC_LONG_WRITE:
case MIPI_DSI_DCS_LONG_WRITE:
case MIPI_DSI_PICTURE_PARAMETER_SET:
+ case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 79fd71cf4934..6b6390dfa203 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -37,6 +37,7 @@ enum {
MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
MIPI_DSI_DCS_READ = 0x06,
+ MIPI_DSI_EXECUTE_QUEUE = 0x16,
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
@@ -46,6 +47,7 @@ enum {
MIPI_DSI_DCS_LONG_WRITE = 0x39,
MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
+ MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
--
2.20.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 45+ messages in thread* [Intel-gfx] [PATCH v2 2/5] drm/dsi: add missing DSI data types
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
Add execute queue and compressed pixel stream packet data types for
completeness.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
include/video/mipi_display.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index f237d80828c3..3f33f02571fd 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
+ case MIPI_DSI_EXECUTE_QUEUE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
case MIPI_DSI_GENERIC_LONG_WRITE:
case MIPI_DSI_DCS_LONG_WRITE:
case MIPI_DSI_PICTURE_PARAMETER_SET:
+ case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 79fd71cf4934..6b6390dfa203 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -37,6 +37,7 @@ enum {
MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
MIPI_DSI_DCS_READ = 0x06,
+ MIPI_DSI_EXECUTE_QUEUE = 0x16,
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
@@ -46,6 +47,7 @@ enum {
MIPI_DSI_DCS_LONG_WRITE = 0x39,
MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
+ MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 45+ messages in thread* RE: [PATCH v2 2/5] drm/dsi: add missing DSI data types
@ 2019-10-30 8:28 ` Kulkarni, Vandita
0 siblings, 0 replies; 45+ messages in thread
From: Kulkarni, Vandita @ 2019-10-30 8:28 UTC (permalink / raw)
To: dri-devel; +Cc: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Monday, October 28, 2019 8:31 PM
> To: dri-devel@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH v2 2/5] drm/dsi: add missing DSI data types
>
> Add execute queue and compressed pixel stream packet data types for
> completeness.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
> include/video/mipi_display.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c
> b/drivers/gpu/drm/drm_mipi_dsi.c index f237d80828c3..3f33f02571fd
> 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> + case MIPI_DSI_EXECUTE_QUEUE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> case MIPI_DSI_PICTURE_PARAMETER_SET:
> + case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 79fd71cf4934..6b6390dfa203 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -37,6 +37,7 @@ enum {
> MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
>
> MIPI_DSI_DCS_READ = 0x06,
> + MIPI_DSI_EXECUTE_QUEUE = 0x16,
>
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE =
> 0x37,
>
> @@ -46,6 +47,7 @@ enum {
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
>
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
> --
> 2.20.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 2/5] drm/dsi: add missing DSI data types
@ 2019-10-30 8:28 ` Kulkarni, Vandita
0 siblings, 0 replies; 45+ messages in thread
From: Kulkarni, Vandita @ 2019-10-30 8:28 UTC (permalink / raw)
To: Nikula, Jani, dri-devel; +Cc: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Monday, October 28, 2019 8:31 PM
> To: dri-devel@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH v2 2/5] drm/dsi: add missing DSI data types
>
> Add execute queue and compressed pixel stream packet data types for
> completeness.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
> include/video/mipi_display.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c
> b/drivers/gpu/drm/drm_mipi_dsi.c index f237d80828c3..3f33f02571fd
> 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> + case MIPI_DSI_EXECUTE_QUEUE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> case MIPI_DSI_PICTURE_PARAMETER_SET:
> + case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 79fd71cf4934..6b6390dfa203 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -37,6 +37,7 @@ enum {
> MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
>
> MIPI_DSI_DCS_READ = 0x06,
> + MIPI_DSI_EXECUTE_QUEUE = 0x16,
>
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE =
> 0x37,
>
> @@ -46,6 +47,7 @@ enum {
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
>
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* RE: [PATCH v2 2/5] drm/dsi: add missing DSI data types
@ 2019-10-30 8:28 ` Kulkarni, Vandita
0 siblings, 0 replies; 45+ messages in thread
From: Kulkarni, Vandita @ 2019-10-30 8:28 UTC (permalink / raw)
To: Nikula, Jani, dri-devel; +Cc: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Monday, October 28, 2019 8:31 PM
> To: dri-devel@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH v2 2/5] drm/dsi: add missing DSI data types
>
> Add execute queue and compressed pixel stream packet data types for
> completeness.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
> include/video/mipi_display.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c
> b/drivers/gpu/drm/drm_mipi_dsi.c index f237d80828c3..3f33f02571fd
> 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> + case MIPI_DSI_EXECUTE_QUEUE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> case MIPI_DSI_PICTURE_PARAMETER_SET:
> + case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 79fd71cf4934..6b6390dfa203 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -37,6 +37,7 @@ enum {
> MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
>
> MIPI_DSI_DCS_READ = 0x06,
> + MIPI_DSI_EXECUTE_QUEUE = 0x16,
>
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE =
> 0x37,
>
> @@ -46,6 +47,7 @@ enum {
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
>
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
> --
> 2.20.1
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v2 2/5] drm/dsi: add missing DSI data types
@ 2019-11-04 15:24 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-04 15:24 UTC (permalink / raw)
To: Jani Nikula; +Cc: Vandita Kulkarni, intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 2303 bytes --]
On Mon, Oct 28, 2019 at 05:00:44PM +0200, Jani Nikula wrote:
> Add execute queue and compressed pixel stream packet data types for
> completeness.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
> include/video/mipi_display.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index f237d80828c3..3f33f02571fd 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> + case MIPI_DSI_EXECUTE_QUEUE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> case MIPI_DSI_PICTURE_PARAMETER_SET:
> + case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 79fd71cf4934..6b6390dfa203 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -37,6 +37,7 @@ enum {
> MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
>
> MIPI_DSI_DCS_READ = 0x06,
> + MIPI_DSI_EXECUTE_QUEUE = 0x16,
>
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> @@ -46,6 +47,7 @@ enum {
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
>
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
Actually, it looks like the ordering is by lowest-significant nibble
first, then by highest-significant nibble, so maybe there's some logic
to this after all.
Hmm... that's mostly true, except for 0x07 and 0x08... anyway, the new
enumeration values and names match the specification, so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 2/5] drm/dsi: add missing DSI data types
@ 2019-11-04 15:24 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-04 15:24 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 2303 bytes --]
On Mon, Oct 28, 2019 at 05:00:44PM +0200, Jani Nikula wrote:
> Add execute queue and compressed pixel stream packet data types for
> completeness.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
> include/video/mipi_display.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index f237d80828c3..3f33f02571fd 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> + case MIPI_DSI_EXECUTE_QUEUE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> case MIPI_DSI_PICTURE_PARAMETER_SET:
> + case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 79fd71cf4934..6b6390dfa203 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -37,6 +37,7 @@ enum {
> MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
>
> MIPI_DSI_DCS_READ = 0x06,
> + MIPI_DSI_EXECUTE_QUEUE = 0x16,
>
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> @@ -46,6 +47,7 @@ enum {
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b,
>
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
Actually, it looks like the ordering is by lowest-significant nibble
first, then by highest-significant nibble, so maybe there's some logic
to this after all.
Hmm... that's mostly true, except for 0x07 and 0x08... anyway, the new
enumeration values and names match the specification, so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
Update from the DCS specification.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/video/mipi_display.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 6b6390dfa203..928f8c4b6658 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -79,7 +79,9 @@ enum {
enum {
MIPI_DCS_NOP = 0x00,
MIPI_DCS_SOFT_RESET = 0x01,
+ MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
MIPI_DCS_GET_DISPLAY_ID = 0x04,
+ MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
MIPI_DCS_GET_RED_CHANNEL = 0x06,
MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
@@ -94,6 +96,8 @@ enum {
MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
+ MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
+ MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
MIPI_DCS_EXIT_INVERT_MODE = 0x20,
MIPI_DCS_ENTER_INVERT_MODE = 0x21,
MIPI_DCS_SET_GAMMA_CURVE = 0x26,
@@ -105,6 +109,7 @@ enum {
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
MIPI_DCS_SET_SCROLL_AREA = 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
MIPI_DCS_SET_TEAR_ON = 0x35,
@@ -114,7 +119,10 @@ enum {
MIPI_DCS_ENTER_IDLE_MODE = 0x39,
MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
+ MIPI_DCS_SET_3D_CONTROL = 0x3D,
MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
+ MIPI_DCS_GET_3D_CONTROL = 0x3F,
+ MIPI_DCS_SET_VSYNC_TIMING = 0x40,
MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
MIPI_DCS_GET_SCANLINE = 0x45,
MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
@@ -126,7 +134,9 @@ enum {
MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
MIPI_DCS_READ_DDB_START = 0xA1,
+ MIPI_DCS_READ_PPS_START = 0xA2,
MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
+ MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
};
/* MIPI DCS pixel formats */
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 45+ messages in thread* [Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
Update from the DCS specification.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/video/mipi_display.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 6b6390dfa203..928f8c4b6658 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -79,7 +79,9 @@ enum {
enum {
MIPI_DCS_NOP = 0x00,
MIPI_DCS_SOFT_RESET = 0x01,
+ MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
MIPI_DCS_GET_DISPLAY_ID = 0x04,
+ MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
MIPI_DCS_GET_RED_CHANNEL = 0x06,
MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
@@ -94,6 +96,8 @@ enum {
MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
+ MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
+ MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
MIPI_DCS_EXIT_INVERT_MODE = 0x20,
MIPI_DCS_ENTER_INVERT_MODE = 0x21,
MIPI_DCS_SET_GAMMA_CURVE = 0x26,
@@ -105,6 +109,7 @@ enum {
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
MIPI_DCS_SET_SCROLL_AREA = 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
MIPI_DCS_SET_TEAR_ON = 0x35,
@@ -114,7 +119,10 @@ enum {
MIPI_DCS_ENTER_IDLE_MODE = 0x39,
MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
+ MIPI_DCS_SET_3D_CONTROL = 0x3D,
MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
+ MIPI_DCS_GET_3D_CONTROL = 0x3F,
+ MIPI_DCS_SET_VSYNC_TIMING = 0x40,
MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
MIPI_DCS_GET_SCANLINE = 0x45,
MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
@@ -126,7 +134,9 @@ enum {
MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
MIPI_DCS_READ_DDB_START = 0xA1,
+ MIPI_DCS_READ_PPS_START = 0xA2,
MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
+ MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
};
/* MIPI DCS pixel formats */
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, Vandita Kulkarni, intel-gfx
Update from the DCS specification.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/video/mipi_display.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 6b6390dfa203..928f8c4b6658 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -79,7 +79,9 @@ enum {
enum {
MIPI_DCS_NOP = 0x00,
MIPI_DCS_SOFT_RESET = 0x01,
+ MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
MIPI_DCS_GET_DISPLAY_ID = 0x04,
+ MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
MIPI_DCS_GET_RED_CHANNEL = 0x06,
MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
@@ -94,6 +96,8 @@ enum {
MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
+ MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
+ MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
MIPI_DCS_EXIT_INVERT_MODE = 0x20,
MIPI_DCS_ENTER_INVERT_MODE = 0x21,
MIPI_DCS_SET_GAMMA_CURVE = 0x26,
@@ -105,6 +109,7 @@ enum {
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
MIPI_DCS_SET_SCROLL_AREA = 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
MIPI_DCS_SET_TEAR_ON = 0x35,
@@ -114,7 +119,10 @@ enum {
MIPI_DCS_ENTER_IDLE_MODE = 0x39,
MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
+ MIPI_DCS_SET_3D_CONTROL = 0x3D,
MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
+ MIPI_DCS_GET_3D_CONTROL = 0x3F,
+ MIPI_DCS_SET_VSYNC_TIMING = 0x40,
MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
MIPI_DCS_GET_SCANLINE = 0x45,
MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
@@ -126,7 +134,9 @@ enum {
MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
MIPI_DCS_READ_DDB_START = 0xA1,
+ MIPI_DCS_READ_PPS_START = 0xA2,
MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
+ MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
};
/* MIPI DCS pixel formats */
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-11-04 15:29 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-04 15:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 2458 bytes --]
On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
> Update from the DCS specification.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/video/mipi_display.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 6b6390dfa203..928f8c4b6658 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -79,7 +79,9 @@ enum {
> enum {
> MIPI_DCS_NOP = 0x00,
> MIPI_DCS_SOFT_RESET = 0x01,
> + MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
> MIPI_DCS_GET_DISPLAY_ID = 0x04,
> + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
> MIPI_DCS_GET_RED_CHANNEL = 0x06,
> MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
> MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
> @@ -94,6 +96,8 @@ enum {
> MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
> MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
> MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
> MIPI_DCS_EXIT_INVERT_MODE = 0x20,
> MIPI_DCS_ENTER_INVERT_MODE = 0x21,
> MIPI_DCS_SET_GAMMA_CURVE = 0x26,
> @@ -105,6 +109,7 @@ enum {
> MIPI_DCS_WRITE_LUT = 0x2D,
> MIPI_DCS_READ_MEMORY_START = 0x2E,
> MIPI_DCS_SET_PARTIAL_AREA = 0x30,
> + MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
> MIPI_DCS_SET_SCROLL_AREA = 0x33,
> MIPI_DCS_SET_TEAR_OFF = 0x34,
> MIPI_DCS_SET_TEAR_ON = 0x35,
> @@ -114,7 +119,10 @@ enum {
> MIPI_DCS_ENTER_IDLE_MODE = 0x39,
> MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
> MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
> + MIPI_DCS_SET_3D_CONTROL = 0x3D,
> MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
> + MIPI_DCS_GET_3D_CONTROL = 0x3F,
> + MIPI_DCS_SET_VSYNC_TIMING = 0x40,
> MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
> MIPI_DCS_GET_SCANLINE = 0x45,
> MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
> @@ -126,7 +134,9 @@ enum {
> MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
> MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
> MIPI_DCS_READ_DDB_START = 0xA1,
> + MIPI_DCS_READ_PPS_START = 0xA2,
> MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
> + MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
> };
>
> /* MIPI DCS pixel formats */
> --
> 2.20.1
I only have a copy of DCS 1.2, which doesn't seem to have these values.
Let me see if I can find a more updated version.
Thierry
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_______________________________________________
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^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-11-04 15:29 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-04 15:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 2458 bytes --]
On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
> Update from the DCS specification.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/video/mipi_display.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 6b6390dfa203..928f8c4b6658 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -79,7 +79,9 @@ enum {
> enum {
> MIPI_DCS_NOP = 0x00,
> MIPI_DCS_SOFT_RESET = 0x01,
> + MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
> MIPI_DCS_GET_DISPLAY_ID = 0x04,
> + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
> MIPI_DCS_GET_RED_CHANNEL = 0x06,
> MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
> MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
> @@ -94,6 +96,8 @@ enum {
> MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
> MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
> MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
> MIPI_DCS_EXIT_INVERT_MODE = 0x20,
> MIPI_DCS_ENTER_INVERT_MODE = 0x21,
> MIPI_DCS_SET_GAMMA_CURVE = 0x26,
> @@ -105,6 +109,7 @@ enum {
> MIPI_DCS_WRITE_LUT = 0x2D,
> MIPI_DCS_READ_MEMORY_START = 0x2E,
> MIPI_DCS_SET_PARTIAL_AREA = 0x30,
> + MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
> MIPI_DCS_SET_SCROLL_AREA = 0x33,
> MIPI_DCS_SET_TEAR_OFF = 0x34,
> MIPI_DCS_SET_TEAR_ON = 0x35,
> @@ -114,7 +119,10 @@ enum {
> MIPI_DCS_ENTER_IDLE_MODE = 0x39,
> MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
> MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
> + MIPI_DCS_SET_3D_CONTROL = 0x3D,
> MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
> + MIPI_DCS_GET_3D_CONTROL = 0x3F,
> + MIPI_DCS_SET_VSYNC_TIMING = 0x40,
> MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
> MIPI_DCS_GET_SCANLINE = 0x45,
> MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
> @@ -126,7 +134,9 @@ enum {
> MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
> MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
> MIPI_DCS_READ_DDB_START = 0xA1,
> + MIPI_DCS_READ_PPS_START = 0xA2,
> MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
> + MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
> };
>
> /* MIPI DCS pixel formats */
> --
> 2.20.1
I only have a copy of DCS 1.2, which doesn't seem to have these values.
Let me see if I can find a more updated version.
Thierry
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-11-04 15:29 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-04 15:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 2458 bytes --]
On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
> Update from the DCS specification.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/video/mipi_display.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 6b6390dfa203..928f8c4b6658 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -79,7 +79,9 @@ enum {
> enum {
> MIPI_DCS_NOP = 0x00,
> MIPI_DCS_SOFT_RESET = 0x01,
> + MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
> MIPI_DCS_GET_DISPLAY_ID = 0x04,
> + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
> MIPI_DCS_GET_RED_CHANNEL = 0x06,
> MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
> MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
> @@ -94,6 +96,8 @@ enum {
> MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
> MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
> MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
> MIPI_DCS_EXIT_INVERT_MODE = 0x20,
> MIPI_DCS_ENTER_INVERT_MODE = 0x21,
> MIPI_DCS_SET_GAMMA_CURVE = 0x26,
> @@ -105,6 +109,7 @@ enum {
> MIPI_DCS_WRITE_LUT = 0x2D,
> MIPI_DCS_READ_MEMORY_START = 0x2E,
> MIPI_DCS_SET_PARTIAL_AREA = 0x30,
> + MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
> MIPI_DCS_SET_SCROLL_AREA = 0x33,
> MIPI_DCS_SET_TEAR_OFF = 0x34,
> MIPI_DCS_SET_TEAR_ON = 0x35,
> @@ -114,7 +119,10 @@ enum {
> MIPI_DCS_ENTER_IDLE_MODE = 0x39,
> MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
> MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
> + MIPI_DCS_SET_3D_CONTROL = 0x3D,
> MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
> + MIPI_DCS_GET_3D_CONTROL = 0x3F,
> + MIPI_DCS_SET_VSYNC_TIMING = 0x40,
> MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
> MIPI_DCS_GET_SCANLINE = 0x45,
> MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
> @@ -126,7 +134,9 @@ enum {
> MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
> MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
> MIPI_DCS_READ_DDB_START = 0xA1,
> + MIPI_DCS_READ_PPS_START = 0xA2,
> MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
> + MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
> };
>
> /* MIPI DCS pixel formats */
> --
> 2.20.1
I only have a copy of DCS 1.2, which doesn't seem to have these values.
Let me see if I can find a more updated version.
Thierry
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-11-05 9:18 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-05 9:18 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 2553 bytes --]
On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
> Update from the DCS specification.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/video/mipi_display.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 6b6390dfa203..928f8c4b6658 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -79,7 +79,9 @@ enum {
> enum {
> MIPI_DCS_NOP = 0x00,
> MIPI_DCS_SOFT_RESET = 0x01,
> + MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
> MIPI_DCS_GET_DISPLAY_ID = 0x04,
> + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
> MIPI_DCS_GET_RED_CHANNEL = 0x06,
> MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
> MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
> @@ -94,6 +96,8 @@ enum {
> MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
> MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
> MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
> MIPI_DCS_EXIT_INVERT_MODE = 0x20,
> MIPI_DCS_ENTER_INVERT_MODE = 0x21,
> MIPI_DCS_SET_GAMMA_CURVE = 0x26,
> @@ -105,6 +109,7 @@ enum {
> MIPI_DCS_WRITE_LUT = 0x2D,
> MIPI_DCS_READ_MEMORY_START = 0x2E,
> MIPI_DCS_SET_PARTIAL_AREA = 0x30,
> + MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
> MIPI_DCS_SET_SCROLL_AREA = 0x33,
> MIPI_DCS_SET_TEAR_OFF = 0x34,
> MIPI_DCS_SET_TEAR_ON = 0x35,
> @@ -114,7 +119,10 @@ enum {
> MIPI_DCS_ENTER_IDLE_MODE = 0x39,
> MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
> MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
> + MIPI_DCS_SET_3D_CONTROL = 0x3D,
> MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
> + MIPI_DCS_GET_3D_CONTROL = 0x3F,
> + MIPI_DCS_SET_VSYNC_TIMING = 0x40,
> MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
> MIPI_DCS_GET_SCANLINE = 0x45,
> MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
> @@ -126,7 +134,9 @@ enum {
> MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
> MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
> MIPI_DCS_READ_DDB_START = 0xA1,
> + MIPI_DCS_READ_PPS_START = 0xA2,
> MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
> + MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
> };
>
> /* MIPI DCS pixel formats */
Okay, found a copy of DCS v1.4 and the above matches the specification,
so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
Does it perhaps make sense to add comments about the version number that
these were introduced with?
Thierry
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[-- Type: application/pgp-signature, Size: 833 bytes --]
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-11-05 9:18 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-05 9:18 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 2553 bytes --]
On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
> Update from the DCS specification.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/video/mipi_display.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index 6b6390dfa203..928f8c4b6658 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -79,7 +79,9 @@ enum {
> enum {
> MIPI_DCS_NOP = 0x00,
> MIPI_DCS_SOFT_RESET = 0x01,
> + MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
> MIPI_DCS_GET_DISPLAY_ID = 0x04,
> + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
> MIPI_DCS_GET_RED_CHANNEL = 0x06,
> MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
> MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
> @@ -94,6 +96,8 @@ enum {
> MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
> MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
> MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
> + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
> MIPI_DCS_EXIT_INVERT_MODE = 0x20,
> MIPI_DCS_ENTER_INVERT_MODE = 0x21,
> MIPI_DCS_SET_GAMMA_CURVE = 0x26,
> @@ -105,6 +109,7 @@ enum {
> MIPI_DCS_WRITE_LUT = 0x2D,
> MIPI_DCS_READ_MEMORY_START = 0x2E,
> MIPI_DCS_SET_PARTIAL_AREA = 0x30,
> + MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
> MIPI_DCS_SET_SCROLL_AREA = 0x33,
> MIPI_DCS_SET_TEAR_OFF = 0x34,
> MIPI_DCS_SET_TEAR_ON = 0x35,
> @@ -114,7 +119,10 @@ enum {
> MIPI_DCS_ENTER_IDLE_MODE = 0x39,
> MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
> MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
> + MIPI_DCS_SET_3D_CONTROL = 0x3D,
> MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
> + MIPI_DCS_GET_3D_CONTROL = 0x3F,
> + MIPI_DCS_SET_VSYNC_TIMING = 0x40,
> MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
> MIPI_DCS_GET_SCANLINE = 0x45,
> MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
> @@ -126,7 +134,9 @@ enum {
> MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
> MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
> MIPI_DCS_READ_DDB_START = 0xA1,
> + MIPI_DCS_READ_PPS_START = 0xA2,
> MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
> + MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
> };
>
> /* MIPI DCS pixel formats */
Okay, found a copy of DCS v1.4 and the above matches the specification,
so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
Does it perhaps make sense to add comments about the version number that
these were introduced with?
Thierry
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-11-05 14:06 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-05 14:06 UTC (permalink / raw)
To: Thierry Reding; +Cc: intel-gfx, dri-devel
On Tue, 05 Nov 2019, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
>> Update from the DCS specification.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> include/video/mipi_display.h | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index 6b6390dfa203..928f8c4b6658 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -79,7 +79,9 @@ enum {
>> enum {
>> MIPI_DCS_NOP = 0x00,
>> MIPI_DCS_SOFT_RESET = 0x01,
>> + MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
>> MIPI_DCS_GET_DISPLAY_ID = 0x04,
>> + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
>> MIPI_DCS_GET_RED_CHANNEL = 0x06,
>> MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
>> MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
>> @@ -94,6 +96,8 @@ enum {
>> MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
>> MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
>> MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
>> + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
>> + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
>> MIPI_DCS_EXIT_INVERT_MODE = 0x20,
>> MIPI_DCS_ENTER_INVERT_MODE = 0x21,
>> MIPI_DCS_SET_GAMMA_CURVE = 0x26,
>> @@ -105,6 +109,7 @@ enum {
>> MIPI_DCS_WRITE_LUT = 0x2D,
>> MIPI_DCS_READ_MEMORY_START = 0x2E,
>> MIPI_DCS_SET_PARTIAL_AREA = 0x30,
>> + MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
>> MIPI_DCS_SET_SCROLL_AREA = 0x33,
>> MIPI_DCS_SET_TEAR_OFF = 0x34,
>> MIPI_DCS_SET_TEAR_ON = 0x35,
>> @@ -114,7 +119,10 @@ enum {
>> MIPI_DCS_ENTER_IDLE_MODE = 0x39,
>> MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
>> MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
>> + MIPI_DCS_SET_3D_CONTROL = 0x3D,
>> MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
>> + MIPI_DCS_GET_3D_CONTROL = 0x3F,
>> + MIPI_DCS_SET_VSYNC_TIMING = 0x40,
>> MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
>> MIPI_DCS_GET_SCANLINE = 0x45,
>> MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
>> @@ -126,7 +134,9 @@ enum {
>> MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
>> MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
>> MIPI_DCS_READ_DDB_START = 0xA1,
>> + MIPI_DCS_READ_PPS_START = 0xA2,
>> MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
>> + MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
>> };
>>
>> /* MIPI DCS pixel formats */
>
> Okay, found a copy of DCS v1.4 and the above matches the specification,
> so:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
>
> Does it perhaps make sense to add comments about the version number that
> these were introduced with?
The trouble is, I don't have the complete chronology of the
specifications, so I can't be sure at which point each one was added.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-11-05 14:06 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-05 14:06 UTC (permalink / raw)
To: Thierry Reding; +Cc: intel-gfx, dri-devel
On Tue, 05 Nov 2019, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
>> Update from the DCS specification.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> include/video/mipi_display.h | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index 6b6390dfa203..928f8c4b6658 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -79,7 +79,9 @@ enum {
>> enum {
>> MIPI_DCS_NOP = 0x00,
>> MIPI_DCS_SOFT_RESET = 0x01,
>> + MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
>> MIPI_DCS_GET_DISPLAY_ID = 0x04,
>> + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
>> MIPI_DCS_GET_RED_CHANNEL = 0x06,
>> MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
>> MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
>> @@ -94,6 +96,8 @@ enum {
>> MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
>> MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
>> MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
>> + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
>> + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
>> MIPI_DCS_EXIT_INVERT_MODE = 0x20,
>> MIPI_DCS_ENTER_INVERT_MODE = 0x21,
>> MIPI_DCS_SET_GAMMA_CURVE = 0x26,
>> @@ -105,6 +109,7 @@ enum {
>> MIPI_DCS_WRITE_LUT = 0x2D,
>> MIPI_DCS_READ_MEMORY_START = 0x2E,
>> MIPI_DCS_SET_PARTIAL_AREA = 0x30,
>> + MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
>> MIPI_DCS_SET_SCROLL_AREA = 0x33,
>> MIPI_DCS_SET_TEAR_OFF = 0x34,
>> MIPI_DCS_SET_TEAR_ON = 0x35,
>> @@ -114,7 +119,10 @@ enum {
>> MIPI_DCS_ENTER_IDLE_MODE = 0x39,
>> MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
>> MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
>> + MIPI_DCS_SET_3D_CONTROL = 0x3D,
>> MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
>> + MIPI_DCS_GET_3D_CONTROL = 0x3F,
>> + MIPI_DCS_SET_VSYNC_TIMING = 0x40,
>> MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
>> MIPI_DCS_GET_SCANLINE = 0x45,
>> MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
>> @@ -126,7 +134,9 @@ enum {
>> MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
>> MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
>> MIPI_DCS_READ_DDB_START = 0xA1,
>> + MIPI_DCS_READ_PPS_START = 0xA2,
>> MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
>> + MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
>> };
>>
>> /* MIPI DCS pixel formats */
>
> Okay, found a copy of DCS v1.4 and the above matches the specification,
> so:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
>
> Does it perhaps make sense to add comments about the version number that
> these were introduced with?
The trouble is, I don't have the complete chronology of the
specifications, so I can't be sure at which point each one was added.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
@ 2019-11-05 14:06 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-05 14:06 UTC (permalink / raw)
To: Thierry Reding; +Cc: intel-gfx, dri-devel
On Tue, 05 Nov 2019, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Mon, Oct 28, 2019 at 05:00:45PM +0200, Jani Nikula wrote:
>> Update from the DCS specification.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> include/video/mipi_display.h | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index 6b6390dfa203..928f8c4b6658 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -79,7 +79,9 @@ enum {
>> enum {
>> MIPI_DCS_NOP = 0x00,
>> MIPI_DCS_SOFT_RESET = 0x01,
>> + MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
>> MIPI_DCS_GET_DISPLAY_ID = 0x04,
>> + MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
>> MIPI_DCS_GET_RED_CHANNEL = 0x06,
>> MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
>> MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
>> @@ -94,6 +96,8 @@ enum {
>> MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
>> MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
>> MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
>> + MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
>> + MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
>> MIPI_DCS_EXIT_INVERT_MODE = 0x20,
>> MIPI_DCS_ENTER_INVERT_MODE = 0x21,
>> MIPI_DCS_SET_GAMMA_CURVE = 0x26,
>> @@ -105,6 +109,7 @@ enum {
>> MIPI_DCS_WRITE_LUT = 0x2D,
>> MIPI_DCS_READ_MEMORY_START = 0x2E,
>> MIPI_DCS_SET_PARTIAL_AREA = 0x30,
>> + MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
>> MIPI_DCS_SET_SCROLL_AREA = 0x33,
>> MIPI_DCS_SET_TEAR_OFF = 0x34,
>> MIPI_DCS_SET_TEAR_ON = 0x35,
>> @@ -114,7 +119,10 @@ enum {
>> MIPI_DCS_ENTER_IDLE_MODE = 0x39,
>> MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
>> MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
>> + MIPI_DCS_SET_3D_CONTROL = 0x3D,
>> MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
>> + MIPI_DCS_GET_3D_CONTROL = 0x3F,
>> + MIPI_DCS_SET_VSYNC_TIMING = 0x40,
>> MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
>> MIPI_DCS_GET_SCANLINE = 0x45,
>> MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
>> @@ -126,7 +134,9 @@ enum {
>> MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */
>> MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */
>> MIPI_DCS_READ_DDB_START = 0xA1,
>> + MIPI_DCS_READ_PPS_START = 0xA2,
>> MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
>> + MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
>> };
>>
>> /* MIPI DCS pixel formats */
>
> Okay, found a copy of DCS v1.4 and the above matches the specification,
> so:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
>
> Does it perhaps make sense to add comments about the version number that
> these were introduced with?
The trouble is, I don't have the complete chronology of the
specifications, so I can't be sure at which point each one was added.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v2 4/5] drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx, David Lechner
The DCS command has been named SET_PARTIAL_ROWS in the DCS spec since
v1.02, for more than a decade. Rename the enumeration to match the spec.
v2: add comment about the rename (David Lechner)
Cc: David Lechner <david@lechnology.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/tiny/st7586.c | 2 +-
include/video/mipi_display.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tiny/st7586.c b/drivers/gpu/drm/tiny/st7586.c
index 3cc21a1b30c8..060cc756194f 100644
--- a/drivers/gpu/drm/tiny/st7586.c
+++ b/drivers/gpu/drm/tiny/st7586.c
@@ -240,7 +240,7 @@ static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe,
mipi_dbi_command(dbi, ST7586_SET_DISP_DUTY, 0x7f);
mipi_dbi_command(dbi, ST7586_SET_PART_DISP, 0xa0);
- mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_AREA, 0x00, 0x00, 0x00, 0x77);
+ mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_ROWS, 0x00, 0x00, 0x00, 0x77);
mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE);
msleep(100);
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 928f8c4b6658..b6d8b874233f 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -108,7 +108,7 @@ enum {
MIPI_DCS_WRITE_MEMORY_START = 0x2C,
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
- MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
MIPI_DCS_SET_SCROLL_AREA = 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 45+ messages in thread* [Intel-gfx] [PATCH v2 4/5] drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx, David Lechner
The DCS command has been named SET_PARTIAL_ROWS in the DCS spec since
v1.02, for more than a decade. Rename the enumeration to match the spec.
v2: add comment about the rename (David Lechner)
Cc: David Lechner <david@lechnology.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/tiny/st7586.c | 2 +-
include/video/mipi_display.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tiny/st7586.c b/drivers/gpu/drm/tiny/st7586.c
index 3cc21a1b30c8..060cc756194f 100644
--- a/drivers/gpu/drm/tiny/st7586.c
+++ b/drivers/gpu/drm/tiny/st7586.c
@@ -240,7 +240,7 @@ static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe,
mipi_dbi_command(dbi, ST7586_SET_DISP_DUTY, 0x7f);
mipi_dbi_command(dbi, ST7586_SET_PART_DISP, 0xa0);
- mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_AREA, 0x00, 0x00, 0x00, 0x77);
+ mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_ROWS, 0x00, 0x00, 0x00, 0x77);
mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE);
msleep(100);
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 928f8c4b6658..b6d8b874233f 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -108,7 +108,7 @@ enum {
MIPI_DCS_WRITE_MEMORY_START = 0x2C,
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
- MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
MIPI_DCS_SET_SCROLL_AREA = 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH v2 4/5] drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, Vandita Kulkarni, intel-gfx, David Lechner
The DCS command has been named SET_PARTIAL_ROWS in the DCS spec since
v1.02, for more than a decade. Rename the enumeration to match the spec.
v2: add comment about the rename (David Lechner)
Cc: David Lechner <david@lechnology.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/tiny/st7586.c | 2 +-
include/video/mipi_display.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tiny/st7586.c b/drivers/gpu/drm/tiny/st7586.c
index 3cc21a1b30c8..060cc756194f 100644
--- a/drivers/gpu/drm/tiny/st7586.c
+++ b/drivers/gpu/drm/tiny/st7586.c
@@ -240,7 +240,7 @@ static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe,
mipi_dbi_command(dbi, ST7586_SET_DISP_DUTY, 0x7f);
mipi_dbi_command(dbi, ST7586_SET_PART_DISP, 0xa0);
- mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_AREA, 0x00, 0x00, 0x00, 0x77);
+ mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_ROWS, 0x00, 0x00, 0x00, 0x77);
mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE);
msleep(100);
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 928f8c4b6658..b6d8b874233f 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -108,7 +108,7 @@ enum {
MIPI_DCS_WRITE_MEMORY_START = 0x2C,
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
- MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31,
MIPI_DCS_SET_SCROLL_AREA = 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
--
2.20.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/5] drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
@ 2019-11-05 9:42 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-05 9:42 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, David Lechner, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 616 bytes --]
On Mon, Oct 28, 2019 at 05:00:46PM +0200, Jani Nikula wrote:
> The DCS command has been named SET_PARTIAL_ROWS in the DCS spec since
> v1.02, for more than a decade. Rename the enumeration to match the spec.
>
> v2: add comment about the rename (David Lechner)
>
> Cc: David Lechner <david@lechnology.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/tiny/st7586.c | 2 +-
> include/video/mipi_display.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/5] drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
@ 2019-11-05 9:42 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-05 9:42 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, David Lechner, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 616 bytes --]
On Mon, Oct 28, 2019 at 05:00:46PM +0200, Jani Nikula wrote:
> The DCS command has been named SET_PARTIAL_ROWS in the DCS spec since
> v1.02, for more than a decade. Rename the enumeration to match the spec.
>
> v2: add comment about the rename (David Lechner)
>
> Cc: David Lechner <david@lechnology.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/tiny/st7586.c | 2 +-
> include/video/mipi_display.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v2 5/5] drm/dsi: add helpers for DSI compression mode and PPS packets
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, Vandita Kulkarni, intel-gfx
Add helper functions for sending the DSI compression mode and picture
parameter set data type packets. For the time being, limit the support
to using VESA DSC 1.1 and the default PPS. This may need updating if the
need arises for proprietary compression or non-default PPS, however keep
it simple for starters.
v2: Add missing EXPORT_SYMBOL
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_mipi_dsi.c | 51 ++++++++++++++++++++++++++++++++++
include/drm/drm_mipi_dsi.h | 4 +++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index 3f33f02571fd..55531895dde6 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -33,6 +33,7 @@
#include <linux/pm_runtime.h>
#include <linux/slab.h>
+#include <drm/drm_dsc.h>
#include <video/mipi_display.h>
/**
@@ -548,6 +549,56 @@ int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
}
EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size);
+/**
+ * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral
+ * @dsi: DSI peripheral device
+ * @enable: Whether to enable or disable the DSC
+ *
+ * Enable or disable Display Stream Compression on the peripheral using the
+ * default Picture Parameter Set and VESA DSC 1.1 algorithm.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)
+{
+ /* Note: Needs updating for non-default PPS or algorithm */
+ u8 tx[2] = { enable << 0, 0 };
+ struct mipi_dsi_msg msg = {
+ .channel = dsi->channel,
+ .type = MIPI_DSI_COMPRESSION_MODE,
+ .tx_len = sizeof(tx),
+ .tx_buf = tx,
+ };
+ int ret = mipi_dsi_device_transfer(dsi, &msg);
+
+ return (ret < 0) ? ret : 0;
+}
+EXPORT_SYMBOL(mipi_dsi_compression_mode);
+
+/**
+ * mipi_dsi_picture_parameter_set() - transmit the DSC PPS to the peripheral
+ * @dsi: DSI peripheral device
+ * @pps: VESA DSC 1.1 Picture Parameter Set
+ *
+ * Transmit the VESA DSC 1.1 Picture Parameter Set to the peripheral.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
+ const struct drm_dsc_picture_parameter_set *pps)
+{
+ struct mipi_dsi_msg msg = {
+ .channel = dsi->channel,
+ .type = MIPI_DSI_PICTURE_PARAMETER_SET,
+ .tx_len = sizeof(*pps),
+ .tx_buf = pps,
+ };
+ int ret = mipi_dsi_device_transfer(dsi, &msg);
+
+ return (ret < 0) ? ret : 0;
+}
+EXPORT_SYMBOL(mipi_dsi_picture_parameter_set);
+
/**
* mipi_dsi_generic_write() - transmit data using a generic write packet
* @dsi: DSI peripheral device
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 13cf2ae59f6c..360e6377e84b 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -13,6 +13,7 @@
struct mipi_dsi_host;
struct mipi_dsi_device;
+struct drm_dsc_picture_parameter_set;
/* request ACK from peripheral */
#define MIPI_DSI_MSG_REQ_ACK BIT(0)
@@ -228,6 +229,9 @@ int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi);
int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi);
int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
u16 value);
+ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable);
+ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
+ const struct drm_dsc_picture_parameter_set *pps);
ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
size_t size);
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 45+ messages in thread* [Intel-gfx] [PATCH v2 5/5] drm/dsi: add helpers for DSI compression mode and PPS packets
@ 2019-10-28 15:00 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-10-28 15:00 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula, intel-gfx
Add helper functions for sending the DSI compression mode and picture
parameter set data type packets. For the time being, limit the support
to using VESA DSC 1.1 and the default PPS. This may need updating if the
need arises for proprietary compression or non-default PPS, however keep
it simple for starters.
v2: Add missing EXPORT_SYMBOL
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_mipi_dsi.c | 51 ++++++++++++++++++++++++++++++++++
include/drm/drm_mipi_dsi.h | 4 +++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index 3f33f02571fd..55531895dde6 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -33,6 +33,7 @@
#include <linux/pm_runtime.h>
#include <linux/slab.h>
+#include <drm/drm_dsc.h>
#include <video/mipi_display.h>
/**
@@ -548,6 +549,56 @@ int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
}
EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size);
+/**
+ * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral
+ * @dsi: DSI peripheral device
+ * @enable: Whether to enable or disable the DSC
+ *
+ * Enable or disable Display Stream Compression on the peripheral using the
+ * default Picture Parameter Set and VESA DSC 1.1 algorithm.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)
+{
+ /* Note: Needs updating for non-default PPS or algorithm */
+ u8 tx[2] = { enable << 0, 0 };
+ struct mipi_dsi_msg msg = {
+ .channel = dsi->channel,
+ .type = MIPI_DSI_COMPRESSION_MODE,
+ .tx_len = sizeof(tx),
+ .tx_buf = tx,
+ };
+ int ret = mipi_dsi_device_transfer(dsi, &msg);
+
+ return (ret < 0) ? ret : 0;
+}
+EXPORT_SYMBOL(mipi_dsi_compression_mode);
+
+/**
+ * mipi_dsi_picture_parameter_set() - transmit the DSC PPS to the peripheral
+ * @dsi: DSI peripheral device
+ * @pps: VESA DSC 1.1 Picture Parameter Set
+ *
+ * Transmit the VESA DSC 1.1 Picture Parameter Set to the peripheral.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
+ const struct drm_dsc_picture_parameter_set *pps)
+{
+ struct mipi_dsi_msg msg = {
+ .channel = dsi->channel,
+ .type = MIPI_DSI_PICTURE_PARAMETER_SET,
+ .tx_len = sizeof(*pps),
+ .tx_buf = pps,
+ };
+ int ret = mipi_dsi_device_transfer(dsi, &msg);
+
+ return (ret < 0) ? ret : 0;
+}
+EXPORT_SYMBOL(mipi_dsi_picture_parameter_set);
+
/**
* mipi_dsi_generic_write() - transmit data using a generic write packet
* @dsi: DSI peripheral device
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 13cf2ae59f6c..360e6377e84b 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -13,6 +13,7 @@
struct mipi_dsi_host;
struct mipi_dsi_device;
+struct drm_dsc_picture_parameter_set;
/* request ACK from peripheral */
#define MIPI_DSI_MSG_REQ_ACK BIT(0)
@@ -228,6 +229,9 @@ int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi);
int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi);
int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
u16 value);
+ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable);
+ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
+ const struct drm_dsc_picture_parameter_set *pps);
ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
size_t size);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH v2 5/5] drm/dsi: add helpers for DSI compression mode and PPS packets
@ 2019-11-05 9:55 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-05 9:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: Vandita Kulkarni, intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 767 bytes --]
On Mon, Oct 28, 2019 at 05:00:47PM +0200, Jani Nikula wrote:
> Add helper functions for sending the DSI compression mode and picture
> parameter set data type packets. For the time being, limit the support
> to using VESA DSC 1.1 and the default PPS. This may need updating if the
> need arises for proprietary compression or non-default PPS, however keep
> it simple for starters.
>
> v2: Add missing EXPORT_SYMBOL
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 51 ++++++++++++++++++++++++++++++++++
> include/drm/drm_mipi_dsi.h | 4 +++
> 2 files changed, 55 insertions(+)
Looks good:
Reviewed-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [Intel-gfx] [PATCH v2 5/5] drm/dsi: add helpers for DSI compression mode and PPS packets
@ 2019-11-05 9:55 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-05 9:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 767 bytes --]
On Mon, Oct 28, 2019 at 05:00:47PM +0200, Jani Nikula wrote:
> Add helper functions for sending the DSI compression mode and picture
> parameter set data type packets. For the time being, limit the support
> to using VESA DSC 1.1 and the default PPS. This may need updating if the
> need arises for proprietary compression or non-default PPS, however keep
> it simple for starters.
>
> v2: Add missing EXPORT_SYMBOL
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 51 ++++++++++++++++++++++++++++++++++
> include/drm/drm_mipi_dsi.h | 4 +++
> 2 files changed, 55 insertions(+)
Looks good:
Reviewed-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
@ 2019-10-28 19:17 ` Patchwork
0 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2019-10-28 19:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
URL : https://patchwork.freedesktop.org/series/68664/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b48e99db722b drm/dsi: clean up DSI data type definitions
1e7022690364 drm/dsi: add missing DSI data types
496dc977089e drm/dsi: add missing DSI DCS commands
4473cd70ee71 drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
-:38: WARNING:LONG_LINE_COMMENT: line over 100 characters
#38: FILE: include/video/mipi_display.h:111:
+ MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
total: 0 errors, 1 warnings, 0 checks, 16 lines checked
17cabd00dabc drm/dsi: add helpers for DSI compression mode and PPS packets
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
@ 2019-10-28 19:17 ` Patchwork
0 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2019-10-28 19:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
URL : https://patchwork.freedesktop.org/series/68664/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b48e99db722b drm/dsi: clean up DSI data type definitions
1e7022690364 drm/dsi: add missing DSI data types
496dc977089e drm/dsi: add missing DSI DCS commands
4473cd70ee71 drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
-:38: WARNING:LONG_LINE_COMMENT: line over 100 characters
#38: FILE: include/video/mipi_display.h:111:
+ MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
total: 0 errors, 1 warnings, 0 checks, 16 lines checked
17cabd00dabc drm/dsi: add helpers for DSI compression mode and PPS packets
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
@ 2019-10-28 19:37 ` Patchwork
0 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2019-10-28 19:37 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
URL : https://patchwork.freedesktop.org/series/68664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15027
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/index.html
Known issues
------------
Here are the changes found in Patchwork_15027 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] / [fdo#111381])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724] / [fdo#112052 ])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_flink_basic@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-icl-u3/igt@gem_flink_basic@basic.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#106766])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
* igt@prime_self_import@basic-llseek-bad:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@prime_self_import@basic-llseek-bad.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-icl-u3/igt@prime_self_import@basic-llseek-bad.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_mmap_gtt@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-icl-u3/igt@gem_mmap_gtt@basic.html
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106766]: https://bugs.freedesktop.org/show_bug.cgi?id=106766
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#112052 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112052
Participating hosts (50 -> 43)
------------------------------
Additional (1): fi-kbl-soraka
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7204 -> Patchwork_15027
CI-20190529: 20190529
CI_DRM_7204: 2ec2c26b76ebf320dfecf692a928ed85797dc6b9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15027: 17cabd00dabc9a12834db06227139823f6b94894 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
17cabd00dabc drm/dsi: add helpers for DSI compression mode and PPS packets
4473cd70ee71 drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
496dc977089e drm/dsi: add missing DSI DCS commands
1e7022690364 drm/dsi: add missing DSI data types
b48e99db722b drm/dsi: clean up DSI data type definitions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/index.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
@ 2019-10-29 14:04 ` Patchwork
0 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2019-10-29 14:04 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
URL : https://patchwork.freedesktop.org/series/68664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15027_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_15027_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][3] -> [FAIL][4] ([fdo#109661])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb5/igt@gem_eio@reset-stress.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-snb5/igt@gem_eio@reset-stress.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +4 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb7/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +5 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +7 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb8/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_linear_blits@interruptible:
- shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927] / [fdo#112067])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl6/igt@gem_linear_blits@interruptible.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-apl2/igt@gem_linear_blits@interruptible.html
* igt@gem_linear_blits@normal:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl6/igt@gem_linear_blits@normal.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-apl6/igt@gem_linear_blits@normal.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][19] -> [DMESG-FAIL][20] ([fdo#111991])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw2/igt@i915_selftest@live_hangcheck.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-hsw6/igt@i915_selftest@live_hangcheck.html
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713] / [fdo#108569])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@i915_selftest@live_hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb2/igt@i915_selftest@live_hangcheck.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl1/igt@i915_suspend@sysfs-reader.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-skl9/igt@i915_suspend@sysfs-reader.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [PASS][25] -> [DMESG-WARN][26] ([fdo#106107])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl5/igt@kms_color@pipe-b-ctm-0-5.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-skl2/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#103232])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][31] -> [INCOMPLETE][32] ([fdo#109507])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl3/igt@kms_flip@flip-vs-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-skl7/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [PASS][33] -> [INCOMPLETE][34] ([fdo#103540])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw6/igt@kms_flip@flip-vs-suspend-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-hsw6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][35] -> [DMESG-WARN][36] ([fdo#108566])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][37] -> [FAIL][38] ([fdo#103167]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_vblank@pipe-a-query-forked-busy-hang:
- shard-iclb: [PASS][41] -> [INCOMPLETE][42] ([fdo#107713])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb3/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb7/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-glk: [PASS][43] -> [INCOMPLETE][44] ([fdo#103359] / [k.org#198133])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-glk1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-glk9/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [SKIP][45] ([fdo#112080]) -> [PASS][46] +7 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb8/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb1/igt@gem_ctx_exec@basic-invalid-context-vcs1.html
* igt@gem_ctx_isolation@vcs0-s3:
- shard-skl: [INCOMPLETE][47] ([fdo#104108]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl4/igt@gem_ctx_isolation@vcs0-s3.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-skl7/igt@gem_ctx_isolation@vcs0-s3.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][49] ([fdo#112146]) -> [PASS][50] +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [FAIL][53] ([fdo#105767]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][55] ([fdo#103167]) -> [PASS][56] +5 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-skl: [FAIL][57] ([fdo#103167]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
- shard-iclb: [INCOMPLETE][59] ([fdo#106978] / [fdo#107713]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb3/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [DMESG-WARN][61] ([fdo#108566]) -> [PASS][62] +5 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][63] ([fdo#108566]) -> [PASS][64] +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][65] ([fdo#103166]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][67] ([fdo#108341]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb1/igt@kms_psr@no_drrs.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb5/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb5/igt@kms_psr@psr2_sprite_plane_onoff.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][71] ([fdo#109276]) -> [PASS][72] +15 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb3/igt@prime_busy@hang-bsd2.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][73] ([fdo#109276] / [fdo#112080]) -> [FAIL][74] ([fdo#111329])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [FAIL][75] ([fdo#111330]) -> [SKIP][76] ([fdo#109276])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb3/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [SKIP][77] ([fdo#109276]) -> [FAIL][78] ([fdo#111330])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb8/igt@gem_mocs_settings@mocs-reset-bsd2.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb1/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-hsw: [DMESG-WARN][79] ([fdo#111870]) -> [DMESG-WARN][80] ([fdo#110789] / [fdo#111870])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw5/igt@gem_userptr_blits@dmabuf-sync.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-hsw6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@kms_content_protection@srm:
- shard-apl: [FAIL][81] ([fdo#110321]) -> [INCOMPLETE][82] ([fdo#103927])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl2/igt@kms_content_protection@srm.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-apl3/igt@kms_content_protection@srm.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][83] ([fdo#107724]) -> [SKIP][84] ([fdo#109349])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991
[fdo#112067]: https://bugs.freedesktop.org/show_bug.cgi?id=112067
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7204 -> Patchwork_15027
CI-20190529: 20190529
CI_DRM_7204: 2ec2c26b76ebf320dfecf692a928ed85797dc6b9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15027: 17cabd00dabc9a12834db06227139823f6b94894 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-04 14:07 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-04 14:07 UTC (permalink / raw)
To: dri-devel
Cc: intel-gfx, Vandita Kulkarni, Sean Paul, Vinay Simha BN, Thierry Reding
Hi all, I'd really appreciate some (non-Intel) acks or reviews on this
series. Don't feel comfortable merging it otherwise. It should be fairly
straightforward stuff as long as you have some DSI specs handy.
BR,
Jani.
On Mon, 28 Oct 2019, Jani Nikula <jani.nikula@intel.com> wrote:
> Rename picture parameter set (it's a long packet, not a long write) and
> compression mode (it's not a DCS command) enumerations according to the
> DSI specification. Order the types according to the spec. Use tabs
> instead of spaces for indentation. Use all lower case for hex.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
> include/video/mipi_display.h | 10 +++++-----
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index bd2498bbd74a..f237d80828c3 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_V_SYNC_END:
> case MIPI_DSI_H_SYNC_START:
> case MIPI_DSI_H_SYNC_END:
> + case MIPI_DSI_COMPRESSION_MODE:
> case MIPI_DSI_END_OF_TRANSMISSION:
> case MIPI_DSI_COLOR_MODE_OFF:
> case MIPI_DSI_COLOR_MODE_ON:
> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> - case MIPI_DSI_DCS_COMPRESSION_MODE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
> bool mipi_dsi_packet_format_is_long(u8 type)
> {
> switch (type) {
> - case MIPI_DSI_PPS_LONG_WRITE:
> case MIPI_DSI_NULL_PACKET:
> case MIPI_DSI_BLANKING_PACKET:
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> + case MIPI_DSI_PICTURE_PARAMETER_SET:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index cba57a678daf..79fd71cf4934 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -17,6 +17,9 @@ enum {
> MIPI_DSI_H_SYNC_START = 0x21,
> MIPI_DSI_H_SYNC_END = 0x31,
>
> + MIPI_DSI_COMPRESSION_MODE = 0x07,
> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> +
> MIPI_DSI_COLOR_MODE_OFF = 0x02,
> MIPI_DSI_COLOR_MODE_ON = 0x12,
> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
> @@ -35,18 +38,15 @@ enum {
>
> MIPI_DSI_DCS_READ = 0x06,
>
> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
> -
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> -
> MIPI_DSI_NULL_PACKET = 0x09,
> MIPI_DSI_BLANKING_PACKET = 0x19,
> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> +
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-04 14:07 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-04 14:07 UTC (permalink / raw)
To: dri-devel
Cc: Andrzej Hajda, intel-gfx, Sean Paul, Vinay Simha BN, Thierry Reding
Hi all, I'd really appreciate some (non-Intel) acks or reviews on this
series. Don't feel comfortable merging it otherwise. It should be fairly
straightforward stuff as long as you have some DSI specs handy.
BR,
Jani.
On Mon, 28 Oct 2019, Jani Nikula <jani.nikula@intel.com> wrote:
> Rename picture parameter set (it's a long packet, not a long write) and
> compression mode (it's not a DCS command) enumerations according to the
> DSI specification. Order the types according to the spec. Use tabs
> instead of spaces for indentation. Use all lower case for hex.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
> include/video/mipi_display.h | 10 +++++-----
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index bd2498bbd74a..f237d80828c3 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_V_SYNC_END:
> case MIPI_DSI_H_SYNC_START:
> case MIPI_DSI_H_SYNC_END:
> + case MIPI_DSI_COMPRESSION_MODE:
> case MIPI_DSI_END_OF_TRANSMISSION:
> case MIPI_DSI_COLOR_MODE_OFF:
> case MIPI_DSI_COLOR_MODE_ON:
> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> - case MIPI_DSI_DCS_COMPRESSION_MODE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
> bool mipi_dsi_packet_format_is_long(u8 type)
> {
> switch (type) {
> - case MIPI_DSI_PPS_LONG_WRITE:
> case MIPI_DSI_NULL_PACKET:
> case MIPI_DSI_BLANKING_PACKET:
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> + case MIPI_DSI_PICTURE_PARAMETER_SET:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index cba57a678daf..79fd71cf4934 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -17,6 +17,9 @@ enum {
> MIPI_DSI_H_SYNC_START = 0x21,
> MIPI_DSI_H_SYNC_END = 0x31,
>
> + MIPI_DSI_COMPRESSION_MODE = 0x07,
> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> +
> MIPI_DSI_COLOR_MODE_OFF = 0x02,
> MIPI_DSI_COLOR_MODE_ON = 0x12,
> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
> @@ -35,18 +38,15 @@ enum {
>
> MIPI_DSI_DCS_READ = 0x06,
>
> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
> -
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> -
> MIPI_DSI_NULL_PACKET = 0x09,
> MIPI_DSI_BLANKING_PACKET = 0x19,
> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> +
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-07 13:21 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-07 13:21 UTC (permalink / raw)
To: dri-devel
Cc: Maxime Ripard, intel-gfx, Vandita Kulkarni, Sean Paul,
Vinay Simha BN, Thierry Reding
On Mon, 04 Nov 2019, Jani Nikula <jani.nikula@intel.com> wrote:
> Hi all, I'd really appreciate some (non-Intel) acks or reviews on this
> series. Don't feel comfortable merging it otherwise. It should be fairly
> straightforward stuff as long as you have some DSI specs handy.
Thanks for the reviews. I've pushed the patches to a new topic branch
drm-intel/topic/drm-mipi-dsi-dsc-updates per feedback from Sean and
Daniel. I'll be needing these dependencies in i915 sooner than a
roundtrip through drm-misc->drm-next->drm-intel would be convenient.
I'll send a pull request to drm-misc soonish, and will also pull to
drm-intel after the merge to drm-misc.
Please holler if you have any issues with this.
BR,
Jani.
>
> BR,
> Jani.
>
>
> On Mon, 28 Oct 2019, Jani Nikula <jani.nikula@intel.com> wrote:
>> Rename picture parameter set (it's a long packet, not a long write) and
>> compression mode (it's not a DCS command) enumerations according to the
>> DSI specification. Order the types according to the spec. Use tabs
>> instead of spaces for indentation. Use all lower case for hex.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
>> include/video/mipi_display.h | 10 +++++-----
>> 2 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
>> index bd2498bbd74a..f237d80828c3 100644
>> --- a/drivers/gpu/drm/drm_mipi_dsi.c
>> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
>> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
>> case MIPI_DSI_V_SYNC_END:
>> case MIPI_DSI_H_SYNC_START:
>> case MIPI_DSI_H_SYNC_END:
>> + case MIPI_DSI_COMPRESSION_MODE:
>> case MIPI_DSI_END_OF_TRANSMISSION:
>> case MIPI_DSI_COLOR_MODE_OFF:
>> case MIPI_DSI_COLOR_MODE_ON:
>> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
>> case MIPI_DSI_DCS_SHORT_WRITE:
>> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
>> case MIPI_DSI_DCS_READ:
>> - case MIPI_DSI_DCS_COMPRESSION_MODE:
>> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
>> return true;
>> }
>> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
>> bool mipi_dsi_packet_format_is_long(u8 type)
>> {
>> switch (type) {
>> - case MIPI_DSI_PPS_LONG_WRITE:
>> case MIPI_DSI_NULL_PACKET:
>> case MIPI_DSI_BLANKING_PACKET:
>> case MIPI_DSI_GENERIC_LONG_WRITE:
>> case MIPI_DSI_DCS_LONG_WRITE:
>> + case MIPI_DSI_PICTURE_PARAMETER_SET:
>> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
>> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
>> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index cba57a678daf..79fd71cf4934 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -17,6 +17,9 @@ enum {
>> MIPI_DSI_H_SYNC_START = 0x21,
>> MIPI_DSI_H_SYNC_END = 0x31,
>>
>> + MIPI_DSI_COMPRESSION_MODE = 0x07,
>> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
>> +
>> MIPI_DSI_COLOR_MODE_OFF = 0x02,
>> MIPI_DSI_COLOR_MODE_ON = 0x12,
>> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
>> @@ -35,18 +38,15 @@ enum {
>>
>> MIPI_DSI_DCS_READ = 0x06,
>>
>> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
>> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
>> -
>> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>>
>> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
>> -
>> MIPI_DSI_NULL_PACKET = 0x09,
>> MIPI_DSI_BLANKING_PACKET = 0x19,
>> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
>> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>>
>> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
>> +
>> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
>> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
>> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-07 13:21 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-07 13:21 UTC (permalink / raw)
To: dri-devel
Cc: Andrzej Hajda, Maxime Ripard, intel-gfx, Sean Paul,
Vinay Simha BN, Thierry Reding
On Mon, 04 Nov 2019, Jani Nikula <jani.nikula@intel.com> wrote:
> Hi all, I'd really appreciate some (non-Intel) acks or reviews on this
> series. Don't feel comfortable merging it otherwise. It should be fairly
> straightforward stuff as long as you have some DSI specs handy.
Thanks for the reviews. I've pushed the patches to a new topic branch
drm-intel/topic/drm-mipi-dsi-dsc-updates per feedback from Sean and
Daniel. I'll be needing these dependencies in i915 sooner than a
roundtrip through drm-misc->drm-next->drm-intel would be convenient.
I'll send a pull request to drm-misc soonish, and will also pull to
drm-intel after the merge to drm-misc.
Please holler if you have any issues with this.
BR,
Jani.
>
> BR,
> Jani.
>
>
> On Mon, 28 Oct 2019, Jani Nikula <jani.nikula@intel.com> wrote:
>> Rename picture parameter set (it's a long packet, not a long write) and
>> compression mode (it's not a DCS command) enumerations according to the
>> DSI specification. Order the types according to the spec. Use tabs
>> instead of spaces for indentation. Use all lower case for hex.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
>> include/video/mipi_display.h | 10 +++++-----
>> 2 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
>> index bd2498bbd74a..f237d80828c3 100644
>> --- a/drivers/gpu/drm/drm_mipi_dsi.c
>> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
>> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
>> case MIPI_DSI_V_SYNC_END:
>> case MIPI_DSI_H_SYNC_START:
>> case MIPI_DSI_H_SYNC_END:
>> + case MIPI_DSI_COMPRESSION_MODE:
>> case MIPI_DSI_END_OF_TRANSMISSION:
>> case MIPI_DSI_COLOR_MODE_OFF:
>> case MIPI_DSI_COLOR_MODE_ON:
>> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
>> case MIPI_DSI_DCS_SHORT_WRITE:
>> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
>> case MIPI_DSI_DCS_READ:
>> - case MIPI_DSI_DCS_COMPRESSION_MODE:
>> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
>> return true;
>> }
>> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
>> bool mipi_dsi_packet_format_is_long(u8 type)
>> {
>> switch (type) {
>> - case MIPI_DSI_PPS_LONG_WRITE:
>> case MIPI_DSI_NULL_PACKET:
>> case MIPI_DSI_BLANKING_PACKET:
>> case MIPI_DSI_GENERIC_LONG_WRITE:
>> case MIPI_DSI_DCS_LONG_WRITE:
>> + case MIPI_DSI_PICTURE_PARAMETER_SET:
>> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
>> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
>> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index cba57a678daf..79fd71cf4934 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -17,6 +17,9 @@ enum {
>> MIPI_DSI_H_SYNC_START = 0x21,
>> MIPI_DSI_H_SYNC_END = 0x31,
>>
>> + MIPI_DSI_COMPRESSION_MODE = 0x07,
>> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
>> +
>> MIPI_DSI_COLOR_MODE_OFF = 0x02,
>> MIPI_DSI_COLOR_MODE_ON = 0x12,
>> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
>> @@ -35,18 +38,15 @@ enum {
>>
>> MIPI_DSI_DCS_READ = 0x06,
>>
>> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
>> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
>> -
>> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>>
>> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
>> -
>> MIPI_DSI_NULL_PACKET = 0x09,
>> MIPI_DSI_BLANKING_PACKET = 0x19,
>> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
>> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>>
>> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
>> +
>> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
>> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
>> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-04 15:20 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-04 15:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 3797 bytes --]
On Mon, Oct 28, 2019 at 05:00:43PM +0200, Jani Nikula wrote:
> Rename picture parameter set (it's a long packet, not a long write) and
> compression mode (it's not a DCS command) enumerations according to the
> DSI specification. Order the types according to the spec. Use tabs
> instead of spaces for indentation. Use all lower case for hex.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
> include/video/mipi_display.h | 10 +++++-----
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index bd2498bbd74a..f237d80828c3 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_V_SYNC_END:
> case MIPI_DSI_H_SYNC_START:
> case MIPI_DSI_H_SYNC_END:
> + case MIPI_DSI_COMPRESSION_MODE:
> case MIPI_DSI_END_OF_TRANSMISSION:
> case MIPI_DSI_COLOR_MODE_OFF:
> case MIPI_DSI_COLOR_MODE_ON:
> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> - case MIPI_DSI_DCS_COMPRESSION_MODE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
> bool mipi_dsi_packet_format_is_long(u8 type)
> {
> switch (type) {
> - case MIPI_DSI_PPS_LONG_WRITE:
> case MIPI_DSI_NULL_PACKET:
> case MIPI_DSI_BLANKING_PACKET:
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> + case MIPI_DSI_PICTURE_PARAMETER_SET:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index cba57a678daf..79fd71cf4934 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -17,6 +17,9 @@ enum {
> MIPI_DSI_H_SYNC_START = 0x21,
> MIPI_DSI_H_SYNC_END = 0x31,
>
> + MIPI_DSI_COMPRESSION_MODE = 0x07,
> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> +
> MIPI_DSI_COLOR_MODE_OFF = 0x02,
> MIPI_DSI_COLOR_MODE_ON = 0x12,
> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
> @@ -35,18 +38,15 @@ enum {
>
> MIPI_DSI_DCS_READ = 0x06,
>
> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
> -
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> -
> MIPI_DSI_NULL_PACKET = 0x09,
> MIPI_DSI_BLANKING_PACKET = 0x19,
> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> +
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
Looks good to me. I haven't specifically checked that the order matches
that in the specification, but given that it's not really ordered in any
sane way in the first place (or perhaps I'm too stupid to see the logic)
I don't really mind about the order.
Took me a while to find the specification. You might want to mention in
the commit message that some of these enumerations are only available in
the DSI 2 specification because I was looking at 1.2 first. Anyway, the
enumerations and names match what's in the spec, so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-04 15:20 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-04 15:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 3797 bytes --]
On Mon, Oct 28, 2019 at 05:00:43PM +0200, Jani Nikula wrote:
> Rename picture parameter set (it's a long packet, not a long write) and
> compression mode (it's not a DCS command) enumerations according to the
> DSI specification. Order the types according to the spec. Use tabs
> instead of spaces for indentation. Use all lower case for hex.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
> include/video/mipi_display.h | 10 +++++-----
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index bd2498bbd74a..f237d80828c3 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_V_SYNC_END:
> case MIPI_DSI_H_SYNC_START:
> case MIPI_DSI_H_SYNC_END:
> + case MIPI_DSI_COMPRESSION_MODE:
> case MIPI_DSI_END_OF_TRANSMISSION:
> case MIPI_DSI_COLOR_MODE_OFF:
> case MIPI_DSI_COLOR_MODE_ON:
> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> - case MIPI_DSI_DCS_COMPRESSION_MODE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
> bool mipi_dsi_packet_format_is_long(u8 type)
> {
> switch (type) {
> - case MIPI_DSI_PPS_LONG_WRITE:
> case MIPI_DSI_NULL_PACKET:
> case MIPI_DSI_BLANKING_PACKET:
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> + case MIPI_DSI_PICTURE_PARAMETER_SET:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index cba57a678daf..79fd71cf4934 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -17,6 +17,9 @@ enum {
> MIPI_DSI_H_SYNC_START = 0x21,
> MIPI_DSI_H_SYNC_END = 0x31,
>
> + MIPI_DSI_COMPRESSION_MODE = 0x07,
> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> +
> MIPI_DSI_COLOR_MODE_OFF = 0x02,
> MIPI_DSI_COLOR_MODE_ON = 0x12,
> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
> @@ -35,18 +38,15 @@ enum {
>
> MIPI_DSI_DCS_READ = 0x06,
>
> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
> -
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> -
> MIPI_DSI_NULL_PACKET = 0x09,
> MIPI_DSI_BLANKING_PACKET = 0x19,
> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> +
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
Looks good to me. I haven't specifically checked that the order matches
that in the specification, but given that it's not really ordered in any
sane way in the first place (or perhaps I'm too stupid to see the logic)
I don't really mind about the order.
Took me a while to find the specification. You might want to mention in
the commit message that some of these enumerations are only available in
the DSI 2 specification because I was looking at 1.2 first. Anyway, the
enumerations and names match what's in the spec, so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-04 15:20 ` Thierry Reding
0 siblings, 0 replies; 45+ messages in thread
From: Thierry Reding @ 2019-11-04 15:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 3797 bytes --]
On Mon, Oct 28, 2019 at 05:00:43PM +0200, Jani Nikula wrote:
> Rename picture parameter set (it's a long packet, not a long write) and
> compression mode (it's not a DCS command) enumerations according to the
> DSI specification. Order the types according to the spec. Use tabs
> instead of spaces for indentation. Use all lower case for hex.
>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
> include/video/mipi_display.h | 10 +++++-----
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index bd2498bbd74a..f237d80828c3 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_V_SYNC_END:
> case MIPI_DSI_H_SYNC_START:
> case MIPI_DSI_H_SYNC_END:
> + case MIPI_DSI_COMPRESSION_MODE:
> case MIPI_DSI_END_OF_TRANSMISSION:
> case MIPI_DSI_COLOR_MODE_OFF:
> case MIPI_DSI_COLOR_MODE_ON:
> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
> case MIPI_DSI_DCS_SHORT_WRITE:
> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
> case MIPI_DSI_DCS_READ:
> - case MIPI_DSI_DCS_COMPRESSION_MODE:
> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
> return true;
> }
> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
> bool mipi_dsi_packet_format_is_long(u8 type)
> {
> switch (type) {
> - case MIPI_DSI_PPS_LONG_WRITE:
> case MIPI_DSI_NULL_PACKET:
> case MIPI_DSI_BLANKING_PACKET:
> case MIPI_DSI_GENERIC_LONG_WRITE:
> case MIPI_DSI_DCS_LONG_WRITE:
> + case MIPI_DSI_PICTURE_PARAMETER_SET:
> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
> index cba57a678daf..79fd71cf4934 100644
> --- a/include/video/mipi_display.h
> +++ b/include/video/mipi_display.h
> @@ -17,6 +17,9 @@ enum {
> MIPI_DSI_H_SYNC_START = 0x21,
> MIPI_DSI_H_SYNC_END = 0x31,
>
> + MIPI_DSI_COMPRESSION_MODE = 0x07,
> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> +
> MIPI_DSI_COLOR_MODE_OFF = 0x02,
> MIPI_DSI_COLOR_MODE_ON = 0x12,
> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
> @@ -35,18 +38,15 @@ enum {
>
> MIPI_DSI_DCS_READ = 0x06,
>
> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
> -
> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>
> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
> -
> MIPI_DSI_NULL_PACKET = 0x09,
> MIPI_DSI_BLANKING_PACKET = 0x19,
> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>
> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
> +
> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
Looks good to me. I haven't specifically checked that the order matches
that in the specification, but given that it's not really ordered in any
sane way in the first place (or perhaps I'm too stupid to see the logic)
I don't really mind about the order.
Took me a while to find the specification. You might want to mention in
the commit message that some of these enumerations are only available in
the DSI 2 specification because I was looking at 1.2 first. Anyway, the
enumerations and names match what's in the spec, so:
Reviewed-by: Thierry Reding <treding@nvidia.com>
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-05 9:18 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-05 9:18 UTC (permalink / raw)
To: Thierry Reding; +Cc: intel-gfx, dri-devel
On Mon, 04 Nov 2019, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Mon, Oct 28, 2019 at 05:00:43PM +0200, Jani Nikula wrote:
>> Rename picture parameter set (it's a long packet, not a long write) and
>> compression mode (it's not a DCS command) enumerations according to the
>> DSI specification. Order the types according to the spec. Use tabs
>> instead of spaces for indentation. Use all lower case for hex.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
>> include/video/mipi_display.h | 10 +++++-----
>> 2 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
>> index bd2498bbd74a..f237d80828c3 100644
>> --- a/drivers/gpu/drm/drm_mipi_dsi.c
>> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
>> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
>> case MIPI_DSI_V_SYNC_END:
>> case MIPI_DSI_H_SYNC_START:
>> case MIPI_DSI_H_SYNC_END:
>> + case MIPI_DSI_COMPRESSION_MODE:
>> case MIPI_DSI_END_OF_TRANSMISSION:
>> case MIPI_DSI_COLOR_MODE_OFF:
>> case MIPI_DSI_COLOR_MODE_ON:
>> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
>> case MIPI_DSI_DCS_SHORT_WRITE:
>> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
>> case MIPI_DSI_DCS_READ:
>> - case MIPI_DSI_DCS_COMPRESSION_MODE:
>> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
>> return true;
>> }
>> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
>> bool mipi_dsi_packet_format_is_long(u8 type)
>> {
>> switch (type) {
>> - case MIPI_DSI_PPS_LONG_WRITE:
>> case MIPI_DSI_NULL_PACKET:
>> case MIPI_DSI_BLANKING_PACKET:
>> case MIPI_DSI_GENERIC_LONG_WRITE:
>> case MIPI_DSI_DCS_LONG_WRITE:
>> + case MIPI_DSI_PICTURE_PARAMETER_SET:
>> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
>> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
>> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index cba57a678daf..79fd71cf4934 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -17,6 +17,9 @@ enum {
>> MIPI_DSI_H_SYNC_START = 0x21,
>> MIPI_DSI_H_SYNC_END = 0x31,
>>
>> + MIPI_DSI_COMPRESSION_MODE = 0x07,
>> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
>> +
>> MIPI_DSI_COLOR_MODE_OFF = 0x02,
>> MIPI_DSI_COLOR_MODE_ON = 0x12,
>> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
>> @@ -35,18 +38,15 @@ enum {
>>
>> MIPI_DSI_DCS_READ = 0x06,
>>
>> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
>> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
>> -
>> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>>
>> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
>> -
>> MIPI_DSI_NULL_PACKET = 0x09,
>> MIPI_DSI_BLANKING_PACKET = 0x19,
>> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
>> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>>
>> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
>> +
>> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
>> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
>> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
>
> Looks good to me. I haven't specifically checked that the order matches
> that in the specification, but given that it's not really ordered in any
> sane way in the first place (or perhaps I'm too stupid to see the logic)
> I don't really mind about the order.
>
> Took me a while to find the specification. You might want to mention in
> the commit message that some of these enumerations are only available in
> the DSI 2 specification because I was looking at 1.2 first. Anyway, the
> enumerations and names match what's in the spec, so:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
Thanks. They are already in DSI 1.3.1 though.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
@ 2019-11-05 9:18 ` Jani Nikula
0 siblings, 0 replies; 45+ messages in thread
From: Jani Nikula @ 2019-11-05 9:18 UTC (permalink / raw)
To: Thierry Reding; +Cc: intel-gfx, dri-devel
On Mon, 04 Nov 2019, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Mon, Oct 28, 2019 at 05:00:43PM +0200, Jani Nikula wrote:
>> Rename picture parameter set (it's a long packet, not a long write) and
>> compression mode (it's not a DCS command) enumerations according to the
>> DSI specification. Order the types according to the spec. Use tabs
>> instead of spaces for indentation. Use all lower case for hex.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
>> include/video/mipi_display.h | 10 +++++-----
>> 2 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
>> index bd2498bbd74a..f237d80828c3 100644
>> --- a/drivers/gpu/drm/drm_mipi_dsi.c
>> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
>> @@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
>> case MIPI_DSI_V_SYNC_END:
>> case MIPI_DSI_H_SYNC_START:
>> case MIPI_DSI_H_SYNC_END:
>> + case MIPI_DSI_COMPRESSION_MODE:
>> case MIPI_DSI_END_OF_TRANSMISSION:
>> case MIPI_DSI_COLOR_MODE_OFF:
>> case MIPI_DSI_COLOR_MODE_ON:
>> @@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
>> case MIPI_DSI_DCS_SHORT_WRITE:
>> case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
>> case MIPI_DSI_DCS_READ:
>> - case MIPI_DSI_DCS_COMPRESSION_MODE:
>> case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
>> return true;
>> }
>> @@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
>> bool mipi_dsi_packet_format_is_long(u8 type)
>> {
>> switch (type) {
>> - case MIPI_DSI_PPS_LONG_WRITE:
>> case MIPI_DSI_NULL_PACKET:
>> case MIPI_DSI_BLANKING_PACKET:
>> case MIPI_DSI_GENERIC_LONG_WRITE:
>> case MIPI_DSI_DCS_LONG_WRITE:
>> + case MIPI_DSI_PICTURE_PARAMETER_SET:
>> case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
>> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
>> case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
>> diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
>> index cba57a678daf..79fd71cf4934 100644
>> --- a/include/video/mipi_display.h
>> +++ b/include/video/mipi_display.h
>> @@ -17,6 +17,9 @@ enum {
>> MIPI_DSI_H_SYNC_START = 0x21,
>> MIPI_DSI_H_SYNC_END = 0x31,
>>
>> + MIPI_DSI_COMPRESSION_MODE = 0x07,
>> + MIPI_DSI_END_OF_TRANSMISSION = 0x08,
>> +
>> MIPI_DSI_COLOR_MODE_OFF = 0x02,
>> MIPI_DSI_COLOR_MODE_ON = 0x12,
>> MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
>> @@ -35,18 +38,15 @@ enum {
>>
>> MIPI_DSI_DCS_READ = 0x06,
>>
>> - MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
>> - MIPI_DSI_PPS_LONG_WRITE = 0x0A,
>> -
>> MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
>>
>> - MIPI_DSI_END_OF_TRANSMISSION = 0x08,
>> -
>> MIPI_DSI_NULL_PACKET = 0x09,
>> MIPI_DSI_BLANKING_PACKET = 0x19,
>> MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
>> MIPI_DSI_DCS_LONG_WRITE = 0x39,
>>
>> + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
>> +
>> MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
>> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
>> MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
>
> Looks good to me. I haven't specifically checked that the order matches
> that in the specification, but given that it's not really ordered in any
> sane way in the first place (or perhaps I'm too stupid to see the logic)
> I don't really mind about the order.
>
> Took me a while to find the specification. You might want to mention in
> the commit message that some of these enumerations are only available in
> the DSI 2 specification because I was looking at 1.2 first. Anyway, the
> enumerations and names match what's in the spec, so:
>
> Reviewed-by: Thierry Reding <treding@nvidia.com>
Thanks. They are already in DSI 1.3.1 though.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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