From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Kuogee Hsieh <quic_khsieh@quicinc.com>, dri-devel@lists.freedesktop.org, robdclark@gmail.com, sean@poorly.run, swboyd@chromium.org, dianders@chromium.org, vkoul@kernel.org, daniel@ffwll.ch, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, airlied@gmail.com Cc: quic_abhinavk@quicinc.com, quic_sbillaka@quicinc.com, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v12 5/5] drm/msm/dp: add support of max dp link rate Date: Wed, 14 Dec 2022 00:06:21 +0200 [thread overview] Message-ID: <8FEED6F1-4F23-4B17-AD4C-8145CDE8C47B@linaro.org> (raw) In-Reply-To: <1670967848-31475-6-git-send-email-quic_khsieh@quicinc.com> On 13 December 2022 23:44:08 EET, Kuogee Hsieh <quic_khsieh@quicinc.com> wrote: >By default, HBR2 (5.4G) is the max link link be supported. This patch uses the >actual limit specified by DT and removes the artificial limitation to 5.4 Gbps. >Supporting HBR3 is a consequence of that. > >Changes in v2: >-- add max link rate from dtsi > >Changes in v3: >-- parser max_data_lanes and max_dp_link_rate from dp_out endpoint > >Changes in v4: >-- delete unnecessary pr_err > >Changes in v5: >-- split parser function into different patch > >Changes in v9: >-- revised commit test > >Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> >Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >--- > drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ > drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++++--- > drivers/gpu/drm/msm/dp/dp_panel.h | 1 + > 3 files changed, 9 insertions(+), 3 deletions(-) > >diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c >index bfd0aef..edee550 100644 >--- a/drivers/gpu/drm/msm/dp/dp_display.c >+++ b/drivers/gpu/drm/msm/dp/dp_display.c >@@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) > struct edid *edid; > > dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; >+ dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate; >+ >+ drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n", >+ dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); > > rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); > if (rc) >diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c >index 5149ceb..933fa9c 100644 >--- a/drivers/gpu/drm/msm/dp/dp_panel.c >+++ b/drivers/gpu/drm/msm/dp/dp_panel.c >@@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) > link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); > link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; > >+ /* Limit data lanes from data-lanes of endpoint properity of dtsi */ Nit: property. And below too. > if (link_info->num_lanes > dp_panel->max_dp_lanes) > link_info->num_lanes = dp_panel->max_dp_lanes; > >- /* Limit support upto HBR2 until HBR3 support is added */ >- if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) >- link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); >+ /* Limit link rate from link-frequencies of endpoint properity of dtsi */ >+ if (link_info->rate > dp_panel->max_dp_link_rate) >+ link_info->rate = dp_panel->max_dp_link_rate; > > drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); > drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); >diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h >index d861197a..f04d021 100644 >--- a/drivers/gpu/drm/msm/dp/dp_panel.h >+++ b/drivers/gpu/drm/msm/dp/dp_panel.h >@@ -50,6 +50,7 @@ struct dp_panel { > > u32 vic; > u32 max_dp_lanes; >+ u32 max_dp_link_rate; > > u32 max_bw_code; > }; -- With best wishes Dmitry
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Kuogee Hsieh <quic_khsieh@quicinc.com>, dri-devel@lists.freedesktop.org, robdclark@gmail.com, sean@poorly.run, swboyd@chromium.org, dianders@chromium.org, vkoul@kernel.org, daniel@ffwll.ch, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, airlied@gmail.com Cc: linux-arm-msm@vger.kernel.org, quic_sbillaka@quicinc.com, freedreno@lists.freedesktop.org, quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v12 5/5] drm/msm/dp: add support of max dp link rate Date: Wed, 14 Dec 2022 00:06:21 +0200 [thread overview] Message-ID: <8FEED6F1-4F23-4B17-AD4C-8145CDE8C47B@linaro.org> (raw) In-Reply-To: <1670967848-31475-6-git-send-email-quic_khsieh@quicinc.com> On 13 December 2022 23:44:08 EET, Kuogee Hsieh <quic_khsieh@quicinc.com> wrote: >By default, HBR2 (5.4G) is the max link link be supported. This patch uses the >actual limit specified by DT and removes the artificial limitation to 5.4 Gbps. >Supporting HBR3 is a consequence of that. > >Changes in v2: >-- add max link rate from dtsi > >Changes in v3: >-- parser max_data_lanes and max_dp_link_rate from dp_out endpoint > >Changes in v4: >-- delete unnecessary pr_err > >Changes in v5: >-- split parser function into different patch > >Changes in v9: >-- revised commit test > >Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> >Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >--- > drivers/gpu/drm/msm/dp/dp_display.c | 4 ++++ > drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++++--- > drivers/gpu/drm/msm/dp/dp_panel.h | 1 + > 3 files changed, 9 insertions(+), 3 deletions(-) > >diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c >index bfd0aef..edee550 100644 >--- a/drivers/gpu/drm/msm/dp/dp_display.c >+++ b/drivers/gpu/drm/msm/dp/dp_display.c >@@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) > struct edid *edid; > > dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; >+ dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate; >+ >+ drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n", >+ dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); > > rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); > if (rc) >diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c >index 5149ceb..933fa9c 100644 >--- a/drivers/gpu/drm/msm/dp/dp_panel.c >+++ b/drivers/gpu/drm/msm/dp/dp_panel.c >@@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) > link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); > link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; > >+ /* Limit data lanes from data-lanes of endpoint properity of dtsi */ Nit: property. And below too. > if (link_info->num_lanes > dp_panel->max_dp_lanes) > link_info->num_lanes = dp_panel->max_dp_lanes; > >- /* Limit support upto HBR2 until HBR3 support is added */ >- if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) >- link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); >+ /* Limit link rate from link-frequencies of endpoint properity of dtsi */ >+ if (link_info->rate > dp_panel->max_dp_link_rate) >+ link_info->rate = dp_panel->max_dp_link_rate; > > drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); > drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); >diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h >index d861197a..f04d021 100644 >--- a/drivers/gpu/drm/msm/dp/dp_panel.h >+++ b/drivers/gpu/drm/msm/dp/dp_panel.h >@@ -50,6 +50,7 @@ struct dp_panel { > > u32 vic; > u32 max_dp_lanes; >+ u32 max_dp_link_rate; > > u32 max_bw_code; > }; -- With best wishes Dmitry
next prev parent reply other threads:[~2022-12-13 22:06 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-13 21:44 [PATCH v12 0/5] Add data-lanes and link-frequencies to dp_out endpoint Kuogee Hsieh 2022-12-13 21:44 ` Kuogee Hsieh 2022-12-13 21:44 ` [PATCH v12 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into " Kuogee Hsieh 2022-12-13 21:44 ` Kuogee Hsieh 2022-12-13 23:31 ` Dmitry Baryshkov 2022-12-13 23:31 ` Dmitry Baryshkov 2022-12-13 21:44 ` [PATCH v12 2/5] dt-bindings: msm/dp: add data-lanes and link-frequencies property Kuogee Hsieh 2022-12-13 21:44 ` Kuogee Hsieh 2022-12-13 22:02 ` Dmitry Baryshkov 2022-12-13 22:02 ` Dmitry Baryshkov 2022-12-13 23:06 ` Stephen Boyd 2022-12-13 23:06 ` Stephen Boyd 2022-12-14 22:56 ` Kuogee Hsieh 2022-12-14 22:56 ` Kuogee Hsieh 2022-12-15 0:38 ` Stephen Boyd 2022-12-15 0:38 ` Stephen Boyd 2022-12-15 17:08 ` Kuogee Hsieh 2022-12-15 17:08 ` Kuogee Hsieh 2022-12-15 20:12 ` Stephen Boyd 2022-12-15 20:12 ` Stephen Boyd 2022-12-15 21:12 ` Dmitry Baryshkov 2022-12-15 21:12 ` Dmitry Baryshkov 2022-12-15 22:57 ` Doug Anderson 2022-12-15 22:57 ` Doug Anderson 2022-12-15 23:02 ` Dmitry Baryshkov 2022-12-15 23:02 ` Dmitry Baryshkov 2022-12-16 2:16 ` Stephen Boyd 2022-12-16 2:16 ` Stephen Boyd 2022-12-16 19:03 ` Kuogee Hsieh 2022-12-16 19:03 ` Kuogee Hsieh 2022-12-16 19:43 ` Dmitry Baryshkov 2022-12-16 19:43 ` Dmitry Baryshkov 2022-12-13 21:44 ` [PATCH v12 3/5] drm/msm/dp: parser data-lanes as property of dp_out endpoint Kuogee Hsieh 2022-12-13 21:44 ` Kuogee Hsieh 2022-12-13 23:11 ` Stephen Boyd 2022-12-13 23:11 ` Stephen Boyd 2022-12-13 21:44 ` [PATCH v12 4/5] drm/msm/dp: parser link-frequencies " Kuogee Hsieh 2022-12-13 21:44 ` Kuogee Hsieh 2022-12-13 22:07 ` Dmitry Baryshkov 2022-12-13 22:07 ` Dmitry Baryshkov 2022-12-13 23:18 ` Stephen Boyd 2022-12-13 23:18 ` Stephen Boyd 2022-12-13 21:44 ` [PATCH v12 5/5] drm/msm/dp: add support of max dp link rate Kuogee Hsieh 2022-12-13 21:44 ` Kuogee Hsieh 2022-12-13 22:06 ` Dmitry Baryshkov [this message] 2022-12-13 22:06 ` Dmitry Baryshkov
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