[PULL 0/2] riscv-to-apply queue

[PULL 0/2] riscv-to-apply queue

[Alistair Francis]

The following changes since commit 3944e93af06f06eb07316e0bef46b007573e0309:

  Update version for v8.1.0-rc3 release (2023-08-10 12:49:56 -0700)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230811-3

for you to fetch changes up to b274c2388e9fcde75d60c6e7c7d8f888874b61b7:

  hw/riscv/virt.c: change 'aclint' TCG check (2023-08-11 14:16:26 -0400)

----------------------------------------------------------------
Sixth RISC-V PR for 8.1

This is a last minute PR for RISC-V.

The main goal is to fix
https://gitlab.com/qemu-project/qemu/-/issues/1823
which is a regression that means the aclint option
cannot be enabled.

While we are here we also fixup KVM issue.

 * KVM: fix mvendorid size
 * Fixup aclint check

----------------------------------------------------------------
Daniel Henrique Barboza (2):
      target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()
      hw/riscv/virt.c: change 'aclint' TCG check

 hw/riscv/virt.c    | 20 +++++++++++++-------
 target/riscv/kvm.c |  9 ++++++++-
 2 files changed, 21 insertions(+), 8 deletions(-)

[PULL 1/2] target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()

[Alistair Francis]

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write
a target_ulong val, i.e. a 64 bit field in a 64 bit host.

Given that we're passing a pointer to the mvendorid field, the reg is
reading 64 bits starting from mvendorid and going 32 bits in the next
field, marchid. Here's an example:

$ ./qemu-system-riscv64 -machine virt,accel=kvm -m 2G -smp 1 \
   -cpu rv64,marchid=0xab,mvendorid=0xcd,mimpid=0xef(...)

(inside the guest)
 # cat /proc/cpuinfo
processor	: 0
hart		: 0
isa		: rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc
mmu		: sv57
mvendorid	: 0xab000000cd
marchid		: 0xab
mimpid		: 0xef

'mvendorid' was written as a combination of 0xab (the value from the
adjacent field, marchid) and its intended value 0xcd.

Fix it by assigning cpu->cfg.mvendorid to a target_ulong var 'reg' and
use it as input for kvm_set_one_reg(). Here's the result with this patch
applied and using the same QEMU command line:

 # cat /proc/cpuinfo
processor	: 0
hart		: 0
isa		: rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc
mmu		: sv57
mvendorid	: 0xcd
marchid		: 0xab
mimpid		: 0xef

This bug affects only the generic (rv64) CPUs when running with KVM in a
64 bit env since the 'host' CPU does not allow the machine IDs to be
changed via command line.

Fixes: 1fb5a622f7 ("target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230802180058.281385-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 9d8a8982f9..b1fd2233c0 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -852,12 +852,19 @@ void kvm_arch_init_irq_routing(KVMState *s)
 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
+    target_ulong reg;
     uint64_t id;
     int ret;
 
     id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
                           KVM_REG_RISCV_CONFIG_REG(mvendorid));
-    ret = kvm_set_one_reg(cs, id, &cpu->cfg.mvendorid);
+    /*
+     * cfg.mvendorid is an uint32 but a target_ulong will
+     * be written. Assign it to a target_ulong var to avoid
+     * writing pieces of other cpu->cfg fields in the reg.
+     */
+    reg = cpu->cfg.mvendorid;
+    ret = kvm_set_one_reg(cs, id, &reg);
     if (ret != 0) {
         return ret;
     }
-- 
2.41.0

[PULL 2/2] hw/riscv/virt.c: change 'aclint' TCG check

[Alistair Francis]

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The 'aclint' property is being conditioned with tcg acceleration in
virt_machine_class_init(). But acceleration code starts later than the
class init of the board, meaning that tcg_enabled() will be always be
false during class_init(), and the option is never being declared even
when declaring TCG accel:

$ ./build/qemu-system-riscv64 -M virt,accel=tcg,aclint=on
qemu-system-riscv64: Property 'virt-machine.aclint' not found

Fix it by moving the check from class_init() to machine_init(). Tune the
description to mention that the option is TCG only.

Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Fixes: c0716c81b ("hw/riscv/virt: Restrict ACLINT to TCG")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1823
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230811160224.440697-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d90286dc46..99c4e6314b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1350,6 +1350,11 @@ static void virt_machine_init(MachineState *machine)
         exit(1);
     }
 
+    if (!tcg_enabled() && s->have_aclint) {
+        error_report("'aclint' is only available with TCG acceleration");
+        exit(1);
+    }
+
     /* Initialize sockets */
     mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
     for (i = 0; i < socket_count; i++) {
@@ -1683,13 +1688,14 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
 #endif
 
-    if (tcg_enabled()) {
-        object_class_property_add_bool(oc, "aclint", virt_get_aclint,
-                                       virt_set_aclint);
-        object_class_property_set_description(oc, "aclint",
-                                              "Set on/off to enable/disable "
-                                              "emulating ACLINT devices");
-    }
+
+    object_class_property_add_bool(oc, "aclint", virt_get_aclint,
+                                   virt_set_aclint);
+    object_class_property_set_description(oc, "aclint",
+                                          "(TCG only) Set on/off to "
+                                          "enable/disable emulating "
+                                          "ACLINT devices");
+
     object_class_property_add_str(oc, "aia", virt_get_aia,
                                   virt_set_aia);
     object_class_property_set_description(oc, "aia",
-- 
2.41.0

Re: [PULL 0/2] riscv-to-apply queue

[Richard Henderson]

On 8/11/23 11:24, Alistair Francis wrote:
> The following changes since commit 3944e93af06f06eb07316e0bef46b007573e0309:
> 
>    Update version for v8.1.0-rc3 release (2023-08-10 12:49:56 -0700)
> 
> are available in the Git repository at:
> 
>    https://github.com/alistair23/qemu.git  tags/pull-riscv-to-apply-20230811-3
> 
> for you to fetch changes up to b274c2388e9fcde75d60c6e7c7d8f888874b61b7:
> 
>    hw/riscv/virt.c: change 'aclint' TCG check (2023-08-11 14:16:26 -0400)
> 
> ----------------------------------------------------------------
> Sixth RISC-V PR for 8.1
> 
> This is a last minute PR for RISC-V.
> 
> The main goal is to fix
> https://gitlab.com/qemu-project/qemu/-/issues/1823
> which is a regression that means the aclint option
> cannot be enabled.
> 
> While we are here we also fixup KVM issue.
> 
>   * KVM: fix mvendorid size
>   * Fixup aclint check

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.


r~

Re: [PULL 0/2] riscv-to-apply queue

[Peter Maydell]

On Tue, 14 Mar 2023 at 06:39, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
>
>   Merge tag 'win-socket-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230314
>
> for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:
>
>   Fix incorrect register name in disassembler for fmv,fabs,fneg instructions (2023-03-14 16:36:43 +1000)
>
> ----------------------------------------------------------------
> Seventh RISC-V PR for 8.0
>
> * Fix slli_uw decoding
> * Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM

[PULL 0/2] riscv-to-apply queue

[Alistair Francis]

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:

  Merge tag 'win-socket-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230314

for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:

  Fix incorrect register name in disassembler for fmv,fabs,fneg instructions (2023-03-14 16:36:43 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for 8.0

* Fix slli_uw decoding
* Fix incorrect register name in disassembler for fmv,fabs,fneg instructions

----------------------------------------------------------------
Ivan Klokov (1):
      disas/riscv: Fix slli_uw decoding

Mikhail Tyutin (1):
      Fix incorrect register name in disassembler for fmv,fabs,fneg instructions

 disas/riscv.c | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

Re: [PULL 0/2] riscv-to-apply queue

[Richard Henderson]

On 7/27/22 17:59, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The following changes since commit 7b17a1a841fc2336eba53afade9cadb14bd3dd9a:
> 
>    Update version for v7.1.0-rc0 release (2022-07-26 18:03:16 -0700)
> 
> are available in the Git repository at:
> 
>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220728
> 
> for you to fetch changes up to 54f218363052be210e77d2ada8c0c1e51b3ad6cd:
> 
>    hw/intc: sifive_plic: Fix multi-socket plic configuraiton (2022-07-28 09:08:44 +1000)
> 
> ----------------------------------------------------------------
> Sixth RISC-V PR for QEMU 7.1
> 
> This is a PR to go in for RC1. It fixes a segfault that occurs
> when using multiple sockets on the RISC-V virt board. It also
> includes a small fix to allow both Zmmul and M extensions.
> 
> * Allow both Zmmul and M extension
> * Fix multi-socket plic configuraiton

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.


r~


> 
> ----------------------------------------------------------------
> Atish Patra (1):
>        hw/intc: sifive_plic: Fix multi-socket plic configuraiton
> 
> Palmer Dabbelt (1):
>        RISC-V: Allow both Zmmul and M
> 
>   hw/intc/sifive_plic.c | 4 ++--
>   target/riscv/cpu.c    | 5 -----
>   2 files changed, 2 insertions(+), 7 deletions(-)
> 

[PULL 0/2] riscv-to-apply queue

[Alistair Francis]

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 7b17a1a841fc2336eba53afade9cadb14bd3dd9a:

  Update version for v7.1.0-rc0 release (2022-07-26 18:03:16 -0700)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220728

for you to fetch changes up to 54f218363052be210e77d2ada8c0c1e51b3ad6cd:

  hw/intc: sifive_plic: Fix multi-socket plic configuraiton (2022-07-28 09:08:44 +1000)

----------------------------------------------------------------
Sixth RISC-V PR for QEMU 7.1

This is a PR to go in for RC1. It fixes a segfault that occurs
when using multiple sockets on the RISC-V virt board. It also
includes a small fix to allow both Zmmul and M extensions.

* Allow both Zmmul and M extension
* Fix multi-socket plic configuraiton

----------------------------------------------------------------
Atish Patra (1):
      hw/intc: sifive_plic: Fix multi-socket plic configuraiton

Palmer Dabbelt (1):
      RISC-V: Allow both Zmmul and M

 hw/intc/sifive_plic.c | 4 ++--
 target/riscv/cpu.c    | 5 -----
 2 files changed, 2 insertions(+), 7 deletions(-)

Re: [PULL 0/2] riscv-to-apply queue

[Peter Maydell]

On Fri, 1 Apr 2022 at 00:50, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit d5341e09135b871199073572f53bc11ae9b44897:
>
>   Merge tag 'pull-tcg-20220331' of https://gitlab.com/rth7680/qemu into staging (2022-03-31 18:36:08 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220401
>
> for you to fetch changes up to 8ff8ac63298611c8373b294ec936475b1a33f63f:
>
>   target/riscv: rvv: Add missing early exit condition for whole register load/store (2022-04-01 08:40:55 +1000)
>
> ----------------------------------------------------------------
> Sixth RISC-V PR for QEMU 7.0
>
> This is a last minute RISC-V PR for 7.0.
>
> It includes a fix to avoid leaking no translation TLB entries. This
> incorrectly cached uncachable baremetal entries. This would break Linux
> boot while single stepping. As the fix is pretty straight forward (flush
> the cache more often) it's being pulled in for 7.0.
>
> At the same time I have included a RISC-V vector extension fixup patch.
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.

-- PMM

[PULL 0/2] riscv-to-apply queue

[Alistair Francis]

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit d5341e09135b871199073572f53bc11ae9b44897:

  Merge tag 'pull-tcg-20220331' of https://gitlab.com/rth7680/qemu into staging (2022-03-31 18:36:08 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220401

for you to fetch changes up to 8ff8ac63298611c8373b294ec936475b1a33f63f:

  target/riscv: rvv: Add missing early exit condition for whole register load/store (2022-04-01 08:40:55 +1000)

----------------------------------------------------------------
Sixth RISC-V PR for QEMU 7.0

This is a last minute RISC-V PR for 7.0.

It includes a fix to avoid leaking no translation TLB entries. This
incorrectly cached uncachable baremetal entries. This would break Linux
boot while single stepping. As the fix is pretty straight forward (flush
the cache more often) it's being pulled in for 7.0.

At the same time I have included a RISC-V vector extension fixup patch.

----------------------------------------------------------------
Palmer Dabbelt (1):
      target/riscv: Avoid leaking "no translation" TLB entries

Yueh-Ting (eop) Chen (1):
      target/riscv: rvv: Add missing early exit condition for whole register load/store

 target/riscv/csr.c                      | 14 ++++++++------
 target/riscv/insn_trans/trans_rvv.c.inc |  5 +++++
 2 files changed, 13 insertions(+), 6 deletions(-)

Re: [PULL 0/2] riscv-to-apply queue

[Richard Henderson]

On 11/22/21 7:52 AM, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
> 
>    Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
> 
> are available in the Git repository at:
> 
>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
> 
> for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
> 
>    hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
> 
> ----------------------------------------------------------------
> Seventh RISC-V PR for QEMU 6.2
> 
>   - Deprecate IF_NONE for SiFive OTP
>   - Don't reset SiFive OTP content
> 
> ----------------------------------------------------------------
> Philippe Mathieu-Daudé (1):
>        hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
> 
> Thomas Huth (1):
>        hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
> 
>   docs/about/deprecated.rst |  6 ++++++
>   hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
>   2 files changed, 19 insertions(+), 9 deletions(-)

Applied, thanks.

r~

[PULL 0/2] riscv-to-apply queue

[Alistair Francis]

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:

  Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122

for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:

  hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for QEMU 6.2

 - Deprecate IF_NONE for SiFive OTP
 - Don't reset SiFive OTP content

----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
      hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset

Thomas Huth (1):
      hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE

 docs/about/deprecated.rst |  6 ++++++
 hw/misc/sifive_u_otp.c    | 22 +++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

Re: [PULL 0/2] riscv-to-apply queue

[Richard Henderson]

On 11/17/21 10:20 AM, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The following changes since commit 8d5fcb1990bc64b62c0bc12121fe510940be5664:
> 
>    Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2021-11-17 07:41:08 +0100)
> 
> are available in the Git repository at:
> 
>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211117-1
> 
> for you to fetch changes up to c94c239496256f1f1cb589825d052c2f3e26ebf6:
> 
>    meson.build: Merge riscv32 and riscv64 cpu family (2021-11-17 19:18:22 +1000)
> 
> ----------------------------------------------------------------
> Sixth RISC-V PR for QEMU 6.2
> 
>   - Fix build for riscv hosts
>   - Soft code alphabetically
> 
> ----------------------------------------------------------------
> Bin Meng (1):
>        target/riscv: machine: Sort the .subsections
> 
> Richard Henderson (1):
>        meson.build: Merge riscv32 and riscv64 cpu family
> 
>   meson.build            |  6 ++++
>   target/riscv/machine.c | 92 +++++++++++++++++++++++++-------------------------
>   2 files changed, 52 insertions(+), 46 deletions(-)
> 

Applied, thanks.


r~

[PULL 0/2] riscv-to-apply queue

[Alistair Francis]

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 8d5fcb1990bc64b62c0bc12121fe510940be5664:

  Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2021-11-17 07:41:08 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211117-1

for you to fetch changes up to c94c239496256f1f1cb589825d052c2f3e26ebf6:

  meson.build: Merge riscv32 and riscv64 cpu family (2021-11-17 19:18:22 +1000)

----------------------------------------------------------------
Sixth RISC-V PR for QEMU 6.2

 - Fix build for riscv hosts
 - Soft code alphabetically

----------------------------------------------------------------
Bin Meng (1):
      target/riscv: machine: Sort the .subsections

Richard Henderson (1):
      meson.build: Merge riscv32 and riscv64 cpu family

 meson.build            |  6 ++++
 target/riscv/machine.c | 92 +++++++++++++++++++++++++-------------------------
 2 files changed, 52 insertions(+), 46 deletions(-)

Re: [PULL 0/2] riscv-to-apply queue

[Peter Maydell]

On Sat, 14 Nov 2020 at 05:56, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 5ececc3a0b0086c6168e12f4d032809477b30fe5:
>
>   Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20201113' into staging (2020-11-13 13:40:23 +0000)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201113-1
>
> for you to fetch changes up to deef3d2568a7fbaa62d9bee07708cf3a4dc3ac53:
>
>   intc/ibex_plic: Ensure we don't loose interrupts (2020-11-13 21:43:48 -0800)
>
> ----------------------------------------------------------------
> Two small additional fixes for the Ibex PLIC.
>
> ----------------------------------------------------------------
> Alistair Francis (2):
>       intc/ibex_plic: Fix some typos in the comments
>       intc/ibex_plic: Ensure we don't loose interrupts


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM

[PULL 0/2] riscv-to-apply queue

[Alistair Francis]

The following changes since commit 5ececc3a0b0086c6168e12f4d032809477b30fe5:

  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20201113' into staging (2020-11-13 13:40:23 +0000)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201113-1

for you to fetch changes up to deef3d2568a7fbaa62d9bee07708cf3a4dc3ac53:

  intc/ibex_plic: Ensure we don't loose interrupts (2020-11-13 21:43:48 -0800)

----------------------------------------------------------------
Two small additional fixes for the Ibex PLIC.

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Alistair Francis (2):
      intc/ibex_plic: Fix some typos in the comments
      intc/ibex_plic: Ensure we don't loose interrupts

 include/hw/intc/ibex_plic.h |  1 +
 hw/intc/ibex_plic.c         | 21 ++++++++++++++++++---
 2 files changed, 19 insertions(+), 3 deletions(-)