* [PATCH 0/3] mtd:fsl-quadspi:add support for the flash on LS1021ATWR
@ 2016-01-29 11:41 ` Yunhui Cui
0 siblings, 0 replies; 13+ messages in thread
From: Yunhui Cui @ 2016-01-29 11:41 UTC (permalink / raw)
To: dwmw2, computersforpeace, han.xu
Cc: linux-kernel, linux-mtd, linux-arm-kernel, yao.yuan
This patch set depend on the patch:
{
https://patchwork.ozlabs.org/patch/545926/
LS1021a also support Freescale Quad SPI controller.
Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
selectable for LS1021A SOC hardwares.
}
There is a N25Q128 flash on LS1021ATWR.
This patch test on this flash on LS1021ATWR board.
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 0/3] mtd:fsl-quadspi:add support for the flash on LS1021ATWR @ 2016-01-29 11:41 ` Yunhui Cui 0 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-01-29 11:41 UTC (permalink / raw) To: linux-arm-kernel This patch set depend on the patch: { https://patchwork.ozlabs.org/patch/545926/ LS1021a also support Freescale Quad SPI controller. Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI selectable for LS1021A SOC hardwares. } There is a N25Q128 flash on LS1021ATWR. This patch test on this flash on LS1021ATWR board. ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/3] mtd:fsl-quadspi:use the property fields of SPI-NOR 2016-01-29 11:41 ` Yunhui Cui @ 2016-01-29 11:41 ` Yunhui Cui -1 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-01-29 11:41 UTC (permalink / raw) To: dwmw2, computersforpeace, han.xu Cc: linux-kernel, linux-mtd, linux-arm-kernel, yao.yuan We can get the read/write/erase opcode from the spi nor framework directly. This patch uses the information stored in the SPI-NOR to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by: Yunhui Cui <B56489@freescale.com> --- drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++--------------------------- 1 file changed, 12 insertions(+), 28 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 9ab2b51..517ffe2 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) void __iomem *base = q->iobase; int rxfifo = q->devtype_data->rxfifo; u32 lut_base; - u8 cmd, addrlen, dummy; int i; + struct spi_nor *nor = &q->nor[0]; + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; + u8 read_op = nor->read_opcode; + u8 read_dm = nor->read_dummy; + fsl_qspi_unlock_lut(q); /* Clear all the LUT table */ @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Quad Read */ lut_base = SEQID_QUAD_READ * 4; - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_READ_1_1_4; - addrlen = ADDR24BIT; - dummy = 8; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_READ_1_1_4; - addrlen = ADDR32BIT; - dummy = 8; - } - - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD4, rxfifo), base + QUADSPI_LUT(lut_base + 1)); /* Write enable */ @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Page Program */ lut_base = SEQID_PP * 4; - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_PP; - addrlen = ADDR24BIT; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_PP; - addrlen = ADDR32BIT; - } - - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | + LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Erase a sector */ lut_base = SEQID_SE * 4; - cmd = q->nor[0].erase_opcode; - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; - - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | + LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); /* Erase the whole chip */ -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 1/3] mtd:fsl-quadspi:use the property fields of SPI-NOR @ 2016-01-29 11:41 ` Yunhui Cui 0 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-01-29 11:41 UTC (permalink / raw) To: linux-arm-kernel We can get the read/write/erase opcode from the spi nor framework directly. This patch uses the information stored in the SPI-NOR to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by: Yunhui Cui <B56489@freescale.com> --- drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++--------------------------- 1 file changed, 12 insertions(+), 28 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 9ab2b51..517ffe2 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) void __iomem *base = q->iobase; int rxfifo = q->devtype_data->rxfifo; u32 lut_base; - u8 cmd, addrlen, dummy; int i; + struct spi_nor *nor = &q->nor[0]; + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; + u8 read_op = nor->read_opcode; + u8 read_dm = nor->read_dummy; + fsl_qspi_unlock_lut(q); /* Clear all the LUT table */ @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Quad Read */ lut_base = SEQID_QUAD_READ * 4; - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_READ_1_1_4; - addrlen = ADDR24BIT; - dummy = 8; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_READ_1_1_4; - addrlen = ADDR32BIT; - dummy = 8; - } - - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD4, rxfifo), base + QUADSPI_LUT(lut_base + 1)); /* Write enable */ @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Page Program */ lut_base = SEQID_PP * 4; - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_PP; - addrlen = ADDR24BIT; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_PP; - addrlen = ADDR32BIT; - } - - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | + LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Erase a sector */ lut_base = SEQID_SE * 4; - cmd = q->nor[0].erase_opcode; - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; - - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | + LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); /* Erase the whole chip */ -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/3] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ 2016-01-29 11:41 ` Yunhui Cui @ 2016-01-29 11:41 ` Yunhui Cui -1 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-01-29 11:41 UTC (permalink / raw) To: dwmw2, computersforpeace, han.xu Cc: linux-kernel, linux-mtd, linux-arm-kernel, yao.yuan There are some read modes for flash, such as NORMAL, FAST, QUAD, DDR QUAD. These modes will use the identical lut table base So rename SEQID_QUAD_READ to SEQID_READ. Signed-off-by: Yunhui Cui <B56489@freescale.com> --- drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 517ffe2..9861290 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -193,7 +193,7 @@ #define QUADSPI_LUT_NUM 64 /* SEQID -- we can have 16 seqids at most. */ -#define SEQID_QUAD_READ 0 +#define SEQID_READ 0 #define SEQID_WREN 1 #define SEQID_WRDI 2 #define SEQID_RDSR 3 @@ -386,8 +386,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) for (i = 0; i < QUADSPI_LUT_NUM; i++) qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4); - /* Quad Read */ - lut_base = SEQID_QUAD_READ * 4; + /* Read */ + lut_base = SEQID_READ * 4; qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); @@ -468,7 +468,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { case SPINOR_OP_READ_1_1_4: - return SEQID_QUAD_READ; + return SEQID_READ; case SPINOR_OP_WREN: return SEQID_WREN; case SPINOR_OP_WRDI: -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/3] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ @ 2016-01-29 11:41 ` Yunhui Cui 0 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-01-29 11:41 UTC (permalink / raw) To: linux-arm-kernel There are some read modes for flash, such as NORMAL, FAST, QUAD, DDR QUAD. These modes will use the identical lut table base So rename SEQID_QUAD_READ to SEQID_READ. Signed-off-by: Yunhui Cui <B56489@freescale.com> --- drivers/mtd/spi-nor/fsl-quadspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 517ffe2..9861290 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -193,7 +193,7 @@ #define QUADSPI_LUT_NUM 64 /* SEQID -- we can have 16 seqids at most. */ -#define SEQID_QUAD_READ 0 +#define SEQID_READ 0 #define SEQID_WREN 1 #define SEQID_WRDI 2 #define SEQID_RDSR 3 @@ -386,8 +386,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) for (i = 0; i < QUADSPI_LUT_NUM; i++) qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4); - /* Quad Read */ - lut_base = SEQID_QUAD_READ * 4; + /* Read */ + lut_base = SEQID_READ * 4; qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); @@ -468,7 +468,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { case SPINOR_OP_READ_1_1_4: - return SEQID_QUAD_READ; + return SEQID_READ; case SPINOR_OP_WREN: return SEQID_WREN; case SPINOR_OP_WRDI: -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support 2016-01-29 11:41 ` Yunhui Cui @ 2016-01-29 11:41 ` Yunhui Cui -1 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-01-29 11:41 UTC (permalink / raw) To: dwmw2, computersforpeace, han.xu Cc: linux-kernel, linux-mtd, linux-arm-kernel, yao.yuan The qspi driver add generic fast-read mode for different flash venders, including Micron family. Also add some special operations for Micron flash read/write in spi-nor.c. Signed-off-by: Yunhui Cui <B56489@freescale.com> --- drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ drivers/mtd/spi-nor/spi-nor.c | 6 +++++- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 9861290..fc4451d 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -389,11 +389,21 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Read */ lut_base = SEQID_READ * 4; - qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | - LUT1(FSL_READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); + if (nor->flash_read == SPI_NOR_FAST) { + qspi_writel(q, LUT0(CMD, PAD1, read_op) | + LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD1, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } else if (nor->flash_read == SPI_NOR_QUAD) { + qspi_writel(q, LUT0(CMD, PAD1, read_op) | + LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD4, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } /* Write enable */ lut_base = SEQID_WREN * 4; @@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { case SPINOR_OP_READ_1_1_4: + case SPINOR_OP_READ_FAST: return SEQID_READ; case SPINOR_OP_WREN: return SEQID_WREN; @@ -963,6 +974,7 @@ static int fsl_qspi_probe(struct platform_device *pdev) struct spi_nor *nor; struct mtd_info *mtd; int ret, i = 0; + enum read_mode mode = SPI_NOR_QUAD; q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL); if (!q) @@ -1064,7 +1076,10 @@ static int fsl_qspi_probe(struct platform_device *pdev) /* set the chip address for READID */ fsl_qspi_set_base_addr(q, nor); - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD); + ret = of_property_read_bool(np, "fast-read"); + mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD; + + ret = spi_nor_scan(nor, NULL, mode); if (ret) goto mutex_failed; diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | + SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || JEDEC_MFR(info) == SNOR_MFR_INTEL || + JEDEC_MFR(info) == SNOR_MFR_MICRON || JEDEC_MFR(info) == SNOR_MFR_SST) { write_enable(nor); write_sr(nor, 0); @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) nor->flash_read = SPI_NOR_QUAD; } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { nor->flash_read = SPI_NOR_DUAL; + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { + nor->flash_read = SPI_NOR_FAST; } /* Default commands */ -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support @ 2016-01-29 11:41 ` Yunhui Cui 0 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-01-29 11:41 UTC (permalink / raw) To: linux-arm-kernel The qspi driver add generic fast-read mode for different flash venders, including Micron family. Also add some special operations for Micron flash read/write in spi-nor.c. Signed-off-by: Yunhui Cui <B56489@freescale.com> --- drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ drivers/mtd/spi-nor/spi-nor.c | 6 +++++- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 9861290..fc4451d 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -389,11 +389,21 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Read */ lut_base = SEQID_READ * 4; - qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | - LUT1(FSL_READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); + if (nor->flash_read == SPI_NOR_FAST) { + qspi_writel(q, LUT0(CMD, PAD1, read_op) | + LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD1, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } else if (nor->flash_read == SPI_NOR_QUAD) { + qspi_writel(q, LUT0(CMD, PAD1, read_op) | + LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | + LUT1(FSL_READ, PAD4, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } /* Write enable */ lut_base = SEQID_WREN * 4; @@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { case SPINOR_OP_READ_1_1_4: + case SPINOR_OP_READ_FAST: return SEQID_READ; case SPINOR_OP_WREN: return SEQID_WREN; @@ -963,6 +974,7 @@ static int fsl_qspi_probe(struct platform_device *pdev) struct spi_nor *nor; struct mtd_info *mtd; int ret, i = 0; + enum read_mode mode = SPI_NOR_QUAD; q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL); if (!q) @@ -1064,7 +1076,10 @@ static int fsl_qspi_probe(struct platform_device *pdev) /* set the chip address for READID */ fsl_qspi_set_base_addr(q, nor); - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD); + ret = of_property_read_bool(np, "fast-read"); + mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD; + + ret = spi_nor_scan(nor, NULL, mode); if (ret) goto mutex_failed; diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | + SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || JEDEC_MFR(info) == SNOR_MFR_INTEL || + JEDEC_MFR(info) == SNOR_MFR_MICRON || JEDEC_MFR(info) == SNOR_MFR_SST) { write_enable(nor); write_sr(nor, 0); @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) nor->flash_read = SPI_NOR_QUAD; } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { nor->flash_read = SPI_NOR_DUAL; + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { + nor->flash_read = SPI_NOR_FAST; } /* Default commands */ -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support 2016-01-29 11:41 ` Yunhui Cui @ 2016-01-29 14:51 ` Cyrille Pitchen -1 siblings, 0 replies; 13+ messages in thread From: Cyrille Pitchen @ 2016-01-29 14:51 UTC (permalink / raw) To: Yunhui Cui, dwmw2, computersforpeace, han.xu Cc: linux-mtd, linux-kernel, linux-arm-kernel, yao.yuan Hi Yunhui, Le 29/01/2016 12:41, Yunhui Cui a écrit : > The qspi driver add generic fast-read mode for different > flash venders, including Micron family. Also add some special > operations for Micron flash read/write in spi-nor.c. > > Signed-off-by: Yunhui Cui <B56489@freescale.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ > drivers/mtd/spi-nor/spi-nor.c | 6 +++++- > 2 files changed, 26 insertions(+), 7 deletions(-) > [...] > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index ed0c19c..79a025c 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | > + SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, This modification looks wrong. First SPI_NOR_FAST is part of enum read_mode (from spi-nor.h) and is not intended to be used as a flag, unlike SPI_NOR_QUAD_READ (defined in spi-nor.c just below the flags field of struct flash_info). Also, creating a new flag to choose between the Read and the Fast Read commands is not needed: see my last comment below. > @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > > if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || > JEDEC_MFR(info) == SNOR_MFR_INTEL || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > JEDEC_MFR(info) == SNOR_MFR_SST) { > write_enable(nor); > write_sr(nor, 0); This update is not related with the support of fast-read mode, it deals with the write protection. Hence it should be moved into a dedicated patch. Also be careful as some bits of the Status Register are non-volatile on Micron memories. This modification may change their values but I guess you only want to clear the write enable/disable (7) bit. > @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > nor->flash_read = SPI_NOR_QUAD; > } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { > nor->flash_read = SPI_NOR_DUAL; > + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { > + nor->flash_read = SPI_NOR_FAST; > } > > /* Default commands */ > The spi-nor framework already checks the "m25p,fast-read" DT property to choose between the Read (0x03) and Fast Read (0x0b) command. So the fsl-quadspi.c driver should rely on this existing property to choose which of SPI_NOR_FAST or SPI_NOR_QUAD is used as the mode argument of spi_nor_scan(). As long as mode is neither SPI_NOR_QUAD nor SPI_NOR_DUAL, the choice of the read op code is done according to whether the "m25p,fast-read" DT property is set or not. Best regards, Cyrille ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support @ 2016-01-29 14:51 ` Cyrille Pitchen 0 siblings, 0 replies; 13+ messages in thread From: Cyrille Pitchen @ 2016-01-29 14:51 UTC (permalink / raw) To: linux-arm-kernel Hi Yunhui, Le 29/01/2016 12:41, Yunhui Cui a ?crit : > The qspi driver add generic fast-read mode for different > flash venders, including Micron family. Also add some special > operations for Micron flash read/write in spi-nor.c. > > Signed-off-by: Yunhui Cui <B56489@freescale.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ > drivers/mtd/spi-nor/spi-nor.c | 6 +++++- > 2 files changed, 26 insertions(+), 7 deletions(-) > [...] > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index ed0c19c..79a025c 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | > + SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, This modification looks wrong. First SPI_NOR_FAST is part of enum read_mode (from spi-nor.h) and is not intended to be used as a flag, unlike SPI_NOR_QUAD_READ (defined in spi-nor.c just below the flags field of struct flash_info). Also, creating a new flag to choose between the Read and the Fast Read commands is not needed: see my last comment below. > @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > > if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || > JEDEC_MFR(info) == SNOR_MFR_INTEL || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > JEDEC_MFR(info) == SNOR_MFR_SST) { > write_enable(nor); > write_sr(nor, 0); This update is not related with the support of fast-read mode, it deals with the write protection. Hence it should be moved into a dedicated patch. Also be careful as some bits of the Status Register are non-volatile on Micron memories. This modification may change their values but I guess you only want to clear the write enable/disable (7) bit. > @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > nor->flash_read = SPI_NOR_QUAD; > } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { > nor->flash_read = SPI_NOR_DUAL; > + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { > + nor->flash_read = SPI_NOR_FAST; > } > > /* Default commands */ > The spi-nor framework already checks the "m25p,fast-read" DT property to choose between the Read (0x03) and Fast Read (0x0b) command. So the fsl-quadspi.c driver should rely on this existing property to choose which of SPI_NOR_FAST or SPI_NOR_QUAD is used as the mode argument of spi_nor_scan(). As long as mode is neither SPI_NOR_QUAD nor SPI_NOR_DUAL, the choice of the read op code is done according to whether the "m25p,fast-read" DT property is set or not. Best regards, Cyrille ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support 2016-01-29 14:51 ` Cyrille Pitchen (?) @ 2016-02-01 11:23 ` Yunhui Cui -1 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-02-01 11:23 UTC (permalink / raw) To: Cyrille Pitchen, Yunhui Cui, dwmw2, computersforpeace, han.xu Cc: linux-mtd, linux-kernel, linux-arm-kernel, Yao Yuan Hi Cyrille, Thanks for your suggestions very much, I'll resend version 2 patch set. Best Regards Yunhui -----Original Message----- From: Cyrille Pitchen [mailto:cyrille.pitchen@atmel.com] Sent: Friday, January 29, 2016 10:51 PM To: Yunhui Cui; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@freescale.com Cc: linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Yao Yuan Subject: Re: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Hi Yunhui, Le 29/01/2016 12:41, Yunhui Cui a écrit : > The qspi driver add generic fast-read mode for different flash > venders, including Micron family. Also add some special operations for > Micron flash read/write in spi-nor.c. > > Signed-off-by: Yunhui Cui <B56489@freescale.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ > drivers/mtd/spi-nor/spi-nor.c | 6 +++++- > 2 files changed, 26 insertions(+), 7 deletions(-) > [...] > diff --git a/drivers/mtd/spi-nor/spi-nor.c > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | > + SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | > USE_FSR | SPI_NOR_QUAD_READ) }, This modification looks wrong. First SPI_NOR_FAST is part of enum read_mode (from spi-nor.h) and is not intended to be used as a flag, unlike SPI_NOR_QUAD_READ (defined in spi-nor.c just below the flags field of struct flash_info). Also, creating a new flag to choose between the Read and the Fast Read commands is not needed: see my last comment below. > @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char > *name, enum read_mode mode) > > if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || > JEDEC_MFR(info) == SNOR_MFR_INTEL || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > JEDEC_MFR(info) == SNOR_MFR_SST) { > write_enable(nor); > write_sr(nor, 0); This update is not related with the support of fast-read mode, it deals with the write protection. Hence it should be moved into a dedicated patch. Also be careful as some bits of the Status Register are non-volatile on Micron memories. This modification may change their values but I guess you only want to clear the write enable/disable (7) bit. > @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > nor->flash_read = SPI_NOR_QUAD; > } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { > nor->flash_read = SPI_NOR_DUAL; > + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { > + nor->flash_read = SPI_NOR_FAST; > } > > /* Default commands */ > The spi-nor framework already checks the "m25p,fast-read" DT property to choose between the Read (0x03) and Fast Read (0x0b) command. So the fsl-quadspi.c driver should rely on this existing property to choose which of SPI_NOR_FAST or SPI_NOR_QUAD is used as the mode argument of spi_nor_scan(). As long as mode is neither SPI_NOR_QUAD nor SPI_NOR_DUAL, the choice of the read op code is done according to whether the "m25p,fast-read" DT property is set or not. Best regards, Cyrille ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support @ 2016-02-01 11:23 ` Yunhui Cui 0 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-02-01 11:23 UTC (permalink / raw) To: linux-arm-kernel Hi Cyrille, Thanks for your suggestions very much, I'll resend version 2 patch set. Best Regards Yunhui -----Original Message----- From: Cyrille Pitchen [mailto:cyrille.pitchen at atmel.com] Sent: Friday, January 29, 2016 10:51 PM To: Yunhui Cui; dwmw2 at infradead.org; computersforpeace at gmail.com; han.xu at freescale.com Cc: linux-mtd at lists.infradead.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Yao Yuan Subject: Re: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Hi Yunhui, Le 29/01/2016 12:41, Yunhui Cui a ?crit : > The qspi driver add generic fast-read mode for different flash > venders, including Micron family. Also add some special operations for > Micron flash read/write in spi-nor.c. > > Signed-off-by: Yunhui Cui <B56489@freescale.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ > drivers/mtd/spi-nor/spi-nor.c | 6 +++++- > 2 files changed, 26 insertions(+), 7 deletions(-) > [...] > diff --git a/drivers/mtd/spi-nor/spi-nor.c > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | > + SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | > USE_FSR | SPI_NOR_QUAD_READ) }, This modification looks wrong. First SPI_NOR_FAST is part of enum read_mode (from spi-nor.h) and is not intended to be used as a flag, unlike SPI_NOR_QUAD_READ (defined in spi-nor.c just below the flags field of struct flash_info). Also, creating a new flag to choose between the Read and the Fast Read commands is not needed: see my last comment below. > @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char > *name, enum read_mode mode) > > if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || > JEDEC_MFR(info) == SNOR_MFR_INTEL || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > JEDEC_MFR(info) == SNOR_MFR_SST) { > write_enable(nor); > write_sr(nor, 0); This update is not related with the support of fast-read mode, it deals with the write protection. Hence it should be moved into a dedicated patch. Also be careful as some bits of the Status Register are non-volatile on Micron memories. This modification may change their values but I guess you only want to clear the write enable/disable (7) bit. > @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > nor->flash_read = SPI_NOR_QUAD; > } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { > nor->flash_read = SPI_NOR_DUAL; > + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { > + nor->flash_read = SPI_NOR_FAST; > } > > /* Default commands */ > The spi-nor framework already checks the "m25p,fast-read" DT property to choose between the Read (0x03) and Fast Read (0x0b) command. So the fsl-quadspi.c driver should rely on this existing property to choose which of SPI_NOR_FAST or SPI_NOR_QUAD is used as the mode argument of spi_nor_scan(). As long as mode is neither SPI_NOR_QUAD nor SPI_NOR_DUAL, the choice of the read op code is done according to whether the "m25p,fast-read" DT property is set or not. Best regards, Cyrille ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support @ 2016-02-01 11:23 ` Yunhui Cui 0 siblings, 0 replies; 13+ messages in thread From: Yunhui Cui @ 2016-02-01 11:23 UTC (permalink / raw) To: Cyrille Pitchen, Yunhui Cui, dwmw2, computersforpeace, han.xu Cc: linux-mtd, linux-kernel, linux-arm-kernel, Yao Yuan Hi Cyrille, Thanks for your suggestions very much, I'll resend version 2 patch set. Best Regards Yunhui -----Original Message----- From: Cyrille Pitchen [mailto:cyrille.pitchen@atmel.com] Sent: Friday, January 29, 2016 10:51 PM To: Yunhui Cui; dwmw2@infradead.org; computersforpeace@gmail.com; han.xu@freescale.com Cc: linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Yao Yuan Subject: Re: [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Hi Yunhui, Le 29/01/2016 12:41, Yunhui Cui a écrit : > The qspi driver add generic fast-read mode for different flash > venders, including Micron family. Also add some special operations for > Micron flash read/write in spi-nor.c. > > Signed-off-by: Yunhui Cui <B56489@freescale.com> > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 27 +++++++++++++++++++++------ > drivers/mtd/spi-nor/spi-nor.c | 6 +++++- > 2 files changed, 26 insertions(+), 7 deletions(-) > [...] > diff --git a/drivers/mtd/spi-nor/spi-nor.c > b/drivers/mtd/spi-nor/spi-nor.c index ed0c19c..79a025c 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -763,7 +763,8 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, > + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_FAST | > + SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | > USE_FSR | SPI_NOR_QUAD_READ) }, This modification looks wrong. First SPI_NOR_FAST is part of enum read_mode (from spi-nor.h) and is not intended to be used as a flag, unlike SPI_NOR_QUAD_READ (defined in spi-nor.c just below the flags field of struct flash_info). Also, creating a new flag to choose between the Read and the Fast Read commands is not needed: see my last comment below. > @@ -1233,6 +1234,7 @@ int spi_nor_scan(struct spi_nor *nor, const char > *name, enum read_mode mode) > > if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || > JEDEC_MFR(info) == SNOR_MFR_INTEL || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > JEDEC_MFR(info) == SNOR_MFR_SST) { > write_enable(nor); > write_sr(nor, 0); This update is not related with the support of fast-read mode, it deals with the write protection. Hence it should be moved into a dedicated patch. Also be careful as some bits of the Status Register are non-volatile on Micron memories. This modification may change their values but I guess you only want to clear the write enable/disable (7) bit. > @@ -1317,6 +1319,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > nor->flash_read = SPI_NOR_QUAD; > } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { > nor->flash_read = SPI_NOR_DUAL; > + } else if (mode == SPI_NOR_FAST && info->flags & SPI_NOR_FAST) { > + nor->flash_read = SPI_NOR_FAST; > } > > /* Default commands */ > The spi-nor framework already checks the "m25p,fast-read" DT property to choose between the Read (0x03) and Fast Read (0x0b) command. So the fsl-quadspi.c driver should rely on this existing property to choose which of SPI_NOR_FAST or SPI_NOR_QUAD is used as the mode argument of spi_nor_scan(). As long as mode is neither SPI_NOR_QUAD nor SPI_NOR_DUAL, the choice of the read op code is done according to whether the "m25p,fast-read" DT property is set or not. Best regards, Cyrille ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2016-02-01 11:55 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-01-29 11:41 [PATCH 0/3] mtd:fsl-quadspi:add support for the flash on LS1021ATWR Yunhui Cui 2016-01-29 11:41 ` Yunhui Cui 2016-01-29 11:41 ` [PATCH 1/3] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui 2016-01-29 11:41 ` Yunhui Cui 2016-01-29 11:41 ` [PATCH 2/3] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ Yunhui Cui 2016-01-29 11:41 ` Yunhui Cui 2016-01-29 11:41 ` [PATCH 3/3] mtd:spi-nor:fsl-quadspi:Add fast-read mode support Yunhui Cui 2016-01-29 11:41 ` Yunhui Cui 2016-01-29 14:51 ` Cyrille Pitchen 2016-01-29 14:51 ` Cyrille Pitchen 2016-02-01 11:23 ` Yunhui Cui 2016-02-01 11:23 ` Yunhui Cui 2016-02-01 11:23 ` Yunhui Cui
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