RE: [PATCH 13/15] ARM: DTS: AM33XX: Add nodes for OCMCRAM and Mailbox

["Bedia, Vaibhav" <vaibhav.bedia@ti.com>]

On Tue, Nov 06, 2012 at 03:15:10, Shilimkar, Santosh wrote:
> On Tuesday 06 November 2012 02:49 AM, Santosh Shilimkar wrote:
> > On Tuesday 06 November 2012 12:59 AM, Kevin Hilman wrote:
> >> "Bedia, Vaibhav" <vaibhav.bedia@ti.com> writes:
> >>
> >>> On Mon, Nov 05, 2012 at 20:23:11, Shilimkar, Santosh wrote:
> >>> [...]
> >>>>>
> >>>> On OMAP the OCMC RAM is always clocked and doesn't need any special
> >>>> clock enable. CM_L3_2_OCMC_RAM_CLKCTRL module mode field is read only.
> >>>> Isn't it same on AMXX ?
> >>>>
> >>>
> >>> On AM33xx, OCMC RAM is in PER domain and the corresponding CLKCLTR
> >>> module
> >>> mode fields are r/w. OCMC RAM needs to be disabled as part of the
> >>> DeepSleep0
> >>> entry to let PER domain transition.
> >>
> >> After DeepSleep0, the ROM code is being given an address in OCMC RAM to
> >> jump to.  If OCMC RAM is disabled as part of suspend, this means that
> >> OCMC RAM contents are maintained even though PER domain transitions?
> >>
> >> If so, that needs to be more clearly documented.
> >>
> > Thats very good point. How does OCMC RAM retains the contents without
> > clock ?
> >
> Ignore the question. I figured out from other patch changelog the OCMC
> RAM supports retention. Please have that clearly captured in
> change log.
> 

Yes, OCMC RAM support retention. Will document that here also.

Regards,
Vaibhav