From: Sunil Kovvuri <sunil.kovvuri@gmail.com> To: Arnd Bergmann <arnd@arndb.de> Cc: LAKML <linux-arm-kernel@lists.infradead.org>, Robert Richter <rric@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, linux-pci <linux-pci@vger.kernel.org>, Liviu Dudau <liviu.dudau@arm.com>, LKML <linux-kernel@vger.kernel.org>, Robert Richter <rrichter@cavium.com>, Sunil Goutham <sgoutham@cavium.com> Subject: Re: [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings Date: Thu, 25 Sep 2014 00:37:00 +0530 [thread overview] Message-ID: <CA+sq2CcXCVrk=fxH79n88ZJj5fBQmbyhnzj08qHNO8EmpZT1Yg@mail.gmail.com> (raw) In-Reply-To: <3414852.SWQ9rRcUDx@wuerfel> On Thu, Sep 25, 2014 at 12:04 AM, Arnd Bergmann <arnd@arndb.de> wrote: > On Wednesday 24 September 2014 23:34:04 Sunil Kovvuri wrote: >> On Wed, Sep 24, 2014 at 9:36 PM, Arnd Bergmann <arnd@arndb.de> wrote: >> > On Wednesday 24 September 2014 17:37:45 Robert Richter wrote: >> >> + compatible = "cavium,thunder-pcie"; >> >> + device_type = "pci"; >> >> + msi-parent = <&its>; >> >> + bus-range = <0 255>; >> >> + #size-cells = <2>; >> >> + #address-cells = <3>; >> >> + reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ >> >> + ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>, /* mem ranges */ >> >> + <0x03000000 0x8300 0x00000000 0x8300 0x00000000 0x80 0x00000000>, >> >> + <0x03000000 0x87e0 0x00000000 0x87e0 0x00000000 0x01 0x00000000>; >> >> + }; >> > >> > If you claim the entire 0-255 bus range, I think you should also >> > specify a domain, otherwise it's not predictable which domain you >> > get. >> > >> > The interrupt-map and interrupt-map-mask properties are required for PCI, >> > otherwise you can't do LSI interrupts. >> >> This PCI controller supports only MSIx interrupts which are edge triggered. > > Interesting, so it's not PCI compliant then? I assume this will be fixed > in the production version of the silicon, right? > > Having no support for interrupts mean that the majority of PCI device drivers > will fail. This controller is for on-board PCI devices and all of them do support MSIx interrupts. > >> > If your hardware can support it, you should also list I/O space and prefetchable >> > memory spaces. Can you explain why you have multiple non-prefetchable ranges? >> >> Our hardware is an ECAM based host controller and doesn't support I/O >> and prefetchable memory spaces. >> All on-board PCI devices connected to this PCI controller have fixed resources >> and doesn't have to be allocated/reassigned. Some of these devices are >> SRIOV based. > > I think you need to mark the ones that are nonrelocatable with flag > 0x80000000, otherwise the PCI core might decide to reassign them. Is this flag part of DT pci node properties ? I am using IORESOURCE_PCI_FIXED flag. Its there in other patches of the same series. > >> Kernel's SRIOV (pci/iov.c) is expecting 'resource->parent' hierarchy >> to be set, otherwise doesn't >> enable SRIOV device. So, here multiple non-prefetchable ranges of root bus >> aid in resource claiming and setting res->parent hierarchy. > > I don't understand. Isn't that just a bug in the code that you are working > around with the DT. Have you tried fixing the code instead? I tried but wasn't sure if its going to impact existing SRIOV devices. Will have a deeper look again . > >> We do call "pci_claim_resource" in controller driver code. >> "[PATCH 1/6] pci, thunder: Add support for Thunder PCIe host controller." > > My guess is that you are using the wrong interface here. Isn't the normal > request_resource() in the host driver enough? Isn't that host driver calls "request_resource" only for resources of root port. i.e requesting from iomem_resource/ioport_resource. Here i am referring to SRIOV devices enumerated upon scan of root port. > > Arnd
WARNING: multiple messages have this Message-ID (diff)
From: sunil.kovvuri@gmail.com (Sunil Kovvuri) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings Date: Thu, 25 Sep 2014 00:37:00 +0530 [thread overview] Message-ID: <CA+sq2CcXCVrk=fxH79n88ZJj5fBQmbyhnzj08qHNO8EmpZT1Yg@mail.gmail.com> (raw) In-Reply-To: <3414852.SWQ9rRcUDx@wuerfel> On Thu, Sep 25, 2014 at 12:04 AM, Arnd Bergmann <arnd@arndb.de> wrote: > On Wednesday 24 September 2014 23:34:04 Sunil Kovvuri wrote: >> On Wed, Sep 24, 2014 at 9:36 PM, Arnd Bergmann <arnd@arndb.de> wrote: >> > On Wednesday 24 September 2014 17:37:45 Robert Richter wrote: >> >> + compatible = "cavium,thunder-pcie"; >> >> + device_type = "pci"; >> >> + msi-parent = <&its>; >> >> + bus-range = <0 255>; >> >> + #size-cells = <2>; >> >> + #address-cells = <3>; >> >> + reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ >> >> + ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>, /* mem ranges */ >> >> + <0x03000000 0x8300 0x00000000 0x8300 0x00000000 0x80 0x00000000>, >> >> + <0x03000000 0x87e0 0x00000000 0x87e0 0x00000000 0x01 0x00000000>; >> >> + }; >> > >> > If you claim the entire 0-255 bus range, I think you should also >> > specify a domain, otherwise it's not predictable which domain you >> > get. >> > >> > The interrupt-map and interrupt-map-mask properties are required for PCI, >> > otherwise you can't do LSI interrupts. >> >> This PCI controller supports only MSIx interrupts which are edge triggered. > > Interesting, so it's not PCI compliant then? I assume this will be fixed > in the production version of the silicon, right? > > Having no support for interrupts mean that the majority of PCI device drivers > will fail. This controller is for on-board PCI devices and all of them do support MSIx interrupts. > >> > If your hardware can support it, you should also list I/O space and prefetchable >> > memory spaces. Can you explain why you have multiple non-prefetchable ranges? >> >> Our hardware is an ECAM based host controller and doesn't support I/O >> and prefetchable memory spaces. >> All on-board PCI devices connected to this PCI controller have fixed resources >> and doesn't have to be allocated/reassigned. Some of these devices are >> SRIOV based. > > I think you need to mark the ones that are nonrelocatable with flag > 0x80000000, otherwise the PCI core might decide to reassign them. Is this flag part of DT pci node properties ? I am using IORESOURCE_PCI_FIXED flag. Its there in other patches of the same series. > >> Kernel's SRIOV (pci/iov.c) is expecting 'resource->parent' hierarchy >> to be set, otherwise doesn't >> enable SRIOV device. So, here multiple non-prefetchable ranges of root bus >> aid in resource claiming and setting res->parent hierarchy. > > I don't understand. Isn't that just a bug in the code that you are working > around with the DT. Have you tried fixing the code instead? I tried but wasn't sure if its going to impact existing SRIOV devices. Will have a deeper look again . > >> We do call "pci_claim_resource" in controller driver code. >> "[PATCH 1/6] pci, thunder: Add support for Thunder PCIe host controller." > > My guess is that you are using the wrong interface here. Isn't the normal > request_resource() in the host driver enough? Isn't that host driver calls "request_resource" only for resources of root port. i.e requesting from iomem_resource/ioport_resource. Here i am referring to SRIOV devices enumerated upon scan of root port. > > Arnd
next prev parent reply other threads:[~2014-09-24 19:07 UTC|newest] Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-09-24 15:37 [PATCH 0/6] pci, thunder: Add Cavium Thunder PCIe host controller Robert Richter 2014-09-24 15:37 ` Robert Richter 2014-09-24 15:37 ` [PATCH 1/6] pci, thunder: Add support for " Robert Richter 2014-09-24 15:37 ` Robert Richter 2014-09-24 15:37 ` Robert Richter 2014-09-24 16:12 ` Arnd Bergmann 2014-09-24 16:12 ` Arnd Bergmann 2014-09-24 16:49 ` Will Deacon 2014-09-24 16:49 ` Will Deacon 2014-09-24 16:49 ` Will Deacon 2014-09-30 9:14 ` Sunil Kovvuri 2014-09-30 9:14 ` Sunil Kovvuri 2014-09-30 9:14 ` Sunil Kovvuri 2014-09-24 15:37 ` [PATCH 2/6] GICv3: Add ITS entry to THUNDER dts Robert Richter 2014-09-24 15:37 ` Robert Richter 2014-09-24 15:37 ` Robert Richter 2015-06-25 23:19 ` Chalamarla, Tirumalesh 2015-06-25 23:19 ` Chalamarla, Tirumalesh 2015-06-25 23:19 ` Chalamarla, Tirumalesh 2015-06-25 23:19 ` Chalamarla, Tirumalesh 2015-06-26 9:00 ` Marc Zyngier 2015-06-26 9:00 ` Marc Zyngier 2015-06-26 9:00 ` Marc Zyngier 2014-09-24 15:37 ` [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings Robert Richter 2014-09-24 15:37 ` Robert Richter 2014-09-24 16:06 ` Arnd Bergmann 2014-09-24 16:06 ` Arnd Bergmann 2014-09-24 18:04 ` Sunil Kovvuri 2014-09-24 18:04 ` Sunil Kovvuri 2014-09-24 18:34 ` Arnd Bergmann 2014-09-24 18:34 ` Arnd Bergmann 2014-09-24 18:34 ` Arnd Bergmann 2014-09-24 19:07 ` Sunil Kovvuri [this message] 2014-09-24 19:07 ` Sunil Kovvuri 2014-09-25 7:31 ` Arnd Bergmann 2014-09-25 7:31 ` Arnd Bergmann 2014-09-25 16:16 ` Bjorn Helgaas 2014-09-25 16:16 ` Bjorn Helgaas 2014-09-25 19:26 ` Arnd Bergmann 2014-09-25 19:26 ` Arnd Bergmann 2014-09-25 20:10 ` Bjorn Helgaas 2014-09-25 20:10 ` Bjorn Helgaas 2014-09-25 20:10 ` Bjorn Helgaas 2014-09-25 20:22 ` Arnd Bergmann 2014-09-25 20:22 ` Arnd Bergmann 2014-09-25 20:22 ` Arnd Bergmann 2014-09-25 20:49 ` Bjorn Helgaas 2014-09-25 20:49 ` Bjorn Helgaas 2014-09-26 18:26 ` Rob Herring 2014-09-26 18:26 ` Rob Herring 2014-09-26 18:26 ` Rob Herring 2014-09-30 9:11 ` Sunil Kovvuri 2014-09-30 9:11 ` Sunil Kovvuri 2014-09-30 9:11 ` Sunil Kovvuri 2014-10-07 14:27 ` Robert Richter 2014-10-07 14:27 ` Robert Richter 2014-10-07 14:27 ` Robert Richter 2014-10-07 15:01 ` Liviu Dudau 2014-10-07 15:01 ` Liviu Dudau 2014-10-07 15:01 ` Liviu Dudau 2014-10-07 15:01 ` Liviu Dudau 2014-10-08 8:49 ` Robert Richter 2014-10-08 8:49 ` Robert Richter 2014-10-08 8:49 ` Robert Richter 2014-10-08 16:44 ` Liviu Dudau 2014-10-08 16:44 ` Liviu Dudau 2014-10-08 16:44 ` Liviu Dudau 2014-10-09 6:23 ` Robert Richter 2014-10-09 6:23 ` Robert Richter 2014-10-09 6:23 ` Robert Richter 2014-10-09 6:23 ` Robert Richter 2014-09-24 15:37 ` [PATCH 4/6] pci, thunder: Document " Robert Richter 2014-09-24 15:37 ` Robert Richter 2014-09-24 15:37 ` [PATCH 5/6] arm64, defconfig: Enable PCI Robert Richter 2014-09-24 15:37 ` Robert Richter 2014-09-24 16:14 ` Arnd Bergmann 2014-09-24 16:14 ` Arnd Bergmann 2014-09-24 16:26 ` Robert Richter 2014-09-24 16:26 ` Robert Richter 2014-09-24 17:10 ` Catalin Marinas 2014-09-24 17:10 ` Catalin Marinas 2014-09-24 17:10 ` Catalin Marinas 2014-09-24 18:40 ` Arnd Bergmann 2014-09-24 18:40 ` Arnd Bergmann 2014-09-24 18:40 ` Arnd Bergmann 2014-09-25 9:35 ` Catalin Marinas 2014-09-25 9:35 ` Catalin Marinas 2014-09-25 9:35 ` Catalin Marinas 2014-09-25 10:45 ` Arnd Bergmann 2014-09-25 10:45 ` Arnd Bergmann 2014-09-25 10:45 ` Arnd Bergmann 2014-09-24 15:37 ` [PATCH 6/6] pci, thunder: Enable Cavium Thunder PCIe host controller Robert Richter 2014-09-24 15:37 ` Robert Richter 2014-09-24 17:12 ` Catalin Marinas 2014-09-24 17:12 ` Catalin Marinas 2014-09-24 17:12 ` Catalin Marinas
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