* [PATCH v2 0/3] support subsets of virtual memory extension
@ 2021-12-31 8:09 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2021-12-31 8:09 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
Specification:
https://github.com/riscv/virtual-memory/tree/main/specs
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v2
To test this implementation, specify cpu argument with 'x-svinval=true,x-svnapot=true,x-svpbmt=true'.
This implementation can pass the riscv-tests for rv64ssvnapot.
v2:
* add extension check for svnapot and svpbmt
Weiwei Li (3):
target/riscv: add support for svnapot extension
target/riscv: add support for svinval extension
target/riscv: add support for svpbmt extension
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 4 ++
target/riscv/cpu_helper.c | 27 ++++++--
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
7 files changed, 116 insertions(+), 4 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/3] target/riscv: add support for svnapot extension
2021-12-31 8:09 ` Weiwei Li
@ 2021-12-31 8:09 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2021-12-31 8:09 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 20 ++++++++++++++++----
4 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6ef3314bce..cbcb7f522b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+ DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index dc10f27093..1fbbde28c6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -315,6 +315,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 1e31f4d35f..1156c941cb 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -483,6 +483,7 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_N 0x8000000000000000 /* NAPOT translation */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 10f3baba53..e044153986 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,9 +619,12 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = pte >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
- if (!(pte & PTE_V)) {
+ RISCVCPU *cpu = env_archcpu(env);
+ if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+ return TRANSLATE_FAIL;
+ } else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
@@ -699,8 +702,17 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
- *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
- (addr & ~TARGET_PAGE_MASK);
+
+ int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
+ if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
+ (napot_bits != 0 && napot_bits != 4)) {
+ return TRANSLATE_FAIL;
+ }
+
+ *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << ptshift) - 1))
+ ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 1/3] target/riscv: add support for svnapot extension
@ 2021-12-31 8:09 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2021-12-31 8:09 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 20 ++++++++++++++++----
4 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6ef3314bce..cbcb7f522b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+ DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index dc10f27093..1fbbde28c6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -315,6 +315,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 1e31f4d35f..1156c941cb 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -483,6 +483,7 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_N 0x8000000000000000 /* NAPOT translation */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 10f3baba53..e044153986 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,9 +619,12 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = pte >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
- if (!(pte & PTE_V)) {
+ RISCVCPU *cpu = env_archcpu(env);
+ if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+ return TRANSLATE_FAIL;
+ } else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
@@ -699,8 +702,17 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
- *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
- (addr & ~TARGET_PAGE_MASK);
+
+ int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
+ if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
+ (napot_bits != 0 && napot_bits != 4)) {
+ return TRANSLATE_FAIL;
+ }
+
+ *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << ptshift) - 1))
+ ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 1/3] target/riscv: add support for svnapot extension
2021-12-31 8:09 ` Weiwei Li
@ 2022-01-01 13:17 ` Anup Patel
-1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-01-01 13:17 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟),
open list:RISC-V, wangjunqiang, Bin Meng, QEMU Developers,
Alistair Francis, Palmer Dabbelt
On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 20 ++++++++++++++++----
> 4 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6ef3314bce..cbcb7f522b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> + DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
Please drop the "x-" prefix here as well. The Svnapot extension is
already ratified.
Regards,
Anup
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index dc10f27093..1fbbde28c6 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -315,6 +315,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_svnapot;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 1e31f4d35f..1156c941cb 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -483,6 +483,7 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_N 0x8000000000000000 /* NAPOT translation */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 10f3baba53..e044153986 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,9 +619,12 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = pte >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
>
> - if (!(pte & PTE_V)) {
> + RISCVCPU *cpu = env_archcpu(env);
> + if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> + return TRANSLATE_FAIL;
> + } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> @@ -699,8 +702,17 @@ restart:
> /* for superpage mappings, make a fake leaf PTE for the TLB's
> benefit. */
> target_ulong vpn = addr >> PGSHIFT;
> - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
> - (addr & ~TARGET_PAGE_MASK);
> +
> + int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
> + if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
> + (napot_bits != 0 && napot_bits != 4)) {
> + return TRANSLATE_FAIL;
> + }
> +
> + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << ptshift) - 1))
> + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
>
> /* set permissions on the TLB entry */
> if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 1/3] target/riscv: add support for svnapot extension
@ 2022-01-01 13:17 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-01-01 13:17 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
QEMU Developers, wangjunqiang, Wei Wu (吴伟)
On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 20 ++++++++++++++++----
> 4 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6ef3314bce..cbcb7f522b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> + DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
Please drop the "x-" prefix here as well. The Svnapot extension is
already ratified.
Regards,
Anup
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index dc10f27093..1fbbde28c6 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -315,6 +315,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_svnapot;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 1e31f4d35f..1156c941cb 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -483,6 +483,7 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_N 0x8000000000000000 /* NAPOT translation */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 10f3baba53..e044153986 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,9 +619,12 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = pte >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
>
> - if (!(pte & PTE_V)) {
> + RISCVCPU *cpu = env_archcpu(env);
> + if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> + return TRANSLATE_FAIL;
> + } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> @@ -699,8 +702,17 @@ restart:
> /* for superpage mappings, make a fake leaf PTE for the TLB's
> benefit. */
> target_ulong vpn = addr >> PGSHIFT;
> - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
> - (addr & ~TARGET_PAGE_MASK);
> +
> + int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
> + if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
> + (napot_bits != 0 && napot_bits != 4)) {
> + return TRANSLATE_FAIL;
> + }
> +
> + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << ptshift) - 1))
> + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
>
> /* set permissions on the TLB entry */
> if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 2/3] target/riscv: add support for svinval extension
2021-12-31 8:09 ` Weiwei Li
@ 2021-12-31 8:09 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2021-12-31 8:09 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
5 files changed, 85 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cbcb7f522b..77ef0f85fe 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+ DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1fbbde28c6..5dd9e53293 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -315,6 +315,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svinval;
bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8617307b29..809464113a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_w_inval 0001100 00000 00000 000 00000 1110011
+sfence_inval_ir 0001100 00001 00000 000 00000 1110011
+hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma
+hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index 0000000000..1dde665661
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2021 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_SVINVAL(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as sfence.vma currently */
+ REQUIRE_EXT(ctx, RVS);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.vvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.gvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_gvma_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5df6c0d800..47541a4db0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -651,6 +651,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_svinval.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 2/3] target/riscv: add support for svinval extension
@ 2021-12-31 8:09 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2021-12-31 8:09 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
5 files changed, 85 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cbcb7f522b..77ef0f85fe 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+ DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1fbbde28c6..5dd9e53293 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -315,6 +315,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svinval;
bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8617307b29..809464113a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_w_inval 0001100 00000 00000 000 00000 1110011
+sfence_inval_ir 0001100 00001 00000 000 00000 1110011
+hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma
+hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index 0000000000..1dde665661
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2021 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_SVINVAL(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as sfence.vma currently */
+ REQUIRE_EXT(ctx, RVS);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.vvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.gvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_gvma_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5df6c0d800..47541a4db0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -651,6 +651,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_svinval.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 2/3] target/riscv: add support for svinval extension
2021-12-31 8:09 ` Weiwei Li
@ 2022-01-01 13:15 ` Anup Patel
-1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-01-01 13:15 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟),
open list:RISC-V, wangjunqiang, Bin Meng, QEMU Developers,
Alistair Francis, Palmer Dabbelt
On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 7 ++
> target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 5 files changed, 85 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cbcb7f522b..77ef0f85fe 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> + DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
Please drop the "x-" prefix. The Svinval extension is already ratified.
Regards,
Anup
> DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1fbbde28c6..5dd9e53293 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -315,6 +315,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_svinval;
> bool ext_svnapot;
> bool ext_zfh;
> bool ext_zfhmin;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 8617307b29..809464113a 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
> fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
> +
> +# *** Svinval Standard Extension ***
> +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
> +sfence_w_inval 0001100 00000 00000 000 00000 1110011
> +sfence_inval_ir 0001100 00001 00000 000 00000 1110011
> +hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma
> +hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma
> diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
> new file mode 100644
> index 0000000000..1dde665661
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_svinval.c.inc
> @@ -0,0 +1,75 @@
> +/*
> + * RISC-V translation routines for the Svinval Standard Instruction Set.
> + *
> + * Copyright (c) 2020-2021 PLCT lab
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_SVINVAL(ctx) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \
> + return false; \
> + } \
> +} while (0)
> +
> +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + /* Do the same as sfence.vma currently */
> + REQUIRE_EXT(ctx, RVS);
> +#ifndef CONFIG_USER_ONLY
> + gen_helper_tlb_flush(cpu_env);
> + return true;
> +#endif
> + return false;
> +}
> +
> +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + REQUIRE_EXT(ctx, RVS);
> + /* Do nothing currently */
> + return true;
> +}
> +
> +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + REQUIRE_EXT(ctx, RVS);
> + /* Do nothing currently */
> + return true;
> +}
> +
> +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + /* Do the same as hfence.vvma currently */
> + REQUIRE_EXT(ctx, RVH);
> +#ifndef CONFIG_USER_ONLY
> + gen_helper_hyp_tlb_flush(cpu_env);
> + return true;
> +#endif
> + return false;
> +}
> +
> +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + /* Do the same as hfence.gvma currently */
> + REQUIRE_EXT(ctx, RVH);
> +#ifndef CONFIG_USER_ONLY
> + gen_helper_hyp_gvma_tlb_flush(cpu_env);
> + return true;
> +#endif
> + return false;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5df6c0d800..47541a4db0 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -651,6 +651,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_rvb.c.inc"
> #include "insn_trans/trans_rvzfh.c.inc"
> #include "insn_trans/trans_privileged.c.inc"
> +#include "insn_trans/trans_svinval.c.inc"
>
> /* Include the auto-generated decoder for 16 bit insn */
> #include "decode-insn16.c.inc"
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 2/3] target/riscv: add support for svinval extension
@ 2022-01-01 13:15 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-01-01 13:15 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
QEMU Developers, wangjunqiang, Wei Wu (吴伟)
On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 7 ++
> target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
> target/riscv/translate.c | 1 +
> 5 files changed, 85 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cbcb7f522b..77ef0f85fe 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> + DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
Please drop the "x-" prefix. The Svinval extension is already ratified.
Regards,
Anup
> DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1fbbde28c6..5dd9e53293 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -315,6 +315,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_svinval;
> bool ext_svnapot;
> bool ext_zfh;
> bool ext_zfhmin;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 8617307b29..809464113a 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
> fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
> fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
> +
> +# *** Svinval Standard Extension ***
> +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
> +sfence_w_inval 0001100 00000 00000 000 00000 1110011
> +sfence_inval_ir 0001100 00001 00000 000 00000 1110011
> +hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma
> +hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma
> diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
> new file mode 100644
> index 0000000000..1dde665661
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_svinval.c.inc
> @@ -0,0 +1,75 @@
> +/*
> + * RISC-V translation routines for the Svinval Standard Instruction Set.
> + *
> + * Copyright (c) 2020-2021 PLCT lab
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_SVINVAL(ctx) do { \
> + if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \
> + return false; \
> + } \
> +} while (0)
> +
> +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + /* Do the same as sfence.vma currently */
> + REQUIRE_EXT(ctx, RVS);
> +#ifndef CONFIG_USER_ONLY
> + gen_helper_tlb_flush(cpu_env);
> + return true;
> +#endif
> + return false;
> +}
> +
> +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + REQUIRE_EXT(ctx, RVS);
> + /* Do nothing currently */
> + return true;
> +}
> +
> +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + REQUIRE_EXT(ctx, RVS);
> + /* Do nothing currently */
> + return true;
> +}
> +
> +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + /* Do the same as hfence.vvma currently */
> + REQUIRE_EXT(ctx, RVH);
> +#ifndef CONFIG_USER_ONLY
> + gen_helper_hyp_tlb_flush(cpu_env);
> + return true;
> +#endif
> + return false;
> +}
> +
> +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
> +{
> + REQUIRE_SVINVAL(ctx);
> + /* Do the same as hfence.gvma currently */
> + REQUIRE_EXT(ctx, RVH);
> +#ifndef CONFIG_USER_ONLY
> + gen_helper_hyp_gvma_tlb_flush(cpu_env);
> + return true;
> +#endif
> + return false;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5df6c0d800..47541a4db0 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -651,6 +651,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_rvb.c.inc"
> #include "insn_trans/trans_rvzfh.c.inc"
> #include "insn_trans/trans_privileged.c.inc"
> +#include "insn_trans/trans_svinval.c.inc"
>
> /* Include the auto-generated decoder for 16 bit insn */
> #include "decode-insn16.c.inc"
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 2/3] target/riscv: add support for svinval extension
2022-01-01 13:15 ` Anup Patel
@ 2022-01-02 5:41 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-02 5:41 UTC (permalink / raw)
To: Anup Patel
Cc: Wei Wu (吴伟),
open list:RISC-V, wangjunqiang, Bin Meng, QEMU Developers,
Alistair Francis, Palmer Dabbelt
Thanks for your comments.
I'll fix the three flags.
在 2022/1/1 下午9:15, Anup Patel 写道:
> On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/cpu.c | 1 +
>> target/riscv/cpu.h | 1 +
>> target/riscv/insn32.decode | 7 ++
>> target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
>> target/riscv/translate.c | 1 +
>> 5 files changed, 85 insertions(+)
>> create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index cbcb7f522b..77ef0f85fe 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
>> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>> + DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
> Please drop the "x-" prefix. The Svinval extension is already ratified.
>
> Regards,
> Anup
>
>> DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
>> /* ePMP 0.9.3 */
>> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 1fbbde28c6..5dd9e53293 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -315,6 +315,7 @@ struct RISCVCPU {
>> bool ext_counters;
>> bool ext_ifencei;
>> bool ext_icsr;
>> + bool ext_svinval;
>> bool ext_svnapot;
>> bool ext_zfh;
>> bool ext_zfhmin;
>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
>> index 8617307b29..809464113a 100644
>> --- a/target/riscv/insn32.decode
>> +++ b/target/riscv/insn32.decode
>> @@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
>> fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
>> fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
>> fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
>> +
>> +# *** Svinval Standard Extension ***
>> +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
>> +sfence_w_inval 0001100 00000 00000 000 00000 1110011
>> +sfence_inval_ir 0001100 00001 00000 000 00000 1110011
>> +hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma
>> +hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma
>> diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
>> new file mode 100644
>> index 0000000000..1dde665661
>> --- /dev/null
>> +++ b/target/riscv/insn_trans/trans_svinval.c.inc
>> @@ -0,0 +1,75 @@
>> +/*
>> + * RISC-V translation routines for the Svinval Standard Instruction Set.
>> + *
>> + * Copyright (c) 2020-2021 PLCT lab
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2 or later, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#define REQUIRE_SVINVAL(ctx) do { \
>> + if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + /* Do the same as sfence.vma currently */
>> + REQUIRE_EXT(ctx, RVS);
>> +#ifndef CONFIG_USER_ONLY
>> + gen_helper_tlb_flush(cpu_env);
>> + return true;
>> +#endif
>> + return false;
>> +}
>> +
>> +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + REQUIRE_EXT(ctx, RVS);
>> + /* Do nothing currently */
>> + return true;
>> +}
>> +
>> +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + REQUIRE_EXT(ctx, RVS);
>> + /* Do nothing currently */
>> + return true;
>> +}
>> +
>> +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + /* Do the same as hfence.vvma currently */
>> + REQUIRE_EXT(ctx, RVH);
>> +#ifndef CONFIG_USER_ONLY
>> + gen_helper_hyp_tlb_flush(cpu_env);
>> + return true;
>> +#endif
>> + return false;
>> +}
>> +
>> +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + /* Do the same as hfence.gvma currently */
>> + REQUIRE_EXT(ctx, RVH);
>> +#ifndef CONFIG_USER_ONLY
>> + gen_helper_hyp_gvma_tlb_flush(cpu_env);
>> + return true;
>> +#endif
>> + return false;
>> +}
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 5df6c0d800..47541a4db0 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -651,6 +651,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>> #include "insn_trans/trans_rvb.c.inc"
>> #include "insn_trans/trans_rvzfh.c.inc"
>> #include "insn_trans/trans_privileged.c.inc"
>> +#include "insn_trans/trans_svinval.c.inc"
>>
>> /* Include the auto-generated decoder for 16 bit insn */
>> #include "decode-insn16.c.inc"
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 2/3] target/riscv: add support for svinval extension
@ 2022-01-02 5:41 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-02 5:41 UTC (permalink / raw)
To: Anup Patel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
QEMU Developers, wangjunqiang, Wei Wu (吴伟)
Thanks for your comments.
I'll fix the three flags.
在 2022/1/1 下午9:15, Anup Patel 写道:
> On Fri, Dec 31, 2021 at 1:43 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/cpu.c | 1 +
>> target/riscv/cpu.h | 1 +
>> target/riscv/insn32.decode | 7 ++
>> target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
>> target/riscv/translate.c | 1 +
>> 5 files changed, 85 insertions(+)
>> create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index cbcb7f522b..77ef0f85fe 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -647,6 +647,7 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
>> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>> + DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
> Please drop the "x-" prefix. The Svinval extension is already ratified.
>
> Regards,
> Anup
>
>> DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
>> /* ePMP 0.9.3 */
>> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 1fbbde28c6..5dd9e53293 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -315,6 +315,7 @@ struct RISCVCPU {
>> bool ext_counters;
>> bool ext_ifencei;
>> bool ext_icsr;
>> + bool ext_svinval;
>> bool ext_svnapot;
>> bool ext_zfh;
>> bool ext_zfhmin;
>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
>> index 8617307b29..809464113a 100644
>> --- a/target/riscv/insn32.decode
>> +++ b/target/riscv/insn32.decode
>> @@ -784,3 +784,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
>> fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
>> fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
>> fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
>> +
>> +# *** Svinval Standard Extension ***
>> +sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
>> +sfence_w_inval 0001100 00000 00000 000 00000 1110011
>> +sfence_inval_ir 0001100 00001 00000 000 00000 1110011
>> +hinval_vvma 0011011 ..... ..... 000 00000 1110011 @hfence_vvma
>> +hinval_gvma 0111011 ..... ..... 000 00000 1110011 @hfence_gvma
>> diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
>> new file mode 100644
>> index 0000000000..1dde665661
>> --- /dev/null
>> +++ b/target/riscv/insn_trans/trans_svinval.c.inc
>> @@ -0,0 +1,75 @@
>> +/*
>> + * RISC-V translation routines for the Svinval Standard Instruction Set.
>> + *
>> + * Copyright (c) 2020-2021 PLCT lab
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2 or later, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#define REQUIRE_SVINVAL(ctx) do { \
>> + if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> +static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + /* Do the same as sfence.vma currently */
>> + REQUIRE_EXT(ctx, RVS);
>> +#ifndef CONFIG_USER_ONLY
>> + gen_helper_tlb_flush(cpu_env);
>> + return true;
>> +#endif
>> + return false;
>> +}
>> +
>> +static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + REQUIRE_EXT(ctx, RVS);
>> + /* Do nothing currently */
>> + return true;
>> +}
>> +
>> +static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + REQUIRE_EXT(ctx, RVS);
>> + /* Do nothing currently */
>> + return true;
>> +}
>> +
>> +static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + /* Do the same as hfence.vvma currently */
>> + REQUIRE_EXT(ctx, RVH);
>> +#ifndef CONFIG_USER_ONLY
>> + gen_helper_hyp_tlb_flush(cpu_env);
>> + return true;
>> +#endif
>> + return false;
>> +}
>> +
>> +static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
>> +{
>> + REQUIRE_SVINVAL(ctx);
>> + /* Do the same as hfence.gvma currently */
>> + REQUIRE_EXT(ctx, RVH);
>> +#ifndef CONFIG_USER_ONLY
>> + gen_helper_hyp_gvma_tlb_flush(cpu_env);
>> + return true;
>> +#endif
>> + return false;
>> +}
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 5df6c0d800..47541a4db0 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -651,6 +651,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>> #include "insn_trans/trans_rvb.c.inc"
>> #include "insn_trans/trans_rvzfh.c.inc"
>> #include "insn_trans/trans_privileged.c.inc"
>> +#include "insn_trans/trans_svinval.c.inc"
>>
>> /* Include the auto-generated decoder for 16 bit insn */
>> #include "decode-insn16.c.inc"
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 3/3] target/riscv: add support for svpbmt extension
2021-12-31 8:09 ` Weiwei Li
@ 2021-12-31 8:09 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2021-12-31 8:09 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Tested-by: Heiko Stuebner <heiko@sntech.de>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 9 ++++++++-
4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 77ef0f85fe..743bcfe297 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -649,6 +649,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
+ DEFINE_PROP_BOOL("x-svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5dd9e53293..6656b8a4f3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -317,6 +317,7 @@ struct RISCVCPU {
bool ext_icsr;
bool ext_svinval;
bool ext_svnapot;
+ bool ext_svpbmt;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 1156c941cb..3dae358aa5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -483,7 +483,10 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
+#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
#define PTE_N 0x8000000000000000 /* NAPOT translation */
+#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e044153986..41d04675b3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,16 +619,23 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
return TRANSLATE_FAIL;
+ } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+ return TRANSLATE_FAIL;
+ } else if (pte & PTE_RSVD) {
+ return TRANSLATE_FAIL;
} else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
+ return TRANSLATE_FAIL;
+ }
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 3/3] target/riscv: add support for svpbmt extension
@ 2021-12-31 8:09 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2021-12-31 8:09 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Tested-by: Heiko Stuebner <heiko@sntech.de>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 9 ++++++++-
4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 77ef0f85fe..743bcfe297 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -649,6 +649,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
+ DEFINE_PROP_BOOL("x-svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5dd9e53293..6656b8a4f3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -317,6 +317,7 @@ struct RISCVCPU {
bool ext_icsr;
bool ext_svinval;
bool ext_svnapot;
+ bool ext_svpbmt;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 1156c941cb..3dae358aa5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -483,7 +483,10 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
+#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
#define PTE_N 0x8000000000000000 /* NAPOT translation */
+#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e044153986..41d04675b3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,16 +619,23 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
return TRANSLATE_FAIL;
+ } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+ return TRANSLATE_FAIL;
+ } else if (pte & PTE_RSVD) {
+ return TRANSLATE_FAIL;
} else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
+ return TRANSLATE_FAIL;
+ }
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 3/3] target/riscv: add support for svpbmt extension
2021-12-31 8:09 ` Weiwei Li
@ 2022-01-01 13:19 ` Anup Patel
-1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-01-01 13:19 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟),
open list:RISC-V, wangjunqiang, Bin Meng, QEMU Developers,
Alistair Francis, Palmer Dabbelt
On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 9 ++++++++-
> 4 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 77ef0f85fe..743bcfe297 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -649,6 +649,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
> + DEFINE_PROP_BOOL("x-svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
Drop the "x-" prefix, same as the other two patches. The Svpmbt extension
is also ratified.
Regards,
Anup
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5dd9e53293..6656b8a4f3 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -317,6 +317,7 @@ struct RISCVCPU {
> bool ext_icsr;
> bool ext_svinval;
> bool ext_svnapot;
> + bool ext_svpbmt;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 1156c941cb..3dae358aa5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -483,7 +483,10 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
> #define PTE_N 0x8000000000000000 /* NAPOT translation */
> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e044153986..41d04675b3 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,16 +619,23 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
>
> RISCVCPU *cpu = env_archcpu(env);
> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> return TRANSLATE_FAIL;
> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
> + return TRANSLATE_FAIL;
> + } else if (pte & PTE_RSVD) {
> + return TRANSLATE_FAIL;
> } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
> + return TRANSLATE_FAIL;
> + }
> base = ppn << PGSHIFT;
> } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
> /* Reserved leaf PTE flags: PTE_W */
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 3/3] target/riscv: add support for svpbmt extension
@ 2022-01-01 13:19 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-01-01 13:19 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
QEMU Developers, wangjunqiang, Wei Wu (吴伟)
On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 9 ++++++++-
> 4 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 77ef0f85fe..743bcfe297 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -649,6 +649,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false),
> + DEFINE_PROP_BOOL("x-svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
Drop the "x-" prefix, same as the other two patches. The Svpmbt extension
is also ratified.
Regards,
Anup
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5dd9e53293..6656b8a4f3 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -317,6 +317,7 @@ struct RISCVCPU {
> bool ext_icsr;
> bool ext_svinval;
> bool ext_svnapot;
> + bool ext_svpbmt;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 1156c941cb..3dae358aa5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -483,7 +483,10 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
> #define PTE_N 0x8000000000000000 /* NAPOT translation */
> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e044153986..41d04675b3 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,16 +619,23 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
>
> RISCVCPU *cpu = env_archcpu(env);
> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> return TRANSLATE_FAIL;
> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
> + return TRANSLATE_FAIL;
> + } else if (pte & PTE_RSVD) {
> + return TRANSLATE_FAIL;
> } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
> + return TRANSLATE_FAIL;
> + }
> base = ppn << PGSHIFT;
> } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
> /* Reserved leaf PTE flags: PTE_W */
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread