* [U-Boot] [PATCH v5 1/8] ARMv7: PSCI: add PSCI v1.0 functions skeleton
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
@ 2016-06-14 7:01 ` macro.wave.z at gmail.com
2016-06-14 7:01 ` [U-Boot] [PATCH v5 2/8] ARMv7: PSCI: factor out reusable psci_cpu_on_common macro.wave.z at gmail.com
` (7 subsequent siblings)
8 siblings, 0 replies; 34+ messages in thread
From: macro.wave.z at gmail.com @ 2016-06-14 7:01 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
---
arch/arm/cpu/armv7/psci.S | 78 ++++++++++++++++++++++++++++++++++++++++++++
arch/arm/cpu/armv7/virt-dt.c | 10 +++++-
arch/arm/include/asm/psci.h | 16 +++++++++
3 files changed, 103 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b..8e25300 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -46,20 +46,62 @@ ENTRY(default_psci_vector)
ENDPROC(default_psci_vector)
.weak default_psci_vector
+ENTRY(psci_version)
ENTRY(psci_cpu_suspend)
ENTRY(psci_cpu_off)
ENTRY(psci_cpu_on)
+ENTRY(psci_affinity_info)
ENTRY(psci_migrate)
+ENTRY(psci_migrate_info_type)
+ENTRY(psci_migrate_info_up_cpu)
+ENTRY(psci_system_off)
+ENTRY(psci_system_reset)
+ENTRY(psci_features)
+ENTRY(psci_cpu_freeze)
+ENTRY(psci_cpu_default_suspend)
+ENTRY(psci_node_hw_state)
+ENTRY(psci_system_suspend)
+ENTRY(psci_set_suspend_mode)
+ENTRY(psi_stat_residency)
+ENTRY(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr
+ENDPROC(psci_stat_count)
+ENDPROC(psi_stat_residency)
+ENDPROC(psci_set_suspend_mode)
+ENDPROC(psci_system_suspend)
+ENDPROC(psci_node_hw_state)
+ENDPROC(psci_cpu_default_suspend)
+ENDPROC(psci_cpu_freeze)
+ENDPROC(psci_features)
+ENDPROC(psci_system_reset)
+ENDPROC(psci_system_off)
+ENDPROC(psci_migrate_info_up_cpu)
+ENDPROC(psci_migrate_info_type)
ENDPROC(psci_migrate)
+ENDPROC(psci_affinity_info)
ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend)
+ENDPROC(psci_version)
+.weak psci_version
.weak psci_cpu_suspend
.weak psci_cpu_off
.weak psci_cpu_on
+.weak psci_affinity_info
.weak psci_migrate
+.weak psci_migrate_info_type
+.weak psci_migrate_info_up_cpu
+.weak psci_system_off
+.weak psci_system_reset
+.weak psci_features
+.weak psci_cpu_freeze
+.weak psci_cpu_default_suspend
+.weak psci_node_hw_state
+.weak psci_system_suspend
+.weak psci_set_suspend_mode
+.weak psi_stat_residency
+.weak psci_stat_count
_psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND
@@ -70,6 +112,42 @@ _psci_table:
.word psci_cpu_on
.word ARM_PSCI_FN_MIGRATE
.word psci_migrate
+ .word ARM_PSCI_0_2_FN_PSCI_VERSION
+ .word psci_version
+ .word ARM_PSCI_0_2_FN_CPU_SUSPEND
+ .word psci_cpu_suspend
+ .word ARM_PSCI_0_2_FN_CPU_OFF
+ .word psci_cpu_off
+ .word ARM_PSCI_0_2_FN_CPU_ON
+ .word psci_cpu_on
+ .word ARM_PSCI_0_2_FN_AFFINITY_INFO
+ .word psci_affinity_info
+ .word ARM_PSCI_0_2_FN_MIGRATE
+ .word psci_migrate
+ .word ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
+ .word psci_migrate_info_type
+ .word ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
+ .word psci_migrate_info_up_cpu
+ .word ARM_PSCI_0_2_FN_SYSTEM_OFF
+ .word psci_system_off
+ .word ARM_PSCI_0_2_FN_SYSTEM_RESET
+ .word psci_system_reset
+ .word ARM_PSCI_1_0_FN_PSCI_FEATURES
+ .word psci_features
+ .word ARM_PSCI_1_0_FN_CPU_FREEZE
+ .word psci_cpu_freeze
+ .word ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
+ .word psci_cpu_default_suspend
+ .word ARM_PSCI_1_0_FN_NODE_HW_STATE
+ .word psci_node_hw_state
+ .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+ .word psci_system_suspend
+ .word ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
+ .word psci_set_suspend_mode
+ .word ARM_PSCI_1_0_FN_STAT_RESIDENCY
+ .word psi_stat_residency
+ .word ARM_PSCI_1_0_FN_STAT_COUNT
+ .word psci_stat_count
.word 0
.word 0
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index 32c368f..5e31891 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -67,7 +67,15 @@ static int fdt_psci(void *fdt)
return nodeoff;
}
- tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
+#ifdef CONFIG_ARMV7_PSCI_1_0
+ tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci-1.0");
+ if (tmp)
+ return tmp;
+ tmp = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci-0.2");
+ if (tmp)
+ return tmp;
+#endif
+ tmp = fdt_appendprop_string(fdt, nodeoff, "compatible", "arm,psci");
if (tmp)
return tmp;
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 3704f07..2367ec0 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -31,6 +31,12 @@
#define ARM_PSCI_RET_NI (-1)
#define ARM_PSCI_RET_INVAL (-2)
#define ARM_PSCI_RET_DENIED (-3)
+#define ARM_PSCI_RET_ALREADY_ON (-4)
+#define ARM_PSCI_RET_ON_PENDING (-5)
+#define ARM_PSCI_RET_INTERNAL_FAILURE (-6)
+#define ARM_PSCI_RET_NOT_PRESENT (-7)
+#define ARM_PSCI_RET_DISABLED (-8)
+#define ARM_PSCI_RET_INVALID_ADDRESS (-9)
/* PSCI 0.2 interface */
#define ARM_PSCI_0_2_FN_BASE 0x84000000
@@ -47,6 +53,16 @@
#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+/* PSCI 1.0 interface */
+#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
+#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11)
+#define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN(12)
+#define ARM_PSCI_1_0_FN_NODE_HW_STATE ARM_PSCI_0_2_FN(13)
+#define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND ARM_PSCI_0_2_FN(14)
+#define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE ARM_PSCI_0_2_FN(15)
+#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
+#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
+
#ifndef __ASSEMBLY__
int psci_update_dt(void *fdt);
void psci_board_init(void);
--
2.1.4
^ permalink raw reply related [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 2/8] ARMv7: PSCI: factor out reusable psci_cpu_on_common
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
2016-06-14 7:01 ` [U-Boot] [PATCH v5 1/8] ARMv7: PSCI: add PSCI v1.0 functions skeleton macro.wave.z at gmail.com
@ 2016-06-14 7:01 ` macro.wave.z at gmail.com
2016-06-28 2:49 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC macro.wave.z at gmail.com
` (6 subsequent siblings)
8 siblings, 1 reply; 34+ messages in thread
From: macro.wave.z at gmail.com @ 2016-06-14 7:01 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
There are codes for saving target PC in each platform psci_cpu_on routines,
these can be factored out as psci_cpu_on_common.
Another purpose is that the codes of saving target PC will be changed a bit and
a new context ID will be saved in the following patches, then we can update the
psci_cpu_on_common mainly instead of touching every platform's psci_cpu_on
functions more times, this makes it easier for coding and being reviewed.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/psci.S | 5 +----
arch/arm/cpu/armv7/mx7/psci.S | 5 +----
arch/arm/cpu/armv7/psci.S | 12 ++++++++++++
arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 5 +----
arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 5 +----
arch/arm/mach-tegra/psci.S | 5 +----
6 files changed, 17 insertions(+), 20 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index cf5cd48..548c507 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -35,10 +35,7 @@ psci_cpu_on:
@ r1 = 0xf01
and r1, r1, #0xff
- mov r0, r1
- bl psci_get_cpu_stack_top
- str r2, [r0]
- dsb
+ bl psci_cpu_on_common
@ Get DCFG base address
movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
index 34c6ab3..74fdc4d 100644
--- a/arch/arm/cpu/armv7/mx7/psci.S
+++ b/arch/arm/cpu/armv7/mx7/psci.S
@@ -29,10 +29,7 @@ psci_arch_init:
psci_cpu_on:
push {lr}
- mov r0, r1
- bl psci_get_cpu_stack_top
- str r2, [r0]
- dsb
+ bl psci_cpu_on_common
ldr r2, =psci_cpu_entry
bl imx_cpu_on
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 8e25300..3b92f1d 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -253,6 +253,18 @@ ENTRY(psci_enable_smp)
ENDPROC(psci_enable_smp)
.weak psci_enable_smp
+/* expects target CPU in r1, target PC in r2 */
+ENTRY(psci_cpu_on_common)
+ push {lr}
+
+ mov r0, r1
+ bl psci_get_cpu_stack_top @ get stack top of target CPU
+ str r2, [r0] @ store target PC at stack top
+ dsb
+
+ pop {pc}
+ENDPROC(psci_cpu_on_common)
+
ENTRY(psci_cpu_off_common)
push {lr}
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd..016e491 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -134,10 +134,7 @@ out: mcr p15, 0, r7, c1, c1, 0
psci_cpu_on:
push {lr}
- mov r0, r1
- bl psci_get_cpu_stack_top @ get stack top of target CPU
- str r2, [r0] @ store target PC at stack top
- dsb
+ bl psci_cpu_on_common
movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
movt r0, #(SUN6I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587..0ebb30e 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -123,10 +123,7 @@ out: mcr p15, 0, r7, c1, c1, 0
psci_cpu_on:
push {lr}
- mov r0, r1
- bl psci_get_cpu_stack_top @ get stack top of target CPU
- str r2, [r0] @ store target PC at stack top
- dsb
+ bl psci_cpu_on_common
movw r0, #(SUN7I_CPUCFG_BASE & 0xffff)
movt r0, #(SUN7I_CPUCFG_BASE >> 16)
diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
index b836da1..8a0147c 100644
--- a/arch/arm/mach-tegra/psci.S
+++ b/arch/arm/mach-tegra/psci.S
@@ -90,10 +90,7 @@ ENDPROC(psci_cpu_off)
ENTRY(psci_cpu_on)
push {lr}
- mov r0, r1
- bl psci_get_cpu_stack_top @ get stack top of target CPU
- str r2, [r0] @ store target PC at stack top
- dsb
+ bl psci_cpu_on_common
ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
ldr r5, =psci_cpu_entry
--
2.1.4
^ permalink raw reply related [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 2/8] ARMv7: PSCI: factor out reusable psci_cpu_on_common
2016-06-14 7:01 ` [U-Boot] [PATCH v5 2/8] ARMv7: PSCI: factor out reusable psci_cpu_on_common macro.wave.z at gmail.com
@ 2016-06-28 2:49 ` Chen-Yu Tsai
2016-06-28 3:50 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-28 2:49 UTC (permalink / raw)
To: u-boot
Hi,
On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> There are codes for saving target PC in each platform psci_cpu_on routines,
> these can be factored out as psci_cpu_on_common.
> Another purpose is that the codes of saving target PC will be changed a bit and
> a new context ID will be saved in the following patches, then we can update the
> psci_cpu_on_common mainly instead of touching every platform's psci_cpu_on
> functions more times, this makes it easier for coding and being reviewed.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
> ---
> arch/arm/cpu/armv7/ls102xa/psci.S | 5 +----
> arch/arm/cpu/armv7/mx7/psci.S | 5 +----
> arch/arm/cpu/armv7/psci.S | 12 ++++++++++++
> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 5 +----
> arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 5 +----
> arch/arm/mach-tegra/psci.S | 5 +----
> 6 files changed, 17 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
> index cf5cd48..548c507 100644
> --- a/arch/arm/cpu/armv7/ls102xa/psci.S
> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
> @@ -35,10 +35,7 @@ psci_cpu_on:
> @ r1 = 0xf01
> and r1, r1, #0xff
>
> - mov r0, r1
> - bl psci_get_cpu_stack_top
> - str r2, [r0]
> - dsb
> + bl psci_cpu_on_common
>
> @ Get DCFG base address
> movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
> diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
> index 34c6ab3..74fdc4d 100644
> --- a/arch/arm/cpu/armv7/mx7/psci.S
> +++ b/arch/arm/cpu/armv7/mx7/psci.S
> @@ -29,10 +29,7 @@ psci_arch_init:
> psci_cpu_on:
> push {lr}
>
> - mov r0, r1
> - bl psci_get_cpu_stack_top
> - str r2, [r0]
> - dsb
> + bl psci_cpu_on_common
>
> ldr r2, =psci_cpu_entry
> bl imx_cpu_on
> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
> index 8e25300..3b92f1d 100644
> --- a/arch/arm/cpu/armv7/psci.S
> +++ b/arch/arm/cpu/armv7/psci.S
> @@ -253,6 +253,18 @@ ENTRY(psci_enable_smp)
> ENDPROC(psci_enable_smp)
> .weak psci_enable_smp
>
> +/* expects target CPU in r1, target PC in r2 */
> +ENTRY(psci_cpu_on_common)
> + push {lr}
> +
> + mov r0, r1
> + bl psci_get_cpu_stack_top @ get stack top of target CPU
> + str r2, [r0] @ store target PC at stack top
> + dsb
> +
> + pop {pc}
> +ENDPROC(psci_cpu_on_common)
> +
Since you are just saving the target PC, why not just name the
function like that?
See https://github.com/wens/u-boot-sunxi/commit/5a42630107e93bea9aa4da27cc16bdb604993dca
> ENTRY(psci_cpu_off_common)
> push {lr}
>
> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> index 90b5bfd..016e491 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
> @@ -134,10 +134,7 @@ out: mcr p15, 0, r7, c1, c1, 0
> psci_cpu_on:
> push {lr}
>
> - mov r0, r1
> - bl psci_get_cpu_stack_top @ get stack top of target CPU
> - str r2, [r0] @ store target PC at stack top
> - dsb
> + bl psci_cpu_on_common
>
> movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
> movt r0, #(SUN6I_CPUCFG_BASE >> 16)
> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> index e15d587..0ebb30e 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> @@ -123,10 +123,7 @@ out: mcr p15, 0, r7, c1, c1, 0
> psci_cpu_on:
> push {lr}
>
> - mov r0, r1
> - bl psci_get_cpu_stack_top @ get stack top of target CPU
> - str r2, [r0] @ store target PC at stack top
> - dsb
> + bl psci_cpu_on_common
The sunxi parts no longer apply. The partial rewrite in C has
landed in master.
Regards
ChenYu
>
> movw r0, #(SUN7I_CPUCFG_BASE & 0xffff)
> movt r0, #(SUN7I_CPUCFG_BASE >> 16)
> diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
> index b836da1..8a0147c 100644
> --- a/arch/arm/mach-tegra/psci.S
> +++ b/arch/arm/mach-tegra/psci.S
> @@ -90,10 +90,7 @@ ENDPROC(psci_cpu_off)
> ENTRY(psci_cpu_on)
> push {lr}
>
> - mov r0, r1
> - bl psci_get_cpu_stack_top @ get stack top of target CPU
> - str r2, [r0] @ store target PC at stack top
> - dsb
> + bl psci_cpu_on_common
>
> ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
> ldr r5, =psci_cpu_entry
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 2/8] ARMv7: PSCI: factor out reusable psci_cpu_on_common
2016-06-28 2:49 ` Chen-Yu Tsai
@ 2016-06-28 3:50 ` Hongbo Zhang
0 siblings, 0 replies; 34+ messages in thread
From: Hongbo Zhang @ 2016-06-28 3:50 UTC (permalink / raw)
To: u-boot
On Tue, Jun 28, 2016 at 10:49 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> Hi,
>
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> There are codes for saving target PC in each platform psci_cpu_on routines,
>> these can be factored out as psci_cpu_on_common.
>> Another purpose is that the codes of saving target PC will be changed a bit and
>> a new context ID will be saved in the following patches, then we can update the
>> psci_cpu_on_common mainly instead of touching every platform's psci_cpu_on
>> functions more times, this makes it easier for coding and being reviewed.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
>> ---
>> arch/arm/cpu/armv7/ls102xa/psci.S | 5 +----
>> arch/arm/cpu/armv7/mx7/psci.S | 5 +----
>> arch/arm/cpu/armv7/psci.S | 12 ++++++++++++
>> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 5 +----
>> arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 5 +----
>> arch/arm/mach-tegra/psci.S | 5 +----
>> 6 files changed, 17 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
>> index cf5cd48..548c507 100644
>> --- a/arch/arm/cpu/armv7/ls102xa/psci.S
>> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
>> @@ -35,10 +35,7 @@ psci_cpu_on:
>> @ r1 = 0xf01
>> and r1, r1, #0xff
>>
>> - mov r0, r1
>> - bl psci_get_cpu_stack_top
>> - str r2, [r0]
>> - dsb
>> + bl psci_cpu_on_common
>>
>> @ Get DCFG base address
>> movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
>> diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S
>> index 34c6ab3..74fdc4d 100644
>> --- a/arch/arm/cpu/armv7/mx7/psci.S
>> +++ b/arch/arm/cpu/armv7/mx7/psci.S
>> @@ -29,10 +29,7 @@ psci_arch_init:
>> psci_cpu_on:
>> push {lr}
>>
>> - mov r0, r1
>> - bl psci_get_cpu_stack_top
>> - str r2, [r0]
>> - dsb
>> + bl psci_cpu_on_common
>>
>> ldr r2, =psci_cpu_entry
>> bl imx_cpu_on
>> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
>> index 8e25300..3b92f1d 100644
>> --- a/arch/arm/cpu/armv7/psci.S
>> +++ b/arch/arm/cpu/armv7/psci.S
>> @@ -253,6 +253,18 @@ ENTRY(psci_enable_smp)
>> ENDPROC(psci_enable_smp)
>> .weak psci_enable_smp
>>
>> +/* expects target CPU in r1, target PC in r2 */
>> +ENTRY(psci_cpu_on_common)
>> + push {lr}
>> +
>> + mov r0, r1
>> + bl psci_get_cpu_stack_top @ get stack top of target CPU
>> + str r2, [r0] @ store target PC at stack top
>> + dsb
>> +
>> + pop {pc}
>> +ENDPROC(psci_cpu_on_common)
>> +
>
> Since you are just saving the target PC, why not just name the
> function like that?
>
No, not only saving target PC, you will see later that the newly added
context ID is saved too.
In my previous patches, I save target PC here, and then in later patch
save target ID too, and at last the common function is factored out,
in this way every platform's code are touched too many times.
Copy one paragraph of my cover letter here:
"Move the patch of factoring out psci_cpu_on_common to earlier place 2/8, so
that the following patches can only update the psci_cpu_on_common instead of
touching each platform's psci_cpu_on, this reduces patches size obviously and
make it easier for review."
> See https://github.com/wens/u-boot-sunxi/commit/5a42630107e93bea9aa4da27cc16bdb604993dca
>
>> ENTRY(psci_cpu_off_common)
>> push {lr}
>>
>> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>> index 90b5bfd..016e491 100644
>> --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>> @@ -134,10 +134,7 @@ out: mcr p15, 0, r7, c1, c1, 0
>> psci_cpu_on:
>> push {lr}
>>
>> - mov r0, r1
>> - bl psci_get_cpu_stack_top @ get stack top of target CPU
>> - str r2, [r0] @ store target PC at stack top
>> - dsb
>> + bl psci_cpu_on_common
>>
>> movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
>> movt r0, #(SUN6I_CPUCFG_BASE >> 16)
>> diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
>> index e15d587..0ebb30e 100644
>> --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
>> +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
>> @@ -123,10 +123,7 @@ out: mcr p15, 0, r7, c1, c1, 0
>> psci_cpu_on:
>> push {lr}
>>
>> - mov r0, r1
>> - bl psci_get_cpu_stack_top @ get stack top of target CPU
>> - str r2, [r0] @ store target PC at stack top
>> - dsb
>> + bl psci_cpu_on_common
>
> The sunxi parts no longer apply. The partial rewrite in C has
> landed in master.
>
OK, will check sunxi's codes again.
> Regards
> ChenYu
>
>>
>> movw r0, #(SUN7I_CPUCFG_BASE & 0xffff)
>> movt r0, #(SUN7I_CPUCFG_BASE >> 16)
>> diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S
>> index b836da1..8a0147c 100644
>> --- a/arch/arm/mach-tegra/psci.S
>> +++ b/arch/arm/mach-tegra/psci.S
>> @@ -90,10 +90,7 @@ ENDPROC(psci_cpu_off)
>> ENTRY(psci_cpu_on)
>> push {lr}
>>
>> - mov r0, r1
>> - bl psci_get_cpu_stack_top @ get stack top of target CPU
>> - str r2, [r0] @ store target PC at stack top
>> - dsb
>> + bl psci_cpu_on_common
>>
>> ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
>> ldr r5, =psci_cpu_entry
>> --
>> 2.1.4
>>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
2016-06-14 7:01 ` [U-Boot] [PATCH v5 1/8] ARMv7: PSCI: add PSCI v1.0 functions skeleton macro.wave.z at gmail.com
2016-06-14 7:01 ` [U-Boot] [PATCH v5 2/8] ARMv7: PSCI: factor out reusable psci_cpu_on_common macro.wave.z at gmail.com
@ 2016-06-14 7:01 ` macro.wave.z at gmail.com
2016-06-28 3:24 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 4/8] ARMv7: PSCI: add codes to save context ID for CPU_ON macro.wave.z at gmail.com
` (5 subsequent siblings)
8 siblings, 1 reply; 34+ messages in thread
From: macro.wave.z at gmail.com @ 2016-06-14 7:01 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
The legacy code saves target PC at stack top, this patch changes it to stack
bottom, because we will save more contents for PSCI v1.0, by this way we don't
need to adjust the stack pointer when more contents are saved.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
---
arch/arm/cpu/armv7/psci.S | 9 +++++----
arch/arm/include/asm/psci.h | 4 ++++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 3b92f1d..5b235df 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -259,7 +259,8 @@ ENTRY(psci_cpu_on_common)
mov r0, r1
bl psci_get_cpu_stack_top @ get stack top of target CPU
- str r2, [r0] @ store target PC at stack top
+ sub r5, r0, #PSCI_TARGET_PC_OFFSET
+ str r2, [r5] @ store target PC
dsb
pop {pc}
@@ -286,14 +287,13 @@ ENDPROC(psci_cpu_off_common)
@ expects CPU ID in r0 and returns stack top in r0
ENTRY(psci_get_cpu_stack_top)
- mov r5, #0x400 @ 1kB of stack per CPU
+ mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU
mul r0, r0, r5
ldr r5, =psci_text_end @ end of monitor text
add r5, r5, #0x2000 @ Skip two pages
lsr r5, r5, #12 @ Align to start of page
lsl r5, r5, #12
- sub r5, r5, #4 @ reserve 1 word for target PC
sub r0, r5, r0 @ here's our stack!
bx lr
@@ -306,7 +306,8 @@ ENTRY(psci_cpu_entry)
bl psci_get_cpu_id @ CPU ID => r0
bl psci_get_cpu_stack_top @ stack top => r0
- ldr r0, [r0] @ target PC at stack top
+ sub r0, r0, #PSCI_TARGET_PC_OFFSET
+ ldr r0, [r0] @ get target PC
b _do_nonsec_entry
ENDPROC(psci_cpu_entry)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 2367ec0..cb08544 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -63,6 +63,10 @@
#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
+/* size of percpu stack, 1kB */
+#define PSCI_PERCPU_STACK_SIZE 0x400
+#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
+
#ifndef __ASSEMBLY__
int psci_update_dt(void *fdt);
void psci_board_init(void);
--
2.1.4
^ permalink raw reply related [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC
2016-06-14 7:01 ` [U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC macro.wave.z at gmail.com
@ 2016-06-28 3:24 ` Chen-Yu Tsai
2016-06-28 9:23 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-28 3:24 UTC (permalink / raw)
To: u-boot
On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> The legacy code saves target PC at stack top, this patch changes it to stack
> bottom, because we will save more contents for PSCI v1.0, by this way we don't
> need to adjust the stack pointer when more contents are saved.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
> ---
> arch/arm/cpu/armv7/psci.S | 9 +++++----
> arch/arm/include/asm/psci.h | 4 ++++
> 2 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
> index 3b92f1d..5b235df 100644
> --- a/arch/arm/cpu/armv7/psci.S
> +++ b/arch/arm/cpu/armv7/psci.S
> @@ -259,7 +259,8 @@ ENTRY(psci_cpu_on_common)
>
> mov r0, r1
> bl psci_get_cpu_stack_top @ get stack top of target CPU
> - str r2, [r0] @ store target PC at stack top
> + sub r5, r0, #PSCI_TARGET_PC_OFFSET
> + str r2, [r5] @ store target PC
IMO having a separate function for this would be better.
It would be clearer, and easier to reuse or replace.
Also you should save and restore r5 across this function.
> dsb
>
> pop {pc}
> @@ -286,14 +287,13 @@ ENDPROC(psci_cpu_off_common)
>
> @ expects CPU ID in r0 and returns stack top in r0
> ENTRY(psci_get_cpu_stack_top)
> - mov r5, #0x400 @ 1kB of stack per CPU
> + mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU
> mul r0, r0, r5
>
> ldr r5, =psci_text_end @ end of monitor text
> add r5, r5, #0x2000 @ Skip two pages
> lsr r5, r5, #12 @ Align to start of page
> lsl r5, r5, #12
> - sub r5, r5, #4 @ reserve 1 word for target PC
> sub r0, r5, r0 @ here's our stack!
This does not apply. r5 was changed to r3.
>
> bx lr
> @@ -306,7 +306,8 @@ ENTRY(psci_cpu_entry)
>
> bl psci_get_cpu_id @ CPU ID => r0
> bl psci_get_cpu_stack_top @ stack top => r0
> - ldr r0, [r0] @ target PC at stack top
> + sub r0, r0, #PSCI_TARGET_PC_OFFSET
> + ldr r0, [r0] @ get target PC
> b _do_nonsec_entry
> ENDPROC(psci_cpu_entry)
>
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index 2367ec0..cb08544 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -63,6 +63,10 @@
> #define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
> #define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
>
> +/* size of percpu stack, 1kB */
> +#define PSCI_PERCPU_STACK_SIZE 0x400
> +#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
I think you want PSCI_PERCPU_STACK_SIZE?
A stack starts at 0x400 and goes down to 0x0. You want to store
the target PC at 0x0, not 0x4.
Regards
ChenYu
> +
> #ifndef __ASSEMBLY__
> int psci_update_dt(void *fdt);
> void psci_board_init(void);
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC
2016-06-28 3:24 ` Chen-Yu Tsai
@ 2016-06-28 9:23 ` Hongbo Zhang
2016-06-28 9:48 ` Chen-Yu Tsai
0 siblings, 1 reply; 34+ messages in thread
From: Hongbo Zhang @ 2016-06-28 9:23 UTC (permalink / raw)
To: u-boot
On Tue, Jun 28, 2016 at 11:24 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> The legacy code saves target PC at stack top, this patch changes it to stack
>> bottom, because we will save more contents for PSCI v1.0, by this way we don't
>> need to adjust the stack pointer when more contents are saved.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
>> ---
>> arch/arm/cpu/armv7/psci.S | 9 +++++----
>> arch/arm/include/asm/psci.h | 4 ++++
>> 2 files changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
>> index 3b92f1d..5b235df 100644
>> --- a/arch/arm/cpu/armv7/psci.S
>> +++ b/arch/arm/cpu/armv7/psci.S
>> @@ -259,7 +259,8 @@ ENTRY(psci_cpu_on_common)
>>
>> mov r0, r1
>> bl psci_get_cpu_stack_top @ get stack top of target CPU
>> - str r2, [r0] @ store target PC at stack top
>> + sub r5, r0, #PSCI_TARGET_PC_OFFSET
>> + str r2, [r5] @ store target PC
>
> IMO having a separate function for this would be better.
> It would be clearer, and easier to reuse or replace.
>
Renaming psci_cpu_on_common to psci_save_target_pc doesn't apply
because saving context id will be added.
Do you mean the psci_cpu_on_common calls two functions
psci_save_target_pc and psci_save_context_id?
> Also you should save and restore r5 across this function.
I did pay attention to this, and found that in the psci codes, general
purpose registers are used carefully without push/pop, and there is
example of using r5 without push/pop, so I just follow this pattern.
Sure saving register context makes it safer.
>
>> dsb
>>
>> pop {pc}
>> @@ -286,14 +287,13 @@ ENDPROC(psci_cpu_off_common)
>>
>> @ expects CPU ID in r0 and returns stack top in r0
>> ENTRY(psci_get_cpu_stack_top)
>> - mov r5, #0x400 @ 1kB of stack per CPU
>> + mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU
>> mul r0, r0, r5
>>
>> ldr r5, =psci_text_end @ end of monitor text
>> add r5, r5, #0x2000 @ Skip two pages
>> lsr r5, r5, #12 @ Align to start of page
>> lsl r5, r5, #12
>> - sub r5, r5, #4 @ reserve 1 word for target PC
>> sub r0, r5, r0 @ here's our stack!
>
> This does not apply. r5 was changed to r3.
>
I noticed you sent such a patch before, but when I sent out this patch
set, it wasn't pulled in.
Will re-check all the updates.
>>
>> bx lr
>> @@ -306,7 +306,8 @@ ENTRY(psci_cpu_entry)
>>
>> bl psci_get_cpu_id @ CPU ID => r0
>> bl psci_get_cpu_stack_top @ stack top => r0
>> - ldr r0, [r0] @ target PC at stack top
>> + sub r0, r0, #PSCI_TARGET_PC_OFFSET
>> + ldr r0, [r0] @ get target PC
>> b _do_nonsec_entry
>> ENDPROC(psci_cpu_entry)
>>
>> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
>> index 2367ec0..cb08544 100644
>> --- a/arch/arm/include/asm/psci.h
>> +++ b/arch/arm/include/asm/psci.h
>> @@ -63,6 +63,10 @@
>> #define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
>> #define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
>>
>> +/* size of percpu stack, 1kB */
>> +#define PSCI_PERCPU_STACK_SIZE 0x400
>> +#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
>
> I think you want PSCI_PERCPU_STACK_SIZE?
>
Yes.
> A stack starts at 0x400 and goes down to 0x0. You want to store
> the target PC at 0x0, not 0x4.
But there are more details here.
Suppose the stack bottom is 0x0 and stack size is 0x400, the top of
stack should be 0x3fc (32bits world, covering 4 bytes 0x3fc ~ 0x3ff),
0x400 is out of the stack range.
If the psci_get_stack_top returns 0x3fc, then (PSCI_PERCPU_STACK_SIZE
- 4) is right value.
But the psci_get_stack_top returns 0x400 actually, I've tried to
change the code to return value like 0x3fc but found out that it isn't
needed, because when push operation executed , sp is subtracted by 4
first and then data is saved into where pointed by the decreased sp.
So I canceled changed to stack top but forgot to update this macro definiation.
>
> Regards
> ChenYu
>
>> +
>> #ifndef __ASSEMBLY__
>> int psci_update_dt(void *fdt);
>> void psci_board_init(void);
>> --
>> 2.1.4
>>
^ permalink raw reply [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC
2016-06-28 9:23 ` Hongbo Zhang
@ 2016-06-28 9:48 ` Chen-Yu Tsai
0 siblings, 0 replies; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-28 9:48 UTC (permalink / raw)
To: u-boot
On Tue, Jun 28, 2016 at 5:23 PM, Hongbo Zhang <macro.wave.z@gmail.com> wrote:
> On Tue, Jun 28, 2016 at 11:24 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>
>>> The legacy code saves target PC at stack top, this patch changes it to stack
>>> bottom, because we will save more contents for PSCI v1.0, by this way we don't
>>> need to adjust the stack pointer when more contents are saved.
>>>
>>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>>> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
>>> ---
>>> arch/arm/cpu/armv7/psci.S | 9 +++++----
>>> arch/arm/include/asm/psci.h | 4 ++++
>>> 2 files changed, 9 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
>>> index 3b92f1d..5b235df 100644
>>> --- a/arch/arm/cpu/armv7/psci.S
>>> +++ b/arch/arm/cpu/armv7/psci.S
>>> @@ -259,7 +259,8 @@ ENTRY(psci_cpu_on_common)
>>>
>>> mov r0, r1
>>> bl psci_get_cpu_stack_top @ get stack top of target CPU
>>> - str r2, [r0] @ store target PC at stack top
>>> + sub r5, r0, #PSCI_TARGET_PC_OFFSET
>>> + str r2, [r5] @ store target PC
>>
>> IMO having a separate function for this would be better.
>> It would be clearer, and easier to reuse or replace.
>>
> Renaming psci_cpu_on_common to psci_save_target_pc doesn't apply
> because saving context id will be added.
> Do you mean the psci_cpu_on_common calls two functions
> psci_save_target_pc and psci_save_context_id?
That's the idea. Having common save/get helper functions for target
PC, context ID, power state, etc. which others can use in their
platform specific code should reduce duplicate code and make it
easier to maintain. The platform code shouldn't care how or where
this stuff is stored, as long as it can be reliably used. With
your patches they are stored at the bottom of the stack. With mine
they are moved to a secure data section.
>
>> Also you should save and restore r5 across this function.
>
> I did pay attention to this, and found that in the psci codes, general
> purpose registers are used carefully without push/pop, and there is
> example of using r5 without push/pop, so I just follow this pattern.
Originally the PSCI implementation was contained in one file, written
by one person. It was easy to check if registers were used. Now it's
split up into a number of files across different platforms, with sunxi
even using C. It's time to start paying attention to these details.
> Sure saving register context makes it safer.
Thanks. With sunxi C code, the compiler might use these registers,
and we might get weird issues after calling such a common function.
>
>>
>>> dsb
>>>
>>> pop {pc}
>>> @@ -286,14 +287,13 @@ ENDPROC(psci_cpu_off_common)
>>>
>>> @ expects CPU ID in r0 and returns stack top in r0
>>> ENTRY(psci_get_cpu_stack_top)
>>> - mov r5, #0x400 @ 1kB of stack per CPU
>>> + mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU
>>> mul r0, r0, r5
>>>
>>> ldr r5, =psci_text_end @ end of monitor text
>>> add r5, r5, #0x2000 @ Skip two pages
>>> lsr r5, r5, #12 @ Align to start of page
>>> lsl r5, r5, #12
>>> - sub r5, r5, #4 @ reserve 1 word for target PC
>>> sub r0, r5, r0 @ here's our stack!
>>
>> This does not apply. r5 was changed to r3.
>>
> I noticed you sent such a patch before, but when I sent out this patch
> set, it wasn't pulled in.
> Will re-check all the updates.
Thanks. The series was pulled in later than expected.
>>>
>>> bx lr
>>> @@ -306,7 +306,8 @@ ENTRY(psci_cpu_entry)
>>>
>>> bl psci_get_cpu_id @ CPU ID => r0
>>> bl psci_get_cpu_stack_top @ stack top => r0
>>> - ldr r0, [r0] @ target PC at stack top
>>> + sub r0, r0, #PSCI_TARGET_PC_OFFSET
>>> + ldr r0, [r0] @ get target PC
>>> b _do_nonsec_entry
>>> ENDPROC(psci_cpu_entry)
>>>
>>> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
>>> index 2367ec0..cb08544 100644
>>> --- a/arch/arm/include/asm/psci.h
>>> +++ b/arch/arm/include/asm/psci.h
>>> @@ -63,6 +63,10 @@
>>> #define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
>>> #define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
>>>
>>> +/* size of percpu stack, 1kB */
>>> +#define PSCI_PERCPU_STACK_SIZE 0x400
>>> +#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
>>
>> I think you want PSCI_PERCPU_STACK_SIZE?
>>
> Yes.
>
>> A stack starts at 0x400 and goes down to 0x0. You want to store
>> the target PC at 0x0, not 0x4.
> But there are more details here.
> Suppose the stack bottom is 0x0 and stack size is 0x400, the top of
> stack should be 0x3fc (32bits world, covering 4 bytes 0x3fc ~ 0x3ff),
> 0x400 is out of the stack range.
Let's define "stack top" as the address of SP when the stack is empty.
> If the psci_get_stack_top returns 0x3fc, then (PSCI_PERCPU_STACK_SIZE
> - 4) is right value.
> But the psci_get_stack_top returns 0x400 actually, I've tried to
> change the code to return value like 0x3fc but found out that it isn't
> needed, because when push operation executed , sp is subtracted by 4
> first and then data is saved into where pointed by the decreased sp.
> So I canceled changed to stack top but forgot to update this macro definiation.
Yes. You are right. This is what I alluded to.
Regards
ChenYu
>
>>
>> Regards
>> ChenYu
>>
>>> +
>>> #ifndef __ASSEMBLY__
>>> int psci_update_dt(void *fdt);
>>> void psci_board_init(void);
>>> --
>>> 2.1.4
>>>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 4/8] ARMv7: PSCI: add codes to save context ID for CPU_ON
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
` (2 preceding siblings ...)
2016-06-14 7:01 ` [U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC macro.wave.z at gmail.com
@ 2016-06-14 7:01 ` macro.wave.z at gmail.com
2016-06-28 3:15 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 5/8] ARMv7: PSCI: ls102xa: check target CPU ID before further operations macro.wave.z at gmail.com
` (4 subsequent siblings)
8 siblings, 1 reply; 34+ messages in thread
From: macro.wave.z at gmail.com @ 2016-06-14 7:01 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
According to latest PSCI specification, the context ID is needed by CPU_ON.
This patch saves context ID to the second lowest address of the stack (next to
where target PC is saved), and restores it to r0 when needed while target CPU
booting up.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
---
arch/arm/cpu/armv7/nonsec_virt.S | 7 +++++++
arch/arm/cpu/armv7/psci.S | 4 +++-
arch/arm/include/asm/psci.h | 1 +
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index b7563ed..6566643 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -11,6 +11,7 @@
#include <asm/gic.h>
#include <asm/armv7.h>
#include <asm/proc-armv/ptrace.h>
+#include <asm/psci.h>
.arch_extension sec
.arch_extension virt
@@ -89,6 +90,12 @@ _secure_monitor:
movne r4, #0
mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
1:
+#ifdef CONFIG_ARMV7_PSCI
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
+ ldr r0, [r0] @ get Context ID in r0
+#endif
mov lr, ip
mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
tst lr, #1 @ Check for Thumb PC
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 5b235df..3ba9e51 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -253,7 +253,7 @@ ENTRY(psci_enable_smp)
ENDPROC(psci_enable_smp)
.weak psci_enable_smp
-/* expects target CPU in r1, target PC in r2 */
+/* expects target CPU in r1, target PC in r2, target conetxt ID in r3 */
ENTRY(psci_cpu_on_common)
push {lr}
@@ -261,6 +261,8 @@ ENTRY(psci_cpu_on_common)
bl psci_get_cpu_stack_top @ get stack top of target CPU
sub r5, r0, #PSCI_TARGET_PC_OFFSET
str r2, [r5] @ store target PC
+ sub r5, r0, #PSCI_CONTEXT_ID_OFFSET
+ str r3, [r5] @ store target context ID
dsb
pop {pc}
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index cb08544..bedcd30 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -66,6 +66,7 @@
/* size of percpu stack, 1kB */
#define PSCI_PERCPU_STACK_SIZE 0x400
#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
+#define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
#ifndef __ASSEMBLY__
int psci_update_dt(void *fdt);
--
2.1.4
^ permalink raw reply related [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 4/8] ARMv7: PSCI: add codes to save context ID for CPU_ON
2016-06-14 7:01 ` [U-Boot] [PATCH v5 4/8] ARMv7: PSCI: add codes to save context ID for CPU_ON macro.wave.z at gmail.com
@ 2016-06-28 3:15 ` Chen-Yu Tsai
2016-06-28 10:29 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-28 3:15 UTC (permalink / raw)
To: u-boot
Hi,
On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> According to latest PSCI specification, the context ID is needed by CPU_ON.
> This patch saves context ID to the second lowest address of the stack (next to
> where target PC is saved), and restores it to r0 when needed while target CPU
> booting up.
Interesting. This doesn't seem to be used by Linux yet. This led me using r3
as a scratch register. See below.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
> ---
> arch/arm/cpu/armv7/nonsec_virt.S | 7 +++++++
> arch/arm/cpu/armv7/psci.S | 4 +++-
> arch/arm/include/asm/psci.h | 1 +
> 3 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
> index b7563ed..6566643 100644
> --- a/arch/arm/cpu/armv7/nonsec_virt.S
> +++ b/arch/arm/cpu/armv7/nonsec_virt.S
> @@ -11,6 +11,7 @@
> #include <asm/gic.h>
> #include <asm/armv7.h>
> #include <asm/proc-armv/ptrace.h>
> +#include <asm/psci.h>
>
> .arch_extension sec
> .arch_extension virt
> @@ -89,6 +90,12 @@ _secure_monitor:
> movne r4, #0
> mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
> 1:
> +#ifdef CONFIG_ARMV7_PSCI
> + bl psci_get_cpu_id
> + bl psci_get_cpu_stack_top
> + sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
> + ldr r0, [r0] @ get Context ID in r0
You should do this in psci_cpu_entry, for a couple of reasons:
- That is also where the target PC is loaded.
- It is PSCI specific.
- All first time SMC calls would go through _secure_monitor.
This includes when U-boot jumps into the kernel through
_do_nonsec_entry, at which point you don't have a proper value
stored, while U-boot passes 0 here. See:
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/lib/bootm.c;h=0838d89907b9a2eb81f4ebb31d8c045e031c5e11;hb=HEAD#l324
> +#endif
> mov lr, ip
> mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
> tst lr, #1 @ Check for Thumb PC
> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
> index 5b235df..3ba9e51 100644
> --- a/arch/arm/cpu/armv7/psci.S
> +++ b/arch/arm/cpu/armv7/psci.S
> @@ -253,7 +253,7 @@ ENTRY(psci_enable_smp)
> ENDPROC(psci_enable_smp)
> .weak psci_enable_smp
>
> -/* expects target CPU in r1, target PC in r2 */
> +/* expects target CPU in r1, target PC in r2, target conetxt ID in r3 */
> ENTRY(psci_cpu_on_common)
> push {lr}
>
> @@ -261,6 +261,8 @@ ENTRY(psci_cpu_on_common)
> bl psci_get_cpu_stack_top @ get stack top of target CPU
r3 get overwritten in psci_get_cpu_stack_top in
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=dae08d228122e4ad296077106520a4db3ca17872
Some of the functions now follow the ARM calling conventions.
You should save r3 and possibly other registers across any function
calls.
Regards
ChenYu
> sub r5, r0, #PSCI_TARGET_PC_OFFSET
> str r2, [r5] @ store target PC
> + sub r5, r0, #PSCI_CONTEXT_ID_OFFSET
> + str r3, [r5] @ store target context ID
> dsb
>
> pop {pc}
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index cb08544..bedcd30 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -66,6 +66,7 @@
> /* size of percpu stack, 1kB */
> #define PSCI_PERCPU_STACK_SIZE 0x400
> #define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
> +#define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
>
> #ifndef __ASSEMBLY__
> int psci_update_dt(void *fdt);
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 4/8] ARMv7: PSCI: add codes to save context ID for CPU_ON
2016-06-28 3:15 ` Chen-Yu Tsai
@ 2016-06-28 10:29 ` Hongbo Zhang
0 siblings, 0 replies; 34+ messages in thread
From: Hongbo Zhang @ 2016-06-28 10:29 UTC (permalink / raw)
To: u-boot
On Tue, Jun 28, 2016 at 11:15 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> Hi,
>
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> According to latest PSCI specification, the context ID is needed by CPU_ON.
>> This patch saves context ID to the second lowest address of the stack (next to
>> where target PC is saved), and restores it to r0 when needed while target CPU
>> booting up.
>
> Interesting. This doesn't seem to be used by Linux yet. This led me using r3
> as a scratch register. See below.
>
Context ID is introduced by PSCI v1.0, since we are adding v1.0
support, I think we should add this although Linux kernel doesn't use
this till now, it is spec.
And what's more, r0, r1, r2 are already used by current codes, and in
the spec paragraph 5.2.1:
"For PSCI functions that use only 32-bit parameters, the arguments are
passed in R0 to R3 (AArch32) or W0 to W3 (AArch64), with return values
in R0 or W0."
All of these make the r3 the only best register for context ID I think.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
>> ---
>> arch/arm/cpu/armv7/nonsec_virt.S | 7 +++++++
>> arch/arm/cpu/armv7/psci.S | 4 +++-
>> arch/arm/include/asm/psci.h | 1 +
>> 3 files changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
>> index b7563ed..6566643 100644
>> --- a/arch/arm/cpu/armv7/nonsec_virt.S
>> +++ b/arch/arm/cpu/armv7/nonsec_virt.S
>> @@ -11,6 +11,7 @@
>> #include <asm/gic.h>
>> #include <asm/armv7.h>
>> #include <asm/proc-armv/ptrace.h>
>> +#include <asm/psci.h>
>>
>> .arch_extension sec
>> .arch_extension virt
>> @@ -89,6 +90,12 @@ _secure_monitor:
>> movne r4, #0
>> mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
>> 1:
>> +#ifdef CONFIG_ARMV7_PSCI
>> + bl psci_get_cpu_id
>> + bl psci_get_cpu_stack_top
>> + sub r0, r0, #PSCI_CONTEXT_ID_OFFSET
>> + ldr r0, [r0] @ get Context ID in r0
>
> You should do this in psci_cpu_entry, for a couple of reasons:
>
Yes, thanks.
> - That is also where the target PC is loaded.
>
> - It is PSCI specific.
>
> - All first time SMC calls would go through _secure_monitor.
> This includes when U-boot jumps into the kernel through
> _do_nonsec_entry, at which point you don't have a proper value
> stored, while U-boot passes 0 here. See:
>
> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/lib/bootm.c;h=0838d89907b9a2eb81f4ebb31d8c045e031c5e11;hb=HEAD#l324
>
>> +#endif
>> mov lr, ip
>> mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
>> tst lr, #1 @ Check for Thumb PC
>> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
>> index 5b235df..3ba9e51 100644
>> --- a/arch/arm/cpu/armv7/psci.S
>> +++ b/arch/arm/cpu/armv7/psci.S
>> @@ -253,7 +253,7 @@ ENTRY(psci_enable_smp)
>> ENDPROC(psci_enable_smp)
>> .weak psci_enable_smp
>>
>> -/* expects target CPU in r1, target PC in r2 */
>> +/* expects target CPU in r1, target PC in r2, target conetxt ID in r3 */
>> ENTRY(psci_cpu_on_common)
>> push {lr}
>>
>> @@ -261,6 +261,8 @@ ENTRY(psci_cpu_on_common)
>> bl psci_get_cpu_stack_top @ get stack top of target CPU
>
> r3 get overwritten in psci_get_cpu_stack_top in
>
> http://git.denx.de/?p=u-boot.git;a=commitdiff;h=dae08d228122e4ad296077106520a4db3ca17872
>
> Some of the functions now follow the ARM calling conventions.
> You should save r3 and possibly other registers across any function
> calls.
>
OK, will consider register saving.
> Regards
> ChenYu
>
>> sub r5, r0, #PSCI_TARGET_PC_OFFSET
>> str r2, [r5] @ store target PC
>> + sub r5, r0, #PSCI_CONTEXT_ID_OFFSET
>> + str r3, [r5] @ store target context ID
>> dsb
>>
>> pop {pc}
>> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
>> index cb08544..bedcd30 100644
>> --- a/arch/arm/include/asm/psci.h
>> +++ b/arch/arm/include/asm/psci.h
>> @@ -66,6 +66,7 @@
>> /* size of percpu stack, 1kB */
>> #define PSCI_PERCPU_STACK_SIZE 0x400
>> #define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
>> +#define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
>>
>> #ifndef __ASSEMBLY__
>> int psci_update_dt(void *fdt);
>> --
>> 2.1.4
>>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 5/8] ARMv7: PSCI: ls102xa: check target CPU ID before further operations
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
` (3 preceding siblings ...)
2016-06-14 7:01 ` [U-Boot] [PATCH v5 4/8] ARMv7: PSCI: add codes to save context ID for CPU_ON macro.wave.z at gmail.com
@ 2016-06-14 7:01 ` macro.wave.z at gmail.com
2016-06-28 4:10 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON macro.wave.z at gmail.com
` (3 subsequent siblings)
8 siblings, 1 reply; 34+ messages in thread
From: macro.wave.z at gmail.com @ 2016-06-14 7:01 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/psci.S | 34 +++++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 548c507..a4482e4 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -25,6 +25,34 @@
#define ONE_MS (GENERIC_TIMER_CLK / 1000)
#define RESET_WAIT (30 * ONE_MS)
+.globl psci_check_target_cpu_id
+psci_check_target_cpu_id:
+ @ Get the real CPU number
+ and r0, r1, #0xff
+
+ @ Verify bit[31:24], bits must be zero.
+ tst r1, #0xff000000
+ bne out_psci_invalid_target_cpu_id
+
+ @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC.
+ tst r1, #0xff0000
+ bne out_psci_invalid_target_cpu_id
+
+ @ Verify Affinity level 1: Processors, should be in 0xf00 format.
+ lsr r1, r1, #8
+ teq r1, #0xf
+ bne out_psci_invalid_target_cpu_id
+
+ @ Verify Affinity level 0: CPU, only 0, 1 are valid values.
+ cmp r0, #2
+ bge out_psci_invalid_target_cpu_id
+
+ bx lr
+
+out_psci_invalid_target_cpu_id:
+ mov r0, #ARM_PSCI_RET_INVAL
+ bx lr
+
@ r1 = target CPU
@ r2 = target PC
.globl psci_cpu_on
@@ -33,7 +61,10 @@ psci_cpu_on:
@ Clear and Get the correct CPU number
@ r1 = 0xf01
- and r1, r1, #0xff
+ bl psci_check_target_cpu_id
+ cmp r0, #ARM_PSCI_RET_INVAL
+ beq out_psci_cpu_on
+ mov r1, r0
bl psci_cpu_on_common
@@ -98,6 +129,7 @@ holdoff_release:
@ Return
mov r0, #ARM_PSCI_RET_SUCCESS
+out_psci_cpu_on:
pop {lr}
bx lr
--
2.1.4
^ permalink raw reply related [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 5/8] ARMv7: PSCI: ls102xa: check target CPU ID before further operations
2016-06-14 7:01 ` [U-Boot] [PATCH v5 5/8] ARMv7: PSCI: ls102xa: check target CPU ID before further operations macro.wave.z at gmail.com
@ 2016-06-28 4:10 ` Chen-Yu Tsai
2016-06-28 10:39 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-28 4:10 UTC (permalink / raw)
To: u-boot
On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> The input parameter CPU ID needs to be validated before furher oprations such
> as CPU_ON, this patch introduces the function to do this.
>
> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> ---
> arch/arm/cpu/armv7/ls102xa/psci.S | 34 +++++++++++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
> index 548c507..a4482e4 100644
> --- a/arch/arm/cpu/armv7/ls102xa/psci.S
> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
> @@ -25,6 +25,34 @@
> #define ONE_MS (GENERIC_TIMER_CLK / 1000)
> #define RESET_WAIT (30 * ONE_MS)
>
A note describing the arguments, the return value, and any other affected
registers would be nice. For example r1 is clobbered.
> +.globl psci_check_target_cpu_id
> +psci_check_target_cpu_id:
You probably don't need .globl.
Also you can use ENTRY() or LENTRY() here. These and ENDPROC() below
are defined in linux/linkage.h
> + @ Get the real CPU number
> + and r0, r1, #0xff
> +
> + @ Verify bit[31:24], bits must be zero.
> + tst r1, #0xff000000
> + bne out_psci_invalid_target_cpu_id
> +
> + @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC.
> + tst r1, #0xff0000
> + bne out_psci_invalid_target_cpu_id
> +
> + @ Verify Affinity level 1: Processors, should be in 0xf00 format.
> + lsr r1, r1, #8
> + teq r1, #0xf
> + bne out_psci_invalid_target_cpu_id
> +
> + @ Verify Affinity level 0: CPU, only 0, 1 are valid values.
> + cmp r0, #2
> + bge out_psci_invalid_target_cpu_id
> +
> + bx lr
> +
> +out_psci_invalid_target_cpu_id:
> + mov r0, #ARM_PSCI_RET_INVAL
> + bx lr
> +
And you could have an ENDPROC() here.
About the whole function, you could use an extra scratch register,
store ARM_PSCI_RET_INVAL in r0 at the beginning, and directly return
at errors. Kind of like:
if (bit[31:24] != 0)
return ARM_PSCI_RET_INVAL;
if (cluster != 0)
return ARM_PSCI_RET_INVAL;
if (processor != 0xf)
return ARM_PSCI_RET_INVAL;
if (cpu >= 2)
return ARM_PSCI_RET_INVAL;
return cpu;
It's just a different style though. Feel free to keep the current
structure.
The code itself looks good.
Regards
ChenYu
> @ r1 = target CPU
> @ r2 = target PC
> .globl psci_cpu_on
> @@ -33,7 +61,10 @@ psci_cpu_on:
>
> @ Clear and Get the correct CPU number
> @ r1 = 0xf01
> - and r1, r1, #0xff
> + bl psci_check_target_cpu_id
> + cmp r0, #ARM_PSCI_RET_INVAL
> + beq out_psci_cpu_on
> + mov r1, r0
>
> bl psci_cpu_on_common
>
> @@ -98,6 +129,7 @@ holdoff_release:
> @ Return
> mov r0, #ARM_PSCI_RET_SUCCESS
>
> +out_psci_cpu_on:
> pop {lr}
> bx lr
>
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 5/8] ARMv7: PSCI: ls102xa: check target CPU ID before further operations
2016-06-28 4:10 ` Chen-Yu Tsai
@ 2016-06-28 10:39 ` Hongbo Zhang
0 siblings, 0 replies; 34+ messages in thread
From: Hongbo Zhang @ 2016-06-28 10:39 UTC (permalink / raw)
To: u-boot
On Tue, Jun 28, 2016 at 12:10 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> The input parameter CPU ID needs to be validated before furher oprations such
>> as CPU_ON, this patch introduces the function to do this.
>>
>> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> ---
>> arch/arm/cpu/armv7/ls102xa/psci.S | 34 +++++++++++++++++++++++++++++++++-
>> 1 file changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
>> index 548c507..a4482e4 100644
>> --- a/arch/arm/cpu/armv7/ls102xa/psci.S
>> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
>> @@ -25,6 +25,34 @@
>> #define ONE_MS (GENERIC_TIMER_CLK / 1000)
>> #define RESET_WAIT (30 * ONE_MS)
>>
>
> A note describing the arguments, the return value, and any other affected
> registers would be nice. For example r1 is clobbered.
Good suggestion, thanks.
>
>> +.globl psci_check_target_cpu_id
>> +psci_check_target_cpu_id:
>
> You probably don't need .globl.
>
Oh, this is due to a carelessness.
> Also you can use ENTRY() or LENTRY() here. These and ENDPROC() below
> are defined in linux/linkage.h
>
Yes, sure.
>> + @ Get the real CPU number
>> + and r0, r1, #0xff
>> +
>> + @ Verify bit[31:24], bits must be zero.
>> + tst r1, #0xff000000
>> + bne out_psci_invalid_target_cpu_id
>> +
>> + @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC.
>> + tst r1, #0xff0000
>> + bne out_psci_invalid_target_cpu_id
>> +
>> + @ Verify Affinity level 1: Processors, should be in 0xf00 format.
>> + lsr r1, r1, #8
>> + teq r1, #0xf
>> + bne out_psci_invalid_target_cpu_id
>> +
>> + @ Verify Affinity level 0: CPU, only 0, 1 are valid values.
>> + cmp r0, #2
>> + bge out_psci_invalid_target_cpu_id
>> +
>> + bx lr
>> +
>> +out_psci_invalid_target_cpu_id:
>> + mov r0, #ARM_PSCI_RET_INVAL
>> + bx lr
>> +
>
> And you could have an ENDPROC() here.
>
> About the whole function, you could use an extra scratch register,
> store ARM_PSCI_RET_INVAL in r0 at the beginning, and directly return
> at errors. Kind of like:
>
> if (bit[31:24] != 0)
> return ARM_PSCI_RET_INVAL;
> if (cluster != 0)
> return ARM_PSCI_RET_INVAL;
> if (processor != 0xf)
> return ARM_PSCI_RET_INVAL;
> if (cpu >= 2)
> return ARM_PSCI_RET_INVAL;
> return cpu;
>
> It's just a different style though. Feel free to keep the current
> structure.
Yes, thanks.
>
> The code itself looks good.
>
> Regards
> ChenYu
>
>> @ r1 = target CPU
>> @ r2 = target PC
>> .globl psci_cpu_on
>> @@ -33,7 +61,10 @@ psci_cpu_on:
>>
>> @ Clear and Get the correct CPU number
>> @ r1 = 0xf01
>> - and r1, r1, #0xff
>> + bl psci_check_target_cpu_id
>> + cmp r0, #ARM_PSCI_RET_INVAL
>> + beq out_psci_cpu_on
>> + mov r1, r0
>>
>> bl psci_cpu_on_common
>>
>> @@ -98,6 +129,7 @@ holdoff_release:
>> @ Return
>> mov r0, #ARM_PSCI_RET_SUCCESS
>>
>> +out_psci_cpu_on:
>> pop {lr}
>> bx lr
>>
>> --
>> 2.1.4
>>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
` (4 preceding siblings ...)
2016-06-14 7:01 ` [U-Boot] [PATCH v5 5/8] ARMv7: PSCI: ls102xa: check target CPU ID before further operations macro.wave.z at gmail.com
@ 2016-06-14 7:01 ` macro.wave.z at gmail.com
2016-06-28 4:30 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 7/8] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention macro.wave.z at gmail.com
` (2 subsequent siblings)
8 siblings, 1 reply; 34+ messages in thread
From: macro.wave.z at gmail.com @ 2016-06-14 7:01 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
For the robustness of codes, while powering on a CPU, it is better to check
if the target CPU is already on or in the process of power on, if yes the
power on routine shouldn't be executed further and should return with the
corresponding status immediately.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/psci.S | 29 +++++++++++++++++++++++++++++
arch/arm/include/asm/psci.h | 5 +++++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index a4482e4..0188ade 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -66,6 +66,22 @@ psci_cpu_on:
beq out_psci_cpu_on
mov r1, r0
+ bl psci_get_cpu_stack_top
+ sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+ ldr r5, [r0]
+
+ cmp r5, #PSCI_CPU_STATUS_ON
+ moveq r0, #ARM_PSCI_RET_ALREADY_ON
+ beq out_psci_cpu_on
+
+ cmp r5, #PSCI_CPU_STATUS_ON_PENDING
+ moveq r0, #ARM_PSCI_RET_ON_PENDING
+ beq out_psci_cpu_on
+
+ mov r5, #PSCI_CPU_STATUS_ON_PENDING
+ str r5, [r0]
+ dsb
+
bl psci_cpu_on_common
@ Get DCFG base address
@@ -123,6 +139,12 @@ holdoff_release:
rev r6, r6
str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
+ mov r0, r1
+ bl psci_get_cpu_stack_top
+ sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+ mov r5, #PSCI_CPU_STATUS_ON
+ str r5, [r0]
+
isb
dsb
@@ -137,6 +159,13 @@ out_psci_cpu_on:
psci_cpu_off:
bl psci_cpu_off_common
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ sub r0, r0, #PSCI_CPU_STATUS_OFFSET
+ mov r5, #PSCI_CPU_STATUS_OFF
+ str r5, [r0]
+ dsb
+
1: wfi
b 1b
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index bedcd30..89a1ba5 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -67,6 +67,11 @@
#define PSCI_PERCPU_STACK_SIZE 0x400
#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
#define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
+#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)
+
+#define PSCI_CPU_STATUS_OFF 0
+#define PSCI_CPU_STATUS_ON 1
+#define PSCI_CPU_STATUS_ON_PENDING 2
#ifndef __ASSEMBLY__
int psci_update_dt(void *fdt);
--
2.1.4
^ permalink raw reply related [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
2016-06-14 7:01 ` [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON macro.wave.z at gmail.com
@ 2016-06-28 4:30 ` Chen-Yu Tsai
2016-06-30 4:24 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-28 4:30 UTC (permalink / raw)
To: u-boot
On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> For the robustness of codes, while powering on a CPU, it is better to check
> if the target CPU is already on or in the process of power on, if yes the
> power on routine shouldn't be executed further and should return with the
> corresponding status immediately.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> ---
> arch/arm/cpu/armv7/ls102xa/psci.S | 29 +++++++++++++++++++++++++++++
> arch/arm/include/asm/psci.h | 5 +++++
> 2 files changed, 34 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
> index a4482e4..0188ade 100644
> --- a/arch/arm/cpu/armv7/ls102xa/psci.S
> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
> @@ -66,6 +66,22 @@ psci_cpu_on:
> beq out_psci_cpu_on
> mov r1, r0
>
> + bl psci_get_cpu_stack_top
> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
> + ldr r5, [r0]
> +
> + cmp r5, #PSCI_CPU_STATUS_ON
> + moveq r0, #ARM_PSCI_RET_ALREADY_ON
> + beq out_psci_cpu_on
> +
> + cmp r5, #PSCI_CPU_STATUS_ON_PENDING
> + moveq r0, #ARM_PSCI_RET_ON_PENDING
> + beq out_psci_cpu_on
> +
> + mov r5, #PSCI_CPU_STATUS_ON_PENDING
> + str r5, [r0]
> + dsb
> +
> bl psci_cpu_on_common
>
> @ Get DCFG base address
> @@ -123,6 +139,12 @@ holdoff_release:
> rev r6, r6
> str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
>
> + mov r0, r1
> + bl psci_get_cpu_stack_top
> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
> + mov r5, #PSCI_CPU_STATUS_ON
> + str r5, [r0]
> +
> isb
> dsb
>
> @@ -137,6 +159,13 @@ out_psci_cpu_on:
> psci_cpu_off:
> bl psci_cpu_off_common
>
> + bl psci_get_cpu_id
> + bl psci_get_cpu_stack_top
> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
> + mov r5, #PSCI_CPU_STATUS_OFF
> + str r5, [r0]
> + dsb
psci_cpu_off_common flushes and disables caches, and turns off SMP.
So the code you're adding might not work as expected? ARM folks
might know more.
The rest looks good, though I expect them to be pulled out into
common helpers and rewritten in C. :)
Regards
ChenYu
> +
> 1: wfi
> b 1b
>
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index bedcd30..89a1ba5 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -67,6 +67,11 @@
> #define PSCI_PERCPU_STACK_SIZE 0x400
> #define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
> #define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
> +#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)
> +
> +#define PSCI_CPU_STATUS_OFF 0
> +#define PSCI_CPU_STATUS_ON 1
> +#define PSCI_CPU_STATUS_ON_PENDING 2
>
> #ifndef __ASSEMBLY__
> int psci_update_dt(void *fdt);
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
2016-06-28 4:30 ` Chen-Yu Tsai
@ 2016-06-30 4:24 ` Hongbo Zhang
2016-06-30 14:47 ` Chen-Yu Tsai
0 siblings, 1 reply; 34+ messages in thread
From: Hongbo Zhang @ 2016-06-30 4:24 UTC (permalink / raw)
To: u-boot
On Tue, Jun 28, 2016 at 12:30 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> For the robustness of codes, while powering on a CPU, it is better to check
>> if the target CPU is already on or in the process of power on, if yes the
>> power on routine shouldn't be executed further and should return with the
>> corresponding status immediately.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> ---
>> arch/arm/cpu/armv7/ls102xa/psci.S | 29 +++++++++++++++++++++++++++++
>> arch/arm/include/asm/psci.h | 5 +++++
>> 2 files changed, 34 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
>> index a4482e4..0188ade 100644
>> --- a/arch/arm/cpu/armv7/ls102xa/psci.S
>> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
>> @@ -66,6 +66,22 @@ psci_cpu_on:
>> beq out_psci_cpu_on
>> mov r1, r0
>>
>> + bl psci_get_cpu_stack_top
>> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
>> + ldr r5, [r0]
>> +
>> + cmp r5, #PSCI_CPU_STATUS_ON
>> + moveq r0, #ARM_PSCI_RET_ALREADY_ON
>> + beq out_psci_cpu_on
>> +
>> + cmp r5, #PSCI_CPU_STATUS_ON_PENDING
>> + moveq r0, #ARM_PSCI_RET_ON_PENDING
>> + beq out_psci_cpu_on
>> +
>> + mov r5, #PSCI_CPU_STATUS_ON_PENDING
>> + str r5, [r0]
>> + dsb
>> +
>> bl psci_cpu_on_common
>>
>> @ Get DCFG base address
>> @@ -123,6 +139,12 @@ holdoff_release:
>> rev r6, r6
>> str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
>>
>> + mov r0, r1
>> + bl psci_get_cpu_stack_top
>> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
>> + mov r5, #PSCI_CPU_STATUS_ON
>> + str r5, [r0]
>> +
>> isb
>> dsb
>>
>> @@ -137,6 +159,13 @@ out_psci_cpu_on:
>> psci_cpu_off:
>> bl psci_cpu_off_common
>>
>> + bl psci_get_cpu_id
>> + bl psci_get_cpu_stack_top
>> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
>> + mov r5, #PSCI_CPU_STATUS_OFF
>> + str r5, [r0]
>> + dsb
>
> psci_cpu_off_common flushes and disables caches, and turns off SMP.
> So the code you're adding might not work as expected? ARM folks
> might know more.
>
Moving this code ahead of psci_cpu_off_common seems better?
I just though such a code should be placed as later as it can.
> The rest looks good, though I expect them to be pulled out into
> common helpers and rewritten in C. :)
>
> Regards
> ChenYu
>
>> +
>> 1: wfi
>> b 1b
>>
>> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
>> index bedcd30..89a1ba5 100644
>> --- a/arch/arm/include/asm/psci.h
>> +++ b/arch/arm/include/asm/psci.h
>> @@ -67,6 +67,11 @@
>> #define PSCI_PERCPU_STACK_SIZE 0x400
>> #define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
>> #define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
>> +#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)
>> +
>> +#define PSCI_CPU_STATUS_OFF 0
>> +#define PSCI_CPU_STATUS_ON 1
>> +#define PSCI_CPU_STATUS_ON_PENDING 2
>>
>> #ifndef __ASSEMBLY__
>> int psci_update_dt(void *fdt);
>> --
>> 2.1.4
>>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
2016-06-30 4:24 ` Hongbo Zhang
@ 2016-06-30 14:47 ` Chen-Yu Tsai
0 siblings, 0 replies; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-30 14:47 UTC (permalink / raw)
To: u-boot
On Thu, Jun 30, 2016 at 12:24 PM, Hongbo Zhang <macro.wave.z@gmail.com> wrote:
> On Tue, Jun 28, 2016 at 12:30 PM, Chen-Yu Tsai <wens@csie.org> wrote:
>> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>
>>> For the robustness of codes, while powering on a CPU, it is better to check
>>> if the target CPU is already on or in the process of power on, if yes the
>>> power on routine shouldn't be executed further and should return with the
>>> corresponding status immediately.
>>>
>>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>>> ---
>>> arch/arm/cpu/armv7/ls102xa/psci.S | 29 +++++++++++++++++++++++++++++
>>> arch/arm/include/asm/psci.h | 5 +++++
>>> 2 files changed, 34 insertions(+)
>>>
>>> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
>>> index a4482e4..0188ade 100644
>>> --- a/arch/arm/cpu/armv7/ls102xa/psci.S
>>> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
>>> @@ -66,6 +66,22 @@ psci_cpu_on:
>>> beq out_psci_cpu_on
>>> mov r1, r0
>>>
>>> + bl psci_get_cpu_stack_top
>>> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
>>> + ldr r5, [r0]
>>> +
>>> + cmp r5, #PSCI_CPU_STATUS_ON
>>> + moveq r0, #ARM_PSCI_RET_ALREADY_ON
>>> + beq out_psci_cpu_on
>>> +
>>> + cmp r5, #PSCI_CPU_STATUS_ON_PENDING
>>> + moveq r0, #ARM_PSCI_RET_ON_PENDING
>>> + beq out_psci_cpu_on
>>> +
>>> + mov r5, #PSCI_CPU_STATUS_ON_PENDING
>>> + str r5, [r0]
>>> + dsb
>>> +
>>> bl psci_cpu_on_common
>>>
>>> @ Get DCFG base address
>>> @@ -123,6 +139,12 @@ holdoff_release:
>>> rev r6, r6
>>> str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
>>>
>>> + mov r0, r1
>>> + bl psci_get_cpu_stack_top
>>> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
>>> + mov r5, #PSCI_CPU_STATUS_ON
>>> + str r5, [r0]
>>> +
>>> isb
>>> dsb
>>>
>>> @@ -137,6 +159,13 @@ out_psci_cpu_on:
>>> psci_cpu_off:
>>> bl psci_cpu_off_common
>>>
>>> + bl psci_get_cpu_id
>>> + bl psci_get_cpu_stack_top
>>> + sub r0, r0, #PSCI_CPU_STATUS_OFFSET
>>> + mov r5, #PSCI_CPU_STATUS_OFF
>>> + str r5, [r0]
>>> + dsb
>>
>> psci_cpu_off_common flushes and disables caches, and turns off SMP.
>> So the code you're adding might not work as expected? ARM folks
>> might know more.
>>
> Moving this code ahead of psci_cpu_off_common seems better?
> I just though such a code should be placed as later as it can.
I agree it should be as late as possible. I'm just not sure about
the cache and AMP/SMP settings. Best to have someone more familiar
with this comment on it.
ChenYu
>> The rest looks good, though I expect them to be pulled out into
>> common helpers and rewritten in C. :)
>>
>> Regards
>> ChenYu
>>
>>> +
>>> 1: wfi
>>> b 1b
>>>
>>> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
>>> index bedcd30..89a1ba5 100644
>>> --- a/arch/arm/include/asm/psci.h
>>> +++ b/arch/arm/include/asm/psci.h
>>> @@ -67,6 +67,11 @@
>>> #define PSCI_PERCPU_STACK_SIZE 0x400
>>> #define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)
>>> #define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)
>>> +#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)
>>> +
>>> +#define PSCI_CPU_STATUS_OFF 0
>>> +#define PSCI_CPU_STATUS_ON 1
>>> +#define PSCI_CPU_STATUS_ON_PENDING 2
>>>
>>> #ifndef __ASSEMBLY__
>>> int psci_update_dt(void *fdt);
>>> --
>>> 2.1.4
>>>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 7/8] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
` (5 preceding siblings ...)
2016-06-14 7:01 ` [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON macro.wave.z at gmail.com
@ 2016-06-14 7:01 ` macro.wave.z at gmail.com
2016-06-30 14:45 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM macro.wave.z at gmail.com
2016-06-15 7:16 ` [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support Chen-Yu Tsai
8 siblings, 1 reply; 34+ messages in thread
From: macro.wave.z at gmail.com @ 2016-06-14 7:01 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.
Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/psci.S | 105 +++++++++++++++++++++++++++--
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
arch/arm/include/asm/psci.h | 5 ++
board/freescale/ls1021aqds/Makefile | 1 +
board/freescale/ls1021aqds/psci.S | 36 ++++++++++
board/freescale/ls1021atwr/Makefile | 1 +
board/freescale/ls1021atwr/psci.S | 28 ++++++++
include/configs/ls1021aqds.h | 3 +
include/configs/ls1021atwr.h | 1 +
9 files changed, 177 insertions(+), 4 deletions(-)
create mode 100644 board/freescale/ls1021aqds/psci.S
create mode 100644 board/freescale/ls1021atwr/psci.S
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 0188ade..084f914 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -12,19 +12,72 @@
#include <asm/arch-armv7/generictimer.h>
#include <asm/psci.h>
+#define RCPM_TWAITSR 0x04C
+
#define SCFG_CORE0_SFT_RST 0x130
#define SCFG_CORESRENCR 0x204
-#define DCFG_CCSR_BRR 0x0E4
-#define DCFG_CCSR_SCRATCHRW1 0x200
+#define DCFG_CCSR_RSTCR 0x0B0
+#define DCFG_CCSR_RSTCR_RESET_REQ 0x2
+#define DCFG_CCSR_BRR 0x0E4
+#define DCFG_CCSR_SCRATCHRW1 0x200
+
+#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
+#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
+#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
+#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
+#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
+#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
.pushsection ._secure.text, "ax"
.arch_extension sec
+ .align 5
+
#define ONE_MS (GENERIC_TIMER_CLK / 1000)
#define RESET_WAIT (30 * ONE_MS)
+.globl psci_version
+psci_version:
+ movw r0, #0
+ movt r0, #1
+
+ bx lr
+
+_ls102x_psci_supported_table:
+ .word ARM_PSCI_0_2_FN_PSCI_VERSION
+ .word PSCI_FN_PSCI_VERSION_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_CPU_SUSPEND
+ .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_CPU_OFF
+ .word PSCI_FN_CPU_OFF_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_CPU_ON
+ .word PSCI_FN_CPU_ON_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_AFFINITY_INFO
+ .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_SYSTEM_OFF
+ .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
+ .word ARM_PSCI_0_2_FN_SYSTEM_RESET
+ .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
+ .word 0
+ .word ARM_PSCI_RET_NI
+
+.globl psci_features
+psci_features:
+ adr r2, _ls102x_psci_supported_table
+1: ldr r3, [r2]
+ cmp r3, #0
+ beq out_psci_features
+ cmp r1, r3
+ addne r2, r2, #8
+ bne 1b
+
+out_psci_features:
+ ldr r0, [r2, #4]
+ bx lr
+
.globl psci_check_target_cpu_id
psci_check_target_cpu_id:
@ Get the real CPU number
@@ -169,6 +222,52 @@ psci_cpu_off:
1: wfi
b 1b
+.globl psci_affinity_info
+psci_affinity_info:
+ push {lr}
+
+ mov r0, #ARM_PSCI_RET_INVAL
+
+ @ Verify Affinity level
+ cmp r2, #0
+ bne out_affinity_info
+
+ bl psci_check_target_cpu_id
+ cmp r0, #ARM_PSCI_RET_INVAL
+ beq out_affinity_info
+ mov r1, r0
+
+ @ Get RCPM base address
+ movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
+ movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+
+ mov r0, #PSCI_AFFINITY_LEVEL_ON
+
+ @ Detect target CPU state
+ ldr r2, [r4, #RCPM_TWAITSR]
+ rev r2, r2
+ lsr r2, r2, r1
+ ands r2, r2, #1
+ beq out_affinity_info
+
+ mov r0, #PSCI_AFFINITY_LEVEL_OFF
+
+out_affinity_info:
+ pop {pc}
+
+.globl psci_system_reset
+psci_system_reset:
+ @ Get DCFG base address
+ movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+
+ mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
+ rev r2, r2
+ str r2, [r1, #DCFG_CCSR_RSTCR]
+
+1: wfi
+ b 1b
+
.globl psci_arch_init
psci_arch_init:
mov r6, lr
@@ -179,6 +278,4 @@ psci_arch_init:
bx r6
- .globl psci_text_end
-psci_text_end:
.popsection
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 04abec4..7a0e4bf 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -32,6 +32,7 @@
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 89a1ba5..1c6d819 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -73,6 +73,11 @@
#define PSCI_CPU_STATUS_ON 1
#define PSCI_CPU_STATUS_ON_PENDING 2
+/* PSCI affinity level state returned by AFFINITY_INFO */
+#define PSCI_AFFINITY_LEVEL_ON 0
+#define PSCI_AFFINITY_LEVEL_OFF 1
+#define PSCI_AFFINITY_LEVEL_ON_PENDING 2
+
#ifndef __ASSEMBLY__
int psci_update_dt(void *fdt);
void psci_board_init(void);
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index ab02344..f0390c1 100644
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -8,3 +8,4 @@ obj-y += ls1021aqds.o
obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aqds/psci.S b/board/freescale/ls1021aqds/psci.S
new file mode 100644
index 0000000..6b75595
--- /dev/null
+++ b/board/freescale/ls1021aqds/psci.S
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+ .align 5
+
+.globl psci_system_off
+psci_system_off:
+ @ Get QIXIS base address
+ movw r1, #(QIXIS_BASE & 0xffff)
+ movt r1, #(QIXIS_BASE >> 16)
+
+ ldrb r2, [r1, #QIXIS_PWR_CTL]
+ orr r2, r2, #QIXIS_PWR_CTL_POWEROFF
+ strb r2, [r1, #QIXIS_PWR_CTL]
+
+1: wfi
+ b 1b
+
+.globl psci_text_end
+psci_text_end:
+ nop
+ .popsection
diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile
index 01296c0..5238b15 100644
--- a/board/freescale/ls1021atwr/Makefile
+++ b/board/freescale/ls1021atwr/Makefile
@@ -6,3 +6,4 @@
obj-y += ls1021atwr.o
obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S
new file mode 100644
index 0000000..adf5b85
--- /dev/null
+++ b/board/freescale/ls1021atwr/psci.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+ .align 5
+
+.globl psci_system_off
+psci_system_off:
+1: wfi
+ b 1b
+
+.globl psci_text_end
+psci_text_end:
+ nop
+ .popsection
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index db684d2..2359fb0 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -10,6 +10,7 @@
#define CONFIG_LS102XA
#define CONFIG_ARMV7_PSCI
+#define CONFIG_ARMV7_PSCI_1_0
#define CONFIG_SYS_FSL_CLK
@@ -279,6 +280,8 @@ unsigned long get_board_ddr_clk(void);
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_PWR_CTL 0x21
+#define QIXIS_PWR_CTL_POWEROFF 0x80
#define QIXIS_RST_CTL_RESET 0x44
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 0fb28ef..9d0c4fe 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -10,6 +10,7 @@
#define CONFIG_LS102XA
#define CONFIG_ARMV7_PSCI
+#define CONFIG_ARMV7_PSCI_1_0
#define CONFIG_SYS_FSL_CLK
--
2.1.4
^ permalink raw reply related [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 7/8] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
2016-06-14 7:01 ` [U-Boot] [PATCH v5 7/8] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention macro.wave.z at gmail.com
@ 2016-06-30 14:45 ` Chen-Yu Tsai
0 siblings, 0 replies; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-30 14:45 UTC (permalink / raw)
To: u-boot
On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
> they are as the list:
> psci_version,
> psci_features,
> psci_cpu_suspend,
> psci_affinity_info,
> psci_system_reset,
> psci_system_off.
>
> Tested on LS1021aQDS, LS1021aTWR.
>
> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> ---
> arch/arm/cpu/armv7/ls102xa/psci.S | 105 +++++++++++++++++++++++++++--
> arch/arm/include/asm/arch-ls102xa/config.h | 1 +
> arch/arm/include/asm/psci.h | 5 ++
> board/freescale/ls1021aqds/Makefile | 1 +
> board/freescale/ls1021aqds/psci.S | 36 ++++++++++
> board/freescale/ls1021atwr/Makefile | 1 +
> board/freescale/ls1021atwr/psci.S | 28 ++++++++
> include/configs/ls1021aqds.h | 3 +
> include/configs/ls1021atwr.h | 1 +
> 9 files changed, 177 insertions(+), 4 deletions(-)
> create mode 100644 board/freescale/ls1021aqds/psci.S
> create mode 100644 board/freescale/ls1021atwr/psci.S
>
> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
> index 0188ade..084f914 100644
> --- a/arch/arm/cpu/armv7/ls102xa/psci.S
> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
> @@ -12,19 +12,72 @@
> #include <asm/arch-armv7/generictimer.h>
> #include <asm/psci.h>
>
> +#define RCPM_TWAITSR 0x04C
> +
> #define SCFG_CORE0_SFT_RST 0x130
> #define SCFG_CORESRENCR 0x204
>
> -#define DCFG_CCSR_BRR 0x0E4
> -#define DCFG_CCSR_SCRATCHRW1 0x200
> +#define DCFG_CCSR_RSTCR 0x0B0
> +#define DCFG_CCSR_RSTCR_RESET_REQ 0x2
> +#define DCFG_CCSR_BRR 0x0E4
> +#define DCFG_CCSR_SCRATCHRW1 0x200
> +
> +#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
> +#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
> +#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
> +#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
> +#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
> +#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
> +#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
>
> .pushsection ._secure.text, "ax"
>
> .arch_extension sec
>
> + .align 5
> +
> #define ONE_MS (GENERIC_TIMER_CLK / 1000)
> #define RESET_WAIT (30 * ONE_MS)
>
> +.globl psci_version
> +psci_version:
> + movw r0, #0
> + movt r0, #1
> +
> + bx lr
> +
> +_ls102x_psci_supported_table:
> + .word ARM_PSCI_0_2_FN_PSCI_VERSION
> + .word PSCI_FN_PSCI_VERSION_FEATURE_MASK
> + .word ARM_PSCI_0_2_FN_CPU_SUSPEND
> + .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
> + .word ARM_PSCI_0_2_FN_CPU_OFF
> + .word PSCI_FN_CPU_OFF_FEATURE_MASK
> + .word ARM_PSCI_0_2_FN_CPU_ON
> + .word PSCI_FN_CPU_ON_FEATURE_MASK
> + .word ARM_PSCI_0_2_FN_AFFINITY_INFO
> + .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
> + .word ARM_PSCI_0_2_FN_SYSTEM_OFF
> + .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
> + .word ARM_PSCI_0_2_FN_SYSTEM_RESET
> + .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
> + .word 0
> + .word ARM_PSCI_RET_NI
> +
> +.globl psci_features
> +psci_features:
> + adr r2, _ls102x_psci_supported_table
> +1: ldr r3, [r2]
> + cmp r3, #0
> + beq out_psci_features
> + cmp r1, r3
> + addne r2, r2, #8
> + bne 1b
> +
> +out_psci_features:
> + ldr r0, [r2, #4]
> + bx lr
> +
> .globl psci_check_target_cpu_id
> psci_check_target_cpu_id:
> @ Get the real CPU number
> @@ -169,6 +222,52 @@ psci_cpu_off:
> 1: wfi
> b 1b
>
> +.globl psci_affinity_info
> +psci_affinity_info:
> + push {lr}
> +
> + mov r0, #ARM_PSCI_RET_INVAL
> +
> + @ Verify Affinity level
> + cmp r2, #0
> + bne out_affinity_info
> +
> + bl psci_check_target_cpu_id
> + cmp r0, #ARM_PSCI_RET_INVAL
> + beq out_affinity_info
> + mov r1, r0
> +
> + @ Get RCPM base address
> + movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
> + movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
> +
> + mov r0, #PSCI_AFFINITY_LEVEL_ON
> +
> + @ Detect target CPU state
> + ldr r2, [r4, #RCPM_TWAITSR]
> + rev r2, r2
> + lsr r2, r2, r1
> + ands r2, r2, #1
tst should suffice.
> + beq out_affinity_info
> +
> + mov r0, #PSCI_AFFINITY_LEVEL_OFF
> +
> +out_affinity_info:
> + pop {pc}
> +
> +.globl psci_system_reset
> +psci_system_reset:
> + @ Get DCFG base address
> + movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
> + movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
> +
> + mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
> + rev r2, r2
> + str r2, [r1, #DCFG_CCSR_RSTCR]
> +
> +1: wfi
> + b 1b
> +
> .globl psci_arch_init
> psci_arch_init:
> mov r6, lr
> @@ -179,6 +278,4 @@ psci_arch_init:
>
> bx r6
>
> - .globl psci_text_end
> -psci_text_end:
> .popsection
> diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
> index 04abec4..7a0e4bf 100644
> --- a/arch/arm/include/asm/arch-ls102xa/config.h
> +++ b/arch/arm/include/asm/arch-ls102xa/config.h
> @@ -32,6 +32,7 @@
> #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
> #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
> #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
> +#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
> #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
> #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
> #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index 89a1ba5..1c6d819 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -73,6 +73,11 @@
> #define PSCI_CPU_STATUS_ON 1
> #define PSCI_CPU_STATUS_ON_PENDING 2
>
> +/* PSCI affinity level state returned by AFFINITY_INFO */
> +#define PSCI_AFFINITY_LEVEL_ON 0
> +#define PSCI_AFFINITY_LEVEL_OFF 1
> +#define PSCI_AFFINITY_LEVEL_ON_PENDING 2
> +
This should be part of the common PSCI 1.0 skeleton patch.
> #ifndef __ASSEMBLY__
> int psci_update_dt(void *fdt);
> void psci_board_init(void);
> diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
> index ab02344..f0390c1 100644
> --- a/board/freescale/ls1021aqds/Makefile
> +++ b/board/freescale/ls1021aqds/Makefile
> @@ -8,3 +8,4 @@ obj-y += ls1021aqds.o
> obj-y += ddr.o
> obj-y += eth.o
> obj-$(CONFIG_FSL_DCU_FB) += dcu.o
> +obj-$(CONFIG_ARMV7_PSCI) += psci.o
> diff --git a/board/freescale/ls1021aqds/psci.S b/board/freescale/ls1021aqds/psci.S
> new file mode 100644
> index 0000000..6b75595
> --- /dev/null
> +++ b/board/freescale/ls1021aqds/psci.S
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright 2016 NXP Semiconductor.
> + * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <config.h>
> +#include <linux/linkage.h>
> +
> +#include <asm/armv7.h>
> +#include <asm/psci.h>
> +
> + .pushsection ._secure.text, "ax"
> +
> + .arch_extension sec
> +
> + .align 5
> +
> +.globl psci_system_off
> +psci_system_off:
> + @ Get QIXIS base address
> + movw r1, #(QIXIS_BASE & 0xffff)
> + movt r1, #(QIXIS_BASE >> 16)
> +
> + ldrb r2, [r1, #QIXIS_PWR_CTL]
> + orr r2, r2, #QIXIS_PWR_CTL_POWEROFF
> + strb r2, [r1, #QIXIS_PWR_CTL]
> +
> +1: wfi
> + b 1b
> +
> +.globl psci_text_end
> +psci_text_end:
> + nop
> + .popsection
> diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile
> index 01296c0..5238b15 100644
> --- a/board/freescale/ls1021atwr/Makefile
> +++ b/board/freescale/ls1021atwr/Makefile
> @@ -6,3 +6,4 @@
>
> obj-y += ls1021atwr.o
> obj-$(CONFIG_FSL_DCU_FB) += dcu.o
> +obj-$(CONFIG_ARMV7_PSCI) += psci.o
> diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S
> new file mode 100644
> index 0000000..adf5b85
> --- /dev/null
> +++ b/board/freescale/ls1021atwr/psci.S
> @@ -0,0 +1,28 @@
> +/*
> + * Copyright 2016 NXP Semiconductor.
> + * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <config.h>
> +#include <linux/linkage.h>
> +
> +#include <asm/armv7.h>
> +#include <asm/psci.h>
> +
> + .pushsection ._secure.text, "ax"
> +
> + .arch_extension sec
> +
> + .align 5
> +
> +.globl psci_system_off
> +psci_system_off:
> +1: wfi
> + b 1b
This does nothing more than halt the machine.
The PSCI spec says "On a SYSTEM_OFF call the implementation completely
removes power from highest power level."
I can understand you might have issues supporting this feature for
external PMICs though. Allwinner/sunxi has the same problem.
Regards
ChenYu
> +
> +.globl psci_text_end
> +psci_text_end:
> + nop
> + .popsection
> diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
> index db684d2..2359fb0 100644
> --- a/include/configs/ls1021aqds.h
> +++ b/include/configs/ls1021aqds.h
> @@ -10,6 +10,7 @@
> #define CONFIG_LS102XA
>
> #define CONFIG_ARMV7_PSCI
> +#define CONFIG_ARMV7_PSCI_1_0
>
> #define CONFIG_SYS_FSL_CLK
>
> @@ -279,6 +280,8 @@ unsigned long get_board_ddr_clk(void);
> #define QIXIS_LBMAP_SHIFT 0
> #define QIXIS_LBMAP_DFLTBANK 0x00
> #define QIXIS_LBMAP_ALTBANK 0x04
> +#define QIXIS_PWR_CTL 0x21
> +#define QIXIS_PWR_CTL_POWEROFF 0x80
> #define QIXIS_RST_CTL_RESET 0x44
> #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
> #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
> diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
> index 0fb28ef..9d0c4fe 100644
> --- a/include/configs/ls1021atwr.h
> +++ b/include/configs/ls1021atwr.h
> @@ -10,6 +10,7 @@
> #define CONFIG_LS102XA
>
> #define CONFIG_ARMV7_PSCI
> +#define CONFIG_ARMV7_PSCI_1_0
>
> #define CONFIG_SYS_FSL_CLK
>
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
` (6 preceding siblings ...)
2016-06-14 7:01 ` [U-Boot] [PATCH v5 7/8] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention macro.wave.z at gmail.com
@ 2016-06-14 7:01 ` macro.wave.z at gmail.com
2016-06-28 4:16 ` Chen-Yu Tsai
2016-06-15 7:16 ` [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support Chen-Yu Tsai
8 siblings, 1 reply; 34+ messages in thread
From: macro.wave.z at gmail.com @ 2016-06-14 7:01 UTC (permalink / raw)
To: u-boot
From: Hongbo Zhang <hongbo.zhang@nxp.com>
LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
include/configs/ls1021atwr.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 7a0e4bf..4729044 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -10,7 +10,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
#define OCRAM_BASE_ADDR 0x10000000
-#define OCRAM_SIZE 0x00020000
+#define OCRAM_SIZE 0x00010000
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 9d0c4fe..e6fbd77 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -12,6 +12,8 @@
#define CONFIG_ARMV7_PSCI
#define CONFIG_ARMV7_PSCI_1_0
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
+
#define CONFIG_SYS_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
--
2.1.4
^ permalink raw reply related [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM
2016-06-14 7:01 ` [U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM macro.wave.z at gmail.com
@ 2016-06-28 4:16 ` Chen-Yu Tsai
2016-06-28 10:45 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-28 4:16 UTC (permalink / raw)
To: u-boot
On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> LS1021 offers two secure OCRAM blocks for trustzone.
> This patch moves all the secure text sections into the OCRAM.
>
> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> ---
> arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
> include/configs/ls1021atwr.h | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
> index 7a0e4bf..4729044 100644
> --- a/arch/arm/include/asm/arch-ls102xa/config.h
> +++ b/arch/arm/include/asm/arch-ls102xa/config.h
> @@ -10,7 +10,7 @@
> #define CONFIG_SYS_CACHELINE_SIZE 64
>
> #define OCRAM_BASE_ADDR 0x10000000
> -#define OCRAM_SIZE 0x00020000
> +#define OCRAM_SIZE 0x00010000
> #define OCRAM_BASE_S_ADDR 0x10010000
> #define OCRAM_S_SIZE 0x00010000
>
> diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
> index 9d0c4fe..e6fbd77 100644
> --- a/include/configs/ls1021atwr.h
> +++ b/include/configs/ls1021atwr.h
> @@ -12,6 +12,8 @@
> #define CONFIG_ARMV7_PSCI
> #define CONFIG_ARMV7_PSCI_1_0
>
> +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
> +
> #define CONFIG_SYS_FSL_CLK
>
> #define CONFIG_DISPLAY_CPUINFO
> --
> 2.1.4
>
The patch itself looks good. Though I wonder if there's some register
you need to configure to split access to the 2 SRAM blocks? If they
are both secure-only, then everything's fine.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM
2016-06-28 4:16 ` Chen-Yu Tsai
@ 2016-06-28 10:45 ` Hongbo Zhang
0 siblings, 0 replies; 34+ messages in thread
From: Hongbo Zhang @ 2016-06-28 10:45 UTC (permalink / raw)
To: u-boot
On Tue, Jun 28, 2016 at 12:16 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> LS1021 offers two secure OCRAM blocks for trustzone.
>> This patch moves all the secure text sections into the OCRAM.
>>
>> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> ---
>> arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
>> include/configs/ls1021atwr.h | 2 ++
>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
>> index 7a0e4bf..4729044 100644
>> --- a/arch/arm/include/asm/arch-ls102xa/config.h
>> +++ b/arch/arm/include/asm/arch-ls102xa/config.h
>> @@ -10,7 +10,7 @@
>> #define CONFIG_SYS_CACHELINE_SIZE 64
>>
>> #define OCRAM_BASE_ADDR 0x10000000
>> -#define OCRAM_SIZE 0x00020000
>> +#define OCRAM_SIZE 0x00010000
>> #define OCRAM_BASE_S_ADDR 0x10010000
>> #define OCRAM_S_SIZE 0x00010000
>>
>> diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
>> index 9d0c4fe..e6fbd77 100644
>> --- a/include/configs/ls1021atwr.h
>> +++ b/include/configs/ls1021atwr.h
>> @@ -12,6 +12,8 @@
>> #define CONFIG_ARMV7_PSCI
>> #define CONFIG_ARMV7_PSCI_1_0
>>
>> +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
>> +
>> #define CONFIG_SYS_FSL_CLK
>>
>> #define CONFIG_DISPLAY_CPUINFO
>> --
>> 2.1.4
>>
>
> The patch itself looks good. Though I wonder if there's some register
> you need to configure to split access to the 2 SRAM blocks? If they
> are both secure-only, then everything's fine.
>
No other registers needed to be configured, this works fine.
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Thanks for the tag.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
` (7 preceding siblings ...)
2016-06-14 7:01 ` [U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM macro.wave.z at gmail.com
@ 2016-06-15 7:16 ` Chen-Yu Tsai
2016-06-15 7:39 ` Marc Zyngier
` (2 more replies)
8 siblings, 3 replies; 34+ messages in thread
From: Chen-Yu Tsai @ 2016-06-15 7:16 UTC (permalink / raw)
To: u-boot
Hi,
On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>
> v5 changes:
> - Give up fixing the potential bug of PSCI stack overlap with secure text end
> when there is more CPUs in system. Because I just want to keep this series as
> simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
> v1.0 implements of our platform.
> While too compplicated patches in assembly language won't call for effective
> reviews, even I think there is potential bug of PSCI stack, let's fix it in
> sepetated patch later.
I've done some patches fixing the stack allocation issue:
https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
These patches are ready, but I want to add a secure data section still.
The data section will be for variables such as target PC, core/cluster
power status, context ID, etc.. IMHO this is better than putting stuff
at the top or bottom of the stack, and can also be referenced directly.
Regards
ChenYu
> - Move the patch of factoring out psci_cpu_on_common to earlier place 2/8, so
> that the following patches can only update the psci_cpu_on_common instead of
> touching each platform's psci_cpu_on, this reduces patches size obviously and
> make it easier for review.
>
> v4 changes:
> - since there is already PSCI v0.2 function IDs definition merged in 5a07abb,
> I give up my previous patches 1/11 and 2/11, and move previous 7/11 "ARMv7:
> PSCI: add PSCI v1.0 functions skeleton" as current first one 1/9
> - accept Andre's comment to add the missed "arm,psci-0,2" into compatible
> string
>
> v3 changes:
> - patch 3/11, re-init the stack pointer to address like start of page instead
> of page end, because for ARM push operation, the stack pointer is encreased
> before storing data.
> - patch 10/11, delete the previous un-implemented cpu_suspend function for ls1
> platform, because there is default blank functions for all those are not
> implemented in specific platform.
>
>
> v2 changes:
> - re-organize psci_cpu_on_common, this code should be called by each platform's
> psci_cpu_on, should not be a function calling each psci_cpu_on, all related
> functions are updated due to this change
> - update some registers usage, e.g. if r10 is used without push/pop, u-boot
> cannot launch rt-kernel
> - update some comments to be clearer, re-organize all patches for easier review
> - add patch to check already_on or on_pending for LS102XA
>
> This patch set contains two parts:
> ARMv7 PSCI common framework: fix some issues and add v1.0 support
> NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation
> And this patch set was initially created by Dongsheng Wang.
>
> Hongbo Zhang (8):
> ARMv7: PSCI: add PSCI v1.0 functions skeleton
> ARMv7: PSCI: factor out reusable psci_cpu_on_common
> ARMv7: PSCI: update the place of saving target PC
> ARMv7: PSCI: add codes to save context ID for CPU_ON
> ARMv7: PSCI: ls102xa: check target CPU ID before further operations
> ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
> ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
> ARMv7: PSCI: ls102xa: move secure text section into OCRAM
>
> arch/arm/cpu/armv7/ls102xa/psci.S | 169 +++++++++++++++++++++++++++--
> arch/arm/cpu/armv7/mx7/psci.S | 5 +-
> arch/arm/cpu/armv7/nonsec_virt.S | 7 ++
> arch/arm/cpu/armv7/psci.S | 99 ++++++++++++++++-
> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 5 +-
> arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 5 +-
> arch/arm/cpu/armv7/virt-dt.c | 10 +-
> arch/arm/include/asm/arch-ls102xa/config.h | 3 +-
> arch/arm/include/asm/psci.h | 31 ++++++
> arch/arm/mach-tegra/psci.S | 5 +-
> board/freescale/ls1021aqds/Makefile | 1 +
> board/freescale/ls1021aqds/psci.S | 36 ++++++
> board/freescale/ls1021atwr/Makefile | 1 +
> board/freescale/ls1021atwr/psci.S | 28 +++++
> include/configs/ls1021aqds.h | 3 +
> include/configs/ls1021atwr.h | 3 +
> 16 files changed, 383 insertions(+), 28 deletions(-)
> create mode 100644 board/freescale/ls1021aqds/psci.S
> create mode 100644 board/freescale/ls1021atwr/psci.S
>
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-06-15 7:16 ` [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support Chen-Yu Tsai
@ 2016-06-15 7:39 ` Marc Zyngier
2016-06-15 8:08 ` Hongbo Zhang
2016-06-24 15:26 ` york sun
2 siblings, 0 replies; 34+ messages in thread
From: Marc Zyngier @ 2016-06-15 7:39 UTC (permalink / raw)
To: u-boot
On Wed, 15 Jun 2016 15:16:08 +0800
Chen-Yu Tsai <wens@csie.org> wrote:
> Hi,
>
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
> > From: Hongbo Zhang <hongbo.zhang@nxp.com>
> >
> > v5 changes:
> > - Give up fixing the potential bug of PSCI stack overlap with secure text end
> > when there is more CPUs in system. Because I just want to keep this series as
> > simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
> > v1.0 implements of our platform.
> > While too compplicated patches in assembly language won't call for effective
> > reviews, even I think there is potential bug of PSCI stack, let's fix it in
> > sepetated patch later.
And have silent corruption from the secure side? I hope not.
>
> I've done some patches fixing the stack allocation issue:
>
> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>
> These patches are ready, but I want to add a secure data section still.
> The data section will be for variables such as target PC, core/cluster
> power status, context ID, etc.. IMHO this is better than putting stuff
> at the top or bottom of the stack, and can also be referenced directly.
I haven't looked at these patches, but I definitely welcome that kind
of development. Please also consider providing some form of per-cpu
infrastructure (which would in turn solve the issue that Hongbo Zhang
wants to sidestep).
Thanks,
M.
--
Jazz is not dead. It just smells funny.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-06-15 7:16 ` [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support Chen-Yu Tsai
2016-06-15 7:39 ` Marc Zyngier
@ 2016-06-15 8:08 ` Hongbo Zhang
2016-06-24 15:26 ` york sun
2 siblings, 0 replies; 34+ messages in thread
From: Hongbo Zhang @ 2016-06-15 8:08 UTC (permalink / raw)
To: u-boot
On Wed, Jun 15, 2016 at 3:16 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> Hi,
>
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> v5 changes:
>> - Give up fixing the potential bug of PSCI stack overlap with secure text end
>> when there is more CPUs in system. Because I just want to keep this series as
>> simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
>> v1.0 implements of our platform.
>> While too compplicated patches in assembly language won't call for effective
>> reviews, even I think there is potential bug of PSCI stack, let's fix it in
>> sepetated patch later.
>
> I've done some patches fixing the stack allocation issue:
>
> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>
> These patches are ready, but I want to add a secure data section still.
> The data section will be for variables such as target PC, core/cluster
> power status, context ID, etc.. IMHO this is better than putting stuff
> at the top or bottom of the stack, and can also be referenced directly.
>
Yes, secure data section is welcome.
I am implementing our suspend-to-ram function in PSCI in C language,
there are some global variables which should be placed into such
secure data section.
> Regards
> ChenYu
>
>> - Move the patch of factoring out psci_cpu_on_common to earlier place 2/8, so
>> that the following patches can only update the psci_cpu_on_common instead of
>> touching each platform's psci_cpu_on, this reduces patches size obviously and
>> make it easier for review.
>>
>> v4 changes:
>> - since there is already PSCI v0.2 function IDs definition merged in 5a07abb,
>> I give up my previous patches 1/11 and 2/11, and move previous 7/11 "ARMv7:
>> PSCI: add PSCI v1.0 functions skeleton" as current first one 1/9
>> - accept Andre's comment to add the missed "arm,psci-0,2" into compatible
>> string
>>
>> v3 changes:
>> - patch 3/11, re-init the stack pointer to address like start of page instead
>> of page end, because for ARM push operation, the stack pointer is encreased
>> before storing data.
>> - patch 10/11, delete the previous un-implemented cpu_suspend function for ls1
>> platform, because there is default blank functions for all those are not
>> implemented in specific platform.
>>
>>
>> v2 changes:
>> - re-organize psci_cpu_on_common, this code should be called by each platform's
>> psci_cpu_on, should not be a function calling each psci_cpu_on, all related
>> functions are updated due to this change
>> - update some registers usage, e.g. if r10 is used without push/pop, u-boot
>> cannot launch rt-kernel
>> - update some comments to be clearer, re-organize all patches for easier review
>> - add patch to check already_on or on_pending for LS102XA
>>
>> This patch set contains two parts:
>> ARMv7 PSCI common framework: fix some issues and add v1.0 support
>> NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation
>> And this patch set was initially created by Dongsheng Wang.
>>
>> Hongbo Zhang (8):
>> ARMv7: PSCI: add PSCI v1.0 functions skeleton
>> ARMv7: PSCI: factor out reusable psci_cpu_on_common
>> ARMv7: PSCI: update the place of saving target PC
>> ARMv7: PSCI: add codes to save context ID for CPU_ON
>> ARMv7: PSCI: ls102xa: check target CPU ID before further operations
>> ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
>> ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
>> ARMv7: PSCI: ls102xa: move secure text section into OCRAM
>>
>> arch/arm/cpu/armv7/ls102xa/psci.S | 169 +++++++++++++++++++++++++++--
>> arch/arm/cpu/armv7/mx7/psci.S | 5 +-
>> arch/arm/cpu/armv7/nonsec_virt.S | 7 ++
>> arch/arm/cpu/armv7/psci.S | 99 ++++++++++++++++-
>> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 5 +-
>> arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 5 +-
>> arch/arm/cpu/armv7/virt-dt.c | 10 +-
>> arch/arm/include/asm/arch-ls102xa/config.h | 3 +-
>> arch/arm/include/asm/psci.h | 31 ++++++
>> arch/arm/mach-tegra/psci.S | 5 +-
>> board/freescale/ls1021aqds/Makefile | 1 +
>> board/freescale/ls1021aqds/psci.S | 36 ++++++
>> board/freescale/ls1021atwr/Makefile | 1 +
>> board/freescale/ls1021atwr/psci.S | 28 +++++
>> include/configs/ls1021aqds.h | 3 +
>> include/configs/ls1021atwr.h | 3 +
>> 16 files changed, 383 insertions(+), 28 deletions(-)
>> create mode 100644 board/freescale/ls1021aqds/psci.S
>> create mode 100644 board/freescale/ls1021atwr/psci.S
>>
>> --
>> 2.1.4
>>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-06-15 7:16 ` [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support Chen-Yu Tsai
2016-06-15 7:39 ` Marc Zyngier
2016-06-15 8:08 ` Hongbo Zhang
@ 2016-06-24 15:26 ` york sun
2016-06-30 5:28 ` Hongbo Zhang
2 siblings, 1 reply; 34+ messages in thread
From: york sun @ 2016-06-24 15:26 UTC (permalink / raw)
To: u-boot
On 06/15/2016 12:16 AM, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> v5 changes:
>> - Give up fixing the potential bug of PSCI stack overlap with secure text end
>> when there is more CPUs in system. Because I just want to keep this series as
>> simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
>> v1.0 implements of our platform.
>> While too compplicated patches in assembly language won't call for effective
>> reviews, even I think there is potential bug of PSCI stack, let's fix it in
>> sepetated patch later.
>
> I've done some patches fixing the stack allocation issue:
>
> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>
> These patches are ready, but I want to add a secure data section still.
> The data section will be for variables such as target PC, core/cluster
> power status, context ID, etc.. IMHO this is better than putting stuff
> at the top or bottom of the stack, and can also be referenced directly.
>
Chenyu,
I see you have been working on PSCI for ARMv7. Can you review Hongbo's
patch set and give your comment or ack?
York
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-06-24 15:26 ` york sun
@ 2016-06-30 5:28 ` Hongbo Zhang
2016-07-04 7:20 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: Hongbo Zhang @ 2016-06-30 5:28 UTC (permalink / raw)
To: u-boot
On Fri, Jun 24, 2016 at 11:26 PM, york sun <york.sun@nxp.com> wrote:
> On 06/15/2016 12:16 AM, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>
>>> v5 changes:
>>> - Give up fixing the potential bug of PSCI stack overlap with secure text end
>>> when there is more CPUs in system. Because I just want to keep this series as
>>> simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
>>> v1.0 implements of our platform.
>>> While too compplicated patches in assembly language won't call for effective
>>> reviews, even I think there is potential bug of PSCI stack, let's fix it in
>>> sepetated patch later.
>>
>> I've done some patches fixing the stack allocation issue:
>>
>> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>>
>> These patches are ready, but I want to add a secure data section still.
>> The data section will be for variables such as target PC, core/cluster
>> power status, context ID, etc.. IMHO this is better than putting stuff
>> at the top or bottom of the stack, and can also be referenced directly.
>>
>
>
> Chenyu,
>
> I see you have been working on PSCI for ARMv7. Can you review Hongbo's
> patch set and give your comment or ack?
>
> York
>
>
Thank Chenyu for valuable review comments, thank you York.
Will send another version soon.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-06-30 5:28 ` Hongbo Zhang
@ 2016-07-04 7:20 ` Hongbo Zhang
2016-07-04 13:11 ` Hans de Goede
0 siblings, 1 reply; 34+ messages in thread
From: Hongbo Zhang @ 2016-07-04 7:20 UTC (permalink / raw)
To: u-boot
I said I would send a new iteration of this series, but there are code
dependencies/conflicts with Chenyu's work, so I'd like to wait for a
few more days to see his v2 sent out or even been merged.
During this stage, any review comments are still appreciated, I am
always looking at this.
Thanks.
On Thu, Jun 30, 2016 at 1:28 PM, Hongbo Zhang <macro.wave.z@gmail.com> wrote:
> On Fri, Jun 24, 2016 at 11:26 PM, york sun <york.sun@nxp.com> wrote:
>> On 06/15/2016 12:16 AM, Chen-Yu Tsai wrote:
>>> Hi,
>>>
>>> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>>
>>>> v5 changes:
>>>> - Give up fixing the potential bug of PSCI stack overlap with secure text end
>>>> when there is more CPUs in system. Because I just want to keep this series as
>>>> simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
>>>> v1.0 implements of our platform.
>>>> While too compplicated patches in assembly language won't call for effective
>>>> reviews, even I think there is potential bug of PSCI stack, let's fix it in
>>>> sepetated patch later.
>>>
>>> I've done some patches fixing the stack allocation issue:
>>>
>>> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>>>
>>> These patches are ready, but I want to add a secure data section still.
>>> The data section will be for variables such as target PC, core/cluster
>>> power status, context ID, etc.. IMHO this is better than putting stuff
>>> at the top or bottom of the stack, and can also be referenced directly.
>>>
>>
>>
>> Chenyu,
>>
>> I see you have been working on PSCI for ARMv7. Can you review Hongbo's
>> patch set and give your comment or ack?
>>
>> York
>>
>>
> Thank Chenyu for valuable review comments, thank you York.
> Will send another version soon.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-07-04 7:20 ` Hongbo Zhang
@ 2016-07-04 13:11 ` Hans de Goede
2016-07-05 2:26 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: Hans de Goede @ 2016-07-04 13:11 UTC (permalink / raw)
To: u-boot
Hi,
On 04-07-16 09:20, Hongbo Zhang wrote:
> I said I would send a new iteration of this series, but there are code
> dependencies/conflicts with Chenyu's work, so I'd like to wait for a
> few more days to see his v2 sent out or even been merged.
> During this stage, any review comments are still appreciated, I am
> always looking at this.
In that case you can probably best base your work on the u-boot-sunxi next
branch, that currently still has v1 of Chen-Yu's patches, but I do not think
things will change that much:
http://git.denx.de/?p=u-boot/u-boot-sunxi.git;a=shortlog;h=refs/heads/next
Regards,
Hans
> Thanks.
>
> On Thu, Jun 30, 2016 at 1:28 PM, Hongbo Zhang <macro.wave.z@gmail.com> wrote:
>> On Fri, Jun 24, 2016 at 11:26 PM, york sun <york.sun@nxp.com> wrote:
>>> On 06/15/2016 12:16 AM, Chen-Yu Tsai wrote:
>>>> Hi,
>>>>
>>>> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>>>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>>>
>>>>> v5 changes:
>>>>> - Give up fixing the potential bug of PSCI stack overlap with secure text end
>>>>> when there is more CPUs in system. Because I just want to keep this series as
>>>>> simple as it could be: adding basic PSCI v1.0 support and adding more PSCI
>>>>> v1.0 implements of our platform.
>>>>> While too compplicated patches in assembly language won't call for effective
>>>>> reviews, even I think there is potential bug of PSCI stack, let's fix it in
>>>>> sepetated patch later.
>>>>
>>>> I've done some patches fixing the stack allocation issue:
>>>>
>>>> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>>>>
>>>> These patches are ready, but I want to add a secure data section still.
>>>> The data section will be for variables such as target PC, core/cluster
>>>> power status, context ID, etc.. IMHO this is better than putting stuff
>>>> at the top or bottom of the stack, and can also be referenced directly.
>>>>
>>>
>>>
>>> Chenyu,
>>>
>>> I see you have been working on PSCI for ARMv7. Can you review Hongbo's
>>> patch set and give your comment or ack?
>>>
>>> York
>>>
>>>
>> Thank Chenyu for valuable review comments, thank you York.
>> Will send another version soon.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-07-04 13:11 ` Hans de Goede
@ 2016-07-05 2:26 ` Hongbo Zhang
2016-07-19 20:34 ` york sun
0 siblings, 1 reply; 34+ messages in thread
From: Hongbo Zhang @ 2016-07-05 2:26 UTC (permalink / raw)
To: u-boot
On Mon, Jul 4, 2016 at 9:11 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 04-07-16 09:20, Hongbo Zhang wrote:
>>
>> I said I would send a new iteration of this series, but there are code
>> dependencies/conflicts with Chenyu's work, so I'd like to wait for a
>> few more days to see his v2 sent out or even been merged.
>> During this stage, any review comments are still appreciated, I am
>> always looking at this.
>
>
> In that case you can probably best base your work on the u-boot-sunxi next
> branch, that currently still has v1 of Chen-Yu's patches, but I do not think
> things will change that much:
>
> http://git.denx.de/?p=u-boot/u-boot-sunxi.git;a=shortlog;h=refs/heads/next
>
OK, I see
> Regards,
>
> Hans
>
>
>
>> Thanks.
>>
>> On Thu, Jun 30, 2016 at 1:28 PM, Hongbo Zhang <macro.wave.z@gmail.com>
>> wrote:
>>>
>>> On Fri, Jun 24, 2016 at 11:26 PM, york sun <york.sun@nxp.com> wrote:
>>>>
>>>> On 06/15/2016 12:16 AM, Chen-Yu Tsai wrote:
>>>>>
>>>>> Hi,
>>>>>
>>>>> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>>>>>>
>>>>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>>>>
>>>>>> v5 changes:
>>>>>> - Give up fixing the potential bug of PSCI stack overlap with secure
>>>>>> text end
>>>>>> when there is more CPUs in system. Because I just want to keep this
>>>>>> series as
>>>>>> simple as it could be: adding basic PSCI v1.0 support and adding more
>>>>>> PSCI
>>>>>> v1.0 implements of our platform.
>>>>>> While too compplicated patches in assembly language won't call for
>>>>>> effective
>>>>>> reviews, even I think there is potential bug of PSCI stack, let's fix
>>>>>> it in
>>>>>> sepetated patch later.
>>>>>
>>>>>
>>>>> I've done some patches fixing the stack allocation issue:
>>>>>
>>>>> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>>>>>
>>>>> These patches are ready, but I want to add a secure data section still.
>>>>> The data section will be for variables such as target PC, core/cluster
>>>>> power status, context ID, etc.. IMHO this is better than putting stuff
>>>>> at the top or bottom of the stack, and can also be referenced directly.
>>>>>
>>>>
>>>>
>>>> Chenyu,
>>>>
>>>> I see you have been working on PSCI for ARMv7. Can you review Hongbo's
>>>> patch set and give your comment or ack?
>>>>
>>>> York
>>>>
>>>>
>>> Thank Chenyu for valuable review comments, thank you York.
>>> Will send another version soon.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-07-05 2:26 ` Hongbo Zhang
@ 2016-07-19 20:34 ` york sun
2016-07-21 4:21 ` Hongbo Zhang
0 siblings, 1 reply; 34+ messages in thread
From: york sun @ 2016-07-19 20:34 UTC (permalink / raw)
To: u-boot
On 07/04/2016 07:26 PM, Hongbo Zhang wrote:
> On Mon, Jul 4, 2016 at 9:11 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 04-07-16 09:20, Hongbo Zhang wrote:
>>>
>>> I said I would send a new iteration of this series, but there are code
>>> dependencies/conflicts with Chenyu's work, so I'd like to wait for a
>>> few more days to see his v2 sent out or even been merged.
>>> During this stage, any review comments are still appreciated, I am
>>> always looking at this.
>>
>>
>> In that case you can probably best base your work on the u-boot-sunxi next
>> branch, that currently still has v1 of Chen-Yu's patches, but I do not think
>> things will change that much:
>>
>> http://git.denx.de/?p=u-boot/u-boot-sunxi.git;a=shortlog;h=refs/heads/next
>>
> OK, I see
>
>> Regards,
>>
>> Hans
>>
>>
>>
>>> Thanks.
>>>
>>> On Thu, Jun 30, 2016 at 1:28 PM, Hongbo Zhang <macro.wave.z@gmail.com>
>>> wrote:
>>>>
>>>> On Fri, Jun 24, 2016 at 11:26 PM, york sun <york.sun@nxp.com> wrote:
>>>>>
>>>>> On 06/15/2016 12:16 AM, Chen-Yu Tsai wrote:
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>>>>>>>
>>>>>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>>>>>
>>>>>>> v5 changes:
>>>>>>> - Give up fixing the potential bug of PSCI stack overlap with secure
>>>>>>> text end
>>>>>>> when there is more CPUs in system. Because I just want to keep this
>>>>>>> series as
>>>>>>> simple as it could be: adding basic PSCI v1.0 support and adding more
>>>>>>> PSCI
>>>>>>> v1.0 implements of our platform.
>>>>>>> While too compplicated patches in assembly language won't call for
>>>>>>> effective
>>>>>>> reviews, even I think there is potential bug of PSCI stack, let's fix
>>>>>>> it in
>>>>>>> sepetated patch later.
>>>>>>
>>>>>>
>>>>>> I've done some patches fixing the stack allocation issue:
>>>>>>
>>>>>> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>>>>>>
>>>>>> These patches are ready, but I want to add a secure data section still.
>>>>>> The data section will be for variables such as target PC, core/cluster
>>>>>> power status, context ID, etc.. IMHO this is better than putting stuff
>>>>>> at the top or bottom of the stack, and can also be referenced directly.
>>>>>>
>>>>>
>>>>>
>>>>> Chenyu,
>>>>>
>>>>> I see you have been working on PSCI for ARMv7. Can you review Hongbo's
>>>>> patch set and give your comment or ack?
>>>>>
>>>>> York
>>>>>
>>>>>
>>>> Thank Chenyu for valuable review comments, thank you York.
>>>> Will send another version soon.
>
Hongbo,
Where are we on this thread? Do you have an update?
York
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support
2016-07-19 20:34 ` york sun
@ 2016-07-21 4:21 ` Hongbo Zhang
0 siblings, 0 replies; 34+ messages in thread
From: Hongbo Zhang @ 2016-07-21 4:21 UTC (permalink / raw)
To: u-boot
Hi York,
I saw sunxi's patches were merged, so I am preparing my patches, will
send it out soon.
On Wed, Jul 20, 2016 at 4:34 AM, york sun <york.sun@nxp.com> wrote:
> On 07/04/2016 07:26 PM, Hongbo Zhang wrote:
>> On Mon, Jul 4, 2016 at 9:11 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>>> Hi,
>>>
>>> On 04-07-16 09:20, Hongbo Zhang wrote:
>>>>
>>>> I said I would send a new iteration of this series, but there are code
>>>> dependencies/conflicts with Chenyu's work, so I'd like to wait for a
>>>> few more days to see his v2 sent out or even been merged.
>>>> During this stage, any review comments are still appreciated, I am
>>>> always looking at this.
>>>
>>>
>>> In that case you can probably best base your work on the u-boot-sunxi next
>>> branch, that currently still has v1 of Chen-Yu's patches, but I do not think
>>> things will change that much:
>>>
>>> http://git.denx.de/?p=u-boot/u-boot-sunxi.git;a=shortlog;h=refs/heads/next
>>>
>> OK, I see
>>
>>> Regards,
>>>
>>> Hans
>>>
>>>
>>>
>>>> Thanks.
>>>>
>>>> On Thu, Jun 30, 2016 at 1:28 PM, Hongbo Zhang <macro.wave.z@gmail.com>
>>>> wrote:
>>>>>
>>>>> On Fri, Jun 24, 2016 at 11:26 PM, york sun <york.sun@nxp.com> wrote:
>>>>>>
>>>>>> On 06/15/2016 12:16 AM, Chen-Yu Tsai wrote:
>>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>>>>>>>>
>>>>>>>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>>>>>>>
>>>>>>>> v5 changes:
>>>>>>>> - Give up fixing the potential bug of PSCI stack overlap with secure
>>>>>>>> text end
>>>>>>>> when there is more CPUs in system. Because I just want to keep this
>>>>>>>> series as
>>>>>>>> simple as it could be: adding basic PSCI v1.0 support and adding more
>>>>>>>> PSCI
>>>>>>>> v1.0 implements of our platform.
>>>>>>>> While too compplicated patches in assembly language won't call for
>>>>>>>> effective
>>>>>>>> reviews, even I think there is potential bug of PSCI stack, let's fix
>>>>>>>> it in
>>>>>>>> sepetated patch later.
>>>>>>>
>>>>>>>
>>>>>>> I've done some patches fixing the stack allocation issue:
>>>>>>>
>>>>>>> https://github.com/wens/u-boot-sunxi/commits/c-psci-part2
>>>>>>>
>>>>>>> These patches are ready, but I want to add a secure data section still.
>>>>>>> The data section will be for variables such as target PC, core/cluster
>>>>>>> power status, context ID, etc.. IMHO this is better than putting stuff
>>>>>>> at the top or bottom of the stack, and can also be referenced directly.
>>>>>>>
>>>>>>
>>>>>>
>>>>>> Chenyu,
>>>>>>
>>>>>> I see you have been working on PSCI for ARMv7. Can you review Hongbo's
>>>>>> patch set and give your comment or ack?
>>>>>>
>>>>>> York
>>>>>>
>>>>>>
>>>>> Thank Chenyu for valuable review comments, thank you York.
>>>>> Will send another version soon.
>>
>
> Hongbo,
>
> Where are we on this thread? Do you have an update?
>
> York
^ permalink raw reply [flat|nested] 34+ messages in thread