[PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency

[PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency

[Rex Zhu]

Display component can get tru max_displ_clk_in_khz instand of hardcode

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 45 +++++++++++++++++++++-
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 5a33461..37f6a5f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -261,6 +261,33 @@ static void pp_to_dc_clock_levels_with_latency(
 	}
 }
 
+static void pp_to_dc_clock_levels_with_voltage(
+		const struct pp_clock_levels_with_voltage *pp_clks,
+		struct dm_pp_clock_levels_with_voltage *clk_level_info,
+		enum dm_pp_clock_type dc_clk_type)
+{
+	uint32_t i;
+
+	if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
+		DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
+				DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
+				pp_clks->num_levels,
+				DM_PP_MAX_CLOCK_LEVELS);
+
+		clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
+	} else
+		clk_level_info->num_levels = pp_clks->num_levels;
+
+	DRM_DEBUG("DM_PPLIB: values for %s clock\n",
+			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
+
+	for (i = 0; i < clk_level_info->num_levels; i++) {
+		DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
+		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
+		clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
+	}
+}
+
 bool dm_pp_get_clock_levels_by_type(
 		const struct dc_context *ctx,
 		enum dm_pp_clock_type clk_type,
@@ -361,8 +388,22 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
 	enum dm_pp_clock_type clk_type,
 	struct dm_pp_clock_levels_with_voltage *clk_level_info)
 {
-	/* TODO: to be implemented */
-	return false;
+	struct amdgpu_device *adev = ctx->driver_context;
+	void *pp_handle = adev->powerplay.pp_handle;
+	struct pp_clock_levels_with_voltage pp_clks = { 0 };
+	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+	if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)
+		return false;
+
+	if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
+						     dc_to_pp_clock_type(clk_type),
+						     &pp_clks))
+		return false;
+
+	pp_to_dc_clock_levels_with_voltage(&pp_clks, clk_level_info, clk_type);
+
+	return true;
 }
 
 bool dm_pp_notify_wm_clock_changes(
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display

[Rex Zhu]

Transfer 10KHz (requested by smu) to KHz needed by Display
component.

This can fix the issue 4k Monitor can't be lit up on Vega/Raven.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  |  4 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +++++-----
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 +++++-----
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 6d5e042..08690c9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1014,7 +1014,7 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
 
 	clocks->num_levels = 0;
 	for (i = 0; i < pclk_vol_table->count; i++) {
-		clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
+		clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
 		clocks->data[i].latency_in_us = latency_required ?
 						smu10_get_mem_latency(hwmgr,
 						pclk_vol_table->entries[i].clk) :
@@ -1065,7 +1065,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 
 	clocks->num_levels = 0;
 	for (i = 0; i < pclk_vol_table->count; i++) {
-		clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
+		clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;
 		clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
 		clocks->num_levels++;
 	}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index f97fce6..6057b59 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4067,7 +4067,7 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
 	for (i = 0; i < dep_table->count; i++) {
 		if (dep_table->entries[i].clk) {
 			clocks->data[clocks->num_levels].clocks_in_khz =
-					dep_table->entries[i].clk;
+					dep_table->entries[i].clk * 10;
 			clocks->num_levels++;
 		}
 	}
@@ -4104,7 +4104,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
 			clocks->data[clocks->num_levels].clocks_in_khz =
 			data->mclk_latency_table.entries
 			[data->mclk_latency_table.count].frequency =
-					dep_table->entries[i].clk;
+					dep_table->entries[i].clk * 10;
 			clocks->data[clocks->num_levels].latency_in_us =
 			data->mclk_latency_table.entries
 			[data->mclk_latency_table.count].latency =
@@ -4126,7 +4126,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
 	uint32_t i;
 
 	for (i = 0; i < dep_table->count; i++) {
-		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
+		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
 		clocks->data[i].latency_in_us = 0;
 		clocks->num_levels++;
 	}
@@ -4142,7 +4142,7 @@ static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
 	uint32_t i;
 
 	for (i = 0; i < dep_table->count; i++) {
-		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
+		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
 		clocks->data[i].latency_in_us = 0;
 		clocks->num_levels++;
 	}
@@ -4202,7 +4202,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 	}
 
 	for (i = 0; i < dep_table->count; i++) {
-		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
+		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
 		clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
 				entries[dep_table->entries[i].vddInd].us_vdd);
 		clocks->num_levels++;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 782e209..d685ce7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1576,7 +1576,7 @@ static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
 
 	for (i = 0; i < ucount; i++) {
 		clocks->data[i].clocks_in_khz =
-			dpm_table->dpm_levels[i].value * 100;
+			dpm_table->dpm_levels[i].value * 1000;
 
 		clocks->data[i].latency_in_us = 0;
 	}
@@ -1608,7 +1608,7 @@ static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
 
 	for (i = 0; i < ucount; i++) {
 		clocks->data[i].clocks_in_khz =
-			dpm_table->dpm_levels[i].value * 100;
+			dpm_table->dpm_levels[i].value * 1000;
 
 		clocks->data[i].latency_in_us =
 			data->mclk_latency_table.entries[i].latency =
@@ -1638,7 +1638,7 @@ static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
 
 	for (i = 0; i < ucount; i++) {
 		clocks->data[i].clocks_in_khz =
-			dpm_table->dpm_levels[i].value * 100;
+			dpm_table->dpm_levels[i].value * 1000;
 
 		clocks->data[i].latency_in_us = 0;
 	}
@@ -1666,7 +1666,7 @@ static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
 
 	for (i = 0; i < ucount; i++) {
 		clocks->data[i].clocks_in_khz =
-			dpm_table->dpm_levels[i].value * 100;
+			dpm_table->dpm_levels[i].value * 1000;
 
 		clocks->data[i].latency_in_us = 0;
 	}
@@ -1838,7 +1838,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
 				return -1);
 		for (i = 0; i < clocks.num_levels; i++)
 			size += sprintf(buf + size, "%d: %uMhz %s\n",
-				i, clocks.data[i].clocks_in_khz / 100,
+				i, clocks.data[i].clocks_in_khz / 1000,
 				(clocks.data[i].clocks_in_khz == now) ? "*" : "");
 		break;
 
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display

[Alex Deucher]

On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Transfer 10KHz (requested by smu) to KHz needed by Display
> component.
>
> This can fix the issue 4k Monitor can't be lit up on Vega/Raven.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  |  4 ++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +++++-----
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 +++++-----
>  3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 6d5e042..08690c9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1014,7 +1014,7 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
>
>         clocks->num_levels = 0;
>         for (i = 0; i < pclk_vol_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
>                 clocks->data[i].latency_in_us = latency_required ?
>                                                 smu10_get_mem_latency(hwmgr,
>                                                 pclk_vol_table->entries[i].clk) :
> @@ -1065,7 +1065,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>
>         clocks->num_levels = 0;
>         for (i = 0; i < pclk_vol_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;
>                 clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
>                 clocks->num_levels++;
>         }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index f97fce6..6057b59 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4067,7 +4067,7 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
>         for (i = 0; i < dep_table->count; i++) {
>                 if (dep_table->entries[i].clk) {
>                         clocks->data[clocks->num_levels].clocks_in_khz =
> -                                       dep_table->entries[i].clk;
> +                                       dep_table->entries[i].clk * 10;
>                         clocks->num_levels++;
>                 }
>         }
> @@ -4104,7 +4104,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
>                         clocks->data[clocks->num_levels].clocks_in_khz =
>                         data->mclk_latency_table.entries
>                         [data->mclk_latency_table.count].frequency =
> -                                       dep_table->entries[i].clk;
> +                                       dep_table->entries[i].clk * 10;
>                         clocks->data[clocks->num_levels].latency_in_us =
>                         data->mclk_latency_table.entries
>                         [data->mclk_latency_table.count].latency =
> @@ -4126,7 +4126,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
>         uint32_t i;
>
>         for (i = 0; i < dep_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
>                 clocks->data[i].latency_in_us = 0;
>                 clocks->num_levels++;
>         }
> @@ -4142,7 +4142,7 @@ static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
>         uint32_t i;
>
>         for (i = 0; i < dep_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
>                 clocks->data[i].latency_in_us = 0;
>                 clocks->num_levels++;
>         }
> @@ -4202,7 +4202,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>         }
>
>         for (i = 0; i < dep_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
>                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
>                                 entries[dep_table->entries[i].vddInd].us_vdd);
>                 clocks->num_levels++;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 782e209..d685ce7 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1576,7 +1576,7 @@ static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
>
>         for (i = 0; i < ucount; i++) {
>                 clocks->data[i].clocks_in_khz =
> -                       dpm_table->dpm_levels[i].value * 100;
> +                       dpm_table->dpm_levels[i].value * 1000;
>
>                 clocks->data[i].latency_in_us = 0;
>         }
> @@ -1608,7 +1608,7 @@ static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
>
>         for (i = 0; i < ucount; i++) {
>                 clocks->data[i].clocks_in_khz =
> -                       dpm_table->dpm_levels[i].value * 100;
> +                       dpm_table->dpm_levels[i].value * 1000;
>
>                 clocks->data[i].latency_in_us =
>                         data->mclk_latency_table.entries[i].latency =
> @@ -1638,7 +1638,7 @@ static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
>
>         for (i = 0; i < ucount; i++) {
>                 clocks->data[i].clocks_in_khz =
> -                       dpm_table->dpm_levels[i].value * 100;
> +                       dpm_table->dpm_levels[i].value * 1000;
>
>                 clocks->data[i].latency_in_us = 0;
>         }
> @@ -1666,7 +1666,7 @@ static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
>
>         for (i = 0; i < ucount; i++) {
>                 clocks->data[i].clocks_in_khz =
> -                       dpm_table->dpm_levels[i].value * 100;
> +                       dpm_table->dpm_levels[i].value * 1000;
>
>                 clocks->data[i].latency_in_us = 0;
>         }
> @@ -1838,7 +1838,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
>                                 return -1);
>                 for (i = 0; i < clocks.num_levels; i++)
>                         size += sprintf(buf + size, "%d: %uMhz %s\n",
> -                               i, clocks.data[i].clocks_in_khz / 100,
> +                               i, clocks.data[i].clocks_in_khz / 1000,
>                                 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
>                 break;
>
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/5] drm/amd/pp: Memory Latency is always 25us on Vega10

[Rex Zhu]

Also use the tolerable latency defined in Display
to find lowest MCLK frequency when disable mclk switch

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 ++--------------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 6057b59..198c7ed 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -55,12 +55,6 @@
 
 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
 
-#define MEM_FREQ_LOW_LATENCY        25000
-#define MEM_FREQ_HIGH_LATENCY       80000
-#define MEM_LATENCY_HIGH            245
-#define MEM_LATENCY_LOW             35
-#define MEM_LATENCY_ERR             0xFFFF
-
 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
 
@@ -3223,7 +3217,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 		/* Find the lowest MCLK frequency that is within
 		 * the tolerable latency defined in DAL
 		 */
-		latency = 0;
+		latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
 		for (i = 0; i < data->mclk_latency_table.count; i++) {
 			if ((data->mclk_latency_table.entries[i].latency <= latency) &&
 				(data->mclk_latency_table.entries[i].frequency >=
@@ -4074,18 +4068,6 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
 
 }
 
-static uint32_t vega10_get_mem_latency(struct pp_hwmgr *hwmgr,
-		uint32_t clock)
-{
-	if (clock >= MEM_FREQ_LOW_LATENCY &&
-			clock < MEM_FREQ_HIGH_LATENCY)
-		return MEM_LATENCY_HIGH;
-	else if (clock >= MEM_FREQ_HIGH_LATENCY)
-		return MEM_LATENCY_LOW;
-	else
-		return MEM_LATENCY_ERR;
-}
-
 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
 		struct pp_clock_levels_with_latency *clocks)
 {
@@ -4107,9 +4089,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
 					dep_table->entries[i].clk * 10;
 			clocks->data[clocks->num_levels].latency_in_us =
 			data->mclk_latency_table.entries
-			[data->mclk_latency_table.count].latency =
-					vega10_get_mem_latency(hwmgr,
-						dep_table->entries[i].clk);
+			[data->mclk_latency_table.count].latency = 25;
 			clocks->num_levels++;
 			data->mclk_latency_table.count++;
 		}
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/5] drm/amd/pp: Memory Latency is always 25us on Vega10

[Alex Deucher]

On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Also use the tolerable latency defined in Display
> to find lowest MCLK frequency when disable mclk switch

This should probably be two patches?  One to fix the memory latency,
and one to switch the tolerable latency for display.  With that fixed:
Acked-by: Alex Deucher <alexander.deucher@amd.com>

>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 ++--------------------
>  1 file changed, 2 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 6057b59..198c7ed 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -55,12 +55,6 @@
>
>  static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
>
> -#define MEM_FREQ_LOW_LATENCY        25000
> -#define MEM_FREQ_HIGH_LATENCY       80000
> -#define MEM_LATENCY_HIGH            245
> -#define MEM_LATENCY_LOW             35
> -#define MEM_LATENCY_ERR             0xFFFF
> -
>  #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
>  #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
>
> @@ -3223,7 +3217,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
>                 /* Find the lowest MCLK frequency that is within
>                  * the tolerable latency defined in DAL
>                  */
> -               latency = 0;
> +               latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
>                 for (i = 0; i < data->mclk_latency_table.count; i++) {
>                         if ((data->mclk_latency_table.entries[i].latency <= latency) &&
>                                 (data->mclk_latency_table.entries[i].frequency >=
> @@ -4074,18 +4068,6 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
>
>  }
>
> -static uint32_t vega10_get_mem_latency(struct pp_hwmgr *hwmgr,
> -               uint32_t clock)
> -{
> -       if (clock >= MEM_FREQ_LOW_LATENCY &&
> -                       clock < MEM_FREQ_HIGH_LATENCY)
> -               return MEM_LATENCY_HIGH;
> -       else if (clock >= MEM_FREQ_HIGH_LATENCY)
> -               return MEM_LATENCY_LOW;
> -       else
> -               return MEM_LATENCY_ERR;
> -}
> -
>  static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
>                 struct pp_clock_levels_with_latency *clocks)
>  {
> @@ -4107,9 +4089,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
>                                         dep_table->entries[i].clk * 10;
>                         clocks->data[clocks->num_levels].latency_in_us =
>                         data->mclk_latency_table.entries
> -                       [data->mclk_latency_table.count].latency =
> -                                       vega10_get_mem_latency(hwmgr,
> -                                               dep_table->entries[i].clk);
> +                       [data->mclk_latency_table.count].latency = 25;
>                         clocks->num_levels++;
>                         data->mclk_latency_table.count++;
>                 }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/5] drm/amd/display: Delete old implementation of bw_calcs_data_update_from_pplib

[Rex Zhu]

this function is copied from dce112. it is not for AI/RV.
driver need to re-implement this function.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 .../drm/amd/display/dc/dce120/dce120_resource.c    | 123 +--------------------
 1 file changed, 1 insertion(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 2d58dac..450f7ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -26,7 +26,6 @@
 
 #include "dm_services.h"
 
-
 #include "stream_encoder.h"
 #include "resource.h"
 #include "include/irq_service_interface.h"
@@ -691,127 +690,7 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool)
 
 static void bw_calcs_data_update_from_pplib(struct dc *dc)
 {
-	struct dm_pp_clock_levels_with_latency eng_clks = {0};
-	struct dm_pp_clock_levels_with_latency mem_clks = {0};
-	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
-	int i;
-	unsigned int clk;
-	unsigned int latency;
-
-	/*do system clock*/
-	if (!dm_pp_get_clock_levels_by_type_with_latency(
-				dc->ctx,
-				DM_PP_CLOCK_TYPE_ENGINE_CLK,
-				&eng_clks) || eng_clks.num_levels == 0) {
-
-		eng_clks.num_levels = 8;
-		clk = 300000;
-
-		for (i = 0; i < eng_clks.num_levels; i++) {
-			eng_clks.data[i].clocks_in_khz = clk;
-			clk += 100000;
-		}
-	}
-
-	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
-	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
-		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
-	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
-		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
-	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
-		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
-	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
-		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
-	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
-		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
-	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
-		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
-	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
-		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
-	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
-			eng_clks.data[0].clocks_in_khz, 1000);
-
-	/*do memory clock*/
-	if (!dm_pp_get_clock_levels_by_type_with_latency(
-			dc->ctx,
-			DM_PP_CLOCK_TYPE_MEMORY_CLK,
-			&mem_clks) || mem_clks.num_levels == 0) {
-
-		mem_clks.num_levels = 3;
-		clk = 250000;
-		latency = 45;
-
-		for (i = 0; i < eng_clks.num_levels; i++) {
-			mem_clks.data[i].clocks_in_khz = clk;
-			mem_clks.data[i].latency_in_us = latency;
-			clk += 500000;
-			latency -= 5;
-		}
-
-	}
-
-	/* we don't need to call PPLIB for validation clock since they
-	 * also give us the highest sclk and highest mclk (UMA clock).
-	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
-	 * YCLK = UMACLK*m_memoryTypeMultiplier
-	 */
-	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
-		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
-	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
-		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
-		1000);
-	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
-		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
-		1000);
-
-	/* Now notify PPLib/SMU about which Watermarks sets they should select
-	 * depending on DPM state they are in. And update BW MGR GFX Engine and
-	 * Memory clock member variables for Watermarks calculations for each
-	 * Watermark Set
-	 */
-	clk_ranges.num_wm_sets = 4;
-	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
-	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
-			eng_clks.data[0].clocks_in_khz;
-	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
-			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
-	clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
-			mem_clks.data[0].clocks_in_khz;
-	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
-			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
-
-	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
-	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
-			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
-	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
-	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
-	clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
-			mem_clks.data[0].clocks_in_khz;
-	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
-			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
-
-	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
-	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
-			eng_clks.data[0].clocks_in_khz;
-	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
-			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
-	clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
-			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
-	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
-	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
-
-	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
-	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
-			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
-	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
-	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
-	clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
-			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
-	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
-	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
-
-	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
-	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
+	/* To be implement for Greenland */
 }
 
 static uint32_t read_pipe_fuses(struct dc_context *ctx)
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 4/5] drm/amd/display: Delete old implementation of bw_calcs_data_update_from_pplib

[Alex Deucher]

On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> this function is copied from dce112. it is not for AI/RV.
> driver need to re-implement this function.

Maybe it's similar enough to be ok for now?  What's better? Harry?

Alex

>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  .../drm/amd/display/dc/dce120/dce120_resource.c    | 123 +--------------------
>  1 file changed, 1 insertion(+), 122 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> index 2d58dac..450f7ec 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> @@ -26,7 +26,6 @@
>
>  #include "dm_services.h"
>
> -
>  #include "stream_encoder.h"
>  #include "resource.h"
>  #include "include/irq_service_interface.h"
> @@ -691,127 +690,7 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool)
>
>  static void bw_calcs_data_update_from_pplib(struct dc *dc)
>  {
> -       struct dm_pp_clock_levels_with_latency eng_clks = {0};
> -       struct dm_pp_clock_levels_with_latency mem_clks = {0};
> -       struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
> -       int i;
> -       unsigned int clk;
> -       unsigned int latency;
> -
> -       /*do system clock*/
> -       if (!dm_pp_get_clock_levels_by_type_with_latency(
> -                               dc->ctx,
> -                               DM_PP_CLOCK_TYPE_ENGINE_CLK,
> -                               &eng_clks) || eng_clks.num_levels == 0) {
> -
> -               eng_clks.num_levels = 8;
> -               clk = 300000;
> -
> -               for (i = 0; i < eng_clks.num_levels; i++) {
> -                       eng_clks.data[i].clocks_in_khz = clk;
> -                       clk += 100000;
> -               }
> -       }
> -
> -       /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
> -       dc->bw_vbios->high_sclk = bw_frc_to_fixed(
> -               eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
> -       dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
> -               eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
> -       dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
> -               eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
> -       dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
> -               eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
> -       dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
> -               eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
> -       dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
> -               eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
> -       dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
> -               eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
> -       dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
> -                       eng_clks.data[0].clocks_in_khz, 1000);
> -
> -       /*do memory clock*/
> -       if (!dm_pp_get_clock_levels_by_type_with_latency(
> -                       dc->ctx,
> -                       DM_PP_CLOCK_TYPE_MEMORY_CLK,
> -                       &mem_clks) || mem_clks.num_levels == 0) {
> -
> -               mem_clks.num_levels = 3;
> -               clk = 250000;
> -               latency = 45;
> -
> -               for (i = 0; i < eng_clks.num_levels; i++) {
> -                       mem_clks.data[i].clocks_in_khz = clk;
> -                       mem_clks.data[i].latency_in_us = latency;
> -                       clk += 500000;
> -                       latency -= 5;
> -               }
> -
> -       }
> -
> -       /* we don't need to call PPLIB for validation clock since they
> -        * also give us the highest sclk and highest mclk (UMA clock).
> -        * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
> -        * YCLK = UMACLK*m_memoryTypeMultiplier
> -        */
> -       dc->bw_vbios->low_yclk = bw_frc_to_fixed(
> -               mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
> -       dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
> -               mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
> -               1000);
> -       dc->bw_vbios->high_yclk = bw_frc_to_fixed(
> -               mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
> -               1000);
> -
> -       /* Now notify PPLib/SMU about which Watermarks sets they should select
> -        * depending on DPM state they are in. And update BW MGR GFX Engine and
> -        * Memory clock member variables for Watermarks calculations for each
> -        * Watermark Set
> -        */
> -       clk_ranges.num_wm_sets = 4;
> -       clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
> -       clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
> -                       eng_clks.data[0].clocks_in_khz;
> -       clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
> -                       eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
> -       clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
> -                       mem_clks.data[0].clocks_in_khz;
> -       clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
> -                       mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
> -
> -       clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
> -       clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
> -                       eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
> -       /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
> -       clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
> -       clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
> -                       mem_clks.data[0].clocks_in_khz;
> -       clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
> -                       mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
> -
> -       clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
> -       clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
> -                       eng_clks.data[0].clocks_in_khz;
> -       clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
> -                       eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
> -       clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
> -                       mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
> -       /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
> -       clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
> -
> -       clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
> -       clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
> -                       eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
> -       /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
> -       clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
> -       clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
> -                       mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
> -       /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
> -       clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
> -
> -       /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
> -       dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
> +       /* To be implement for Greenland */
>  }
>
>  static uint32_t read_pipe_fuses(struct dc_context *ctx)
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/5] drm/amd/display: Refine the interface dm_pp_notify_wm_clock_changes

[Rex Zhu]

change function parameter type from dm_pp_wm_sets_with_clock_ranges * to
void *. so this interface can be supported on AI/RV.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dm_services.h               | 2 +-
 drivers/gpu/drm/amd/include/kgd_pp_interface.h             | 2 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c              | 6 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c      | 4 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c          | 3 ++-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c         | 3 ++-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c         | 3 ++-
 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h        | 2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h                  | 3 +--
 10 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 37f6a5f..92d36fe 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -408,7 +408,7 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
 
 bool dm_pp_notify_wm_clock_changes(
 	const struct dc_context *ctx,
-	struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
+	void *clock_ranges)
 {
 	/* TODO: to be implemented */
 	return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 4ff9b2b..535b415 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -217,7 +217,7 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
 
 bool dm_pp_notify_wm_clock_changes(
 	const struct dc_context *ctx,
-	struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
+	void *clock_ranges);
 
 void dm_pp_get_funcs_rv(struct dc_context *ctx,
 		struct pp_smu_funcs_rv *funcs);
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 4535756..06f7ef2 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -261,7 +261,7 @@ struct amd_pm_funcs {
 		enum amd_pp_clock_type type,
 		struct pp_clock_levels_with_voltage *clocks);
 	int (*set_watermarks_for_clocks_ranges)(void *handle,
-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
+						void *clock_ranges);
 	int (*display_clock_voltage_request)(void *handle,
 				struct pp_display_clock_request *clock);
 	int (*get_display_mode_validation_clocks)(void *handle,
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 7b0ff9d..ba5e0e2 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1103,17 +1103,17 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
 }
 
 static int pp_set_watermarks_for_clocks_ranges(void *handle,
-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+		void *clock_ranges)
 {
 	struct pp_hwmgr *hwmgr = handle;
 	int ret = 0;
 
-	if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
+	if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
 		return -EINVAL;
 
 	mutex_lock(&hwmgr->smu_lock);
 	ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
-			wm_with_clock_ranges);
+			clock_ranges);
 	mutex_unlock(&hwmgr->smu_lock);
 
 	return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index a0bb921..53207e7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -435,7 +435,7 @@ int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 }
 
 int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+					void *clock_ranges)
 {
 	PHM_FUNC_CHECK(hwmgr);
 
@@ -443,7 +443,7 @@ int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
 		return -EINVAL;
 
 	return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
-			wm_with_clock_ranges);
+								clock_ranges);
 }
 
 int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 08690c9..4ca8033 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1131,9 +1131,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 }
 
 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+		void *clock_ranges)
 {
 	struct smu10_hwmgr *data = hwmgr->backend;
+	struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
 	Watermarks_t *table = &(data->water_marks_table);
 	int result = 0;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 198c7ed..8554ede 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4195,9 +4195,10 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 }
 
 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+							void *clock_range)
 {
 	struct vega10_hwmgr *data = hwmgr->backend;
+	struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
 	Watermarks_t *table = &(data->smc_state_table.water_marks_table);
 	int result = 0;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index d685ce7..bcb64cd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1713,10 +1713,11 @@ static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 }
 
 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+							void *clock_ranges)
 {
 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 	Watermarks_t *table = &(data->smc_state_table.water_marks_table);
+	struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
 	int result = 0;
 	uint32_t i;
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index a202247..429c9c4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -455,7 +455,7 @@ extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 		enum amd_pp_clock_type type,
 		struct pp_clock_levels_with_voltage *clocks);
 extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
+						void *clock_ranges);
 extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 		struct pp_display_clock_request *clock);
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index fe549ac..29d1481 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -293,8 +293,7 @@ struct pp_hwmgr_func {
 	int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
 			enum amd_pp_clock_type type,
 			struct pp_clock_levels_with_voltage *clocks);
-	int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
-			struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
+	int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
 	int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
 			struct pp_display_clock_request *clock);
 	int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 5/5] drm/amd/display: Refine the interface dm_pp_notify_wm_clock_changes

[Alex Deucher]

On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> change function parameter type from dm_pp_wm_sets_with_clock_ranges * to
> void *. so this interface can be supported on AI/RV.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>
but should probably be approved by the DC team as well.

Alex

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 2 +-
>  drivers/gpu/drm/amd/display/dc/dm_services.h               | 2 +-
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h             | 2 +-
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c              | 6 +++---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c      | 4 ++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c          | 3 ++-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c         | 3 ++-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c         | 3 ++-
>  drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h        | 2 +-
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h                  | 3 +--
>  10 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> index 37f6a5f..92d36fe 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> @@ -408,7 +408,7 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
>
>  bool dm_pp_notify_wm_clock_changes(
>         const struct dc_context *ctx,
> -       struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
> +       void *clock_ranges)
>  {
>         /* TODO: to be implemented */
>         return false;
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
> index 4ff9b2b..535b415 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_services.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
> @@ -217,7 +217,7 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
>
>  bool dm_pp_notify_wm_clock_changes(
>         const struct dc_context *ctx,
> -       struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
> +       void *clock_ranges);
>
>  void dm_pp_get_funcs_rv(struct dc_context *ctx,
>                 struct pp_smu_funcs_rv *funcs);
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 4535756..06f7ef2 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -261,7 +261,7 @@ struct amd_pm_funcs {
>                 enum amd_pp_clock_type type,
>                 struct pp_clock_levels_with_voltage *clocks);
>         int (*set_watermarks_for_clocks_ranges)(void *handle,
> -               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
> +                                               void *clock_ranges);
>         int (*display_clock_voltage_request)(void *handle,
>                                 struct pp_display_clock_request *clock);
>         int (*get_display_mode_validation_clocks)(void *handle,
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 7b0ff9d..ba5e0e2 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1103,17 +1103,17 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
>  }
>
>  static int pp_set_watermarks_for_clocks_ranges(void *handle,
> -               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> +               void *clock_ranges)
>  {
>         struct pp_hwmgr *hwmgr = handle;
>         int ret = 0;
>
> -       if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
> +       if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
>                 return -EINVAL;
>
>         mutex_lock(&hwmgr->smu_lock);
>         ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
> -                       wm_with_clock_ranges);
> +                       clock_ranges);
>         mutex_unlock(&hwmgr->smu_lock);
>
>         return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index a0bb921..53207e7 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -435,7 +435,7 @@ int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>  }
>
>  int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> -               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> +                                       void *clock_ranges)
>  {
>         PHM_FUNC_CHECK(hwmgr);
>
> @@ -443,7 +443,7 @@ int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
>                 return -EINVAL;
>
>         return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
> -                       wm_with_clock_ranges);
> +                                                               clock_ranges);
>  }
>
>  int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 08690c9..4ca8033 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1131,9 +1131,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
>  }
>
>  static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> -               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> +               void *clock_ranges)
>  {
>         struct smu10_hwmgr *data = hwmgr->backend;
> +       struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
>         Watermarks_t *table = &(data->water_marks_table);
>         int result = 0;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 198c7ed..8554ede 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4195,9 +4195,10 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>  }
>
>  static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> -               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> +                                                       void *clock_range)
>  {
>         struct vega10_hwmgr *data = hwmgr->backend;
> +       struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
>         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
>         int result = 0;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index d685ce7..bcb64cd 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1713,10 +1713,11 @@ static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>  }
>
>  static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> -               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> +                                                       void *clock_ranges)
>  {
>         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
>         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
> +       struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
>         int result = 0;
>         uint32_t i;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> index a202247..429c9c4 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> @@ -455,7 +455,7 @@ extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>                 enum amd_pp_clock_type type,
>                 struct pp_clock_levels_with_voltage *clocks);
>  extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> -               struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
> +                                               void *clock_ranges);
>  extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
>                 struct pp_display_clock_request *clock);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index fe549ac..29d1481 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -293,8 +293,7 @@ struct pp_hwmgr_func {
>         int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
>                         enum amd_pp_clock_type type,
>                         struct pp_clock_levels_with_voltage *clocks);
> -       int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
> -                       struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
> +       int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
>         int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
>                         struct pp_display_clock_request *clock);
>         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency

[Alex Deucher]

On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Display component can get tru max_displ_clk_in_khz instand of hardcode

tru -> true
With that fixed:
Acked-by: Alex Deucher <alexander.deucher@amd.com>

>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 45 +++++++++++++++++++++-
>  1 file changed, 43 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> index 5a33461..37f6a5f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> @@ -261,6 +261,33 @@ static void pp_to_dc_clock_levels_with_latency(
>         }
>  }
>
> +static void pp_to_dc_clock_levels_with_voltage(
> +               const struct pp_clock_levels_with_voltage *pp_clks,
> +               struct dm_pp_clock_levels_with_voltage *clk_level_info,
> +               enum dm_pp_clock_type dc_clk_type)
> +{
> +       uint32_t i;
> +
> +       if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
> +               DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
> +                               DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
> +                               pp_clks->num_levels,
> +                               DM_PP_MAX_CLOCK_LEVELS);
> +
> +               clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
> +       } else
> +               clk_level_info->num_levels = pp_clks->num_levels;
> +
> +       DRM_DEBUG("DM_PPLIB: values for %s clock\n",
> +                       DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
> +
> +       for (i = 0; i < clk_level_info->num_levels; i++) {
> +               DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
> +               clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
> +               clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
> +       }
> +}
> +
>  bool dm_pp_get_clock_levels_by_type(
>                 const struct dc_context *ctx,
>                 enum dm_pp_clock_type clk_type,
> @@ -361,8 +388,22 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
>         enum dm_pp_clock_type clk_type,
>         struct dm_pp_clock_levels_with_voltage *clk_level_info)
>  {
> -       /* TODO: to be implemented */
> -       return false;
> +       struct amdgpu_device *adev = ctx->driver_context;
> +       void *pp_handle = adev->powerplay.pp_handle;
> +       struct pp_clock_levels_with_voltage pp_clks = { 0 };
> +       const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
> +
> +       if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)
> +               return false;
> +
> +       if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
> +                                                    dc_to_pp_clock_type(clk_type),
> +                                                    &pp_clks))
> +               return false;
> +
> +       pp_to_dc_clock_levels_with_voltage(&pp_clks, clk_level_info, clk_type);
> +
> +       return true;
>  }
>
>  bool dm_pp_notify_wm_clock_changes(
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency

[Harry Wentland]

On 2018-06-18 07:18 AM, Rex Zhu wrote:
> Display component can get tru max_displ_clk_in_khz instand of hardcode
> 
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Mikita has pretty much the same patch (part of the DC patchset going out tomorrow) and did the *10 on our end. I prefer your version, though, as that multiplication should probably come from powerplay. Haven't had a ton of time to look at this patchset closely today but will do so tomorrow with Mikita and get back to you.

Harry

> ---
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 45 +++++++++++++++++++++-
>  1 file changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> index 5a33461..37f6a5f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> @@ -261,6 +261,33 @@ static void pp_to_dc_clock_levels_with_latency(
>  	}
>  }
>  
> +static void pp_to_dc_clock_levels_with_voltage(
> +		const struct pp_clock_levels_with_voltage *pp_clks,
> +		struct dm_pp_clock_levels_with_voltage *clk_level_info,
> +		enum dm_pp_clock_type dc_clk_type)
> +{
> +	uint32_t i;
> +
> +	if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
> +		DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
> +				DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
> +				pp_clks->num_levels,
> +				DM_PP_MAX_CLOCK_LEVELS);
> +
> +		clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
> +	} else
> +		clk_level_info->num_levels = pp_clks->num_levels;
> +
> +	DRM_DEBUG("DM_PPLIB: values for %s clock\n",
> +			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
> +
> +	for (i = 0; i < clk_level_info->num_levels; i++) {
> +		DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
> +		clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
> +		clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
> +	}
> +}
> +
>  bool dm_pp_get_clock_levels_by_type(
>  		const struct dc_context *ctx,
>  		enum dm_pp_clock_type clk_type,
> @@ -361,8 +388,22 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
>  	enum dm_pp_clock_type clk_type,
>  	struct dm_pp_clock_levels_with_voltage *clk_level_info)
>  {
> -	/* TODO: to be implemented */
> -	return false;
> +	struct amdgpu_device *adev = ctx->driver_context;
> +	void *pp_handle = adev->powerplay.pp_handle;
> +	struct pp_clock_levels_with_voltage pp_clks = { 0 };
> +	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
> +
> +	if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)
> +		return false;
> +
> +	if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
> +						     dc_to_pp_clock_type(clk_type),
> +						     &pp_clks))
> +		return false;
> +
> +	pp_to_dc_clock_levels_with_voltage(&pp_clks, clk_level_info, clk_type);
> +
> +	return true;
>  }
>  
>  bool dm_pp_notify_wm_clock_changes(
> 
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 0/5] Rex's pplib/dc changes rebased on latest DC

[Harry Wentland]

Sending Rex's pplib changes rebased on the latest DC as that had some work Mikita did in the same area.

Patch 1 is
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Patches 2-3 are
Acked-by: Harry Wentland <harry.wentland@amd.com>

Not sure yet about 4-5. Will need to get someone with more expertise to eyeball those.

Harry

Rex Zhu (5):
  drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency
  drm/amd/pp: Fix wrong clock-unit exported to Display
  drm/amd/pp: Memory Latency is always 25us on Vega10
  drm/amd/display: Delete old implementation of
    bw_calcs_data_update_from_pplib
  drm/amd/display: Refine the interface dm_pp_notify_wm_clock_changes

 .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |  16 ++-
 .../display/amdgpu_dm/amdgpu_dm_services.c    |   2 +-
 .../amd/display/dc/dce120/dce120_resource.c   | 123 +-----------------
 drivers/gpu/drm/amd/display/dc/dm_services.h  |   2 +-
 .../gpu/drm/amd/include/kgd_pp_interface.h    |   2 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   6 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |   4 +-
 .../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c |   7 +-
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c    |  37 ++----
 .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c    |  13 +-
 .../drm/amd/powerplay/inc/hardwaremanager.h   |   2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h     |   3 +-
 12 files changed, 40 insertions(+), 177 deletions(-)

-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/5] drm/amd/pp: Memory Latency is always 25us on Vega10

[Harry Wentland]

From: Rex Zhu <Rex.Zhu@amd.com>

Also use the tolerable latency defined in Display
to find lowest MCLK frequency when disable mclk switch

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c    | 24 ++-----------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index e9a8b527d481..3e54de061496 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -55,12 +55,6 @@
 
 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
 
-#define MEM_FREQ_LOW_LATENCY        25000
-#define MEM_FREQ_HIGH_LATENCY       80000
-#define MEM_LATENCY_HIGH            245
-#define MEM_LATENCY_LOW             35
-#define MEM_LATENCY_ERR             0xFFFF
-
 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
 
@@ -3223,7 +3217,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 		/* Find the lowest MCLK frequency that is within
 		 * the tolerable latency defined in DAL
 		 */
-		latency = 0;
+		latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
 		for (i = 0; i < data->mclk_latency_table.count; i++) {
 			if ((data->mclk_latency_table.entries[i].latency <= latency) &&
 				(data->mclk_latency_table.entries[i].frequency >=
@@ -4074,18 +4068,6 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
 
 }
 
-static uint32_t vega10_get_mem_latency(struct pp_hwmgr *hwmgr,
-		uint32_t clock)
-{
-	if (clock >= MEM_FREQ_LOW_LATENCY &&
-			clock < MEM_FREQ_HIGH_LATENCY)
-		return MEM_LATENCY_HIGH;
-	else if (clock >= MEM_FREQ_HIGH_LATENCY)
-		return MEM_LATENCY_LOW;
-	else
-		return MEM_LATENCY_ERR;
-}
-
 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
 		struct pp_clock_levels_with_latency *clocks)
 {
@@ -4107,9 +4089,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
 					dep_table->entries[i].clk * 10;
 			clocks->data[clocks->num_levels].latency_in_us =
 			data->mclk_latency_table.entries
-			[data->mclk_latency_table.count].latency =
-					vega10_get_mem_latency(hwmgr,
-						dep_table->entries[i].clk);
+			[data->mclk_latency_table.count].latency = 25;
 			clocks->num_levels++;
 			data->mclk_latency_table.count++;
 		}
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx