* [PATCH v3 00/10] RISC-V SiFive FU540 support SPL
@ 2020-01-24 5:50 Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 01/10] misc: add driver for the Sifive otp controller Pragnesh Patel
` (9 more replies)
0 siblings, 10 replies; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
This series add support for SPL to FU540.U-Boot SPL can boot from
L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and
U-Boot proper from MMC devices.
How to test this patch:
1) Go to OpenSBI-dir : make PLATFORM=sifive/fu540 O=build_dir I=install_dir FW_DYNAMIC=y install
2) cp install_dir/platform/sifive/fu540/firmware/fw_dynamic.bin <u-boot-dir>/
3) Change to u-boot-dir
4) make sifive_fu540_spl_defconfig
5) make all
6) ZSBL loads the U-boot SPL(u-boot-spl.bin) from a partition with
GUID type 2e54b353-1271-4842-806f-e436d6af6985
sudo dd if=spl/u-boot-spl.bin of=/dev/sdc4 bs=1M
7) U-boot SPL expects a u-boot FIT image(u-boot.itb) from 1st partition(/dev/sdc1)
of SD card irrespective of GUID
sudo dd if=u-boot.itb of=/dev/sdc1 bs=1M
Following are the boot messages on FU540 five cores SMP platform:
U-Boot SPL 2020.01-00178-g30592e8819 (Jan 22 2020 - 14:37:24 +0530)
Trying to boot from MMC1
U-Boot 2020.01-00178-g30592e8819 (Jan 22 2020 - 14:37:24 +0530)
CPU: rv64imafdc
Model: SiFive HiFive Unleashed A00
DRAM: 8 GiB
MMC: spi at 10050000:mmc at 0: 0
In: serial at 10010000
Out: serial at 10010000
Err: serial at 10010000
Board serial number should not be 0 !!
Net:
Warning: ethernet at 10090000 (eth0) using random MAC address - e6:40:50:48:0d:8b
eth0: ethernet at 10090000
Hit any key to stop autoboot: 0
=> setenv serverip 172.16.35.74;setenv ipaddr 172.16.35.40;tftpboot 0x83000000 fit.itb;bootm 0x83000000
ethernet at 10090000: PHY present at 0
ethernet at 10090000: Starting autonegotiation...
ethernet at 10090000: Autonegotiation complete
ethernet at 10090000: link up, 100Mbps full-duplex (lpa: 0x41e1)
Using ethernet at 10090000 device
TFTP from server 172.16.35.74; our IP address is 172.16.35.40
Filename 'fit.itb'.
Load address: 0x83000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
###################################
940.4 KiB/s
done
Bytes transferred = 13823823 (d2ef4f hex)
## Loading kernel from FIT Image at 83000000 ...
Using 'config-1' configuration
Trying 'kernel at 1' kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: uncompressed
Data Start: 0x830000d8
Data Size: 9247260 Bytes = 8.8 MiB
Architecture: RISC-V
OS: Linux
Load Address: 0x80200000
Entry Point: 0x80200000
Verifying Hash Integrity ... OK
## Loading ramdisk from FIT Image at 83000000 ...
Using 'config-1' configuration
Trying 'ramdisk at 1' ramdisk subimage
Description: ramdisk
Type: RAMDisk Image
Compression: gzip compressed
Data Start: 0x838d3378
Data Size: 4568674 Bytes = 4.4 MiB
Architecture: RISC-V
OS: Linux
Load Address: 0x82000000
Entry Point: unavailable
Verifying Hash Integrity ... OK
Loading ramdisk from 0x838d3378 to 0x82000000
WARNING: 'compression' nodes for ramdisks are deprecated, please fix your .its file!
## Loading fdt from FIT Image at 83000000 ...
Using 'config-1' configuration
Trying 'fdt at 1' fdt subimage
Description: unavailable
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x838d1b80
Data Size: 6023 Bytes = 5.9 KiB
Architecture: RISC-V
Verifying Hash Integrity ... OK
Booting using the fdt blob at 0x838d1b80
Loading Kernel Image
Using Device Tree in place at 00000000838d1b80, end 00000000838d6306
Starting kernel ...
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
[ 0.000000] Linux version 5.3.0-13236-g97f9a3c4eee5 (pragneshp at sachinj2-OptiPlex-7010) (gcc version 8.2.0 (Buildroot 2018.11-rc2-00003-ga0787e9
[ 0.000000] earlycon: sifive0 at MMIO 0x0000000010010000 (options '')
[ 0.000000] printk: bootconsole [sifive0] enabled
[ 0.000000] Initial ramdisk at: 0x(____ptrval____) (4568674 bytes)
....
....
Welcome to Buildroot
buildroot login: root
Password:
#
Changes in v3:
- Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/
- Split SPL patches into DDR and SPL and spl defconfig
- Update fu540/MAINTAINERS file
- Update fu540.rst on how to build and flash U-boot SPL
Changes in v2:
- Add DM driver Sifive OTP
- Split SPL patches into multiple patches
- Add a seprate patch for _image_binary_end and crc7.c
- Add a seprate patch to add board -u-boot.dtsi files
- Update FU540 RISC-V documentation
Pragnesh Patel (10):
misc: add driver for the Sifive otp controller
riscv: Add _image_binary_end for SPL
lib: Makefile: build crc7.c when CONFIG_MMC_SPI
riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
riscv: sifive: fu540: add DDR4 info
riscv: sifive: fu540: add SPL configuration
configs: fu540: Add config file for U-boot SPL
riscv: sifive: fu540: enable all cache ways from u-boot proper
sifive: fix palmer's email address and add sifive_fu540_spl_defconfig
doc: update FU540 RISC-V documentation
arch/riscv/cpu/u-boot-spl.lds | 1 +
arch/riscv/dts/fu540-c000-u-boot.dtsi | 55 +
.../dts/hifive-unleashed-a00-u-boot.dtsi | 22 +
board/sifive/fu540/Kconfig | 8 +
board/sifive/fu540/MAINTAINERS | 3 +-
board/sifive/fu540/Makefile | 6 +
board/sifive/fu540/cache.c | 30 +
board/sifive/fu540/cache.h | 13 +
board/sifive/fu540/ddr.c | 868 ++++++++++++
board/sifive/fu540/fu540-memory-map.h | 33 +
board/sifive/fu540/fu540.c | 139 +-
board/sifive/fu540/regconfig-ctl.h | 270 ++++
board/sifive/fu540/regconfig-phy.h | 1220 +++++++++++++++++
board/sifive/fu540/spl.c | 252 ++++
board/sifive/fu540/ux00ddr.h | 45 +
board/sifive/fu540/ux00prci.h | 56 +
configs/sifive_fu540_defconfig | 2 +
configs/sifive_fu540_spl_defconfig | 26 +
doc/board/sifive/fu540.rst | 376 +++++
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/ememory-otp.c | 207 +++
include/configs/sifive-fu540.h | 18 +
lib/Makefile | 1 +
24 files changed, 3585 insertions(+), 74 deletions(-)
create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
create mode 100644 board/sifive/fu540/cache.c
create mode 100644 board/sifive/fu540/cache.h
create mode 100644 board/sifive/fu540/ddr.c
create mode 100644 board/sifive/fu540/fu540-memory-map.h
create mode 100644 board/sifive/fu540/regconfig-ctl.h
create mode 100644 board/sifive/fu540/regconfig-phy.h
create mode 100644 board/sifive/fu540/spl.c
create mode 100644 board/sifive/fu540/ux00ddr.h
create mode 100644 board/sifive/fu540/ux00prci.h
create mode 100644 configs/sifive_fu540_spl_defconfig
create mode 100644 drivers/misc/ememory-otp.c
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 01/10] misc: add driver for the Sifive otp controller
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-24 6:41 ` Jagan Teki
2020-01-24 5:50 ` [PATCH v3 02/10] riscv: Add _image_binary_end for SPL Pragnesh Patel
` (8 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
Added a misc driver to handle OTP memory in FU540.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 13 ++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
board/sifive/fu540/fu540.c | 113 ++++------
configs/sifive_fu540_defconfig | 2 +
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/ememory-otp.c | 207 ++++++++++++++++++
7 files changed, 276 insertions(+), 73 deletions(-)
create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
create mode 100644 drivers/misc/ememory-otp.c
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
new file mode 100644
index 0000000000..615a68c0e9
--- /dev/null
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 SiFive, Inc
+ */
+
+/ {
+ soc {
+ otp: otp at 10070000 {
+ compatible = "sifive,fu540-otp";
+ reg = <0x0 0x10070000 0x0 0x0FFF>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
new file mode 100644
index 0000000000..bec0d19134
--- /dev/null
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 SiFive, Inc
+ */
+
+#include "fu540-c000-u-boot.dtsi"
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 47a2090251..3a5e74f1fb 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -10,94 +10,61 @@
#include <dm.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <misc.h>
-#ifdef CONFIG_MISC_INIT_R
-
-#define FU540_OTP_BASE_ADDR 0x10070000
-
-struct fu540_otp_regs {
- u32 pa; /* Address input */
- u32 paio; /* Program address input */
- u32 pas; /* Program redundancy cell selection input */
- u32 pce; /* OTP Macro enable input */
- u32 pclk; /* Clock input */
- u32 pdin; /* Write data input */
- u32 pdout; /* Read data output */
- u32 pdstb; /* Deep standby mode enable input (active low) */
- u32 pprog; /* Program mode enable input */
- u32 ptc; /* Test column enable input */
- u32 ptm; /* Test mode enable input */
- u32 ptm_rep;/* Repair function test mode enable input */
- u32 ptr; /* Test row enable input */
- u32 ptrim; /* Repair function enable input */
- u32 pwe; /* Write enable input (defines program cycle) */
-} __packed;
-
-#define BYTES_PER_FUSE 4
-#define NUM_FUSES 0x1000
-
-static int fu540_otp_read(int offset, void *buf, int size)
-{
- struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
- unsigned int i;
- int fuseidx = offset / BYTES_PER_FUSE;
- int fusecount = size / BYTES_PER_FUSE;
- u32 fusebuf[fusecount];
-
- /* check bounds */
- if (offset < 0 || size < 0)
- return -EINVAL;
- if (fuseidx >= NUM_FUSES)
- return -EINVAL;
- if ((fuseidx + fusecount) > NUM_FUSES)
- return -EINVAL;
-
- /* init OTP */
- writel(0x01, ®s->pdstb); /* wake up from stand-by */
- writel(0x01, ®s->ptrim); /* enable repair function */
- writel(0x01, ®s->pce); /* enable input */
-
- /* read all requested fuses */
- for (i = 0; i < fusecount; i++, fuseidx++) {
- writel(fuseidx, ®s->pa);
-
- /* cycle clock to read */
- writel(0x01, ®s->pclk);
- mdelay(1);
- writel(0x00, ®s->pclk);
- mdelay(1);
-
- /* read the value */
- fusebuf[i] = readl(®s->pdout);
- }
-
- /* shut down */
- writel(0, ®s->pce);
- writel(0, ®s->ptrim);
- writel(0, ®s->pdstb);
-
- /* copy out */
- memcpy(buf, fusebuf, size);
+/*
+ * This define is a value used for error/unknown serial.
+ * If we really care about distinguishing errors and 0 is
+ * valid, we'll need a different one.
+ */
+#define ERROR_READING_SERIAL_NUMBER 0
- return 0;
-}
+#ifdef CONFIG_MISC_INIT_R
-static u32 fu540_read_serialnum(void)
+#if CONFIG_IS_ENABLED(EMEMORY_OTP)
+static u32 otp_read_serialnum(struct udevice *dev)
{
int ret;
u32 serial[2] = {0};
for (int i = 0xfe * 4; i > 0; i -= 8) {
- ret = fu540_otp_read(i, serial, sizeof(serial));
+ ret = misc_read(dev, i, serial, sizeof(serial));
+
if (ret) {
- printf("%s: error reading from OTP\n", __func__);
+ printf("%s: error reading serial from OTP\n", __func__);
break;
}
+
if (serial[0] == ~serial[1])
return serial[0];
}
- return 0;
+ return ERROR_READING_SERIAL_NUMBER;
+}
+#endif
+
+static u32 fu540_read_serialnum(void)
+{
+ u32 serial = ERROR_READING_SERIAL_NUMBER;
+
+#if CONFIG_IS_ENABLED(EMEMORY_OTP)
+ struct udevice *dev;
+ int ret;
+
+ // init OTP
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(hifive_otp), &dev);
+
+ if (ret) {
+ debug("%s: could not find otp device\n", __func__);
+ return serial;
+ }
+
+ // read serial from OTP and set env var
+ serial = otp_read_serialnum(dev);
+#endif
+
+ return serial;
}
static void fu540_setup_macaddr(u32 serialnum)
diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
index 6d61e6c960..40e78f12a2 100644
--- a/configs/sifive_fu540_defconfig
+++ b/configs/sifive_fu540_defconfig
@@ -6,6 +6,8 @@ CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_MISC=y
+CONFIG_EMEMORY_OTP=y
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f18aa8f7ba..cbda0deb14 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -68,6 +68,13 @@ config ROCKCHIP_OTP
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
+config EMEMORY_OTP
+ bool "Sifive Ememory OTP driver"
+ depends on RISCV && MISC
+ help
+ Enable support for reading the Ememory OTP on the HiFive Unleashed
+ OTP storage.
+
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 2b843de93c..dcf9b628c8 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
+obj-$(CONFIG_EMEMORY_OTP) += ememory-otp.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
diff --git a/drivers/misc/ememory-otp.c b/drivers/misc/ememory-otp.c
new file mode 100644
index 0000000000..73e7af496a
--- /dev/null
+++ b/drivers/misc/ememory-otp.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
+ * One-Time-Programmable (OTP) memory used within the SiFive FU540.
+ * It is documented in the FU540 manual here:
+ * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
+ *
+ * Copyright (C) 2018 Philipp Hug <philipp@hug.cx>
+ * Copyright (C) 2018 Joey Hewitt <joey@joeyhewitt.com>
+ *
+ * Copyright (C) 2020 SiFive, Inc
+ */
+
+/*
+ * The FU540 stores 4096x32 bit (16KiB) values.
+ * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/read.h>
+#include <linux/io.h>
+#include <misc.h>
+
+struct hifive_otp_regs {
+ u32 pa; /* Address input */
+ u32 paio; /* Program address input */
+ u32 pas; /* Program redundancy cell selection input */
+ u32 pce; /* OTP Macro enable input */
+ u32 pclk; /* Clock input */
+ u32 pdin; /* Write data input */
+ u32 pdout; /* Read data output */
+ u32 pdstb; /* Deep standby mode enable input (active low) */
+ u32 pprog; /* Program mode enable input */
+ u32 ptc; /* Test column enable input */
+ u32 ptm; /* Test mode enable input */
+ u32 ptm_rep;/* Repair function test mode enable input */
+ u32 ptr; /* Test row enable input */
+ u32 ptrim; /* Repair function enable input */
+ u32 pwe; /* Write enable input (defines program cycle) */
+} __packed;
+
+struct hifive_otp_platdata {
+ struct hifive_otp_regs __iomem *regs;
+};
+
+typedef u32 fuse_value_t;
+#define BYTES_PER_FUSE 4
+
+#define NUM_FUSES 0x1000
+
+/*
+ * offset and size are assumed aligned to the size of the fuses (32bit).
+ */
+static int hifive_otp_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct hifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct hifive_otp_regs *regs = (struct hifive_otp_regs *)plat->regs;
+
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+ fuse_value_t fusebuf[fusecount];
+
+ // check bounds
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= NUM_FUSES)
+ return -EINVAL;
+ if ((fuseidx + fusecount) > NUM_FUSES)
+ return -EINVAL;
+
+ // init OTP
+ iowrite32(0x01, ®s->pdstb); // wake up from stand-by
+ iowrite32(0x01, ®s->ptrim); // enable repair function
+ iowrite32(0x01, ®s->pce); // enable input
+
+ // read all requested fuses
+ for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
+ iowrite32(fuseidx, ®s->pa);
+
+ // cycle clock to read
+ iowrite32(0x01, ®s->pclk);
+ mdelay(1);
+ iowrite32(0x00, ®s->pclk);
+ mdelay(1);
+
+ // read the value
+ fusebuf[i] = ioread32(®s->pdout);
+ }
+
+ // shut down
+ iowrite32(0, ®s->pce);
+ iowrite32(0, ®s->ptrim);
+ iowrite32(0, ®s->pdstb);
+
+ // copy out
+ memcpy(buf, fusebuf, size);
+
+ return 0;
+}
+
+/*
+ * Caution:
+ * OTP can be write only once, so use carefully.
+ *
+ * offset and size are assumed aligned to the size of the fuses (32bit).
+ */
+static int hifive_otp_write(struct udevice *dev, int offset,
+ const void *buf, int size)
+{
+ struct hifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct hifive_otp_regs *regs = (struct hifive_otp_regs *)plat->regs;
+
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+ u32 *write_buf = (u32 *)buf;
+ u32 write_data;
+ int i, pas, bit;
+
+ // check bounds
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= NUM_FUSES)
+ return -EINVAL;
+ if ((fuseidx + fusecount) > NUM_FUSES)
+ return -EINVAL;
+
+ // init OTP
+ iowrite32(0x01, ®s->pdstb); // wake up from stand-by
+ iowrite32(0x01, ®s->ptrim); // enable repair function
+
+ iowrite32(0x00, ®s->pclk);
+ iowrite32(0x00, ®s->pa);
+ iowrite32(0x00, ®s->pas);
+ iowrite32(0x00, ®s->paio);
+ iowrite32(0x00, ®s->pdin);
+ iowrite32(0x00, ®s->pwe);
+ iowrite32(0x02, ®s->ptm);
+ mdelay(1);
+
+ iowrite32(0x01, ®s->pce); // enable input
+ iowrite32(0x01, ®s->pprog); // Program mode enable input
+ iowrite32(0x01, ®s->ptrim);
+
+ // write all requested fuses
+ for (i = 0; i < fusecount; i++, fuseidx++) {
+ iowrite32(fuseidx, ®s->pa);
+ write_data = *(write_buf++);
+
+ for (pas = 0; pas < 2; pas++) {
+ iowrite32(pas, ®s->pas);
+
+ for (bit = 0; bit < 32; bit++) {
+ iowrite32(bit, ®s->paio);
+ iowrite32(((write_data >> bit) & 1),
+ ®s->pdin);
+ mdelay(1);
+
+ iowrite32(0x01, ®s->pwe);
+ mdelay(1);
+ iowrite32(0x00, ®s->pwe);
+ mdelay(1);
+ }
+ }
+
+ iowrite32(0x00, ®s->pas);
+ }
+
+ // shut down
+ iowrite32(0x00, ®s->pwe);
+ iowrite32(0x00, ®s->pprog);
+ iowrite32(0x00, ®s->pce);
+ iowrite32(0x00, ®s->ptm);
+
+ iowrite32(0x00, ®s->ptrim);
+ iowrite32(0x00, ®s->pdstb);
+
+ return 0;
+}
+
+static int hifive_otp_ofdata_to_platdata(struct udevice *dev)
+{
+ struct hifive_otp_platdata *plat = dev_get_platdata(dev);
+
+ plat->regs = dev_read_addr_ptr(dev);
+ return 0;
+}
+
+static const struct misc_ops hifive_otp_ops = {
+ .read = hifive_otp_read,
+ .write = hifive_otp_write,
+};
+
+static const struct udevice_id hifive_otp_ids[] = {
+ { .compatible = "sifive,fu540-otp" },
+ {}
+};
+
+U_BOOT_DRIVER(hifive_otp) = {
+ .name = "hifive_otp",
+ .id = UCLASS_MISC,
+ .of_match = hifive_otp_ids,
+ .ofdata_to_platdata = hifive_otp_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct hifive_otp_platdata),
+ .ops = &hifive_otp_ops,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 02/10] riscv: Add _image_binary_end for SPL
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 01/10] misc: add driver for the Sifive otp controller Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-24 6:44 ` Jagan Teki
2020-01-24 5:50 ` [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
` (7 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 955dd3106d..d0495ce248 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -72,6 +72,7 @@ SECTIONS
. = ALIGN(4);
_end = .;
+ _image_binary_end = .;
.bss : {
__bss_start = .;
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 01/10] misc: add driver for the Sifive otp controller Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 02/10] riscv: Add _image_binary_end for SPL Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-24 6:27 ` Jagan Teki
2020-01-24 5:50 ` [PATCH v3 04/10] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
` (6 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
When build U-boot SPL, meet an issue of undefined reference to
'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
CONFIG_MMC_SPI selected.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
lib/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/Makefile b/lib/Makefile
index 51eba80b89..d21e0a6b3a 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -78,6 +78,7 @@ endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
+obj-$(CONFIG_MMC_SPI) += crc7.o
obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o
obj-y += net_utils.o
endif
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 04/10] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (2 preceding siblings ...)
2020-01-24 5:50 ` [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info Pragnesh Patel
` (5 subsequent siblings)
9 siblings, 0 replies; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these u-boot in FU540 would also require
some u-boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain u-boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 42 +++++++++++++++++++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 16 +++++++
2 files changed, 58 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 615a68c0e9..7a7abc7cce 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -4,10 +4,52 @@
*/
/ {
+ cpus {
+ u-boot,dm-spl;
+ cpu0: cpu at 0 {
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu at 1 {
+ u-boot,dm-spl;
+ };
+ cpu2: cpu at 2 {
+ u-boot,dm-spl;
+ };
+ cpu3: cpu at 3 {
+ u-boot,dm-spl;
+ };
+ cpu4: cpu at 4 {
+ u-boot,dm-spl;
+ };
+ };
+
soc {
+ u-boot,dm-spl;
otp: otp at 10070000 {
compatible = "sifive,fu540-otp";
reg = <0x0 0x10070000 0x0 0x0FFF>;
};
+ clint at 2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 >;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ u-boot,dm-spl;
+ };
};
};
+
+&prci {
+ u-boot,dm-spl;
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&qspi2 {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index bec0d19134..cce1bd943e 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -4,3 +4,19 @@
*/
#include "fu540-c000-u-boot.dtsi"
+
+/ {
+ hfclk {
+ u-boot,dm-spl;
+ };
+
+ rtcclk {
+ u-boot,dm-spl;
+ };
+};
+
+&qspi2 {
+ mmc at 0 {
+ u-boot,dm-spl;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (3 preceding siblings ...)
2020-01-24 5:50 ` [PATCH v3 04/10] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-25 8:31 ` Anup Patel
2020-01-27 7:51 ` Jagan Teki
2020-01-24 5:50 ` [PATCH v3 06/10] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
` (4 subsequent siblings)
9 siblings, 2 replies; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
Add ddr4 controller and phy related files
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
board/sifive/fu540/Makefile | 4 +
board/sifive/fu540/ddr.c | 868 ++++++++++++++++++++
board/sifive/fu540/regconfig-ctl.h | 270 ++++++
board/sifive/fu540/regconfig-phy.h | 1220 ++++++++++++++++++++++++++++
board/sifive/fu540/ux00ddr.h | 45 +
5 files changed, 2407 insertions(+)
create mode 100644 board/sifive/fu540/ddr.c
create mode 100644 board/sifive/fu540/regconfig-ctl.h
create mode 100644 board/sifive/fu540/regconfig-phy.h
create mode 100644 board/sifive/fu540/ux00ddr.h
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index 6e1862c475..e4e76e1de3 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -3,3 +3,7 @@
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += ddr.o
+endif
diff --git a/board/sifive/fu540/ddr.c b/board/sifive/fu540/ddr.c
new file mode 100644
index 0000000000..a4a86b1173
--- /dev/null
+++ b/board/sifive/fu540/ddr.c
@@ -0,0 +1,868 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#include <common.h>
+
+#include "regconfig-ctl.h"
+#include "regconfig-phy.h"
+
+#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
+
+#define DRAM_CLASS_OFFSET 8
+#define OPTIMAL_RMODW_EN_OFFSET 0
+#define DISABLE_RD_INTERLEAVE_OFFSET 16
+#define OUT_OF_RANGE_OFFSET 1
+#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
+#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
+#define MC_INIT_COMPLETE_OFFSET 8
+#define LEVELING_OPERATION_COMPLETED_OFFSET 22
+#define DFI_PHY_WRLELV_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
+#define VREF_EN_OFFSET 24
+#define PORT_ADDR_PROTECTION_EN_OFFSET 0
+#define AXI0_ADDRESS_RANGE_ENABLE 8
+#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
+#define RDLVL_EN_OFFSET 16
+#define RDLVL_GATE_EN_OFFSET 24
+#define WRLVL_EN_OFFSET 0
+
+#define PHY_RX_CAL_DQ0_0_OFFSET 0
+#define PHY_RX_CAL_DQ1_0_OFFSET 16
+
+static void phy_reset(u32 *ddrphyreg, const
+ u32 *physettings)
+{
+ unsigned int i;
+
+ for (i = 1152; i <= 1214; i++) {
+ u32 physet = physettings[i];
+ /*if (physet!=0)*/ ddrphyreg[i] = physet;
+ }
+
+ for (i = 0; i <= 1151; i++) {
+ u32 physet = physettings[i];
+ /*if (physet!=0)*/ ddrphyreg[i] = physet;
+ }
+}
+
+void ux00ddr_writeregmap(size_t ahbregaddr, const
+ u32 *ctlsettings, const u32 *physettings)
+{
+ u32 *ddrctlreg = (u32 *)ahbregaddr;
+ u32 *ddrphyreg = ((u32 *)ahbregaddr) +
+ (0x2000 / sizeof(u32));
+
+ unsigned int i;
+
+ for (i = 0; i <= 264; i++) {
+ u32 ctlset = ctlsettings[i];
+ /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset;
+ }
+
+ phy_reset(ddrphyreg, physettings);
+}
+
+void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend)
+{
+ // START register@ddrctl register base offset 0
+ u32 regdata = _REG32(0 << 2, ahbregaddr);
+
+ regdata |= 0x1;
+ _REG32(0 << 2, ahbregaddr) = regdata;
+
+ /*
+ * WAIT for initialization complete : bit 8 of INT_STATUS
+ * (DENALI_CTL_132) 0x210
+ */
+ while ((_REG32(132 << 2, ahbregaddr) & (1 <<
+ MC_INIT_COMPLETE_OFFSET)) == 0) {
+ }
+
+ // Disable the BusBlocker in front of the controller AXI slave ports
+ u64 *filterreg = (u64 *)filteraddr;
+
+ filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
+}
+
+void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr)
+{
+ /*
+ * Mask off Bit 8 of Interrupt Status
+ * Bit [8] The MC initialization has been completed
+ */
+
+ _REG32(136 << 2, ahbregaddr) |= (1 << MC_INIT_COMPLETE_OFFSET);
+}
+
+void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr)
+{
+ /*
+ * Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status
+ * Bit [2] Multiple accesses outside the defined PHYSICAL memory
+ * space have occurred
+ * Bit [1] A memory access outside the defined PHYSICAL memory
+ * space has occurred
+ */
+
+ _REG32(136 << 2, ahbregaddr) |= ((1 << OUT_OF_RANGE_OFFSET) | (1 <<
+ MULTIPLE_OUT_OF_RANGE_OFFSET));
+}
+
+void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr)
+{
+ /*
+ * Mask off Bit 7 of Interrupt Status
+ * Bit [7] An error occurred on the port command channel
+ */
+
+ _REG32(136 << 2, ahbregaddr) |= (1 <<
+ PORT_COMMAND_CHANNEL_ERROR_OFFSET);
+}
+
+void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr)
+{
+ /*
+ * Mask off Bit 22 of Interrupt Status
+ * Bit [22] The leveling operation has completed
+ */
+
+ _REG32(136 << 2, ahbregaddr) |= (1 <<
+ LEVELING_OPERATION_COMPLETED_OFFSET);
+}
+
+void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr)
+{
+ _REG32(209 << 2, ahbregaddr) = 0x0;
+ size_t end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
+
+ _REG32(210 << 2, ahbregaddr) = ((u32)end_addr_16kblocks);
+ _REG32(212 << 2, ahbregaddr) = 0x0;
+ _REG32(214 << 2, ahbregaddr) = 0x0;
+ _REG32(216 << 2, ahbregaddr) = 0x0;
+ _REG32(224 << 2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
+ _REG32(225 << 2, ahbregaddr) = 0xFFFFFFFF;
+ _REG32(208 << 2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
+ _REG32(208 << 2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
+}
+
+void ux00ddr_disableaxireadinterleave(size_t ahbregaddr)
+{
+ _REG32(120 << 2, ahbregaddr) |= (1 << DISABLE_RD_INTERLEAVE_OFFSET);
+}
+
+void ux00ddr_disableoptimalrmodw(size_t ahbregaddr)
+{
+ _REG32(21 << 2, ahbregaddr) &= (~(1 << OPTIMAL_RMODW_EN_OFFSET));
+}
+
+void ux00ddr_enablewriteleveling(size_t ahbregaddr)
+{
+ _REG32(170 << 2, ahbregaddr) |= ((1 << WRLVL_EN_OFFSET) | (1 <<
+ DFI_PHY_WRLELV_MODE_OFFSET));
+}
+
+void ux00ddr_enablereadleveling(size_t ahbregaddr)
+{
+ _REG32(181 << 2, ahbregaddr) |= (1 << DFI_PHY_RDLVL_MODE_OFFSET);
+ _REG32(260 << 2, ahbregaddr) |= (1 << RDLVL_EN_OFFSET);
+}
+
+void ux00ddr_enablereadlevelinggate(size_t ahbregaddr)
+{
+ _REG32(260 << 2, ahbregaddr) |= (1 << RDLVL_GATE_EN_OFFSET);
+ _REG32(182 << 2, ahbregaddr) |= (1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
+}
+
+void ux00ddr_enablevreftraining(size_t ahbregaddr)
+{
+ _REG32(184 << 2, ahbregaddr) |= (1 << VREF_EN_OFFSET);
+}
+
+u32 ux00ddr_getdramclass(size_t ahbregaddr)
+{
+ return((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF);
+}
+
+u64 ux00ddr_phy_fixup(size_t ahbregaddr)
+{
+ // return bitmask of failed lanes
+
+ size_t ddrphyreg = ahbregaddr + 0x2000;
+
+ u64 fails = 0;
+ u32 slicebase = 0;
+ u32 dq = 0;
+
+ // check errata condition
+ for (u32 slice = 0; slice < 8; slice++) {
+ u32 regbase = slicebase + 34;
+
+ for (u32 reg = 0; reg < 4; reg++) {
+ u32 updownreg = _REG32((regbase + reg) << 2,
+ ddrphyreg);
+
+ for (u32 bit = 0; bit < 2; bit++) {
+ u32 phy_rx_cal_dqn_0_offset;
+
+ if (bit == 0) {
+ phy_rx_cal_dqn_0_offset =
+ PHY_RX_CAL_DQ0_0_OFFSET;
+ } else {
+ phy_rx_cal_dqn_0_offset =
+ PHY_RX_CAL_DQ1_0_OFFSET;
+ }
+
+ u32 down = (updownreg >>
+ phy_rx_cal_dqn_0_offset) & 0x3F;
+ u32 up = (updownreg >>
+ (phy_rx_cal_dqn_0_offset + 6)) &
+ 0x3F;
+
+ u8 failc0 = ((down == 0) && (up == 0x3F));
+ u8 failc1 = ((up == 0) && (down == 0x3F));
+
+ // print error message on failure
+ if (failc0 || failc1) {
+ if (fails == 0)
+ printf("DDR error in fixing up\n");
+
+ fails |= (1 << dq);
+
+ char slicelsc = '0';
+ char slicemsc = '0';
+
+ slicelsc += (dq % 10);
+ slicemsc += (dq / 10);
+ printf("S ");
+ printf("%c", slicemsc);
+ printf("%c", slicelsc);
+
+ if (failc0)
+ printf("U");
+ else
+ printf("D");
+
+ printf("\n");
+ }
+ dq++;
+ }
+ }
+ slicebase += 128;
+ }
+ return(0);
+}
+
+u32 ddr_phy_settings[1215] = {
+ DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, DENALI_PHY_02_DATA,
+ DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, DENALI_PHY_05_DATA,
+ DENALI_PHY_06_DATA, DENALI_PHY_07_DATA, DENALI_PHY_08_DATA,
+ DENALI_PHY_09_DATA,
+ DENALI_PHY_10_DATA, DENALI_PHY_11_DATA, DENALI_PHY_12_DATA,
+ DENALI_PHY_13_DATA, DENALI_PHY_14_DATA, DENALI_PHY_15_DATA,
+ DENALI_PHY_16_DATA, DENALI_PHY_17_DATA, DENALI_PHY_18_DATA,
+ DENALI_PHY_19_DATA,
+ DENALI_PHY_20_DATA, DENALI_PHY_21_DATA, DENALI_PHY_22_DATA,
+ DENALI_PHY_23_DATA, DENALI_PHY_24_DATA, DENALI_PHY_25_DATA,
+ DENALI_PHY_26_DATA, DENALI_PHY_27_DATA, DENALI_PHY_28_DATA,
+ DENALI_PHY_29_DATA,
+ DENALI_PHY_30_DATA, DENALI_PHY_31_DATA, DENALI_PHY_32_DATA,
+ DENALI_PHY_33_DATA, DENALI_PHY_34_DATA, DENALI_PHY_35_DATA,
+ DENALI_PHY_36_DATA, DENALI_PHY_37_DATA, DENALI_PHY_38_DATA,
+ DENALI_PHY_39_DATA,
+ DENALI_PHY_40_DATA, DENALI_PHY_41_DATA, DENALI_PHY_42_DATA,
+ DENALI_PHY_43_DATA, DENALI_PHY_44_DATA, DENALI_PHY_45_DATA,
+ DENALI_PHY_46_DATA, DENALI_PHY_47_DATA, DENALI_PHY_48_DATA,
+ DENALI_PHY_49_DATA,
+ DENALI_PHY_50_DATA, DENALI_PHY_51_DATA, DENALI_PHY_52_DATA,
+ DENALI_PHY_53_DATA, DENALI_PHY_54_DATA, DENALI_PHY_55_DATA,
+ DENALI_PHY_56_DATA, DENALI_PHY_57_DATA, DENALI_PHY_58_DATA,
+ DENALI_PHY_59_DATA,
+ DENALI_PHY_60_DATA, DENALI_PHY_61_DATA, DENALI_PHY_62_DATA,
+ DENALI_PHY_63_DATA, DENALI_PHY_64_DATA, DENALI_PHY_65_DATA,
+ DENALI_PHY_66_DATA, DENALI_PHY_67_DATA, DENALI_PHY_68_DATA,
+ DENALI_PHY_69_DATA,
+ DENALI_PHY_70_DATA, DENALI_PHY_71_DATA, DENALI_PHY_72_DATA,
+ DENALI_PHY_73_DATA, DENALI_PHY_74_DATA, DENALI_PHY_75_DATA,
+ DENALI_PHY_76_DATA, DENALI_PHY_77_DATA, DENALI_PHY_78_DATA,
+ DENALI_PHY_79_DATA,
+ DENALI_PHY_80_DATA, DENALI_PHY_81_DATA, DENALI_PHY_82_DATA,
+ DENALI_PHY_83_DATA, DENALI_PHY_84_DATA, DENALI_PHY_85_DATA,
+ DENALI_PHY_86_DATA, DENALI_PHY_87_DATA, DENALI_PHY_88_DATA,
+ DENALI_PHY_89_DATA,
+ DENALI_PHY_90_DATA, DENALI_PHY_91_DATA, DENALI_PHY_92_DATA,
+ DENALI_PHY_93_DATA, DENALI_PHY_94_DATA, DENALI_PHY_95_DATA,
+ DENALI_PHY_96_DATA, DENALI_PHY_97_DATA, DENALI_PHY_98_DATA,
+ DENALI_PHY_99_DATA,
+
+ DENALI_PHY_100_DATA, DENALI_PHY_101_DATA, DENALI_PHY_102_DATA,
+ DENALI_PHY_103_DATA, DENALI_PHY_104_DATA, DENALI_PHY_105_DATA,
+ DENALI_PHY_106_DATA, DENALI_PHY_107_DATA, DENALI_PHY_108_DATA,
+ DENALI_PHY_109_DATA,
+ DENALI_PHY_110_DATA, DENALI_PHY_111_DATA, DENALI_PHY_112_DATA,
+ DENALI_PHY_113_DATA, DENALI_PHY_114_DATA, DENALI_PHY_115_DATA,
+ DENALI_PHY_116_DATA, DENALI_PHY_117_DATA, DENALI_PHY_118_DATA,
+ DENALI_PHY_119_DATA,
+ DENALI_PHY_120_DATA, DENALI_PHY_121_DATA, DENALI_PHY_122_DATA,
+ DENALI_PHY_123_DATA, DENALI_PHY_124_DATA, DENALI_PHY_125_DATA,
+ DENALI_PHY_126_DATA, DENALI_PHY_127_DATA, DENALI_PHY_128_DATA,
+ DENALI_PHY_129_DATA,
+ DENALI_PHY_130_DATA, DENALI_PHY_131_DATA, DENALI_PHY_132_DATA,
+ DENALI_PHY_133_DATA, DENALI_PHY_134_DATA, DENALI_PHY_135_DATA,
+ DENALI_PHY_136_DATA, DENALI_PHY_137_DATA, DENALI_PHY_138_DATA,
+ DENALI_PHY_139_DATA,
+ DENALI_PHY_140_DATA, DENALI_PHY_141_DATA, DENALI_PHY_142_DATA,
+ DENALI_PHY_143_DATA, DENALI_PHY_144_DATA, DENALI_PHY_145_DATA,
+ DENALI_PHY_146_DATA, DENALI_PHY_147_DATA, DENALI_PHY_148_DATA,
+ DENALI_PHY_149_DATA,
+ DENALI_PHY_150_DATA, DENALI_PHY_151_DATA, DENALI_PHY_152_DATA,
+ DENALI_PHY_153_DATA, DENALI_PHY_154_DATA, DENALI_PHY_155_DATA,
+ DENALI_PHY_156_DATA, DENALI_PHY_157_DATA, DENALI_PHY_158_DATA,
+ DENALI_PHY_159_DATA,
+ DENALI_PHY_160_DATA, DENALI_PHY_161_DATA, DENALI_PHY_162_DATA,
+ DENALI_PHY_163_DATA, DENALI_PHY_164_DATA, DENALI_PHY_165_DATA,
+ DENALI_PHY_166_DATA, DENALI_PHY_167_DATA, DENALI_PHY_168_DATA,
+ DENALI_PHY_169_DATA,
+ DENALI_PHY_170_DATA, DENALI_PHY_171_DATA, DENALI_PHY_172_DATA,
+ DENALI_PHY_173_DATA, DENALI_PHY_174_DATA, DENALI_PHY_175_DATA,
+ DENALI_PHY_176_DATA, DENALI_PHY_177_DATA, DENALI_PHY_178_DATA,
+ DENALI_PHY_179_DATA,
+ DENALI_PHY_180_DATA, DENALI_PHY_181_DATA, DENALI_PHY_182_DATA,
+ DENALI_PHY_183_DATA, DENALI_PHY_184_DATA, DENALI_PHY_185_DATA,
+ DENALI_PHY_186_DATA, DENALI_PHY_187_DATA, DENALI_PHY_188_DATA,
+ DENALI_PHY_189_DATA,
+ DENALI_PHY_190_DATA, DENALI_PHY_191_DATA, DENALI_PHY_192_DATA,
+ DENALI_PHY_193_DATA, DENALI_PHY_194_DATA, DENALI_PHY_195_DATA,
+ DENALI_PHY_196_DATA, DENALI_PHY_197_DATA, DENALI_PHY_198_DATA,
+ DENALI_PHY_199_DATA,
+
+ DENALI_PHY_200_DATA, DENALI_PHY_201_DATA, DENALI_PHY_202_DATA,
+ DENALI_PHY_203_DATA, DENALI_PHY_204_DATA, DENALI_PHY_205_DATA,
+ DENALI_PHY_206_DATA, DENALI_PHY_207_DATA, DENALI_PHY_208_DATA,
+ DENALI_PHY_209_DATA,
+ DENALI_PHY_210_DATA, DENALI_PHY_211_DATA, DENALI_PHY_212_DATA,
+ DENALI_PHY_213_DATA, DENALI_PHY_214_DATA, DENALI_PHY_215_DATA,
+ DENALI_PHY_216_DATA, DENALI_PHY_217_DATA, DENALI_PHY_218_DATA,
+ DENALI_PHY_219_DATA,
+ DENALI_PHY_220_DATA, DENALI_PHY_221_DATA, DENALI_PHY_222_DATA,
+ DENALI_PHY_223_DATA, DENALI_PHY_224_DATA, DENALI_PHY_225_DATA,
+ DENALI_PHY_226_DATA, DENALI_PHY_227_DATA, DENALI_PHY_228_DATA,
+ DENALI_PHY_229_DATA,
+ DENALI_PHY_230_DATA, DENALI_PHY_231_DATA, DENALI_PHY_232_DATA,
+ DENALI_PHY_233_DATA, DENALI_PHY_234_DATA, DENALI_PHY_235_DATA,
+ DENALI_PHY_236_DATA, DENALI_PHY_237_DATA, DENALI_PHY_238_DATA,
+ DENALI_PHY_239_DATA,
+ DENALI_PHY_240_DATA, DENALI_PHY_241_DATA, DENALI_PHY_242_DATA,
+ DENALI_PHY_243_DATA, DENALI_PHY_244_DATA, DENALI_PHY_245_DATA,
+ DENALI_PHY_246_DATA, DENALI_PHY_247_DATA, DENALI_PHY_248_DATA,
+ DENALI_PHY_249_DATA,
+ DENALI_PHY_250_DATA, DENALI_PHY_251_DATA, DENALI_PHY_252_DATA,
+ DENALI_PHY_253_DATA, DENALI_PHY_254_DATA, DENALI_PHY_255_DATA,
+ DENALI_PHY_256_DATA, DENALI_PHY_257_DATA, DENALI_PHY_258_DATA,
+ DENALI_PHY_259_DATA,
+ DENALI_PHY_260_DATA, DENALI_PHY_261_DATA, DENALI_PHY_262_DATA,
+ DENALI_PHY_263_DATA, DENALI_PHY_264_DATA, DENALI_PHY_265_DATA,
+ DENALI_PHY_266_DATA, DENALI_PHY_267_DATA, DENALI_PHY_268_DATA,
+ DENALI_PHY_269_DATA,
+ DENALI_PHY_270_DATA, DENALI_PHY_271_DATA, DENALI_PHY_272_DATA,
+ DENALI_PHY_273_DATA, DENALI_PHY_274_DATA, DENALI_PHY_275_DATA,
+ DENALI_PHY_276_DATA, DENALI_PHY_277_DATA, DENALI_PHY_278_DATA,
+ DENALI_PHY_279_DATA,
+ DENALI_PHY_280_DATA, DENALI_PHY_281_DATA, DENALI_PHY_282_DATA,
+ DENALI_PHY_283_DATA, DENALI_PHY_284_DATA, DENALI_PHY_285_DATA,
+ DENALI_PHY_286_DATA, DENALI_PHY_287_DATA, DENALI_PHY_288_DATA,
+ DENALI_PHY_289_DATA,
+ DENALI_PHY_290_DATA, DENALI_PHY_291_DATA, DENALI_PHY_292_DATA,
+ DENALI_PHY_293_DATA, DENALI_PHY_294_DATA, DENALI_PHY_295_DATA,
+ DENALI_PHY_296_DATA, DENALI_PHY_297_DATA, DENALI_PHY_298_DATA,
+ DENALI_PHY_299_DATA,
+
+ DENALI_PHY_300_DATA, DENALI_PHY_301_DATA, DENALI_PHY_302_DATA,
+ DENALI_PHY_303_DATA, DENALI_PHY_304_DATA, DENALI_PHY_305_DATA,
+ DENALI_PHY_306_DATA, DENALI_PHY_307_DATA, DENALI_PHY_308_DATA,
+ DENALI_PHY_309_DATA,
+ DENALI_PHY_310_DATA, DENALI_PHY_311_DATA, DENALI_PHY_312_DATA,
+ DENALI_PHY_313_DATA, DENALI_PHY_314_DATA, DENALI_PHY_315_DATA,
+ DENALI_PHY_316_DATA, DENALI_PHY_317_DATA, DENALI_PHY_318_DATA,
+ DENALI_PHY_319_DATA,
+ DENALI_PHY_320_DATA, DENALI_PHY_321_DATA, DENALI_PHY_322_DATA,
+ DENALI_PHY_323_DATA, DENALI_PHY_324_DATA, DENALI_PHY_325_DATA,
+ DENALI_PHY_326_DATA, DENALI_PHY_327_DATA, DENALI_PHY_328_DATA,
+ DENALI_PHY_329_DATA,
+ DENALI_PHY_330_DATA, DENALI_PHY_331_DATA, DENALI_PHY_332_DATA,
+ DENALI_PHY_333_DATA, DENALI_PHY_334_DATA, DENALI_PHY_335_DATA,
+ DENALI_PHY_336_DATA, DENALI_PHY_337_DATA, DENALI_PHY_338_DATA,
+ DENALI_PHY_339_DATA,
+ DENALI_PHY_340_DATA, DENALI_PHY_341_DATA, DENALI_PHY_342_DATA,
+ DENALI_PHY_343_DATA, DENALI_PHY_344_DATA, DENALI_PHY_345_DATA,
+ DENALI_PHY_346_DATA, DENALI_PHY_347_DATA, DENALI_PHY_348_DATA,
+ DENALI_PHY_349_DATA,
+ DENALI_PHY_350_DATA, DENALI_PHY_351_DATA, DENALI_PHY_352_DATA,
+ DENALI_PHY_353_DATA, DENALI_PHY_354_DATA, DENALI_PHY_355_DATA,
+ DENALI_PHY_356_DATA, DENALI_PHY_357_DATA, DENALI_PHY_358_DATA,
+ DENALI_PHY_359_DATA,
+ DENALI_PHY_360_DATA, DENALI_PHY_361_DATA, DENALI_PHY_362_DATA,
+ DENALI_PHY_363_DATA, DENALI_PHY_364_DATA, DENALI_PHY_365_DATA,
+ DENALI_PHY_366_DATA, DENALI_PHY_367_DATA, DENALI_PHY_368_DATA,
+ DENALI_PHY_369_DATA,
+ DENALI_PHY_370_DATA, DENALI_PHY_371_DATA, DENALI_PHY_372_DATA,
+ DENALI_PHY_373_DATA, DENALI_PHY_374_DATA, DENALI_PHY_375_DATA,
+ DENALI_PHY_376_DATA, DENALI_PHY_377_DATA, DENALI_PHY_378_DATA,
+ DENALI_PHY_379_DATA,
+ DENALI_PHY_380_DATA, DENALI_PHY_381_DATA, DENALI_PHY_382_DATA,
+ DENALI_PHY_383_DATA, DENALI_PHY_384_DATA, DENALI_PHY_385_DATA,
+ DENALI_PHY_386_DATA, DENALI_PHY_387_DATA, DENALI_PHY_388_DATA,
+ DENALI_PHY_389_DATA,
+ DENALI_PHY_390_DATA, DENALI_PHY_391_DATA, DENALI_PHY_392_DATA,
+ DENALI_PHY_393_DATA, DENALI_PHY_394_DATA, DENALI_PHY_395_DATA,
+ DENALI_PHY_396_DATA, DENALI_PHY_397_DATA, DENALI_PHY_398_DATA,
+ DENALI_PHY_399_DATA,
+
+ DENALI_PHY_400_DATA, DENALI_PHY_401_DATA, DENALI_PHY_402_DATA,
+ DENALI_PHY_403_DATA, DENALI_PHY_404_DATA, DENALI_PHY_405_DATA,
+ DENALI_PHY_406_DATA, DENALI_PHY_407_DATA, DENALI_PHY_408_DATA,
+ DENALI_PHY_409_DATA,
+ DENALI_PHY_410_DATA, DENALI_PHY_411_DATA, DENALI_PHY_412_DATA,
+ DENALI_PHY_413_DATA, DENALI_PHY_414_DATA, DENALI_PHY_415_DATA,
+ DENALI_PHY_416_DATA, DENALI_PHY_417_DATA, DENALI_PHY_418_DATA,
+ DENALI_PHY_419_DATA,
+ DENALI_PHY_420_DATA, DENALI_PHY_421_DATA, DENALI_PHY_422_DATA,
+ DENALI_PHY_423_DATA, DENALI_PHY_424_DATA, DENALI_PHY_425_DATA,
+ DENALI_PHY_426_DATA, DENALI_PHY_427_DATA, DENALI_PHY_428_DATA,
+ DENALI_PHY_429_DATA,
+ DENALI_PHY_430_DATA, DENALI_PHY_431_DATA, DENALI_PHY_432_DATA,
+ DENALI_PHY_433_DATA, DENALI_PHY_434_DATA, DENALI_PHY_435_DATA,
+ DENALI_PHY_436_DATA, DENALI_PHY_437_DATA, DENALI_PHY_438_DATA,
+ DENALI_PHY_439_DATA,
+ DENALI_PHY_440_DATA, DENALI_PHY_441_DATA, DENALI_PHY_442_DATA,
+ DENALI_PHY_443_DATA, DENALI_PHY_444_DATA, DENALI_PHY_445_DATA,
+ DENALI_PHY_446_DATA, DENALI_PHY_447_DATA, DENALI_PHY_448_DATA,
+ DENALI_PHY_449_DATA,
+ DENALI_PHY_450_DATA, DENALI_PHY_451_DATA, DENALI_PHY_452_DATA,
+ DENALI_PHY_453_DATA, DENALI_PHY_454_DATA, DENALI_PHY_455_DATA,
+ DENALI_PHY_456_DATA, DENALI_PHY_457_DATA, DENALI_PHY_458_DATA,
+ DENALI_PHY_459_DATA,
+ DENALI_PHY_460_DATA, DENALI_PHY_461_DATA, DENALI_PHY_462_DATA,
+ DENALI_PHY_463_DATA, DENALI_PHY_464_DATA, DENALI_PHY_465_DATA,
+ DENALI_PHY_466_DATA, DENALI_PHY_467_DATA, DENALI_PHY_468_DATA,
+ DENALI_PHY_469_DATA,
+ DENALI_PHY_470_DATA, DENALI_PHY_471_DATA, DENALI_PHY_472_DATA,
+ DENALI_PHY_473_DATA, DENALI_PHY_474_DATA, DENALI_PHY_475_DATA,
+ DENALI_PHY_476_DATA, DENALI_PHY_477_DATA, DENALI_PHY_478_DATA,
+ DENALI_PHY_479_DATA,
+ DENALI_PHY_480_DATA, DENALI_PHY_481_DATA, DENALI_PHY_482_DATA,
+ DENALI_PHY_483_DATA, DENALI_PHY_484_DATA, DENALI_PHY_485_DATA,
+ DENALI_PHY_486_DATA, DENALI_PHY_487_DATA, DENALI_PHY_488_DATA,
+ DENALI_PHY_489_DATA,
+ DENALI_PHY_490_DATA, DENALI_PHY_491_DATA, DENALI_PHY_492_DATA,
+ DENALI_PHY_493_DATA, DENALI_PHY_494_DATA, DENALI_PHY_495_DATA,
+ DENALI_PHY_496_DATA, DENALI_PHY_497_DATA, DENALI_PHY_498_DATA,
+ DENALI_PHY_499_DATA,
+
+ DENALI_PHY_500_DATA, DENALI_PHY_501_DATA, DENALI_PHY_502_DATA,
+ DENALI_PHY_503_DATA, DENALI_PHY_504_DATA, DENALI_PHY_505_DATA,
+ DENALI_PHY_506_DATA, DENALI_PHY_507_DATA, DENALI_PHY_508_DATA,
+ DENALI_PHY_509_DATA,
+ DENALI_PHY_510_DATA, DENALI_PHY_511_DATA, DENALI_PHY_512_DATA,
+ DENALI_PHY_513_DATA, DENALI_PHY_514_DATA, DENALI_PHY_515_DATA,
+ DENALI_PHY_516_DATA, DENALI_PHY_517_DATA, DENALI_PHY_518_DATA,
+ DENALI_PHY_519_DATA,
+ DENALI_PHY_520_DATA, DENALI_PHY_521_DATA, DENALI_PHY_522_DATA,
+ DENALI_PHY_523_DATA, DENALI_PHY_524_DATA, DENALI_PHY_525_DATA,
+ DENALI_PHY_526_DATA, DENALI_PHY_527_DATA, DENALI_PHY_528_DATA,
+ DENALI_PHY_529_DATA,
+ DENALI_PHY_530_DATA, DENALI_PHY_531_DATA, DENALI_PHY_532_DATA,
+ DENALI_PHY_533_DATA, DENALI_PHY_534_DATA, DENALI_PHY_535_DATA,
+ DENALI_PHY_536_DATA, DENALI_PHY_537_DATA, DENALI_PHY_538_DATA,
+ DENALI_PHY_539_DATA,
+ DENALI_PHY_540_DATA, DENALI_PHY_541_DATA, DENALI_PHY_542_DATA,
+ DENALI_PHY_543_DATA, DENALI_PHY_544_DATA, DENALI_PHY_545_DATA,
+ DENALI_PHY_546_DATA, DENALI_PHY_547_DATA, DENALI_PHY_548_DATA,
+ DENALI_PHY_549_DATA,
+ DENALI_PHY_550_DATA, DENALI_PHY_551_DATA, DENALI_PHY_552_DATA,
+ DENALI_PHY_553_DATA, DENALI_PHY_554_DATA, DENALI_PHY_555_DATA,
+ DENALI_PHY_556_DATA, DENALI_PHY_557_DATA, DENALI_PHY_558_DATA,
+ DENALI_PHY_559_DATA,
+ DENALI_PHY_560_DATA, DENALI_PHY_561_DATA, DENALI_PHY_562_DATA,
+ DENALI_PHY_563_DATA, DENALI_PHY_564_DATA, DENALI_PHY_565_DATA,
+ DENALI_PHY_566_DATA, DENALI_PHY_567_DATA, DENALI_PHY_568_DATA,
+ DENALI_PHY_569_DATA,
+ DENALI_PHY_570_DATA, DENALI_PHY_571_DATA, DENALI_PHY_572_DATA,
+ DENALI_PHY_573_DATA, DENALI_PHY_574_DATA, DENALI_PHY_575_DATA,
+ DENALI_PHY_576_DATA, DENALI_PHY_577_DATA, DENALI_PHY_578_DATA,
+ DENALI_PHY_579_DATA,
+ DENALI_PHY_580_DATA, DENALI_PHY_581_DATA, DENALI_PHY_582_DATA,
+ DENALI_PHY_583_DATA, DENALI_PHY_584_DATA, DENALI_PHY_585_DATA,
+ DENALI_PHY_586_DATA, DENALI_PHY_587_DATA, DENALI_PHY_588_DATA,
+ DENALI_PHY_589_DATA,
+ DENALI_PHY_590_DATA, DENALI_PHY_591_DATA, DENALI_PHY_592_DATA,
+ DENALI_PHY_593_DATA, DENALI_PHY_594_DATA, DENALI_PHY_595_DATA,
+ DENALI_PHY_596_DATA, DENALI_PHY_597_DATA, DENALI_PHY_598_DATA,
+ DENALI_PHY_599_DATA,
+
+ DENALI_PHY_600_DATA, DENALI_PHY_601_DATA, DENALI_PHY_602_DATA,
+ DENALI_PHY_603_DATA, DENALI_PHY_604_DATA, DENALI_PHY_605_DATA,
+ DENALI_PHY_606_DATA, DENALI_PHY_607_DATA, DENALI_PHY_608_DATA,
+ DENALI_PHY_609_DATA,
+ DENALI_PHY_610_DATA, DENALI_PHY_611_DATA, DENALI_PHY_612_DATA,
+ DENALI_PHY_613_DATA, DENALI_PHY_614_DATA, DENALI_PHY_615_DATA,
+ DENALI_PHY_616_DATA, DENALI_PHY_617_DATA, DENALI_PHY_618_DATA,
+ DENALI_PHY_619_DATA,
+ DENALI_PHY_620_DATA, DENALI_PHY_621_DATA, DENALI_PHY_622_DATA,
+ DENALI_PHY_623_DATA, DENALI_PHY_624_DATA, DENALI_PHY_625_DATA,
+ DENALI_PHY_626_DATA, DENALI_PHY_627_DATA, DENALI_PHY_628_DATA,
+ DENALI_PHY_629_DATA,
+ DENALI_PHY_630_DATA, DENALI_PHY_631_DATA, DENALI_PHY_632_DATA,
+ DENALI_PHY_633_DATA, DENALI_PHY_634_DATA, DENALI_PHY_635_DATA,
+ DENALI_PHY_636_DATA, DENALI_PHY_637_DATA, DENALI_PHY_638_DATA,
+ DENALI_PHY_639_DATA,
+ DENALI_PHY_640_DATA, DENALI_PHY_641_DATA, DENALI_PHY_642_DATA,
+ DENALI_PHY_643_DATA, DENALI_PHY_644_DATA, DENALI_PHY_645_DATA,
+ DENALI_PHY_646_DATA, DENALI_PHY_647_DATA, DENALI_PHY_648_DATA,
+ DENALI_PHY_649_DATA,
+ DENALI_PHY_650_DATA, DENALI_PHY_651_DATA, DENALI_PHY_652_DATA,
+ DENALI_PHY_653_DATA, DENALI_PHY_654_DATA, DENALI_PHY_655_DATA,
+ DENALI_PHY_656_DATA, DENALI_PHY_657_DATA, DENALI_PHY_658_DATA,
+ DENALI_PHY_659_DATA,
+ DENALI_PHY_660_DATA, DENALI_PHY_661_DATA, DENALI_PHY_662_DATA,
+ DENALI_PHY_663_DATA, DENALI_PHY_664_DATA, DENALI_PHY_665_DATA,
+ DENALI_PHY_666_DATA, DENALI_PHY_667_DATA, DENALI_PHY_668_DATA,
+ DENALI_PHY_669_DATA,
+ DENALI_PHY_670_DATA, DENALI_PHY_671_DATA, DENALI_PHY_672_DATA,
+ DENALI_PHY_673_DATA, DENALI_PHY_674_DATA, DENALI_PHY_675_DATA,
+ DENALI_PHY_676_DATA, DENALI_PHY_677_DATA, DENALI_PHY_678_DATA,
+ DENALI_PHY_679_DATA,
+ DENALI_PHY_680_DATA, DENALI_PHY_681_DATA, DENALI_PHY_682_DATA,
+ DENALI_PHY_683_DATA, DENALI_PHY_684_DATA, DENALI_PHY_685_DATA,
+ DENALI_PHY_686_DATA, DENALI_PHY_687_DATA, DENALI_PHY_688_DATA,
+ DENALI_PHY_689_DATA,
+ DENALI_PHY_690_DATA, DENALI_PHY_691_DATA, DENALI_PHY_692_DATA,
+ DENALI_PHY_693_DATA, DENALI_PHY_694_DATA, DENALI_PHY_695_DATA,
+ DENALI_PHY_696_DATA, DENALI_PHY_697_DATA, DENALI_PHY_698_DATA,
+ DENALI_PHY_699_DATA,
+
+ DENALI_PHY_700_DATA, DENALI_PHY_701_DATA, DENALI_PHY_702_DATA,
+ DENALI_PHY_703_DATA, DENALI_PHY_704_DATA, DENALI_PHY_705_DATA,
+ DENALI_PHY_706_DATA, DENALI_PHY_707_DATA, DENALI_PHY_708_DATA,
+ DENALI_PHY_709_DATA,
+ DENALI_PHY_710_DATA, DENALI_PHY_711_DATA, DENALI_PHY_712_DATA,
+ DENALI_PHY_713_DATA, DENALI_PHY_714_DATA, DENALI_PHY_715_DATA,
+ DENALI_PHY_716_DATA, DENALI_PHY_717_DATA, DENALI_PHY_718_DATA,
+ DENALI_PHY_719_DATA,
+ DENALI_PHY_720_DATA, DENALI_PHY_721_DATA, DENALI_PHY_722_DATA,
+ DENALI_PHY_723_DATA, DENALI_PHY_724_DATA, DENALI_PHY_725_DATA,
+ DENALI_PHY_726_DATA, DENALI_PHY_727_DATA, DENALI_PHY_728_DATA,
+ DENALI_PHY_729_DATA,
+ DENALI_PHY_730_DATA, DENALI_PHY_731_DATA, DENALI_PHY_732_DATA,
+ DENALI_PHY_733_DATA, DENALI_PHY_734_DATA, DENALI_PHY_735_DATA,
+ DENALI_PHY_736_DATA, DENALI_PHY_737_DATA, DENALI_PHY_738_DATA,
+ DENALI_PHY_739_DATA,
+ DENALI_PHY_740_DATA, DENALI_PHY_741_DATA, DENALI_PHY_742_DATA,
+ DENALI_PHY_743_DATA, DENALI_PHY_744_DATA, DENALI_PHY_745_DATA,
+ DENALI_PHY_746_DATA, DENALI_PHY_747_DATA, DENALI_PHY_748_DATA,
+ DENALI_PHY_749_DATA,
+ DENALI_PHY_750_DATA, DENALI_PHY_751_DATA, DENALI_PHY_752_DATA,
+ DENALI_PHY_753_DATA, DENALI_PHY_754_DATA, DENALI_PHY_755_DATA,
+ DENALI_PHY_756_DATA, DENALI_PHY_757_DATA, DENALI_PHY_758_DATA,
+ DENALI_PHY_759_DATA,
+ DENALI_PHY_760_DATA, DENALI_PHY_761_DATA, DENALI_PHY_762_DATA,
+ DENALI_PHY_763_DATA, DENALI_PHY_764_DATA, DENALI_PHY_765_DATA,
+ DENALI_PHY_766_DATA, DENALI_PHY_767_DATA, DENALI_PHY_768_DATA,
+ DENALI_PHY_769_DATA,
+ DENALI_PHY_770_DATA, DENALI_PHY_771_DATA, DENALI_PHY_772_DATA,
+ DENALI_PHY_773_DATA, DENALI_PHY_774_DATA, DENALI_PHY_775_DATA,
+ DENALI_PHY_776_DATA, DENALI_PHY_777_DATA, DENALI_PHY_778_DATA,
+ DENALI_PHY_779_DATA,
+ DENALI_PHY_780_DATA, DENALI_PHY_781_DATA, DENALI_PHY_782_DATA,
+ DENALI_PHY_783_DATA, DENALI_PHY_784_DATA, DENALI_PHY_785_DATA,
+ DENALI_PHY_786_DATA, DENALI_PHY_787_DATA, DENALI_PHY_788_DATA,
+ DENALI_PHY_789_DATA,
+ DENALI_PHY_790_DATA, DENALI_PHY_791_DATA, DENALI_PHY_792_DATA,
+ DENALI_PHY_793_DATA, DENALI_PHY_794_DATA, DENALI_PHY_795_DATA,
+ DENALI_PHY_796_DATA, DENALI_PHY_797_DATA, DENALI_PHY_798_DATA,
+ DENALI_PHY_799_DATA,
+
+ DENALI_PHY_800_DATA, DENALI_PHY_801_DATA, DENALI_PHY_802_DATA,
+ DENALI_PHY_803_DATA, DENALI_PHY_804_DATA, DENALI_PHY_805_DATA,
+ DENALI_PHY_806_DATA, DENALI_PHY_807_DATA, DENALI_PHY_808_DATA,
+ DENALI_PHY_809_DATA,
+ DENALI_PHY_810_DATA, DENALI_PHY_811_DATA, DENALI_PHY_812_DATA,
+ DENALI_PHY_813_DATA, DENALI_PHY_814_DATA, DENALI_PHY_815_DATA,
+ DENALI_PHY_816_DATA, DENALI_PHY_817_DATA, DENALI_PHY_818_DATA,
+ DENALI_PHY_819_DATA,
+ DENALI_PHY_820_DATA, DENALI_PHY_821_DATA, DENALI_PHY_822_DATA,
+ DENALI_PHY_823_DATA, DENALI_PHY_824_DATA, DENALI_PHY_825_DATA,
+ DENALI_PHY_826_DATA, DENALI_PHY_827_DATA, DENALI_PHY_828_DATA,
+ DENALI_PHY_829_DATA,
+ DENALI_PHY_830_DATA, DENALI_PHY_831_DATA, DENALI_PHY_832_DATA,
+ DENALI_PHY_833_DATA, DENALI_PHY_834_DATA, DENALI_PHY_835_DATA,
+ DENALI_PHY_836_DATA, DENALI_PHY_837_DATA, DENALI_PHY_838_DATA,
+ DENALI_PHY_839_DATA,
+ DENALI_PHY_840_DATA, DENALI_PHY_841_DATA, DENALI_PHY_842_DATA,
+ DENALI_PHY_843_DATA, DENALI_PHY_844_DATA, DENALI_PHY_845_DATA,
+ DENALI_PHY_846_DATA, DENALI_PHY_847_DATA, DENALI_PHY_848_DATA,
+ DENALI_PHY_849_DATA,
+ DENALI_PHY_850_DATA, DENALI_PHY_851_DATA, DENALI_PHY_852_DATA,
+ DENALI_PHY_853_DATA, DENALI_PHY_854_DATA, DENALI_PHY_855_DATA,
+ DENALI_PHY_856_DATA, DENALI_PHY_857_DATA, DENALI_PHY_858_DATA,
+ DENALI_PHY_859_DATA,
+ DENALI_PHY_860_DATA, DENALI_PHY_861_DATA, DENALI_PHY_862_DATA,
+ DENALI_PHY_863_DATA, DENALI_PHY_864_DATA, DENALI_PHY_865_DATA,
+ DENALI_PHY_866_DATA, DENALI_PHY_867_DATA, DENALI_PHY_868_DATA,
+ DENALI_PHY_869_DATA,
+ DENALI_PHY_870_DATA, DENALI_PHY_871_DATA, DENALI_PHY_872_DATA,
+ DENALI_PHY_873_DATA, DENALI_PHY_874_DATA, DENALI_PHY_875_DATA,
+ DENALI_PHY_876_DATA, DENALI_PHY_877_DATA, DENALI_PHY_878_DATA,
+ DENALI_PHY_879_DATA,
+ DENALI_PHY_880_DATA, DENALI_PHY_881_DATA, DENALI_PHY_882_DATA,
+ DENALI_PHY_883_DATA, DENALI_PHY_884_DATA, DENALI_PHY_885_DATA,
+ DENALI_PHY_886_DATA, DENALI_PHY_887_DATA, DENALI_PHY_888_DATA,
+ DENALI_PHY_889_DATA,
+ DENALI_PHY_890_DATA, DENALI_PHY_891_DATA, DENALI_PHY_892_DATA,
+ DENALI_PHY_893_DATA, DENALI_PHY_894_DATA, DENALI_PHY_895_DATA,
+ DENALI_PHY_896_DATA, DENALI_PHY_897_DATA, DENALI_PHY_898_DATA,
+ DENALI_PHY_899_DATA,
+
+ DENALI_PHY_900_DATA, DENALI_PHY_901_DATA, DENALI_PHY_902_DATA,
+ DENALI_PHY_903_DATA, DENALI_PHY_904_DATA, DENALI_PHY_905_DATA,
+ DENALI_PHY_906_DATA, DENALI_PHY_907_DATA, DENALI_PHY_908_DATA,
+ DENALI_PHY_909_DATA,
+ DENALI_PHY_910_DATA, DENALI_PHY_911_DATA, DENALI_PHY_912_DATA,
+ DENALI_PHY_913_DATA, DENALI_PHY_914_DATA, DENALI_PHY_915_DATA,
+ DENALI_PHY_916_DATA, DENALI_PHY_917_DATA, DENALI_PHY_918_DATA,
+ DENALI_PHY_919_DATA,
+ DENALI_PHY_920_DATA, DENALI_PHY_921_DATA, DENALI_PHY_922_DATA,
+ DENALI_PHY_923_DATA, DENALI_PHY_924_DATA, DENALI_PHY_925_DATA,
+ DENALI_PHY_926_DATA, DENALI_PHY_927_DATA, DENALI_PHY_928_DATA,
+ DENALI_PHY_929_DATA,
+ DENALI_PHY_930_DATA, DENALI_PHY_931_DATA, DENALI_PHY_932_DATA,
+ DENALI_PHY_933_DATA, DENALI_PHY_934_DATA, DENALI_PHY_935_DATA,
+ DENALI_PHY_936_DATA, DENALI_PHY_937_DATA, DENALI_PHY_938_DATA,
+ DENALI_PHY_939_DATA,
+ DENALI_PHY_940_DATA, DENALI_PHY_941_DATA, DENALI_PHY_942_DATA,
+ DENALI_PHY_943_DATA, DENALI_PHY_944_DATA, DENALI_PHY_945_DATA,
+ DENALI_PHY_946_DATA, DENALI_PHY_947_DATA, DENALI_PHY_948_DATA,
+ DENALI_PHY_949_DATA,
+ DENALI_PHY_950_DATA, DENALI_PHY_951_DATA, DENALI_PHY_952_DATA,
+ DENALI_PHY_953_DATA, DENALI_PHY_954_DATA, DENALI_PHY_955_DATA,
+ DENALI_PHY_956_DATA, DENALI_PHY_957_DATA, DENALI_PHY_958_DATA,
+ DENALI_PHY_959_DATA,
+ DENALI_PHY_960_DATA, DENALI_PHY_961_DATA, DENALI_PHY_962_DATA,
+ DENALI_PHY_963_DATA, DENALI_PHY_964_DATA, DENALI_PHY_965_DATA,
+ DENALI_PHY_966_DATA, DENALI_PHY_967_DATA, DENALI_PHY_968_DATA,
+ DENALI_PHY_969_DATA,
+ DENALI_PHY_970_DATA, DENALI_PHY_971_DATA, DENALI_PHY_972_DATA,
+ DENALI_PHY_973_DATA, DENALI_PHY_974_DATA, DENALI_PHY_975_DATA,
+ DENALI_PHY_976_DATA, DENALI_PHY_977_DATA, DENALI_PHY_978_DATA,
+ DENALI_PHY_979_DATA,
+ DENALI_PHY_980_DATA, DENALI_PHY_981_DATA, DENALI_PHY_982_DATA,
+ DENALI_PHY_983_DATA, DENALI_PHY_984_DATA, DENALI_PHY_985_DATA,
+ DENALI_PHY_986_DATA, DENALI_PHY_987_DATA, DENALI_PHY_988_DATA,
+ DENALI_PHY_989_DATA,
+ DENALI_PHY_990_DATA, DENALI_PHY_991_DATA, DENALI_PHY_992_DATA,
+ DENALI_PHY_993_DATA, DENALI_PHY_994_DATA, DENALI_PHY_995_DATA,
+ DENALI_PHY_996_DATA, DENALI_PHY_997_DATA, DENALI_PHY_998_DATA,
+ DENALI_PHY_999_DATA,
+
+ DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA, DENALI_PHY_1002_DATA,
+ DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA, DENALI_PHY_1005_DATA,
+ DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA, DENALI_PHY_1008_DATA,
+ DENALI_PHY_1009_DATA,
+ DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA, DENALI_PHY_1012_DATA,
+ DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA, DENALI_PHY_1015_DATA,
+ DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA, DENALI_PHY_1018_DATA,
+ DENALI_PHY_1019_DATA,
+ DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA, DENALI_PHY_1022_DATA,
+ DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA, DENALI_PHY_1025_DATA,
+ DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA, DENALI_PHY_1028_DATA,
+ DENALI_PHY_1029_DATA,
+ DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA, DENALI_PHY_1032_DATA,
+ DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA, DENALI_PHY_1035_DATA,
+ DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA, DENALI_PHY_1038_DATA,
+ DENALI_PHY_1039_DATA,
+ DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA, DENALI_PHY_1042_DATA,
+ DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA, DENALI_PHY_1045_DATA,
+ DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA, DENALI_PHY_1048_DATA,
+ DENALI_PHY_1049_DATA,
+ DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA, DENALI_PHY_1052_DATA,
+ DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA, DENALI_PHY_1055_DATA,
+ DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA, DENALI_PHY_1058_DATA,
+ DENALI_PHY_1059_DATA,
+ DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA, DENALI_PHY_1062_DATA,
+ DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA, DENALI_PHY_1065_DATA,
+ DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA, DENALI_PHY_1068_DATA,
+ DENALI_PHY_1069_DATA,
+ DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA, DENALI_PHY_1072_DATA,
+ DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA, DENALI_PHY_1075_DATA,
+ DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA, DENALI_PHY_1078_DATA,
+ DENALI_PHY_1079_DATA,
+ DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA, DENALI_PHY_1082_DATA,
+ DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA, DENALI_PHY_1085_DATA,
+ DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA, DENALI_PHY_1088_DATA,
+ DENALI_PHY_1089_DATA,
+ DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA, DENALI_PHY_1092_DATA,
+ DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA, DENALI_PHY_1095_DATA,
+ DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA, DENALI_PHY_1098_DATA,
+ DENALI_PHY_1099_DATA,
+
+ DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA, DENALI_PHY_1102_DATA,
+ DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA, DENALI_PHY_1105_DATA,
+ DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA, DENALI_PHY_1108_DATA,
+ DENALI_PHY_1109_DATA,
+ DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA, DENALI_PHY_1112_DATA,
+ DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA, DENALI_PHY_1115_DATA,
+ DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA, DENALI_PHY_1118_DATA,
+ DENALI_PHY_1119_DATA,
+ DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA, DENALI_PHY_1122_DATA,
+ DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA, DENALI_PHY_1125_DATA,
+ DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA, DENALI_PHY_1128_DATA,
+ DENALI_PHY_1129_DATA,
+ DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA, DENALI_PHY_1132_DATA,
+ DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA, DENALI_PHY_1135_DATA,
+ DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA, DENALI_PHY_1138_DATA,
+ DENALI_PHY_1139_DATA,
+ DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA, DENALI_PHY_1142_DATA,
+ DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA, DENALI_PHY_1145_DATA,
+ DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA, DENALI_PHY_1148_DATA,
+ DENALI_PHY_1149_DATA,
+ DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA, DENALI_PHY_1152_DATA,
+ DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA, DENALI_PHY_1155_DATA,
+ DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA, DENALI_PHY_1158_DATA,
+ DENALI_PHY_1159_DATA,
+ DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA, DENALI_PHY_1162_DATA,
+ DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA, DENALI_PHY_1165_DATA,
+ DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA, DENALI_PHY_1168_DATA,
+ DENALI_PHY_1169_DATA,
+ DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA, DENALI_PHY_1172_DATA,
+ DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA, DENALI_PHY_1175_DATA,
+ DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA, DENALI_PHY_1178_DATA,
+ DENALI_PHY_1179_DATA,
+ DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA, DENALI_PHY_1182_DATA,
+ DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA, DENALI_PHY_1185_DATA,
+ DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA, DENALI_PHY_1188_DATA,
+ DENALI_PHY_1189_DATA,
+ DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA, DENALI_PHY_1192_DATA,
+ DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA, DENALI_PHY_1195_DATA,
+ DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA, DENALI_PHY_1198_DATA,
+ DENALI_PHY_1199_DATA,
+
+ DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA,
+ DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA,
+ DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA,
+ DENALI_PHY_1209_DATA,
+ DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA,
+ DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA
+};
+
+u32 ddr_ctl_settings[265] = {
+ DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA,
+ DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA,
+ DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA,
+ DENALI_CTL_09_DATA,
+ DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA,
+ DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA,
+ DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA,
+ DENALI_CTL_19_DATA,
+ DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA,
+ DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA,
+ DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA,
+ DENALI_CTL_29_DATA,
+ DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA,
+ DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA,
+ DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA,
+ DENALI_CTL_39_DATA,
+ DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA,
+ DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA,
+ DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA,
+ DENALI_CTL_49_DATA,
+ DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA,
+ DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA,
+ DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA,
+ DENALI_CTL_59_DATA,
+ DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA,
+ DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA,
+ DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA,
+ DENALI_CTL_69_DATA,
+ DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA,
+ DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA,
+ DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA,
+ DENALI_CTL_79_DATA,
+ DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA,
+ DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA,
+ DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA,
+ DENALI_CTL_89_DATA,
+ DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA,
+ DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA,
+ DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA,
+ DENALI_CTL_99_DATA,
+
+ DENALI_CTL_100_DATA, DENALI_CTL_101_DATA, DENALI_CTL_102_DATA,
+ DENALI_CTL_103_DATA, DENALI_CTL_104_DATA, DENALI_CTL_105_DATA,
+ DENALI_CTL_106_DATA, DENALI_CTL_107_DATA, DENALI_CTL_108_DATA,
+ DENALI_CTL_109_DATA,
+ DENALI_CTL_110_DATA, DENALI_CTL_111_DATA, DENALI_CTL_112_DATA,
+ DENALI_CTL_113_DATA, DENALI_CTL_114_DATA, DENALI_CTL_115_DATA,
+ DENALI_CTL_116_DATA, DENALI_CTL_117_DATA, DENALI_CTL_118_DATA,
+ DENALI_CTL_119_DATA,
+ DENALI_CTL_120_DATA, DENALI_CTL_121_DATA, DENALI_CTL_122_DATA,
+ DENALI_CTL_123_DATA, DENALI_CTL_124_DATA, DENALI_CTL_125_DATA,
+ DENALI_CTL_126_DATA, DENALI_CTL_127_DATA, DENALI_CTL_128_DATA,
+ DENALI_CTL_129_DATA,
+ DENALI_CTL_130_DATA, DENALI_CTL_131_DATA, DENALI_CTL_132_DATA,
+ DENALI_CTL_133_DATA, DENALI_CTL_134_DATA, DENALI_CTL_135_DATA,
+ DENALI_CTL_136_DATA, DENALI_CTL_137_DATA, DENALI_CTL_138_DATA,
+ DENALI_CTL_139_DATA,
+ DENALI_CTL_140_DATA, DENALI_CTL_141_DATA, DENALI_CTL_142_DATA,
+ DENALI_CTL_143_DATA, DENALI_CTL_144_DATA, DENALI_CTL_145_DATA,
+ DENALI_CTL_146_DATA, DENALI_CTL_147_DATA, DENALI_CTL_148_DATA,
+ DENALI_CTL_149_DATA,
+ DENALI_CTL_150_DATA, DENALI_CTL_151_DATA, DENALI_CTL_152_DATA,
+ DENALI_CTL_153_DATA, DENALI_CTL_154_DATA, DENALI_CTL_155_DATA,
+ DENALI_CTL_156_DATA, DENALI_CTL_157_DATA, DENALI_CTL_158_DATA,
+ DENALI_CTL_159_DATA,
+ DENALI_CTL_160_DATA, DENALI_CTL_161_DATA, DENALI_CTL_162_DATA,
+ DENALI_CTL_163_DATA, DENALI_CTL_164_DATA, DENALI_CTL_165_DATA,
+ DENALI_CTL_166_DATA, DENALI_CTL_167_DATA, DENALI_CTL_168_DATA,
+ DENALI_CTL_169_DATA,
+ DENALI_CTL_170_DATA, DENALI_CTL_171_DATA, DENALI_CTL_172_DATA,
+ DENALI_CTL_173_DATA, DENALI_CTL_174_DATA, DENALI_CTL_175_DATA,
+ DENALI_CTL_176_DATA, DENALI_CTL_177_DATA, DENALI_CTL_178_DATA,
+ DENALI_CTL_179_DATA,
+ DENALI_CTL_180_DATA, DENALI_CTL_181_DATA, DENALI_CTL_182_DATA,
+ DENALI_CTL_183_DATA, DENALI_CTL_184_DATA, DENALI_CTL_185_DATA,
+ DENALI_CTL_186_DATA, DENALI_CTL_187_DATA, DENALI_CTL_188_DATA,
+ DENALI_CTL_189_DATA,
+ DENALI_CTL_190_DATA, DENALI_CTL_191_DATA, DENALI_CTL_192_DATA,
+ DENALI_CTL_193_DATA, DENALI_CTL_194_DATA, DENALI_CTL_195_DATA,
+ DENALI_CTL_196_DATA, DENALI_CTL_197_DATA, DENALI_CTL_198_DATA,
+ DENALI_CTL_199_DATA,
+
+ DENALI_CTL_200_DATA, DENALI_CTL_201_DATA, DENALI_CTL_202_DATA,
+ DENALI_CTL_203_DATA, DENALI_CTL_204_DATA, DENALI_CTL_205_DATA,
+ DENALI_CTL_206_DATA, DENALI_CTL_207_DATA, DENALI_CTL_208_DATA,
+ DENALI_CTL_209_DATA,
+ DENALI_CTL_210_DATA, DENALI_CTL_211_DATA, DENALI_CTL_212_DATA,
+ DENALI_CTL_213_DATA, DENALI_CTL_214_DATA, DENALI_CTL_215_DATA,
+ DENALI_CTL_216_DATA, DENALI_CTL_217_DATA, DENALI_CTL_218_DATA,
+ DENALI_CTL_219_DATA,
+ DENALI_CTL_220_DATA, DENALI_CTL_221_DATA, DENALI_CTL_222_DATA,
+ DENALI_CTL_223_DATA, DENALI_CTL_224_DATA, DENALI_CTL_225_DATA,
+ DENALI_CTL_226_DATA, DENALI_CTL_227_DATA, DENALI_CTL_228_DATA,
+ DENALI_CTL_229_DATA,
+ DENALI_CTL_230_DATA, DENALI_CTL_231_DATA, DENALI_CTL_232_DATA,
+ DENALI_CTL_233_DATA, DENALI_CTL_234_DATA, DENALI_CTL_235_DATA,
+ DENALI_CTL_236_DATA, DENALI_CTL_237_DATA, DENALI_CTL_238_DATA,
+ DENALI_CTL_239_DATA,
+ DENALI_CTL_240_DATA, DENALI_CTL_241_DATA, DENALI_CTL_242_DATA,
+ DENALI_CTL_243_DATA, DENALI_CTL_244_DATA, DENALI_CTL_245_DATA,
+ DENALI_CTL_246_DATA, DENALI_CTL_247_DATA, DENALI_CTL_248_DATA,
+ DENALI_CTL_249_DATA,
+ DENALI_CTL_250_DATA, DENALI_CTL_251_DATA, DENALI_CTL_252_DATA,
+ DENALI_CTL_253_DATA, DENALI_CTL_254_DATA, DENALI_CTL_255_DATA,
+ DENALI_CTL_256_DATA, DENALI_CTL_257_DATA, DENALI_CTL_258_DATA,
+ DENALI_CTL_259_DATA,
+ DENALI_CTL_260_DATA, DENALI_CTL_261_DATA, DENALI_CTL_262_DATA,
+ DENALI_CTL_263_DATA, DENALI_CTL_264_DATA
+};
diff --git a/board/sifive/fu540/regconfig-ctl.h b/board/sifive/fu540/regconfig-ctl.h
new file mode 100644
index 0000000000..b8f50f5b35
--- /dev/null
+++ b/board/sifive/fu540/regconfig-ctl.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#define DENALI_CTL_00_DATA 0x00000a00
+#define DENALI_CTL_01_DATA 0x00000000
+#define DENALI_CTL_02_DATA 0x00000000
+#define DENALI_CTL_03_DATA 0x00000000
+#define DENALI_CTL_04_DATA 0x00000000
+#define DENALI_CTL_05_DATA 0x00000000
+#define DENALI_CTL_06_DATA 0x0000000a
+#define DENALI_CTL_07_DATA 0x0002d362
+#define DENALI_CTL_08_DATA 0x00071073
+#define DENALI_CTL_09_DATA 0x0a1c0255
+#define DENALI_CTL_10_DATA 0x1c1c0400
+#define DENALI_CTL_11_DATA 0x0404990b
+#define DENALI_CTL_12_DATA 0x2b050405
+#define DENALI_CTL_13_DATA 0x0e0c081e
+#define DENALI_CTL_14_DATA 0x08090914
+#define DENALI_CTL_15_DATA 0x00fde718
+#define DENALI_CTL_16_DATA 0x00180a05
+#define DENALI_CTL_17_DATA 0x008b130e
+#define DENALI_CTL_18_DATA 0x01000118
+#define DENALI_CTL_19_DATA 0x0e032101
+#define DENALI_CTL_20_DATA 0x00000000
+#define DENALI_CTL_21_DATA 0x00000101
+#define DENALI_CTL_22_DATA 0x00000000
+#define DENALI_CTL_23_DATA 0x0a000000
+#define DENALI_CTL_24_DATA 0x00000000
+#define DENALI_CTL_25_DATA 0x01450100
+#define DENALI_CTL_26_DATA 0x00001c36
+#define DENALI_CTL_27_DATA 0x00000005
+#define DENALI_CTL_28_DATA 0x00170006
+#define DENALI_CTL_29_DATA 0x014e0300
+#define DENALI_CTL_30_DATA 0x03010000
+#define DENALI_CTL_31_DATA 0x000a0e00
+#define DENALI_CTL_32_DATA 0x04030200
+#define DENALI_CTL_33_DATA 0x0000031f
+#define DENALI_CTL_34_DATA 0x00070004
+#define DENALI_CTL_35_DATA 0x00000000
+#define DENALI_CTL_36_DATA 0x00000000
+#define DENALI_CTL_37_DATA 0x00000000
+#define DENALI_CTL_38_DATA 0x00000000
+#define DENALI_CTL_39_DATA 0x00000000
+#define DENALI_CTL_40_DATA 0x00000000
+#define DENALI_CTL_41_DATA 0x00000000
+#define DENALI_CTL_42_DATA 0x00000000
+#define DENALI_CTL_43_DATA 0x00000000
+#define DENALI_CTL_44_DATA 0x00000000
+#define DENALI_CTL_45_DATA 0x00000000
+#define DENALI_CTL_46_DATA 0x00000000
+#define DENALI_CTL_47_DATA 0x00000000
+#define DENALI_CTL_48_DATA 0x00000000
+#define DENALI_CTL_49_DATA 0x00000000
+#define DENALI_CTL_50_DATA 0x00000000
+#define DENALI_CTL_51_DATA 0x00000000
+#define DENALI_CTL_52_DATA 0x00000000
+#define DENALI_CTL_53_DATA 0x00000000
+#define DENALI_CTL_54_DATA 0x00000000
+#define DENALI_CTL_55_DATA 0x00000000
+#define DENALI_CTL_56_DATA 0x00000000
+#define DENALI_CTL_57_DATA 0x00000000
+#define DENALI_CTL_58_DATA 0x00000000
+#define DENALI_CTL_59_DATA 0x00000000
+#define DENALI_CTL_60_DATA 0x00000424
+#define DENALI_CTL_61_DATA 0x00000201
+#define DENALI_CTL_62_DATA 0x00001008
+#define DENALI_CTL_63_DATA 0x00000000
+#define DENALI_CTL_64_DATA 0x00000200
+#define DENALI_CTL_65_DATA 0x00000000
+#define DENALI_CTL_66_DATA 0x00000481
+#define DENALI_CTL_67_DATA 0x00000400
+#define DENALI_CTL_68_DATA 0x00000424
+#define DENALI_CTL_69_DATA 0x00000201
+#define DENALI_CTL_70_DATA 0x00001008
+#define DENALI_CTL_71_DATA 0x00000000
+#define DENALI_CTL_72_DATA 0x00000200
+#define DENALI_CTL_73_DATA 0x00000000
+#define DENALI_CTL_74_DATA 0x00000481
+#define DENALI_CTL_75_DATA 0x00000400
+#define DENALI_CTL_76_DATA 0x01010000
+#define DENALI_CTL_77_DATA 0x00000000
+#define DENALI_CTL_78_DATA 0x00000000
+#define DENALI_CTL_79_DATA 0x00000000
+#define DENALI_CTL_80_DATA 0x00000000
+#define DENALI_CTL_81_DATA 0x00000000
+#define DENALI_CTL_82_DATA 0x00000000
+#define DENALI_CTL_83_DATA 0x00000000
+#define DENALI_CTL_84_DATA 0x00000000
+#define DENALI_CTL_85_DATA 0x00000000
+#define DENALI_CTL_86_DATA 0x00000000
+#define DENALI_CTL_87_DATA 0x00000000
+#define DENALI_CTL_88_DATA 0x00000000
+#define DENALI_CTL_89_DATA 0x00000000
+#define DENALI_CTL_90_DATA 0x00000000
+#define DENALI_CTL_91_DATA 0x00000000
+#define DENALI_CTL_92_DATA 0x00000000
+#define DENALI_CTL_93_DATA 0x00000000
+#define DENALI_CTL_94_DATA 0x00000000
+#define DENALI_CTL_95_DATA 0x00000000
+#define DENALI_CTL_96_DATA 0x00000000
+#define DENALI_CTL_97_DATA 0x00000000
+#define DENALI_CTL_98_DATA 0x00000000
+#define DENALI_CTL_99_DATA 0x00000000
+#define DENALI_CTL_100_DATA 0x00000000
+#define DENALI_CTL_101_DATA 0x00000000
+#define DENALI_CTL_102_DATA 0x00000000
+#define DENALI_CTL_103_DATA 0x00000000
+#define DENALI_CTL_104_DATA 0x00000000
+#define DENALI_CTL_105_DATA 0x00000003
+#define DENALI_CTL_106_DATA 0x00000000
+#define DENALI_CTL_107_DATA 0x00000000
+#define DENALI_CTL_108_DATA 0x00000000
+#define DENALI_CTL_109_DATA 0x00000000
+#define DENALI_CTL_110_DATA 0x01000000
+#define DENALI_CTL_111_DATA 0x00040000
+#define DENALI_CTL_112_DATA 0x00800200
+#define DENALI_CTL_113_DATA 0x00000200
+#define DENALI_CTL_114_DATA 0x00000040
+#define DENALI_CTL_115_DATA 0x01000100
+#define DENALI_CTL_116_DATA 0x0a000002
+#define DENALI_CTL_117_DATA 0x0101ffff
+#define DENALI_CTL_118_DATA 0x01010101
+#define DENALI_CTL_119_DATA 0x01010101
+#define DENALI_CTL_120_DATA 0x0000010b
+#define DENALI_CTL_121_DATA 0x00000c01
+#define DENALI_CTL_122_DATA 0x00000000
+#define DENALI_CTL_123_DATA 0x00000000
+#define DENALI_CTL_124_DATA 0x00000000
+#define DENALI_CTL_125_DATA 0x00000000
+#define DENALI_CTL_126_DATA 0x00030300
+#define DENALI_CTL_127_DATA 0x00000000
+#define DENALI_CTL_128_DATA 0x00010001
+#define DENALI_CTL_129_DATA 0x00000000
+#define DENALI_CTL_130_DATA 0x00000000
+#define DENALI_CTL_131_DATA 0x00000000
+#define DENALI_CTL_132_DATA 0x00000000
+#define DENALI_CTL_133_DATA 0x00000000
+#define DENALI_CTL_134_DATA 0x00000000
+#define DENALI_CTL_135_DATA 0x00000000
+#define DENALI_CTL_136_DATA 0x00000000
+#define DENALI_CTL_137_DATA 0x00000000
+#define DENALI_CTL_138_DATA 0x00000000
+#define DENALI_CTL_139_DATA 0x00000000
+#define DENALI_CTL_140_DATA 0x00000000
+#define DENALI_CTL_141_DATA 0x00000000
+#define DENALI_CTL_142_DATA 0x00000000
+#define DENALI_CTL_143_DATA 0x00000000
+#define DENALI_CTL_144_DATA 0x00000000
+#define DENALI_CTL_145_DATA 0x00000000
+#define DENALI_CTL_146_DATA 0x00000000
+#define DENALI_CTL_147_DATA 0x00000000
+#define DENALI_CTL_148_DATA 0x00000000
+#define DENALI_CTL_149_DATA 0x00000000
+#define DENALI_CTL_150_DATA 0x00000000
+#define DENALI_CTL_151_DATA 0x00000000
+#define DENALI_CTL_152_DATA 0x00000000
+#define DENALI_CTL_153_DATA 0x00000000
+#define DENALI_CTL_154_DATA 0x00000000
+#define DENALI_CTL_155_DATA 0x00000000
+#define DENALI_CTL_156_DATA 0x00000000
+#define DENALI_CTL_157_DATA 0x00000000
+#define DENALI_CTL_158_DATA 0x00000000
+#define DENALI_CTL_159_DATA 0x00000000
+#define DENALI_CTL_160_DATA 0x00000000
+#define DENALI_CTL_161_DATA 0x02010102
+#define DENALI_CTL_162_DATA 0x0107070d
+#define DENALI_CTL_163_DATA 0x04040400
+#define DENALI_CTL_164_DATA 0x03000503
+#define DENALI_CTL_165_DATA 0x00000000
+#define DENALI_CTL_166_DATA 0x00000000
+#define DENALI_CTL_167_DATA 0x00000000
+#define DENALI_CTL_168_DATA 0x00000000
+#define DENALI_CTL_169_DATA 0x280d0000
+#define DENALI_CTL_170_DATA 0x01000000
+#define DENALI_CTL_171_DATA 0x00000000
+#define DENALI_CTL_172_DATA 0x00010001
+#define DENALI_CTL_173_DATA 0x00000000
+#define DENALI_CTL_174_DATA 0x00000000
+#define DENALI_CTL_175_DATA 0x00000000
+#define DENALI_CTL_176_DATA 0x00000000
+#define DENALI_CTL_177_DATA 0x00000000
+#define DENALI_CTL_178_DATA 0x00000000
+#define DENALI_CTL_179_DATA 0x00000000
+#define DENALI_CTL_180_DATA 0x00000000
+#define DENALI_CTL_181_DATA 0x01000000
+#define DENALI_CTL_182_DATA 0x00000001
+#define DENALI_CTL_183_DATA 0x00000100
+#define DENALI_CTL_184_DATA 0x00000101
+#define DENALI_CTL_185_DATA 0x67676701
+#define DENALI_CTL_186_DATA 0x67676767
+#define DENALI_CTL_187_DATA 0x67676767
+#define DENALI_CTL_188_DATA 0x67676767
+#define DENALI_CTL_189_DATA 0x67676767
+#define DENALI_CTL_190_DATA 0x67676767
+#define DENALI_CTL_191_DATA 0x67676767
+#define DENALI_CTL_192_DATA 0x67676767
+#define DENALI_CTL_193_DATA 0x67676767
+#define DENALI_CTL_194_DATA 0x01000067
+#define DENALI_CTL_195_DATA 0x00000001
+#define DENALI_CTL_196_DATA 0x00000101
+#define DENALI_CTL_197_DATA 0x00000000
+#define DENALI_CTL_198_DATA 0x00000000
+#define DENALI_CTL_199_DATA 0x00000000
+#define DENALI_CTL_200_DATA 0x00000000
+#define DENALI_CTL_201_DATA 0x00000000
+#define DENALI_CTL_202_DATA 0x00000000
+#define DENALI_CTL_203_DATA 0x00000000
+#define DENALI_CTL_204_DATA 0x00000000
+#define DENALI_CTL_205_DATA 0x00000000
+#define DENALI_CTL_206_DATA 0x00000000
+#define DENALI_CTL_207_DATA 0x00000000
+#define DENALI_CTL_208_DATA 0x00000001
+#define DENALI_CTL_209_DATA 0x00000000
+#define DENALI_CTL_210_DATA 0x007fffff
+#define DENALI_CTL_211_DATA 0x00000000
+#define DENALI_CTL_212_DATA 0x007fffff
+#define DENALI_CTL_213_DATA 0x00000000
+#define DENALI_CTL_214_DATA 0x007fffff
+#define DENALI_CTL_215_DATA 0x00000000
+#define DENALI_CTL_216_DATA 0x007fffff
+#define DENALI_CTL_217_DATA 0x00000000
+#define DENALI_CTL_218_DATA 0x007fffff
+#define DENALI_CTL_219_DATA 0x00000000
+#define DENALI_CTL_220_DATA 0x007fffff
+#define DENALI_CTL_221_DATA 0x00000000
+#define DENALI_CTL_222_DATA 0x007fffff
+#define DENALI_CTL_223_DATA 0x00000000
+#define DENALI_CTL_224_DATA 0x037fffff
+#define DENALI_CTL_225_DATA 0xffffffff
+#define DENALI_CTL_226_DATA 0x000f000f
+#define DENALI_CTL_227_DATA 0x00ffff03
+#define DENALI_CTL_228_DATA 0x000fffff
+#define DENALI_CTL_229_DATA 0x0003000f
+#define DENALI_CTL_230_DATA 0xffffffff
+#define DENALI_CTL_231_DATA 0x000f000f
+#define DENALI_CTL_232_DATA 0x00ffff03
+#define DENALI_CTL_233_DATA 0x000fffff
+#define DENALI_CTL_234_DATA 0x0003000f
+#define DENALI_CTL_235_DATA 0xffffffff
+#define DENALI_CTL_236_DATA 0x000f000f
+#define DENALI_CTL_237_DATA 0x00ffff03
+#define DENALI_CTL_238_DATA 0x000fffff
+#define DENALI_CTL_239_DATA 0x0003000f
+#define DENALI_CTL_240_DATA 0xffffffff
+#define DENALI_CTL_241_DATA 0x000f000f
+#define DENALI_CTL_242_DATA 0x00ffff03
+#define DENALI_CTL_243_DATA 0x000fffff
+#define DENALI_CTL_244_DATA 0x6407000f
+#define DENALI_CTL_245_DATA 0x01640001
+#define DENALI_CTL_246_DATA 0x00000000
+#define DENALI_CTL_247_DATA 0x00000000
+#define DENALI_CTL_248_DATA 0x00001700
+#define DENALI_CTL_249_DATA 0x00386c05
+#define DENALI_CTL_250_DATA 0x02000200
+#define DENALI_CTL_251_DATA 0x02000200
+#define DENALI_CTL_252_DATA 0x0000386c
+#define DENALI_CTL_253_DATA 0x00023438
+#define DENALI_CTL_254_DATA 0x02020d10
+#define DENALI_CTL_255_DATA 0x00140303
+#define DENALI_CTL_256_DATA 0x00000000
+#define DENALI_CTL_257_DATA 0x00000000
+#define DENALI_CTL_258_DATA 0x00001403
+#define DENALI_CTL_259_DATA 0x00000000
+#define DENALI_CTL_260_DATA 0x00000000
+#define DENALI_CTL_261_DATA 0x00000000
+#define DENALI_CTL_262_DATA 0x00000000
+#define DENALI_CTL_263_DATA 0x0d010000
+#define DENALI_CTL_264_DATA 0x00000008
diff --git a/board/sifive/fu540/regconfig-phy.h b/board/sifive/fu540/regconfig-phy.h
new file mode 100644
index 0000000000..62163290b9
--- /dev/null
+++ b/board/sifive/fu540/regconfig-phy.h
@@ -0,0 +1,1220 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#define DENALI_PHY_00_DATA 0x31706542
+#define DENALI_PHY_01_DATA 0x0004c008
+#define DENALI_PHY_02_DATA 0x000000da
+#define DENALI_PHY_03_DATA 0x00000000
+#define DENALI_PHY_04_DATA 0x00000000
+#define DENALI_PHY_05_DATA 0x00010000
+#define DENALI_PHY_06_DATA 0x01DDDD90
+#define DENALI_PHY_07_DATA 0x01DDDD90
+#define DENALI_PHY_08_DATA 0x01030000
+#define DENALI_PHY_09_DATA 0x01000000
+#define DENALI_PHY_10_DATA 0x00c00000
+#define DENALI_PHY_11_DATA 0x00000007
+#define DENALI_PHY_12_DATA 0x00000000
+#define DENALI_PHY_13_DATA 0x00000000
+#define DENALI_PHY_14_DATA 0x04000408
+#define DENALI_PHY_15_DATA 0x00000408
+#define DENALI_PHY_16_DATA 0x00e4e400
+#define DENALI_PHY_17_DATA 0x00000000
+#define DENALI_PHY_18_DATA 0x00000000
+#define DENALI_PHY_19_DATA 0x00000000
+#define DENALI_PHY_20_DATA 0x00000000
+#define DENALI_PHY_21_DATA 0x00000000
+#define DENALI_PHY_22_DATA 0x00000000
+#define DENALI_PHY_23_DATA 0x00000000
+#define DENALI_PHY_24_DATA 0x00000000
+#define DENALI_PHY_25_DATA 0x00000000
+#define DENALI_PHY_26_DATA 0x00000000
+#define DENALI_PHY_27_DATA 0x00000000
+#define DENALI_PHY_28_DATA 0x00000000
+#define DENALI_PHY_29_DATA 0x00000000
+#define DENALI_PHY_30_DATA 0x00000000
+#define DENALI_PHY_31_DATA 0x00000000
+#define DENALI_PHY_32_DATA 0x00000000
+#define DENALI_PHY_33_DATA 0x00200000
+#define DENALI_PHY_34_DATA 0x00000000
+#define DENALI_PHY_35_DATA 0x00000000
+#define DENALI_PHY_36_DATA 0x00000000
+#define DENALI_PHY_37_DATA 0x00000000
+#define DENALI_PHY_38_DATA 0x00000000
+#define DENALI_PHY_39_DATA 0x00000000
+#define DENALI_PHY_40_DATA 0x02800280
+#define DENALI_PHY_41_DATA 0x02800280
+#define DENALI_PHY_42_DATA 0x02800280
+#define DENALI_PHY_43_DATA 0x02800280
+#define DENALI_PHY_44_DATA 0x00000280
+#define DENALI_PHY_45_DATA 0x00000000
+#define DENALI_PHY_46_DATA 0x00000000
+#define DENALI_PHY_47_DATA 0x00000000
+#define DENALI_PHY_48_DATA 0x00000000
+#define DENALI_PHY_49_DATA 0x00000000
+#define DENALI_PHY_50_DATA 0x00800080
+#define DENALI_PHY_51_DATA 0x00800080
+#define DENALI_PHY_52_DATA 0x00800080
+#define DENALI_PHY_53_DATA 0x00800080
+#define DENALI_PHY_54_DATA 0x00800080
+#define DENALI_PHY_55_DATA 0x00800080
+#define DENALI_PHY_56_DATA 0x00800080
+#define DENALI_PHY_57_DATA 0x00800080
+#define DENALI_PHY_58_DATA 0x00800080
+#define DENALI_PHY_59_DATA 0x000100da
+#define DENALI_PHY_60_DATA 0x01000200
+#define DENALI_PHY_61_DATA 0x00000000
+#define DENALI_PHY_62_DATA 0x00000000
+#define DENALI_PHY_63_DATA 0x00000002
+#define DENALI_PHY_64_DATA 0x51313152
+#define DENALI_PHY_65_DATA 0x80013130
+#define DENALI_PHY_66_DATA 0x02000080
+#define DENALI_PHY_67_DATA 0x00100001
+#define DENALI_PHY_68_DATA 0x0c064208
+#define DENALI_PHY_69_DATA 0x000f0c0f
+#define DENALI_PHY_70_DATA 0x01000140
+#define DENALI_PHY_71_DATA 0x0000000c
+#define DENALI_PHY_72_DATA 0x00000000
+#define DENALI_PHY_73_DATA 0x00000000
+#define DENALI_PHY_74_DATA 0x00000000
+#define DENALI_PHY_75_DATA 0x00000000
+#define DENALI_PHY_76_DATA 0x00000000
+#define DENALI_PHY_77_DATA 0x00000000
+#define DENALI_PHY_78_DATA 0x00000000
+#define DENALI_PHY_79_DATA 0x00000000
+#define DENALI_PHY_80_DATA 0x00000000
+#define DENALI_PHY_81_DATA 0x00000000
+#define DENALI_PHY_82_DATA 0x00000000
+#define DENALI_PHY_83_DATA 0x00000000
+#define DENALI_PHY_84_DATA 0x00000000
+#define DENALI_PHY_85_DATA 0x00000000
+#define DENALI_PHY_86_DATA 0x00000000
+#define DENALI_PHY_87_DATA 0x00000000
+#define DENALI_PHY_88_DATA 0x00000000
+#define DENALI_PHY_89_DATA 0x00000000
+#define DENALI_PHY_90_DATA 0x00000000
+#define DENALI_PHY_91_DATA 0x00000000
+#define DENALI_PHY_92_DATA 0x00000000
+#define DENALI_PHY_93_DATA 0x00000000
+#define DENALI_PHY_94_DATA 0x00000000
+#define DENALI_PHY_95_DATA 0x00000000
+#define DENALI_PHY_96_DATA 0x00000000
+#define DENALI_PHY_97_DATA 0x00000000
+#define DENALI_PHY_98_DATA 0x00000000
+#define DENALI_PHY_99_DATA 0x00000000
+#define DENALI_PHY_100_DATA 0x00000000
+#define DENALI_PHY_101_DATA 0x00000000
+#define DENALI_PHY_102_DATA 0x00000000
+#define DENALI_PHY_103_DATA 0x00000000
+#define DENALI_PHY_104_DATA 0x00000000
+#define DENALI_PHY_105_DATA 0x00000000
+#define DENALI_PHY_106_DATA 0x00000000
+#define DENALI_PHY_107_DATA 0x00000000
+#define DENALI_PHY_108_DATA 0x00000000
+#define DENALI_PHY_109_DATA 0x00000000
+#define DENALI_PHY_110_DATA 0x00000000
+#define DENALI_PHY_111_DATA 0x00000000
+#define DENALI_PHY_112_DATA 0x00000000
+#define DENALI_PHY_113_DATA 0x00000000
+#define DENALI_PHY_114_DATA 0x00000000
+#define DENALI_PHY_115_DATA 0x00000000
+#define DENALI_PHY_116_DATA 0x00000000
+#define DENALI_PHY_117_DATA 0x00000000
+#define DENALI_PHY_118_DATA 0x00000000
+#define DENALI_PHY_119_DATA 0x00000000
+#define DENALI_PHY_120_DATA 0x00000000
+#define DENALI_PHY_121_DATA 0x00000000
+#define DENALI_PHY_122_DATA 0x00000000
+#define DENALI_PHY_123_DATA 0x00000000
+#define DENALI_PHY_124_DATA 0x00000000
+#define DENALI_PHY_125_DATA 0x00000000
+#define DENALI_PHY_126_DATA 0x00000000
+#define DENALI_PHY_127_DATA 0x00000000
+#define DENALI_PHY_128_DATA 0x40263571
+#define DENALI_PHY_129_DATA 0x0004c008
+#define DENALI_PHY_130_DATA 0x000000da
+#define DENALI_PHY_131_DATA 0x00000000
+#define DENALI_PHY_132_DATA 0x00000000
+#define DENALI_PHY_133_DATA 0x00010000
+#define DENALI_PHY_134_DATA 0x01DDDD90
+#define DENALI_PHY_135_DATA 0x01DDDD90
+#define DENALI_PHY_136_DATA 0x01030000
+#define DENALI_PHY_137_DATA 0x01000000
+#define DENALI_PHY_138_DATA 0x00c00000
+#define DENALI_PHY_139_DATA 0x00000007
+#define DENALI_PHY_140_DATA 0x00000000
+#define DENALI_PHY_141_DATA 0x00000000
+#define DENALI_PHY_142_DATA 0x04000408
+#define DENALI_PHY_143_DATA 0x00000408
+#define DENALI_PHY_144_DATA 0x00e4e400
+#define DENALI_PHY_145_DATA 0x00000000
+#define DENALI_PHY_146_DATA 0x00000000
+#define DENALI_PHY_147_DATA 0x00000000
+#define DENALI_PHY_148_DATA 0x00000000
+#define DENALI_PHY_149_DATA 0x00000000
+#define DENALI_PHY_150_DATA 0x00000000
+#define DENALI_PHY_151_DATA 0x00000000
+#define DENALI_PHY_152_DATA 0x00000000
+#define DENALI_PHY_153_DATA 0x00000000
+#define DENALI_PHY_154_DATA 0x00000000
+#define DENALI_PHY_155_DATA 0x00000000
+#define DENALI_PHY_156_DATA 0x00000000
+#define DENALI_PHY_157_DATA 0x00000000
+#define DENALI_PHY_158_DATA 0x00000000
+#define DENALI_PHY_159_DATA 0x00000000
+#define DENALI_PHY_160_DATA 0x00000000
+#define DENALI_PHY_161_DATA 0x00200000
+#define DENALI_PHY_162_DATA 0x00000000
+#define DENALI_PHY_163_DATA 0x00000000
+#define DENALI_PHY_164_DATA 0x00000000
+#define DENALI_PHY_165_DATA 0x00000000
+#define DENALI_PHY_166_DATA 0x00000000
+#define DENALI_PHY_167_DATA 0x00000000
+#define DENALI_PHY_168_DATA 0x02800280
+#define DENALI_PHY_169_DATA 0x02800280
+#define DENALI_PHY_170_DATA 0x02800280
+#define DENALI_PHY_171_DATA 0x02800280
+#define DENALI_PHY_172_DATA 0x00000280
+#define DENALI_PHY_173_DATA 0x00000000
+#define DENALI_PHY_174_DATA 0x00000000
+#define DENALI_PHY_175_DATA 0x00000000
+#define DENALI_PHY_176_DATA 0x00000000
+#define DENALI_PHY_177_DATA 0x00000000
+#define DENALI_PHY_178_DATA 0x00800080
+#define DENALI_PHY_179_DATA 0x00800080
+#define DENALI_PHY_180_DATA 0x00800080
+#define DENALI_PHY_181_DATA 0x00800080
+#define DENALI_PHY_182_DATA 0x00800080
+#define DENALI_PHY_183_DATA 0x00800080
+#define DENALI_PHY_184_DATA 0x00800080
+#define DENALI_PHY_185_DATA 0x00800080
+#define DENALI_PHY_186_DATA 0x00800080
+#define DENALI_PHY_187_DATA 0x000100da
+#define DENALI_PHY_188_DATA 0x01000200
+#define DENALI_PHY_189_DATA 0x00000000
+#define DENALI_PHY_190_DATA 0x00000000
+#define DENALI_PHY_191_DATA 0x00000002
+#define DENALI_PHY_192_DATA 0x51313152
+#define DENALI_PHY_193_DATA 0x80013130
+#define DENALI_PHY_194_DATA 0x02000080
+#define DENALI_PHY_195_DATA 0x00100001
+#define DENALI_PHY_196_DATA 0x0c064208
+#define DENALI_PHY_197_DATA 0x000f0c0f
+#define DENALI_PHY_198_DATA 0x01000140
+#define DENALI_PHY_199_DATA 0x0000000c
+#define DENALI_PHY_200_DATA 0x00000000
+#define DENALI_PHY_201_DATA 0x00000000
+#define DENALI_PHY_202_DATA 0x00000000
+#define DENALI_PHY_203_DATA 0x00000000
+#define DENALI_PHY_204_DATA 0x00000000
+#define DENALI_PHY_205_DATA 0x00000000
+#define DENALI_PHY_206_DATA 0x00000000
+#define DENALI_PHY_207_DATA 0x00000000
+#define DENALI_PHY_208_DATA 0x00000000
+#define DENALI_PHY_209_DATA 0x00000000
+#define DENALI_PHY_210_DATA 0x00000000
+#define DENALI_PHY_211_DATA 0x00000000
+#define DENALI_PHY_212_DATA 0x00000000
+#define DENALI_PHY_213_DATA 0x00000000
+#define DENALI_PHY_214_DATA 0x00000000
+#define DENALI_PHY_215_DATA 0x00000000
+#define DENALI_PHY_216_DATA 0x00000000
+#define DENALI_PHY_217_DATA 0x00000000
+#define DENALI_PHY_218_DATA 0x00000000
+#define DENALI_PHY_219_DATA 0x00000000
+#define DENALI_PHY_220_DATA 0x00000000
+#define DENALI_PHY_221_DATA 0x00000000
+#define DENALI_PHY_222_DATA 0x00000000
+#define DENALI_PHY_223_DATA 0x00000000
+#define DENALI_PHY_224_DATA 0x00000000
+#define DENALI_PHY_225_DATA 0x00000000
+#define DENALI_PHY_226_DATA 0x00000000
+#define DENALI_PHY_227_DATA 0x00000000
+#define DENALI_PHY_228_DATA 0x00000000
+#define DENALI_PHY_229_DATA 0x00000000
+#define DENALI_PHY_230_DATA 0x00000000
+#define DENALI_PHY_231_DATA 0x00000000
+#define DENALI_PHY_232_DATA 0x00000000
+#define DENALI_PHY_233_DATA 0x00000000
+#define DENALI_PHY_234_DATA 0x00000000
+#define DENALI_PHY_235_DATA 0x00000000
+#define DENALI_PHY_236_DATA 0x00000000
+#define DENALI_PHY_237_DATA 0x00000000
+#define DENALI_PHY_238_DATA 0x00000000
+#define DENALI_PHY_239_DATA 0x00000000
+#define DENALI_PHY_240_DATA 0x00000000
+#define DENALI_PHY_241_DATA 0x00000000
+#define DENALI_PHY_242_DATA 0x00000000
+#define DENALI_PHY_243_DATA 0x00000000
+#define DENALI_PHY_244_DATA 0x00000000
+#define DENALI_PHY_245_DATA 0x00000000
+#define DENALI_PHY_246_DATA 0x00000000
+#define DENALI_PHY_247_DATA 0x00000000
+#define DENALI_PHY_248_DATA 0x00000000
+#define DENALI_PHY_249_DATA 0x00000000
+#define DENALI_PHY_250_DATA 0x00000000
+#define DENALI_PHY_251_DATA 0x00000000
+#define DENALI_PHY_252_DATA 0x00000000
+#define DENALI_PHY_253_DATA 0x00000000
+#define DENALI_PHY_254_DATA 0x00000000
+#define DENALI_PHY_255_DATA 0x00000000
+#define DENALI_PHY_256_DATA 0x46052371
+#define DENALI_PHY_257_DATA 0x0004c008
+#define DENALI_PHY_258_DATA 0x000000da
+#define DENALI_PHY_259_DATA 0x00000000
+#define DENALI_PHY_260_DATA 0x00000000
+#define DENALI_PHY_261_DATA 0x00010000
+#define DENALI_PHY_262_DATA 0x01DDDD90
+#define DENALI_PHY_263_DATA 0x01DDDD90
+#define DENALI_PHY_264_DATA 0x01030000
+#define DENALI_PHY_265_DATA 0x01000000
+#define DENALI_PHY_266_DATA 0x00c00000
+#define DENALI_PHY_267_DATA 0x00000007
+#define DENALI_PHY_268_DATA 0x00000000
+#define DENALI_PHY_269_DATA 0x00000000
+#define DENALI_PHY_270_DATA 0x04000408
+#define DENALI_PHY_271_DATA 0x00000408
+#define DENALI_PHY_272_DATA 0x00e4e400
+#define DENALI_PHY_273_DATA 0x00000000
+#define DENALI_PHY_274_DATA 0x00000000
+#define DENALI_PHY_275_DATA 0x00000000
+#define DENALI_PHY_276_DATA 0x00000000
+#define DENALI_PHY_277_DATA 0x00000000
+#define DENALI_PHY_278_DATA 0x00000000
+#define DENALI_PHY_279_DATA 0x00000000
+#define DENALI_PHY_280_DATA 0x00000000
+#define DENALI_PHY_281_DATA 0x00000000
+#define DENALI_PHY_282_DATA 0x00000000
+#define DENALI_PHY_283_DATA 0x00000000
+#define DENALI_PHY_284_DATA 0x00000000
+#define DENALI_PHY_285_DATA 0x00000000
+#define DENALI_PHY_286_DATA 0x00000000
+#define DENALI_PHY_287_DATA 0x00000000
+#define DENALI_PHY_288_DATA 0x00000000
+#define DENALI_PHY_289_DATA 0x00200000
+#define DENALI_PHY_290_DATA 0x00000000
+#define DENALI_PHY_291_DATA 0x00000000
+#define DENALI_PHY_292_DATA 0x00000000
+#define DENALI_PHY_293_DATA 0x00000000
+#define DENALI_PHY_294_DATA 0x00000000
+#define DENALI_PHY_295_DATA 0x00000000
+#define DENALI_PHY_296_DATA 0x02800280
+#define DENALI_PHY_297_DATA 0x02800280
+#define DENALI_PHY_298_DATA 0x02800280
+#define DENALI_PHY_299_DATA 0x02800280
+#define DENALI_PHY_300_DATA 0x00000280
+#define DENALI_PHY_301_DATA 0x00000000
+#define DENALI_PHY_302_DATA 0x00000000
+#define DENALI_PHY_303_DATA 0x00000000
+#define DENALI_PHY_304_DATA 0x00000000
+#define DENALI_PHY_305_DATA 0x00000000
+#define DENALI_PHY_306_DATA 0x00800080
+#define DENALI_PHY_307_DATA 0x00800080
+#define DENALI_PHY_308_DATA 0x00800080
+#define DENALI_PHY_309_DATA 0x00800080
+#define DENALI_PHY_310_DATA 0x00800080
+#define DENALI_PHY_311_DATA 0x00800080
+#define DENALI_PHY_312_DATA 0x00800080
+#define DENALI_PHY_313_DATA 0x00800080
+#define DENALI_PHY_314_DATA 0x00800080
+#define DENALI_PHY_315_DATA 0x000100da
+#define DENALI_PHY_316_DATA 0x00000200
+#define DENALI_PHY_317_DATA 0x00000000
+#define DENALI_PHY_318_DATA 0x00000000
+#define DENALI_PHY_319_DATA 0x00000002
+#define DENALI_PHY_320_DATA 0x51313152
+#define DENALI_PHY_321_DATA 0x80013130
+#define DENALI_PHY_322_DATA 0x02000080
+#define DENALI_PHY_323_DATA 0x00100001
+#define DENALI_PHY_324_DATA 0x0c064208
+#define DENALI_PHY_325_DATA 0x000f0c0f
+#define DENALI_PHY_326_DATA 0x01000140
+#define DENALI_PHY_327_DATA 0x0000000c
+#define DENALI_PHY_328_DATA 0x00000000
+#define DENALI_PHY_329_DATA 0x00000000
+#define DENALI_PHY_330_DATA 0x00000000
+#define DENALI_PHY_331_DATA 0x00000000
+#define DENALI_PHY_332_DATA 0x00000000
+#define DENALI_PHY_333_DATA 0x00000000
+#define DENALI_PHY_334_DATA 0x00000000
+#define DENALI_PHY_335_DATA 0x00000000
+#define DENALI_PHY_336_DATA 0x00000000
+#define DENALI_PHY_337_DATA 0x00000000
+#define DENALI_PHY_338_DATA 0x00000000
+#define DENALI_PHY_339_DATA 0x00000000
+#define DENALI_PHY_340_DATA 0x00000000
+#define DENALI_PHY_341_DATA 0x00000000
+#define DENALI_PHY_342_DATA 0x00000000
+#define DENALI_PHY_343_DATA 0x00000000
+#define DENALI_PHY_344_DATA 0x00000000
+#define DENALI_PHY_345_DATA 0x00000000
+#define DENALI_PHY_346_DATA 0x00000000
+#define DENALI_PHY_347_DATA 0x00000000
+#define DENALI_PHY_348_DATA 0x00000000
+#define DENALI_PHY_349_DATA 0x00000000
+#define DENALI_PHY_350_DATA 0x00000000
+#define DENALI_PHY_351_DATA 0x00000000
+#define DENALI_PHY_352_DATA 0x00000000
+#define DENALI_PHY_353_DATA 0x00000000
+#define DENALI_PHY_354_DATA 0x00000000
+#define DENALI_PHY_355_DATA 0x00000000
+#define DENALI_PHY_356_DATA 0x00000000
+#define DENALI_PHY_357_DATA 0x00000000
+#define DENALI_PHY_358_DATA 0x00000000
+#define DENALI_PHY_359_DATA 0x00000000
+#define DENALI_PHY_360_DATA 0x00000000
+#define DENALI_PHY_361_DATA 0x00000000
+#define DENALI_PHY_362_DATA 0x00000000
+#define DENALI_PHY_363_DATA 0x00000000
+#define DENALI_PHY_364_DATA 0x00000000
+#define DENALI_PHY_365_DATA 0x00000000
+#define DENALI_PHY_366_DATA 0x00000000
+#define DENALI_PHY_367_DATA 0x00000000
+#define DENALI_PHY_368_DATA 0x00000000
+#define DENALI_PHY_369_DATA 0x00000000
+#define DENALI_PHY_370_DATA 0x00000000
+#define DENALI_PHY_371_DATA 0x00000000
+#define DENALI_PHY_372_DATA 0x00000000
+#define DENALI_PHY_373_DATA 0x00000000
+#define DENALI_PHY_374_DATA 0x00000000
+#define DENALI_PHY_375_DATA 0x00000000
+#define DENALI_PHY_376_DATA 0x00000000
+#define DENALI_PHY_377_DATA 0x00000000
+#define DENALI_PHY_378_DATA 0x00000000
+#define DENALI_PHY_379_DATA 0x00000000
+#define DENALI_PHY_380_DATA 0x00000000
+#define DENALI_PHY_381_DATA 0x00000000
+#define DENALI_PHY_382_DATA 0x00000000
+#define DENALI_PHY_383_DATA 0x00000000
+#define DENALI_PHY_384_DATA 0x37654120
+#define DENALI_PHY_385_DATA 0x0004c008
+#define DENALI_PHY_386_DATA 0x000000da
+#define DENALI_PHY_387_DATA 0x00000000
+#define DENALI_PHY_388_DATA 0x00000000
+#define DENALI_PHY_389_DATA 0x00010000
+#define DENALI_PHY_390_DATA 0x01DDDD90
+#define DENALI_PHY_391_DATA 0x01DDDD90
+#define DENALI_PHY_392_DATA 0x01030000
+#define DENALI_PHY_393_DATA 0x01000000
+#define DENALI_PHY_394_DATA 0x00c00000
+#define DENALI_PHY_395_DATA 0x00000007
+#define DENALI_PHY_396_DATA 0x00000000
+#define DENALI_PHY_397_DATA 0x00000000
+#define DENALI_PHY_398_DATA 0x04000408
+#define DENALI_PHY_399_DATA 0x00000408
+#define DENALI_PHY_400_DATA 0x00e4e400
+#define DENALI_PHY_401_DATA 0x00000000
+#define DENALI_PHY_402_DATA 0x00000000
+#define DENALI_PHY_403_DATA 0x00000000
+#define DENALI_PHY_404_DATA 0x00000000
+#define DENALI_PHY_405_DATA 0x00000000
+#define DENALI_PHY_406_DATA 0x00000000
+#define DENALI_PHY_407_DATA 0x00000000
+#define DENALI_PHY_408_DATA 0x00000000
+#define DENALI_PHY_409_DATA 0x00000000
+#define DENALI_PHY_410_DATA 0x00000000
+#define DENALI_PHY_411_DATA 0x00000000
+#define DENALI_PHY_412_DATA 0x00000000
+#define DENALI_PHY_413_DATA 0x00000000
+#define DENALI_PHY_414_DATA 0x00000000
+#define DENALI_PHY_415_DATA 0x00000000
+#define DENALI_PHY_416_DATA 0x00000000
+#define DENALI_PHY_417_DATA 0x00200000
+#define DENALI_PHY_418_DATA 0x00000000
+#define DENALI_PHY_419_DATA 0x00000000
+#define DENALI_PHY_420_DATA 0x00000000
+#define DENALI_PHY_421_DATA 0x00000000
+#define DENALI_PHY_422_DATA 0x00000000
+#define DENALI_PHY_423_DATA 0x00000000
+#define DENALI_PHY_424_DATA 0x02800280
+#define DENALI_PHY_425_DATA 0x02800280
+#define DENALI_PHY_426_DATA 0x02800280
+#define DENALI_PHY_427_DATA 0x02800280
+#define DENALI_PHY_428_DATA 0x00000280
+#define DENALI_PHY_429_DATA 0x00000000
+#define DENALI_PHY_430_DATA 0x00000000
+#define DENALI_PHY_431_DATA 0x00000000
+#define DENALI_PHY_432_DATA 0x00000000
+#define DENALI_PHY_433_DATA 0x00000000
+#define DENALI_PHY_434_DATA 0x00800080
+#define DENALI_PHY_435_DATA 0x00800080
+#define DENALI_PHY_436_DATA 0x00800080
+#define DENALI_PHY_437_DATA 0x00800080
+#define DENALI_PHY_438_DATA 0x00800080
+#define DENALI_PHY_439_DATA 0x00800080
+#define DENALI_PHY_440_DATA 0x00800080
+#define DENALI_PHY_441_DATA 0x00800080
+#define DENALI_PHY_442_DATA 0x00800080
+#define DENALI_PHY_443_DATA 0x000100da
+#define DENALI_PHY_444_DATA 0x00000200
+#define DENALI_PHY_445_DATA 0x00000000
+#define DENALI_PHY_446_DATA 0x00000000
+#define DENALI_PHY_447_DATA 0x00000002
+#define DENALI_PHY_448_DATA 0x51313152
+#define DENALI_PHY_449_DATA 0x80013130
+#define DENALI_PHY_450_DATA 0x02000080
+#define DENALI_PHY_451_DATA 0x00100001
+#define DENALI_PHY_452_DATA 0x0c064208
+#define DENALI_PHY_453_DATA 0x000f0c0f
+#define DENALI_PHY_454_DATA 0x01000140
+#define DENALI_PHY_455_DATA 0x0000000c
+#define DENALI_PHY_456_DATA 0x00000000
+#define DENALI_PHY_457_DATA 0x00000000
+#define DENALI_PHY_458_DATA 0x00000000
+#define DENALI_PHY_459_DATA 0x00000000
+#define DENALI_PHY_460_DATA 0x00000000
+#define DENALI_PHY_461_DATA 0x00000000
+#define DENALI_PHY_462_DATA 0x00000000
+#define DENALI_PHY_463_DATA 0x00000000
+#define DENALI_PHY_464_DATA 0x00000000
+#define DENALI_PHY_465_DATA 0x00000000
+#define DENALI_PHY_466_DATA 0x00000000
+#define DENALI_PHY_467_DATA 0x00000000
+#define DENALI_PHY_468_DATA 0x00000000
+#define DENALI_PHY_469_DATA 0x00000000
+#define DENALI_PHY_470_DATA 0x00000000
+#define DENALI_PHY_471_DATA 0x00000000
+#define DENALI_PHY_472_DATA 0x00000000
+#define DENALI_PHY_473_DATA 0x00000000
+#define DENALI_PHY_474_DATA 0x00000000
+#define DENALI_PHY_475_DATA 0x00000000
+#define DENALI_PHY_476_DATA 0x00000000
+#define DENALI_PHY_477_DATA 0x00000000
+#define DENALI_PHY_478_DATA 0x00000000
+#define DENALI_PHY_479_DATA 0x00000000
+#define DENALI_PHY_480_DATA 0x00000000
+#define DENALI_PHY_481_DATA 0x00000000
+#define DENALI_PHY_482_DATA 0x00000000
+#define DENALI_PHY_483_DATA 0x00000000
+#define DENALI_PHY_484_DATA 0x00000000
+#define DENALI_PHY_485_DATA 0x00000000
+#define DENALI_PHY_486_DATA 0x00000000
+#define DENALI_PHY_487_DATA 0x00000000
+#define DENALI_PHY_488_DATA 0x00000000
+#define DENALI_PHY_489_DATA 0x00000000
+#define DENALI_PHY_490_DATA 0x00000000
+#define DENALI_PHY_491_DATA 0x00000000
+#define DENALI_PHY_492_DATA 0x00000000
+#define DENALI_PHY_493_DATA 0x00000000
+#define DENALI_PHY_494_DATA 0x00000000
+#define DENALI_PHY_495_DATA 0x00000000
+#define DENALI_PHY_496_DATA 0x00000000
+#define DENALI_PHY_497_DATA 0x00000000
+#define DENALI_PHY_498_DATA 0x00000000
+#define DENALI_PHY_499_DATA 0x00000000
+#define DENALI_PHY_500_DATA 0x00000000
+#define DENALI_PHY_501_DATA 0x00000000
+#define DENALI_PHY_502_DATA 0x00000000
+#define DENALI_PHY_503_DATA 0x00000000
+#define DENALI_PHY_504_DATA 0x00000000
+#define DENALI_PHY_505_DATA 0x00000000
+#define DENALI_PHY_506_DATA 0x00000000
+#define DENALI_PHY_507_DATA 0x00000000
+#define DENALI_PHY_508_DATA 0x00000000
+#define DENALI_PHY_509_DATA 0x00000000
+#define DENALI_PHY_510_DATA 0x00000000
+#define DENALI_PHY_511_DATA 0x00000000
+#define DENALI_PHY_512_DATA 0x24316750
+#define DENALI_PHY_513_DATA 0x0004c008
+#define DENALI_PHY_514_DATA 0x000000da
+#define DENALI_PHY_515_DATA 0x00000000
+#define DENALI_PHY_516_DATA 0x00000000
+#define DENALI_PHY_517_DATA 0x00010000
+#define DENALI_PHY_518_DATA 0x01DDDD90
+#define DENALI_PHY_519_DATA 0x01DDDD90
+#define DENALI_PHY_520_DATA 0x01030000
+#define DENALI_PHY_521_DATA 0x01000000
+#define DENALI_PHY_522_DATA 0x00c00000
+#define DENALI_PHY_523_DATA 0x00000007
+#define DENALI_PHY_524_DATA 0x00000000
+#define DENALI_PHY_525_DATA 0x00000000
+#define DENALI_PHY_526_DATA 0x04000408
+#define DENALI_PHY_527_DATA 0x00000408
+#define DENALI_PHY_528_DATA 0x00e4e400
+#define DENALI_PHY_529_DATA 0x00000000
+#define DENALI_PHY_530_DATA 0x00000000
+#define DENALI_PHY_531_DATA 0x00000000
+#define DENALI_PHY_532_DATA 0x00000000
+#define DENALI_PHY_533_DATA 0x00000000
+#define DENALI_PHY_534_DATA 0x00000000
+#define DENALI_PHY_535_DATA 0x00000000
+#define DENALI_PHY_536_DATA 0x00000000
+#define DENALI_PHY_537_DATA 0x00000000
+#define DENALI_PHY_538_DATA 0x00000000
+#define DENALI_PHY_539_DATA 0x00000000
+#define DENALI_PHY_540_DATA 0x00000000
+#define DENALI_PHY_541_DATA 0x00000000
+#define DENALI_PHY_542_DATA 0x00000000
+#define DENALI_PHY_543_DATA 0x00000000
+#define DENALI_PHY_544_DATA 0x00000000
+#define DENALI_PHY_545_DATA 0x00200000
+#define DENALI_PHY_546_DATA 0x00000000
+#define DENALI_PHY_547_DATA 0x00000000
+#define DENALI_PHY_548_DATA 0x00000000
+#define DENALI_PHY_549_DATA 0x00000000
+#define DENALI_PHY_550_DATA 0x00000000
+#define DENALI_PHY_551_DATA 0x00000000
+#define DENALI_PHY_552_DATA 0x02800280
+#define DENALI_PHY_553_DATA 0x02800280
+#define DENALI_PHY_554_DATA 0x02800280
+#define DENALI_PHY_555_DATA 0x02800280
+#define DENALI_PHY_556_DATA 0x00000280
+#define DENALI_PHY_557_DATA 0x00000000
+#define DENALI_PHY_558_DATA 0x00000000
+#define DENALI_PHY_559_DATA 0x00000000
+#define DENALI_PHY_560_DATA 0x00000000
+#define DENALI_PHY_561_DATA 0x00000000
+#define DENALI_PHY_562_DATA 0x00800080
+#define DENALI_PHY_563_DATA 0x00800080
+#define DENALI_PHY_564_DATA 0x00800080
+#define DENALI_PHY_565_DATA 0x00800080
+#define DENALI_PHY_566_DATA 0x00800080
+#define DENALI_PHY_567_DATA 0x00800080
+#define DENALI_PHY_568_DATA 0x00800080
+#define DENALI_PHY_569_DATA 0x00800080
+#define DENALI_PHY_570_DATA 0x00800080
+#define DENALI_PHY_571_DATA 0x000100da
+#define DENALI_PHY_572_DATA 0x00000200
+#define DENALI_PHY_573_DATA 0x00000000
+#define DENALI_PHY_574_DATA 0x00000000
+#define DENALI_PHY_575_DATA 0x00000002
+#define DENALI_PHY_576_DATA 0x51313152
+#define DENALI_PHY_577_DATA 0x80013130
+#define DENALI_PHY_578_DATA 0x02000080
+#define DENALI_PHY_579_DATA 0x00100001
+#define DENALI_PHY_580_DATA 0x0c064208
+#define DENALI_PHY_581_DATA 0x000f0c0f
+#define DENALI_PHY_582_DATA 0x01000140
+#define DENALI_PHY_583_DATA 0x0000000c
+#define DENALI_PHY_584_DATA 0x00000000
+#define DENALI_PHY_585_DATA 0x00000000
+#define DENALI_PHY_586_DATA 0x00000000
+#define DENALI_PHY_587_DATA 0x00000000
+#define DENALI_PHY_588_DATA 0x00000000
+#define DENALI_PHY_589_DATA 0x00000000
+#define DENALI_PHY_590_DATA 0x00000000
+#define DENALI_PHY_591_DATA 0x00000000
+#define DENALI_PHY_592_DATA 0x00000000
+#define DENALI_PHY_593_DATA 0x00000000
+#define DENALI_PHY_594_DATA 0x00000000
+#define DENALI_PHY_595_DATA 0x00000000
+#define DENALI_PHY_596_DATA 0x00000000
+#define DENALI_PHY_597_DATA 0x00000000
+#define DENALI_PHY_598_DATA 0x00000000
+#define DENALI_PHY_599_DATA 0x00000000
+#define DENALI_PHY_600_DATA 0x00000000
+#define DENALI_PHY_601_DATA 0x00000000
+#define DENALI_PHY_602_DATA 0x00000000
+#define DENALI_PHY_603_DATA 0x00000000
+#define DENALI_PHY_604_DATA 0x00000000
+#define DENALI_PHY_605_DATA 0x00000000
+#define DENALI_PHY_606_DATA 0x00000000
+#define DENALI_PHY_607_DATA 0x00000000
+#define DENALI_PHY_608_DATA 0x00000000
+#define DENALI_PHY_609_DATA 0x00000000
+#define DENALI_PHY_610_DATA 0x00000000
+#define DENALI_PHY_611_DATA 0x00000000
+#define DENALI_PHY_612_DATA 0x00000000
+#define DENALI_PHY_613_DATA 0x00000000
+#define DENALI_PHY_614_DATA 0x00000000
+#define DENALI_PHY_615_DATA 0x00000000
+#define DENALI_PHY_616_DATA 0x00000000
+#define DENALI_PHY_617_DATA 0x00000000
+#define DENALI_PHY_618_DATA 0x00000000
+#define DENALI_PHY_619_DATA 0x00000000
+#define DENALI_PHY_620_DATA 0x00000000
+#define DENALI_PHY_621_DATA 0x00000000
+#define DENALI_PHY_622_DATA 0x00000000
+#define DENALI_PHY_623_DATA 0x00000000
+#define DENALI_PHY_624_DATA 0x00000000
+#define DENALI_PHY_625_DATA 0x00000000
+#define DENALI_PHY_626_DATA 0x00000000
+#define DENALI_PHY_627_DATA 0x00000000
+#define DENALI_PHY_628_DATA 0x00000000
+#define DENALI_PHY_629_DATA 0x00000000
+#define DENALI_PHY_630_DATA 0x00000000
+#define DENALI_PHY_631_DATA 0x00000000
+#define DENALI_PHY_632_DATA 0x00000000
+#define DENALI_PHY_633_DATA 0x00000000
+#define DENALI_PHY_634_DATA 0x00000000
+#define DENALI_PHY_635_DATA 0x00000000
+#define DENALI_PHY_636_DATA 0x00000000
+#define DENALI_PHY_637_DATA 0x00000000
+#define DENALI_PHY_638_DATA 0x00000000
+#define DENALI_PHY_639_DATA 0x00000000
+#define DENALI_PHY_640_DATA 0x35174620
+#define DENALI_PHY_641_DATA 0x0004c008
+#define DENALI_PHY_642_DATA 0x000000da
+#define DENALI_PHY_643_DATA 0x00000000
+#define DENALI_PHY_644_DATA 0x00000000
+#define DENALI_PHY_645_DATA 0x00010000
+#define DENALI_PHY_646_DATA 0x01DDDD90
+#define DENALI_PHY_647_DATA 0x01DDDD90
+#define DENALI_PHY_648_DATA 0x01030000
+#define DENALI_PHY_649_DATA 0x01000000
+#define DENALI_PHY_650_DATA 0x00c00000
+#define DENALI_PHY_651_DATA 0x00000007
+#define DENALI_PHY_652_DATA 0x00000000
+#define DENALI_PHY_653_DATA 0x00000000
+#define DENALI_PHY_654_DATA 0x04000408
+#define DENALI_PHY_655_DATA 0x00000408
+#define DENALI_PHY_656_DATA 0x00e4e400
+#define DENALI_PHY_657_DATA 0x00000000
+#define DENALI_PHY_658_DATA 0x00000000
+#define DENALI_PHY_659_DATA 0x00000000
+#define DENALI_PHY_660_DATA 0x00000000
+#define DENALI_PHY_661_DATA 0x00000000
+#define DENALI_PHY_662_DATA 0x00000000
+#define DENALI_PHY_663_DATA 0x00000000
+#define DENALI_PHY_664_DATA 0x00000000
+#define DENALI_PHY_665_DATA 0x00000000
+#define DENALI_PHY_666_DATA 0x00000000
+#define DENALI_PHY_667_DATA 0x00000000
+#define DENALI_PHY_668_DATA 0x00000000
+#define DENALI_PHY_669_DATA 0x00000000
+#define DENALI_PHY_670_DATA 0x00000000
+#define DENALI_PHY_671_DATA 0x00000000
+#define DENALI_PHY_672_DATA 0x00000000
+#define DENALI_PHY_673_DATA 0x00200000
+#define DENALI_PHY_674_DATA 0x00000000
+#define DENALI_PHY_675_DATA 0x00000000
+#define DENALI_PHY_676_DATA 0x00000000
+#define DENALI_PHY_677_DATA 0x00000000
+#define DENALI_PHY_678_DATA 0x00000000
+#define DENALI_PHY_679_DATA 0x00000000
+#define DENALI_PHY_680_DATA 0x02800280
+#define DENALI_PHY_681_DATA 0x02800280
+#define DENALI_PHY_682_DATA 0x02800280
+#define DENALI_PHY_683_DATA 0x02800280
+#define DENALI_PHY_684_DATA 0x00000280
+#define DENALI_PHY_685_DATA 0x00000000
+#define DENALI_PHY_686_DATA 0x00000000
+#define DENALI_PHY_687_DATA 0x00000000
+#define DENALI_PHY_688_DATA 0x00000000
+#define DENALI_PHY_689_DATA 0x00000000
+#define DENALI_PHY_690_DATA 0x00800080
+#define DENALI_PHY_691_DATA 0x00800080
+#define DENALI_PHY_692_DATA 0x00800080
+#define DENALI_PHY_693_DATA 0x00800080
+#define DENALI_PHY_694_DATA 0x00800080
+#define DENALI_PHY_695_DATA 0x00800080
+#define DENALI_PHY_696_DATA 0x00800080
+#define DENALI_PHY_697_DATA 0x00800080
+#define DENALI_PHY_698_DATA 0x00800080
+#define DENALI_PHY_699_DATA 0x000100da
+#define DENALI_PHY_700_DATA 0x00000200
+#define DENALI_PHY_701_DATA 0x00000000
+#define DENALI_PHY_702_DATA 0x00000000
+#define DENALI_PHY_703_DATA 0x00000002
+#define DENALI_PHY_704_DATA 0x51313152
+#define DENALI_PHY_705_DATA 0x80013130
+#define DENALI_PHY_706_DATA 0x02000080
+#define DENALI_PHY_707_DATA 0x00100001
+#define DENALI_PHY_708_DATA 0x0c064208
+#define DENALI_PHY_709_DATA 0x000f0c0f
+#define DENALI_PHY_710_DATA 0x01000140
+#define DENALI_PHY_711_DATA 0x0000000c
+#define DENALI_PHY_712_DATA 0x00000000
+#define DENALI_PHY_713_DATA 0x00000000
+#define DENALI_PHY_714_DATA 0x00000000
+#define DENALI_PHY_715_DATA 0x00000000
+#define DENALI_PHY_716_DATA 0x00000000
+#define DENALI_PHY_717_DATA 0x00000000
+#define DENALI_PHY_718_DATA 0x00000000
+#define DENALI_PHY_719_DATA 0x00000000
+#define DENALI_PHY_720_DATA 0x00000000
+#define DENALI_PHY_721_DATA 0x00000000
+#define DENALI_PHY_722_DATA 0x00000000
+#define DENALI_PHY_723_DATA 0x00000000
+#define DENALI_PHY_724_DATA 0x00000000
+#define DENALI_PHY_725_DATA 0x00000000
+#define DENALI_PHY_726_DATA 0x00000000
+#define DENALI_PHY_727_DATA 0x00000000
+#define DENALI_PHY_728_DATA 0x00000000
+#define DENALI_PHY_729_DATA 0x00000000
+#define DENALI_PHY_730_DATA 0x00000000
+#define DENALI_PHY_731_DATA 0x00000000
+#define DENALI_PHY_732_DATA 0x00000000
+#define DENALI_PHY_733_DATA 0x00000000
+#define DENALI_PHY_734_DATA 0x00000000
+#define DENALI_PHY_735_DATA 0x00000000
+#define DENALI_PHY_736_DATA 0x00000000
+#define DENALI_PHY_737_DATA 0x00000000
+#define DENALI_PHY_738_DATA 0x00000000
+#define DENALI_PHY_739_DATA 0x00000000
+#define DENALI_PHY_740_DATA 0x00000000
+#define DENALI_PHY_741_DATA 0x00000000
+#define DENALI_PHY_742_DATA 0x00000000
+#define DENALI_PHY_743_DATA 0x00000000
+#define DENALI_PHY_744_DATA 0x00000000
+#define DENALI_PHY_745_DATA 0x00000000
+#define DENALI_PHY_746_DATA 0x00000000
+#define DENALI_PHY_747_DATA 0x00000000
+#define DENALI_PHY_748_DATA 0x00000000
+#define DENALI_PHY_749_DATA 0x00000000
+#define DENALI_PHY_750_DATA 0x00000000
+#define DENALI_PHY_751_DATA 0x00000000
+#define DENALI_PHY_752_DATA 0x00000000
+#define DENALI_PHY_753_DATA 0x00000000
+#define DENALI_PHY_754_DATA 0x00000000
+#define DENALI_PHY_755_DATA 0x00000000
+#define DENALI_PHY_756_DATA 0x00000000
+#define DENALI_PHY_757_DATA 0x00000000
+#define DENALI_PHY_758_DATA 0x00000000
+#define DENALI_PHY_759_DATA 0x00000000
+#define DENALI_PHY_760_DATA 0x00000000
+#define DENALI_PHY_761_DATA 0x00000000
+#define DENALI_PHY_762_DATA 0x00000000
+#define DENALI_PHY_763_DATA 0x00000000
+#define DENALI_PHY_764_DATA 0x00000000
+#define DENALI_PHY_765_DATA 0x00000000
+#define DENALI_PHY_766_DATA 0x00000000
+#define DENALI_PHY_767_DATA 0x00000000
+#define DENALI_PHY_768_DATA 0x15203476
+#define DENALI_PHY_769_DATA 0x0004c008
+#define DENALI_PHY_770_DATA 0x000000da
+#define DENALI_PHY_771_DATA 0x00000000
+#define DENALI_PHY_772_DATA 0x00000000
+#define DENALI_PHY_773_DATA 0x00010000
+#define DENALI_PHY_774_DATA 0x01DDDD90
+#define DENALI_PHY_775_DATA 0x01DDDD90
+#define DENALI_PHY_776_DATA 0x01030000
+#define DENALI_PHY_777_DATA 0x01000000
+#define DENALI_PHY_778_DATA 0x00c00000
+#define DENALI_PHY_779_DATA 0x00000007
+#define DENALI_PHY_780_DATA 0x00000000
+#define DENALI_PHY_781_DATA 0x00000000
+#define DENALI_PHY_782_DATA 0x04000408
+#define DENALI_PHY_783_DATA 0x00000408
+#define DENALI_PHY_784_DATA 0x00e4e400
+#define DENALI_PHY_785_DATA 0x00000000
+#define DENALI_PHY_786_DATA 0x00000000
+#define DENALI_PHY_787_DATA 0x00000000
+#define DENALI_PHY_788_DATA 0x00000000
+#define DENALI_PHY_789_DATA 0x00000000
+#define DENALI_PHY_790_DATA 0x00000000
+#define DENALI_PHY_791_DATA 0x00000000
+#define DENALI_PHY_792_DATA 0x00000000
+#define DENALI_PHY_793_DATA 0x00000000
+#define DENALI_PHY_794_DATA 0x00000000
+#define DENALI_PHY_795_DATA 0x00000000
+#define DENALI_PHY_796_DATA 0x00000000
+#define DENALI_PHY_797_DATA 0x00000000
+#define DENALI_PHY_798_DATA 0x00000000
+#define DENALI_PHY_799_DATA 0x00000000
+#define DENALI_PHY_800_DATA 0x00000000
+#define DENALI_PHY_801_DATA 0x00200000
+#define DENALI_PHY_802_DATA 0x00000000
+#define DENALI_PHY_803_DATA 0x00000000
+#define DENALI_PHY_804_DATA 0x00000000
+#define DENALI_PHY_805_DATA 0x00000000
+#define DENALI_PHY_806_DATA 0x00000000
+#define DENALI_PHY_807_DATA 0x00000000
+#define DENALI_PHY_808_DATA 0x02800280
+#define DENALI_PHY_809_DATA 0x02800280
+#define DENALI_PHY_810_DATA 0x02800280
+#define DENALI_PHY_811_DATA 0x02800280
+#define DENALI_PHY_812_DATA 0x00000280
+#define DENALI_PHY_813_DATA 0x00000000
+#define DENALI_PHY_814_DATA 0x00000000
+#define DENALI_PHY_815_DATA 0x00000000
+#define DENALI_PHY_816_DATA 0x00000000
+#define DENALI_PHY_817_DATA 0x00000000
+#define DENALI_PHY_818_DATA 0x00800080
+#define DENALI_PHY_819_DATA 0x00800080
+#define DENALI_PHY_820_DATA 0x00800080
+#define DENALI_PHY_821_DATA 0x00800080
+#define DENALI_PHY_822_DATA 0x00800080
+#define DENALI_PHY_823_DATA 0x00800080
+#define DENALI_PHY_824_DATA 0x00800080
+#define DENALI_PHY_825_DATA 0x00800080
+#define DENALI_PHY_826_DATA 0x00800080
+#define DENALI_PHY_827_DATA 0x000100da
+#define DENALI_PHY_828_DATA 0x00000200
+#define DENALI_PHY_829_DATA 0x00000000
+#define DENALI_PHY_830_DATA 0x00000000
+#define DENALI_PHY_831_DATA 0x00000002
+#define DENALI_PHY_832_DATA 0x51313152
+#define DENALI_PHY_833_DATA 0x80013130
+#define DENALI_PHY_834_DATA 0x02000080
+#define DENALI_PHY_835_DATA 0x00100001
+#define DENALI_PHY_836_DATA 0x0c064208
+#define DENALI_PHY_837_DATA 0x000f0c0f
+#define DENALI_PHY_838_DATA 0x01000140
+#define DENALI_PHY_839_DATA 0x0000000c
+#define DENALI_PHY_840_DATA 0x00000000
+#define DENALI_PHY_841_DATA 0x00000000
+#define DENALI_PHY_842_DATA 0x00000000
+#define DENALI_PHY_843_DATA 0x00000000
+#define DENALI_PHY_844_DATA 0x00000000
+#define DENALI_PHY_845_DATA 0x00000000
+#define DENALI_PHY_846_DATA 0x00000000
+#define DENALI_PHY_847_DATA 0x00000000
+#define DENALI_PHY_848_DATA 0x00000000
+#define DENALI_PHY_849_DATA 0x00000000
+#define DENALI_PHY_850_DATA 0x00000000
+#define DENALI_PHY_851_DATA 0x00000000
+#define DENALI_PHY_852_DATA 0x00000000
+#define DENALI_PHY_853_DATA 0x00000000
+#define DENALI_PHY_854_DATA 0x00000000
+#define DENALI_PHY_855_DATA 0x00000000
+#define DENALI_PHY_856_DATA 0x00000000
+#define DENALI_PHY_857_DATA 0x00000000
+#define DENALI_PHY_858_DATA 0x00000000
+#define DENALI_PHY_859_DATA 0x00000000
+#define DENALI_PHY_860_DATA 0x00000000
+#define DENALI_PHY_861_DATA 0x00000000
+#define DENALI_PHY_862_DATA 0x00000000
+#define DENALI_PHY_863_DATA 0x00000000
+#define DENALI_PHY_864_DATA 0x00000000
+#define DENALI_PHY_865_DATA 0x00000000
+#define DENALI_PHY_866_DATA 0x00000000
+#define DENALI_PHY_867_DATA 0x00000000
+#define DENALI_PHY_868_DATA 0x00000000
+#define DENALI_PHY_869_DATA 0x00000000
+#define DENALI_PHY_870_DATA 0x00000000
+#define DENALI_PHY_871_DATA 0x00000000
+#define DENALI_PHY_872_DATA 0x00000000
+#define DENALI_PHY_873_DATA 0x00000000
+#define DENALI_PHY_874_DATA 0x00000000
+#define DENALI_PHY_875_DATA 0x00000000
+#define DENALI_PHY_876_DATA 0x00000000
+#define DENALI_PHY_877_DATA 0x00000000
+#define DENALI_PHY_878_DATA 0x00000000
+#define DENALI_PHY_879_DATA 0x00000000
+#define DENALI_PHY_880_DATA 0x00000000
+#define DENALI_PHY_881_DATA 0x00000000
+#define DENALI_PHY_882_DATA 0x00000000
+#define DENALI_PHY_883_DATA 0x00000000
+#define DENALI_PHY_884_DATA 0x00000000
+#define DENALI_PHY_885_DATA 0x00000000
+#define DENALI_PHY_886_DATA 0x00000000
+#define DENALI_PHY_887_DATA 0x00000000
+#define DENALI_PHY_888_DATA 0x00000000
+#define DENALI_PHY_889_DATA 0x00000000
+#define DENALI_PHY_890_DATA 0x00000000
+#define DENALI_PHY_891_DATA 0x00000000
+#define DENALI_PHY_892_DATA 0x00000000
+#define DENALI_PHY_893_DATA 0x00000000
+#define DENALI_PHY_894_DATA 0x00000000
+#define DENALI_PHY_895_DATA 0x00000000
+#define DENALI_PHY_896_DATA 0x41753206
+#define DENALI_PHY_897_DATA 0x0004c008
+#define DENALI_PHY_898_DATA 0x000000da
+#define DENALI_PHY_899_DATA 0x00000000
+#define DENALI_PHY_900_DATA 0x00000000
+#define DENALI_PHY_901_DATA 0x00010000
+#define DENALI_PHY_902_DATA 0x01DDDD90
+#define DENALI_PHY_903_DATA 0x01DDDD90
+#define DENALI_PHY_904_DATA 0x01030000
+#define DENALI_PHY_905_DATA 0x01000000
+#define DENALI_PHY_906_DATA 0x00c00000
+#define DENALI_PHY_907_DATA 0x00000007
+#define DENALI_PHY_908_DATA 0x00000000
+#define DENALI_PHY_909_DATA 0x00000000
+#define DENALI_PHY_910_DATA 0x04000408
+#define DENALI_PHY_911_DATA 0x00000408
+#define DENALI_PHY_912_DATA 0x00e4e400
+#define DENALI_PHY_913_DATA 0x00000000
+#define DENALI_PHY_914_DATA 0x00000000
+#define DENALI_PHY_915_DATA 0x00000000
+#define DENALI_PHY_916_DATA 0x00000000
+#define DENALI_PHY_917_DATA 0x00000000
+#define DENALI_PHY_918_DATA 0x00000000
+#define DENALI_PHY_919_DATA 0x00000000
+#define DENALI_PHY_920_DATA 0x00000000
+#define DENALI_PHY_921_DATA 0x00000000
+#define DENALI_PHY_922_DATA 0x00000000
+#define DENALI_PHY_923_DATA 0x00000000
+#define DENALI_PHY_924_DATA 0x00000000
+#define DENALI_PHY_925_DATA 0x00000000
+#define DENALI_PHY_926_DATA 0x00000000
+#define DENALI_PHY_927_DATA 0x00000000
+#define DENALI_PHY_928_DATA 0x00000000
+#define DENALI_PHY_929_DATA 0x00200000
+#define DENALI_PHY_930_DATA 0x00000000
+#define DENALI_PHY_931_DATA 0x00000000
+#define DENALI_PHY_932_DATA 0x00000000
+#define DENALI_PHY_933_DATA 0x00000000
+#define DENALI_PHY_934_DATA 0x00000000
+#define DENALI_PHY_935_DATA 0x00000000
+#define DENALI_PHY_936_DATA 0x02800280
+#define DENALI_PHY_937_DATA 0x02800280
+#define DENALI_PHY_938_DATA 0x02800280
+#define DENALI_PHY_939_DATA 0x02800280
+#define DENALI_PHY_940_DATA 0x00000280
+#define DENALI_PHY_941_DATA 0x00000000
+#define DENALI_PHY_942_DATA 0x00000000
+#define DENALI_PHY_943_DATA 0x00000000
+#define DENALI_PHY_944_DATA 0x00000000
+#define DENALI_PHY_945_DATA 0x00000000
+#define DENALI_PHY_946_DATA 0x00800080
+#define DENALI_PHY_947_DATA 0x00800080
+#define DENALI_PHY_948_DATA 0x00800080
+#define DENALI_PHY_949_DATA 0x00800080
+#define DENALI_PHY_950_DATA 0x00800080
+#define DENALI_PHY_951_DATA 0x00800080
+#define DENALI_PHY_952_DATA 0x00800080
+#define DENALI_PHY_953_DATA 0x00800080
+#define DENALI_PHY_954_DATA 0x00800080
+#define DENALI_PHY_955_DATA 0x000100da
+#define DENALI_PHY_956_DATA 0x00000200
+#define DENALI_PHY_957_DATA 0x00000000
+#define DENALI_PHY_958_DATA 0x00000000
+#define DENALI_PHY_959_DATA 0x00000002
+#define DENALI_PHY_960_DATA 0x51313152
+#define DENALI_PHY_961_DATA 0x80013130
+#define DENALI_PHY_962_DATA 0x02000080
+#define DENALI_PHY_963_DATA 0x00100001
+#define DENALI_PHY_964_DATA 0x0c064208
+#define DENALI_PHY_965_DATA 0x000f0c0f
+#define DENALI_PHY_966_DATA 0x01000140
+#define DENALI_PHY_967_DATA 0x0000000c
+#define DENALI_PHY_968_DATA 0x00000000
+#define DENALI_PHY_969_DATA 0x00000000
+#define DENALI_PHY_970_DATA 0x00000000
+#define DENALI_PHY_971_DATA 0x00000000
+#define DENALI_PHY_972_DATA 0x00000000
+#define DENALI_PHY_973_DATA 0x00000000
+#define DENALI_PHY_974_DATA 0x00000000
+#define DENALI_PHY_975_DATA 0x00000000
+#define DENALI_PHY_976_DATA 0x00000000
+#define DENALI_PHY_977_DATA 0x00000000
+#define DENALI_PHY_978_DATA 0x00000000
+#define DENALI_PHY_979_DATA 0x00000000
+#define DENALI_PHY_980_DATA 0x00000000
+#define DENALI_PHY_981_DATA 0x00000000
+#define DENALI_PHY_982_DATA 0x00000000
+#define DENALI_PHY_983_DATA 0x00000000
+#define DENALI_PHY_984_DATA 0x00000000
+#define DENALI_PHY_985_DATA 0x00000000
+#define DENALI_PHY_986_DATA 0x00000000
+#define DENALI_PHY_987_DATA 0x00000000
+#define DENALI_PHY_988_DATA 0x00000000
+#define DENALI_PHY_989_DATA 0x00000000
+#define DENALI_PHY_990_DATA 0x00000000
+#define DENALI_PHY_991_DATA 0x00000000
+#define DENALI_PHY_992_DATA 0x00000000
+#define DENALI_PHY_993_DATA 0x00000000
+#define DENALI_PHY_994_DATA 0x00000000
+#define DENALI_PHY_995_DATA 0x00000000
+#define DENALI_PHY_996_DATA 0x00000000
+#define DENALI_PHY_997_DATA 0x00000000
+#define DENALI_PHY_998_DATA 0x00000000
+#define DENALI_PHY_999_DATA 0x00000000
+#define DENALI_PHY_1000_DATA 0x00000000
+#define DENALI_PHY_1001_DATA 0x00000000
+#define DENALI_PHY_1002_DATA 0x00000000
+#define DENALI_PHY_1003_DATA 0x00000000
+#define DENALI_PHY_1004_DATA 0x00000000
+#define DENALI_PHY_1005_DATA 0x00000000
+#define DENALI_PHY_1006_DATA 0x00000000
+#define DENALI_PHY_1007_DATA 0x00000000
+#define DENALI_PHY_1008_DATA 0x00000000
+#define DENALI_PHY_1009_DATA 0x00000000
+#define DENALI_PHY_1010_DATA 0x00000000
+#define DENALI_PHY_1011_DATA 0x00000000
+#define DENALI_PHY_1012_DATA 0x00000000
+#define DENALI_PHY_1013_DATA 0x00000000
+#define DENALI_PHY_1014_DATA 0x00000000
+#define DENALI_PHY_1015_DATA 0x00000000
+#define DENALI_PHY_1016_DATA 0x00000000
+#define DENALI_PHY_1017_DATA 0x00000000
+#define DENALI_PHY_1018_DATA 0x00000000
+#define DENALI_PHY_1019_DATA 0x00000000
+#define DENALI_PHY_1020_DATA 0x00000000
+#define DENALI_PHY_1021_DATA 0x00000000
+#define DENALI_PHY_1022_DATA 0x00000000
+#define DENALI_PHY_1023_DATA 0x00000000
+#define DENALI_PHY_1024_DATA 0x36025174
+#define DENALI_PHY_1025_DATA 0x0004c008
+#define DENALI_PHY_1026_DATA 0x000000da
+#define DENALI_PHY_1027_DATA 0x00000000
+#define DENALI_PHY_1028_DATA 0x00000000
+#define DENALI_PHY_1029_DATA 0x00010000
+#define DENALI_PHY_1030_DATA 0x01DDDD90
+#define DENALI_PHY_1031_DATA 0x01DDDD90
+#define DENALI_PHY_1032_DATA 0x01030000
+#define DENALI_PHY_1033_DATA 0x01000000
+#define DENALI_PHY_1034_DATA 0x00c00000
+#define DENALI_PHY_1035_DATA 0x00000007
+#define DENALI_PHY_1036_DATA 0x00000000
+#define DENALI_PHY_1037_DATA 0x00000000
+#define DENALI_PHY_1038_DATA 0x04000408
+#define DENALI_PHY_1039_DATA 0x00000408
+#define DENALI_PHY_1040_DATA 0x00e4e400
+#define DENALI_PHY_1041_DATA 0x00000000
+#define DENALI_PHY_1042_DATA 0x00000000
+#define DENALI_PHY_1043_DATA 0x00000000
+#define DENALI_PHY_1044_DATA 0x00000000
+#define DENALI_PHY_1045_DATA 0x00000000
+#define DENALI_PHY_1046_DATA 0x00000000
+#define DENALI_PHY_1047_DATA 0x00000000
+#define DENALI_PHY_1048_DATA 0x00000000
+#define DENALI_PHY_1049_DATA 0x00000000
+#define DENALI_PHY_1050_DATA 0x00000000
+#define DENALI_PHY_1051_DATA 0x00000000
+#define DENALI_PHY_1052_DATA 0x00000000
+#define DENALI_PHY_1053_DATA 0x00000000
+#define DENALI_PHY_1054_DATA 0x00000000
+#define DENALI_PHY_1055_DATA 0x00000000
+#define DENALI_PHY_1056_DATA 0x00000000
+#define DENALI_PHY_1057_DATA 0x00200000
+#define DENALI_PHY_1058_DATA 0x00000000
+#define DENALI_PHY_1059_DATA 0x00000000
+#define DENALI_PHY_1060_DATA 0x00000000
+#define DENALI_PHY_1061_DATA 0x00000000
+#define DENALI_PHY_1062_DATA 0x00000000
+#define DENALI_PHY_1063_DATA 0x00000000
+#define DENALI_PHY_1064_DATA 0x02800280
+#define DENALI_PHY_1065_DATA 0x02800280
+#define DENALI_PHY_1066_DATA 0x02800280
+#define DENALI_PHY_1067_DATA 0x02800280
+#define DENALI_PHY_1068_DATA 0x00000280
+#define DENALI_PHY_1069_DATA 0x00000000
+#define DENALI_PHY_1070_DATA 0x00000000
+#define DENALI_PHY_1071_DATA 0x00000000
+#define DENALI_PHY_1072_DATA 0x00000000
+#define DENALI_PHY_1073_DATA 0x00000000
+#define DENALI_PHY_1074_DATA 0x00800080
+#define DENALI_PHY_1075_DATA 0x00800080
+#define DENALI_PHY_1076_DATA 0x00800080
+#define DENALI_PHY_1077_DATA 0x00800080
+#define DENALI_PHY_1078_DATA 0x00800080
+#define DENALI_PHY_1079_DATA 0x00800080
+#define DENALI_PHY_1080_DATA 0x00800080
+#define DENALI_PHY_1081_DATA 0x00800080
+#define DENALI_PHY_1082_DATA 0x00800080
+#define DENALI_PHY_1083_DATA 0x000100da
+#define DENALI_PHY_1084_DATA 0x00000200
+#define DENALI_PHY_1085_DATA 0x00000000
+#define DENALI_PHY_1086_DATA 0x00000000
+#define DENALI_PHY_1087_DATA 0x00000002
+#define DENALI_PHY_1088_DATA 0x51313152
+#define DENALI_PHY_1089_DATA 0x80013130
+#define DENALI_PHY_1090_DATA 0x02000080
+#define DENALI_PHY_1091_DATA 0x00100001
+#define DENALI_PHY_1092_DATA 0x0c064208
+#define DENALI_PHY_1093_DATA 0x000f0c0f
+#define DENALI_PHY_1094_DATA 0x01000140
+#define DENALI_PHY_1095_DATA 0x0000000c
+#define DENALI_PHY_1096_DATA 0x00000000
+#define DENALI_PHY_1097_DATA 0x00000000
+#define DENALI_PHY_1098_DATA 0x00000000
+#define DENALI_PHY_1099_DATA 0x00000000
+#define DENALI_PHY_1100_DATA 0x00000000
+#define DENALI_PHY_1101_DATA 0x00000000
+#define DENALI_PHY_1102_DATA 0x00000000
+#define DENALI_PHY_1103_DATA 0x00000000
+#define DENALI_PHY_1104_DATA 0x00000000
+#define DENALI_PHY_1105_DATA 0x00000000
+#define DENALI_PHY_1106_DATA 0x00000000
+#define DENALI_PHY_1107_DATA 0x00000000
+#define DENALI_PHY_1108_DATA 0x00000000
+#define DENALI_PHY_1109_DATA 0x00000000
+#define DENALI_PHY_1110_DATA 0x00000000
+#define DENALI_PHY_1111_DATA 0x00000000
+#define DENALI_PHY_1112_DATA 0x00000000
+#define DENALI_PHY_1113_DATA 0x00000000
+#define DENALI_PHY_1114_DATA 0x00000000
+#define DENALI_PHY_1115_DATA 0x00000000
+#define DENALI_PHY_1116_DATA 0x00000000
+#define DENALI_PHY_1117_DATA 0x00000000
+#define DENALI_PHY_1118_DATA 0x00000000
+#define DENALI_PHY_1119_DATA 0x00000000
+#define DENALI_PHY_1120_DATA 0x00000000
+#define DENALI_PHY_1121_DATA 0x00000000
+#define DENALI_PHY_1122_DATA 0x00000000
+#define DENALI_PHY_1123_DATA 0x00000000
+#define DENALI_PHY_1124_DATA 0x00000000
+#define DENALI_PHY_1125_DATA 0x00000000
+#define DENALI_PHY_1126_DATA 0x00000000
+#define DENALI_PHY_1127_DATA 0x00000000
+#define DENALI_PHY_1128_DATA 0x00000000
+#define DENALI_PHY_1129_DATA 0x00000000
+#define DENALI_PHY_1130_DATA 0x00000000
+#define DENALI_PHY_1131_DATA 0x00000000
+#define DENALI_PHY_1132_DATA 0x00000000
+#define DENALI_PHY_1133_DATA 0x00000000
+#define DENALI_PHY_1134_DATA 0x00000000
+#define DENALI_PHY_1135_DATA 0x00000000
+#define DENALI_PHY_1136_DATA 0x00000000
+#define DENALI_PHY_1137_DATA 0x00000000
+#define DENALI_PHY_1138_DATA 0x00000000
+#define DENALI_PHY_1139_DATA 0x00000000
+#define DENALI_PHY_1140_DATA 0x00000000
+#define DENALI_PHY_1141_DATA 0x00000000
+#define DENALI_PHY_1142_DATA 0x00000000
+#define DENALI_PHY_1143_DATA 0x00000000
+#define DENALI_PHY_1144_DATA 0x00000000
+#define DENALI_PHY_1145_DATA 0x00000000
+#define DENALI_PHY_1146_DATA 0x00000000
+#define DENALI_PHY_1147_DATA 0x00000000
+#define DENALI_PHY_1148_DATA 0x00000000
+#define DENALI_PHY_1149_DATA 0x00000000
+#define DENALI_PHY_1150_DATA 0x00000000
+#define DENALI_PHY_1151_DATA 0x00000000
+#define DENALI_PHY_1152_DATA 0x00000000
+#define DENALI_PHY_1153_DATA 0x00000000
+#define DENALI_PHY_1154_DATA 0x00050000
+#define DENALI_PHY_1155_DATA 0x00000000
+#define DENALI_PHY_1156_DATA 0x00000000
+#define DENALI_PHY_1157_DATA 0x00000000
+#define DENALI_PHY_1158_DATA 0x00000100
+#define DENALI_PHY_1159_DATA 0x00000000
+#define DENALI_PHY_1160_DATA 0x00000000
+#define DENALI_PHY_1161_DATA 0x00506401
+#define DENALI_PHY_1162_DATA 0x01221102
+#define DENALI_PHY_1163_DATA 0x00000122
+#define DENALI_PHY_1164_DATA 0x00000000
+#define DENALI_PHY_1165_DATA 0x000B1F00
+#define DENALI_PHY_1166_DATA 0x0B1F0B1F
+#define DENALI_PHY_1167_DATA 0x0B1F0B1B
+#define DENALI_PHY_1168_DATA 0x0B1F0B1F
+#define DENALI_PHY_1169_DATA 0x0B1F0B1F
+#define DENALI_PHY_1170_DATA 0x00000B00
+#define DENALI_PHY_1171_DATA 0x42080010
+#define DENALI_PHY_1172_DATA 0x01000100
+#define DENALI_PHY_1173_DATA 0x01000100
+#define DENALI_PHY_1174_DATA 0x01000100
+#define DENALI_PHY_1175_DATA 0x01000100
+#define DENALI_PHY_1176_DATA 0x00000000
+#define DENALI_PHY_1177_DATA 0x00000000
+#define DENALI_PHY_1178_DATA 0x00000000
+#define DENALI_PHY_1179_DATA 0x00000000
+#define DENALI_PHY_1180_DATA 0x00000000
+#define DENALI_PHY_1181_DATA 0x00000803
+#define DENALI_PHY_1182_DATA 0x223FFF00
+#define DENALI_PHY_1183_DATA 0x000008FF
+#define DENALI_PHY_1184_DATA 0x0000057F
+#define DENALI_PHY_1185_DATA 0x0000057F
+#define DENALI_PHY_1186_DATA 0x00037FFF
+#define DENALI_PHY_1187_DATA 0x00037FFF
+#define DENALI_PHY_1188_DATA 0x00004410
+#define DENALI_PHY_1189_DATA 0x00004410
+#define DENALI_PHY_1190_DATA 0x00004410
+#define DENALI_PHY_1191_DATA 0x00004410
+#define DENALI_PHY_1192_DATA 0x00004410
+#define DENALI_PHY_1193_DATA 0x00037FFF
+#define DENALI_PHY_1194_DATA 0x00037FFF
+#define DENALI_PHY_1195_DATA 0x00000000
+#define DENALI_PHY_1196_DATA 0x00000000
+#define DENALI_PHY_1197_DATA 0x00000000
+#define DENALI_PHY_1198_DATA 0x04000000
+#define DENALI_PHY_1199_DATA 0x00000000
+#define DENALI_PHY_1200_DATA 0x00000000
+#define DENALI_PHY_1201_DATA 0x00000108
+#define DENALI_PHY_1202_DATA 0x00000000
+#define DENALI_PHY_1203_DATA 0x00000000
+#define DENALI_PHY_1204_DATA 0x00000000
+#define DENALI_PHY_1205_DATA 0x00000001
+#define DENALI_PHY_1206_DATA 0x00000000
+#define DENALI_PHY_1207_DATA 0x00000000
+#define DENALI_PHY_1208_DATA 0x00000000
+#define DENALI_PHY_1209_DATA 0x00000000
+#define DENALI_PHY_1210_DATA 0x00000000
+#define DENALI_PHY_1211_DATA 0x00000000
+#define DENALI_PHY_1212_DATA 0x00020100
+#define DENALI_PHY_1213_DATA 0x00000000
+#define DENALI_PHY_1214_DATA 0x00000000
diff --git a/board/sifive/fu540/ux00ddr.h b/board/sifive/fu540/ux00ddr.h
new file mode 100644
index 0000000000..6c18db251a
--- /dev/null
+++ b/board/sifive/fu540/ux00ddr.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#ifndef FU540_UX00DDR_H
+#define FU540_UX00DDR_H
+
+#define DRAM_CLASS_DDR4 0xA
+
+extern u32 ddr_phy_settings[1215];
+extern u32 ddr_ctl_settings[265];
+
+void ux00ddr_writeregmap(size_t ahbregaddr, const
+ u32 *ctlsettings, const u32 *physettings);
+
+void ux00ddr_disableaxireadinterleave(size_t ahbregaddr);
+
+void ux00ddr_disableoptimalrmodw(size_t ahbregaddr);
+
+void ux00ddr_enablewriteleveling(size_t ahbregaddr);
+
+void ux00ddr_enablereadleveling(size_t ahbregaddr);
+
+void ux00ddr_enablereadlevelinggate(size_t ahbregaddr);
+
+void ux00ddr_enablevreftraining(size_t ahbregaddr);
+
+u32 ux00ddr_getdramclass(size_t ahbregaddr);
+
+void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr);
+
+void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr);
+
+void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr);
+
+void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr);
+
+void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr);
+
+void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend);
+
+u64 ux00ddr_phy_fixup(size_t ahbregaddr);
+
+#endif /* FU540_UX00DDR_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 06/10] riscv: sifive: fu540: add SPL configuration
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (4 preceding siblings ...)
2020-01-24 5:50 ` [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-25 8:35 ` Anup Patel
2020-01-24 5:50 ` [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL Pragnesh Patel
` (3 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware
and U-Boot proper images from 1st partition of MMC boot devices.
SPL related code is leverage from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
board/sifive/fu540/Kconfig | 8 +
board/sifive/fu540/Makefile | 1 +
board/sifive/fu540/fu540-memory-map.h | 33 ++++
board/sifive/fu540/fu540.c | 24 +++
board/sifive/fu540/spl.c | 252 ++++++++++++++++++++++++++
board/sifive/fu540/ux00prci.h | 56 ++++++
include/configs/sifive-fu540.h | 18 ++
7 files changed, 392 insertions(+)
create mode 100644 board/sifive/fu540/fu540-memory-map.h
create mode 100644 board/sifive/fu540/spl.c
create mode 100644 board/sifive/fu540/ux00prci.h
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 5ca21474de..edb224ed7a 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
default "sifive-fu540"
config SYS_TEXT_BASE
+ default 0x80200000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x80200000 if RISCV_SMODE
+config SPL_TEXT_BASE
+ default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x80000000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
+ select SUPPORT_SPL
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index e4e76e1de3..cdcf894ade 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -5,5 +5,6 @@
obj-y += fu540.o
ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
obj-y += ddr.o
endif
diff --git a/board/sifive/fu540/fu540-memory-map.h b/board/sifive/fu540/fu540-memory-map.h
new file mode 100644
index 0000000000..c65203726b
--- /dev/null
+++ b/board/sifive/fu540/fu540-memory-map.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#ifndef FU540_MEMORY_MAP
+#define FU540_MEMORY_MAP
+
+#include <asm/arch/gpio.h>
+#include "ux00prci.h"
+
+/****************************************************************************
+ * Platform definitions
+ *****************************************************************************/
+
+/* Memory map */
+#define GPIO_CTRL_ADDR _AC(0x10060000, UL)
+
+#define PHYSICAL_FILTER_CTRL_ADDR _AC(0x100b8000, UL)
+
+#define UX00DDR_CTRL_ADDR _AC(0x100b0000, UL)
+#define UX00PRCI_CTRL_ADDR _AC(0x10000000, UL)
+
+/* Helper functions */
+#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
+
+#define UX00PRCI_REG(offset) \
+ _REG32(UX00PRCI_CTRL_ADDR, \
+ offset)
+
+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
+
+#endif /* FU540_MEMORY_MAP */
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 3a5e74f1fb..b81003aa6f 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -11,6 +11,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <misc.h>
+#include <spl.h>
/*
* This define is a value used for error/unknown serial.
@@ -114,3 +115,26 @@ int board_init(void)
return 0;
}
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+ u8 i;
+ u32 boot_devices[] = {
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ BOOT_DEVICE_MMC1,
+#endif
+ };
+
+ for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+ spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
new file mode 100644
index 0000000000..c7ae4aa292
--- /dev/null
+++ b/board/sifive/fu540/spl.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <misc.h>
+
+#include "ux00ddr.h"
+#include "fu540-memory-map.h"
+
+#define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL)
+#define DDRCTLPLL_F 55
+#define DDRCTLPLL_Q 2
+
+#define PHY_NRESET 0x1000
+
+static inline int ux00prci_select_corepll(volatile u32 *coreclkselreg,
+ volatile u32 *corepllcfg,
+ volatile u32 *corepllout,
+ u32 pllconfigval)
+{
+ (*corepllcfg) = pllconfigval;
+
+ // Wait for lock
+ while (((*corepllcfg) & (PLL_LOCK(1))) == 0)
+ ;
+
+ u32 core_out =
+ (PLLOUT_DIV(PLLOUT_DIV_default)) |
+ (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
+ (PLLOUT_CLK_EN(1));
+ (*corepllout) = core_out;
+
+ // Set CORECLKSELREG to select COREPLL
+ (*coreclkselreg) = PLL_CORECLKSEL_COREPLL;
+
+ return 0;
+}
+
+static inline int ux00prci_select_corepll_500mhz(volatile u32 *coreclkselreg,
+ volatile u32 *corepllcfg,
+ volatile u32 *corepllout)
+{
+ /*
+ * CORE pll init
+ * Set corepll 33MHz -> 1GHz
+ */
+
+ u32 core500mhz =
+ (PLL_R(0)) |
+ (PLL_F(59)) | // 4000MHz VCO
+ (PLL_Q(3)) | /* /8 Output divider */
+ (PLL_RANGE(0x4)) |
+ (PLL_BYPASS(0)) |
+ (PLL_FSE(1));
+
+ return ux00prci_select_corepll(coreclkselreg, corepllcfg, corepllout,
+ core500mhz);
+}
+
+static inline int ux00prci_select_corepll_1ghz(volatile u32 *coreclkselreg,
+ volatile u32 *corepllcfg,
+ volatile u32 *corepllout)
+{
+ /*
+ * CORE pll init
+ * Set corepll 33MHz -> 1GHz
+ */
+
+ u32 core1ghz =
+ (PLL_R(0)) |
+ (PLL_F(59)) | // 4000MHz VCO
+ (PLL_Q(2)) | /* /4 Output divider */
+ (PLL_RANGE(0x4)) |
+ (PLL_BYPASS(0)) |
+ (PLL_FSE(1));
+
+ return ux00prci_select_corepll(coreclkselreg, corepllcfg, corepllout,
+ core1ghz);
+}
+
+long nsec_per_cyc = 300; // 33.333MHz
+void nsleep(long nsec)
+{
+ long step = nsec_per_cyc * 2;
+
+ while (nsec > 0)
+ nsec -= step;
+}
+
+void init_clk_and_ddr(void)
+{
+ // PRCI init
+
+ // Check Reset Values (lock don't care)
+ u32 pll_default =
+ (PLL_R(PLL_R_default)) |
+ (PLL_F(PLL_F_default)) |
+ (PLL_Q(PLL_Q_default)) |
+ (PLL_RANGE(PLL_RANGE_default)) |
+ (PLL_BYPASS(PLL_BYPASS_default)) |
+ (PLL_FSE(PLL_FSE_default));
+ u32 lockmask = ~PLL_LOCK(1);
+ u32 pllout_default =
+ (PLLOUT_DIV(PLLOUT_DIV_default)) |
+ (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
+ (PLLOUT_CLK_EN(PLLOUT_CLK_EN_default));
+
+ if ((UX00PRCI_REG(UX00PRCI_COREPLLCFG) ^ pll_default) & lockmask)
+ return;
+ if ((UX00PRCI_REG(UX00PRCI_COREPLLOUT) ^ pllout_default))
+ return;
+ if ((UX00PRCI_REG(UX00PRCI_DDRPLLCFG) ^ pll_default) & lockmask)
+ return;
+ if ((UX00PRCI_REG(UX00PRCI_DDRPLLOUT) ^ pllout_default))
+ return;
+ if (((UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG)) ^ pll_default) & lockmask)
+ return;
+ if (((UX00PRCI_REG(UX00PRCI_GEMGXLPLLOUT)) ^ pllout_default))
+ return;
+
+ /* CORE pll init
+ * If tlclksel is set for 2:1 operation,
+ * Set corepll 33Mhz -> 1GHz
+ * Otherwise, set corepll 33MHz -> 500MHz.
+ */
+
+ if (UX00PRCI_REG(UX00PRCI_CLKMUXSTATUSREG) & CLKMUX_STATUS_TLCLKSEL) {
+ ux00prci_select_corepll_500mhz
+ (&UX00PRCI_REG(UX00PRCI_CORECLKSELREG),
+ &UX00PRCI_REG(UX00PRCI_COREPLLCFG),
+ &UX00PRCI_REG(UX00PRCI_COREPLLOUT));
+ } else {
+ ux00prci_select_corepll_1ghz
+ (&UX00PRCI_REG(UX00PRCI_CORECLKSELREG),
+ &UX00PRCI_REG(UX00PRCI_COREPLLCFG),
+ &UX00PRCI_REG(UX00PRCI_COREPLLOUT));
+ }
+
+ //DDR init
+ u32 ddrctlmhz =
+ (PLL_R(0)) |
+ (PLL_F(DDRCTLPLL_F)) |
+ (PLL_Q(DDRCTLPLL_Q)) |
+ (PLL_RANGE(0x4)) |
+ (PLL_BYPASS(0)) |
+ (PLL_FSE(1));
+ UX00PRCI_REG(UX00PRCI_DDRPLLCFG) = ddrctlmhz;
+
+ // Wait for lock
+ while ((UX00PRCI_REG(UX00PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0)
+ ;
+
+ u32 ddrctl_out =
+ (PLLOUT_DIV(PLLOUT_DIV_default)) |
+ (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
+ (PLLOUT_CLK_EN(1));
+ (UX00PRCI_REG(UX00PRCI_DDRPLLOUT)) = ddrctl_out;
+
+ //Release DDR reset.
+ UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |=
+ DEVICESRESET_DDR_CTRL_RST_N(1);
+
+ // HACK to get the '1 full controller clock cycle'.
+ asm volatile ("fence");
+ UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |= DEVICESRESET_DDR_AXI_RST_N(1)
+ | DEVICESRESET_DDR_AHB_RST_N(1) | DEVICESRESET_DDR_PHY_RST_N(1);
+ // HACK to get the '1 full controller clock cycle'.
+ asm volatile ("fence");
+
+ /* These take like 16 cycles to actually propagate. We can't go sending
+ * stuff before they come out of reset. So wait. (TODO: Add a register
+ * to read the current reset states, or DDR Control device?)
+ */
+ for (int i = 0; i < 256; i++)
+ asm volatile ("nop");
+
+ ux00ddr_writeregmap(UX00DDR_CTRL_ADDR, ddr_ctl_settings,
+ ddr_phy_settings);
+ ux00ddr_disableaxireadinterleave(UX00DDR_CTRL_ADDR);
+
+ ux00ddr_disableoptimalrmodw(UX00DDR_CTRL_ADDR);
+
+ ux00ddr_enablewriteleveling(UX00DDR_CTRL_ADDR);
+ ux00ddr_enablereadleveling(UX00DDR_CTRL_ADDR);
+ ux00ddr_enablereadlevelinggate(UX00DDR_CTRL_ADDR);
+ if (ux00ddr_getdramclass(UX00DDR_CTRL_ADDR) == DRAM_CLASS_DDR4)
+ ux00ddr_enablevreftraining(UX00DDR_CTRL_ADDR);
+ //mask off interrupts for leveling completion
+ ux00ddr_mask_leveling_completed_interrupt(UX00DDR_CTRL_ADDR);
+
+ ux00ddr_mask_mc_init_complete_interrupt(UX00DDR_CTRL_ADDR);
+ ux00ddr_mask_outofrange_interrupts(UX00DDR_CTRL_ADDR);
+ ux00ddr_setuprangeprotection(UX00DDR_CTRL_ADDR, DDR_SIZE);
+ ux00ddr_mask_port_command_error_interrupt(UX00DDR_CTRL_ADDR);
+
+ const u64 ddr_size = DDR_SIZE;
+ const u64 ddr_end = CONFIG_SYS_SDRAM_BASE + ddr_size;
+
+ ux00ddr_start(UX00DDR_CTRL_ADDR, PHYSICAL_FILTER_CTRL_ADDR, ddr_end);
+ ux00ddr_phy_fixup(UX00DDR_CTRL_ADDR);
+
+ //GEMGXL init
+ u32 gemgxl125mhz =
+ (PLL_R(0)) |
+ (PLL_F(59)) | //4000Mhz VCO
+ (PLL_Q(5)) | /* /32 */
+ (PLL_RANGE(0x4)) |
+ (PLL_BYPASS(0)) |
+ (PLL_FSE(1));
+ UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG) = gemgxl125mhz;
+
+ // Wait for lock
+ while ((UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG) & PLL_LOCK(1)) == 0)
+ ;
+
+ u32 gemgxlctl_out =
+ (PLLOUT_DIV(PLLOUT_DIV_default)) |
+ (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
+ (PLLOUT_CLK_EN(1));
+ UX00PRCI_REG(UX00PRCI_GEMGXLPLLOUT) = gemgxlctl_out;
+
+ //Release GEMGXL reset (set bit DEVICESRESET_GEMGXL to 1)
+ UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |= DEVICESRESET_GEMGXL_RST_N(1);
+
+ // VSC8541 PHY reset sequence; leave pull-down active for 2ms
+ nsleep(2000000);
+ // Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1
+ GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET;
+ GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET;
+ nsleep(100);
+
+ // Procmon => core clock
+ UX00PRCI_REG(UX00PRCI_PROCMONCFG) = 0x1 << 24;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ arch_cpu_init_dm();
+
+ init_clk_and_ddr();
+
+ preloader_console_init();
+}
diff --git a/board/sifive/fu540/ux00prci.h b/board/sifive/fu540/ux00prci.h
new file mode 100644
index 0000000000..90ca3cd258
--- /dev/null
+++ b/board/sifive/fu540/ux00prci.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#ifndef _SIFIVE_UX00PRCI_H
+#define _SIFIVE_UX00PRCI_H
+
+/* Register offsets */
+#define UX00PRCI_HFROSCCFG (0x0000)
+#define UX00PRCI_COREPLLCFG (0x0004)
+#define UX00PRCI_COREPLLOUT (0x0008)
+#define UX00PRCI_DDRPLLCFG (0x000C)
+#define UX00PRCI_DDRPLLOUT (0x0010)
+#define UX00PRCI_GEMGXLPLLCFG (0x001C)
+#define UX00PRCI_GEMGXLPLLOUT (0x0020)
+#define UX00PRCI_CORECLKSELREG (0x0024)
+#define UX00PRCI_DEVICESRESETREG (0x0028)
+#define UX00PRCI_CLKMUXSTATUSREG (0x002C)
+#define UX00PRCI_PROCMONCFG (0x00F0)
+
+#define PLL_R(x) (((x) & 0x3F) << 0)
+#define PLL_F(x) (((x) & 0x1FF) << 6)
+#define PLL_Q(x) (((x) & 0x7) << 15)
+#define PLL_RANGE(x) (((x) & 0x7) << 18)
+#define PLL_BYPASS(x) (((x) & 0x1) << 24)
+#define PLL_FSE(x) (((x) & 0x1) << 25)
+#define PLL_LOCK(x) (((x) & 0x1) << 31)
+
+#define PLLOUT_DIV(x) (((x) & 0x7F) << 0)
+#define PLLOUT_DIV_BY_1(x) (((x) & 0x1) << 8)
+#define PLLOUT_CLK_EN(x) (((x) & 0x1) << 31)
+
+#define PLL_R_default 0x1
+#define PLL_F_default 0x1F
+#define PLL_Q_default 0x3
+#define PLL_RANGE_default 0x0
+#define PLL_BYPASS_default 0x1
+#define PLL_FSE_default 0x1
+
+#define PLLOUT_DIV_default 0x0
+#define PLLOUT_DIV_BY_1_default 0x0
+#define PLLOUT_CLK_EN_default 0x0
+
+#define PLL_CORECLKSEL_HFXIN 0x1
+#define PLL_CORECLKSEL_COREPLL 0x0
+
+#define DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1) << 0)
+#define DEVICESRESET_DDR_AXI_RST_N(x) (((x) & 0x1) << 1)
+#define DEVICESRESET_DDR_AHB_RST_N(x) (((x) & 0x1) << 2)
+#define DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3)
+#define DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)
+
+#define CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
+
+#endif // _SIFIVE_UX00PRCI_H
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index 2756ed5a77..ef3ae9b650 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -11,6 +11,22 @@
#include <linux/sizes.h>
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE 0x00100000
+#define CONFIG_SPL_BSS_START_ADDR 0x85000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000
+
+#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif
+
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
@@ -24,6 +40,7 @@
/* Environment options */
+#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
@@ -43,5 +60,6 @@
#define CONFIG_PREBOOT \
"setenv fdt_addr ${fdtcontroladdr};" \
"fdt addr ${fdtcontroladdr};"
+#endif
#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (5 preceding siblings ...)
2020-01-24 5:50 ` [PATCH v3 06/10] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-24 6:50 ` Jagan Teki
2020-01-24 5:50 ` [PATCH v3 08/10] riscv: sifive: fu540: enable all cache ways from u-boot proper Pragnesh Patel
` (2 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
With sifive_fu540_spl_defconfig:
U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
image u-boot.itb from 1st partition of SD card (replace fw_payload.bin
with u-boot.itb) into RAM.
U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD
card irrespective of GUID
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
configs/sifive_fu540_spl_defconfig | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 configs/sifive_fu540_spl_defconfig
diff --git a/configs/sifive_fu540_spl_defconfig b/configs/sifive_fu540_spl_defconfig
new file mode 100644
index 0000000000..4053743f4c
--- /dev/null
+++ b/configs/sifive_fu540_spl_defconfig
@@ -0,0 +1,26 @@
+CONFIG_RISCV=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_SIFIVE_FU540=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_MISC=y
+CONFIG_EMEMORY_OTP=y
+CONFIG_MISC_INIT_R=y
+CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_OF_SEPARATE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_MTD=y
+CONFIG_SPL=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=1
+CONFIG_SPL_CLK=y
+CONFIG_SPL_PAYLOAD="u-boot.itb"
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 08/10] riscv: sifive: fu540: enable all cache ways from u-boot proper
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (6 preceding siblings ...)
2020-01-24 5:50 ` [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-25 8:36 ` Anup Patel
2020-01-24 5:50 ` [PATCH v3 09/10] sifive: fix palmer's email address and add sifive_fu540_spl_defconfig Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 10/10] doc: update FU540 RISC-V documentation Pragnesh Patel
9 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
This patch enables all cache ways from u-boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
board/sifive/fu540/Makefile | 1 +
board/sifive/fu540/cache.c | 30 ++++++++++++++++++++++++++++++
board/sifive/fu540/cache.h | 13 +++++++++++++
board/sifive/fu540/fu540.c | 6 ++++--
4 files changed, 48 insertions(+), 2 deletions(-)
create mode 100644 board/sifive/fu540/cache.c
create mode 100644 board/sifive/fu540/cache.h
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
index cdcf894ade..a79928a0bf 100644
--- a/board/sifive/fu540/Makefile
+++ b/board/sifive/fu540/Makefile
@@ -3,6 +3,7 @@
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
+obj-y += cache.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
new file mode 100644
index 0000000000..c91728a678
--- /dev/null
+++ b/board/sifive/fu540/cache.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+#include <stdint.h>
+#include <linux/types.h>
+
+/* Register offsets */
+#define CACHE_ENABLE 0x008
+
+/* Block memory access until operation completed */
+static void cache_barrier_0(void)
+{
+ asm volatile("fence rw, io" : : : "memory");
+}
+
+static void cache_barrier_1(void)
+{
+ asm volatile("fence io, rw" : : : "memory");
+}
+
+/* Enable ways; allow cache to use these ways */
+void cache_enable_ways(u64 base_addr, u8 value)
+{
+ volatile u32 *enable = (volatile u32 *)(base_addr +
+ CACHE_ENABLE);
+ cache_barrier_0();
+ (*enable) = value;
+ cache_barrier_1();
+}
diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
new file mode 100644
index 0000000000..425124a23b
--- /dev/null
+++ b/board/sifive/fu540/cache.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ */
+
+#ifndef FU540_CACHE_H
+#define FU540_CACHE_H
+
+#define CACHE_CTRL_ADDR _AC(0x2010000, UL)
+
+void cache_enable_ways(u64 base_addr, u8 value);
+
+#endif /* FU540_CACHE_H */
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index b81003aa6f..7fde881e72 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -13,6 +13,8 @@
#include <misc.h>
#include <spl.h>
+#include "cache.h"
+
/*
* This define is a value used for error/unknown serial.
* If we really care about distinguishing errors and 0 is
@@ -111,8 +113,8 @@ int misc_init_r(void)
int board_init(void)
{
- /* For now nothing to do here. */
-
+ /* enable all cache ways */
+ cache_enable_ways(CACHE_CTRL_ADDR, 15);
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 09/10] sifive: fix palmer's email address and add sifive_fu540_spl_defconfig
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (7 preceding siblings ...)
2020-01-24 5:50 ` [PATCH v3 08/10] riscv: sifive: fu540: enable all cache ways from u-boot proper Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
2020-01-25 8:37 ` Anup Patel
2020-01-24 5:50 ` [PATCH v3 10/10] doc: update FU540 RISC-V documentation Pragnesh Patel
9 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
Fix Palmer's email address and add sifive_fu540_spl_defconfig
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
board/sifive/fu540/MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
index 702d803ad8..909a1bf300 100644
--- a/board/sifive/fu540/MAINTAINERS
+++ b/board/sifive/fu540/MAINTAINERS
@@ -1,9 +1,10 @@
SiFive FU540 BOARD
M: Paul Walmsley <paul.walmsley@sifive.com>
-M: Palmer Dabbelt <palmer@sifive.com>
+M: Palmer Dabbelt <palmerdabbelt@google.com>
M: Anup Patel <anup.patel@wdc.com>
M: Atish Patra <atish.patra@wdc.com>
S: Maintained
F: board/sifive/fu540/
F: include/configs/sifive-fu540.h
F: configs/sifive_fu540_defconfig
+F: configs/sifive_fu540_spl_defconfig
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 10/10] doc: update FU540 RISC-V documentation
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
` (8 preceding siblings ...)
2020-01-24 5:50 ` [PATCH v3 09/10] sifive: fix palmer's email address and add sifive_fu540_spl_defconfig Pragnesh Patel
@ 2020-01-24 5:50 ` Pragnesh Patel
9 siblings, 0 replies; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 5:50 UTC (permalink / raw)
To: u-boot
Add descriptions about U-Boot SPL feature and how to build and run.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
doc/board/sifive/fu540.rst | 376 +++++++++++++++++++++++++++++++++++++
1 file changed, 376 insertions(+)
diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
index 3937222c6c..b75b3c80af 100644
--- a/doc/board/sifive/fu540.rst
+++ b/doc/board/sifive/fu540.rst
@@ -363,3 +363,379 @@ load uImage.
Please press Enter to activate this console.
/ #
+
+
+How to build U-Boot SPL
+-----------------------
+
+Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be
+cloned and build for FU540 as below:
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=sifive/fu540
+
+Copy OpenSBI FW_DYNAMIC image (build/platform/sifive/fu540/firmware/fw_dynamic.bin)
+into U-Boot root directory
+
+
+How to build U-Boot SPL booting from MMC
+----------------------------------------
+
+With sifive_fu540_spl_defconfig:
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation enviornment variable:
+
+.. code-block:: none
+
+ export ARCH=riscv
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+3. make sifive_fu540_spl_defconfig
+4. make
+
+
+Flashing
+--------
+
+ZSBL loads the U-boot SPL(u-boot-spl.bin) from a partition with
+GUID type 2e54b353-1271-4842-806f-e436d6af6985
+
+U-boot SPL expects a u-boot FIT image(u-boot.itb) from 1st partition(/dev/sdc1)
+of SD card irrespective of GUID
+
+FIT image(u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob(hifive-unleashed-a00.dtb)
+
+.. code-block:: none
+
+ sudo dd if=spl/u-boot-spl.bin of=/dev/disk2s4 bs=1024
+ sudo dd if=u-boot.itb of=/dev/disk2s1 bs=1024
+
+
+Running U-Boot SPL
+------------------
+
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+The U-Boot SPL will boot in M mode and load the FIT image which include
+OpenSBI and U-Boot proper images. After loading progress, it will jump
+to OpenSBI first and then U-Boot proper which will run in S mode.
+
+
+Sample boot log from HiFive Unleashed board
+-------------------------------------------
+
+.. code-block:: none
+
+ U-Boot SPL 2020.01-00176-g095f705725-dirty (Jan 22 2020 - 12:53:16 +0530)
+ Trying to boot from MMC1
+
+
+ U-Boot 2020.01-00176-g095f705725-dirty (Jan 22 2020 - 12:53:16 +0530)
+
+ CPU: rv64imafdc
+ Model: SiFive HiFive Unleashed A00
+ DRAM: 8 GiB
+ MMC: spi at 10050000:mmc at 0: 0
+ In: serial at 10010000
+ Out: serial at 10010000
+ Err: serial at 10010000
+ Board serial number should not be 0 !!
+ Net:
+ Warning: ethernet at 10090000 (eth0) using random MAC address - ce:dc:0d:a4:e4:76
+ eth0: ethernet at 10090000
+ Hit any key to stop autoboot: 0
+ => version
+ U-Boot 2020.01-00176-g095f705725-dirty (Jan 22 2020 - 12:53:16 +0530)
+
+ riscv64-unknown-linux-gnu-gcc (crosstool-NG 1.24.0.37-3f461da) 9.2.0
+ GNU ld (crosstool-NG 1.24.0.37-3f461da) 2.32
+ => mmc info
+ Device: spi at 10050000:mmc at 0
+ Manufacturer ID: 3
+ OEM: 5344
+ Name: SC16G
+ Bus Speed: 20000000
+ Mode: SD Legacy
+ Rd Block Len: 512
+ SD version 2.0
+ High Capacity: Yes
+ Capacity: 14.8 GiB
+ Bus Width: 1-bit
+ Erase Group Size: 512 Bytes
+ => mmc part
+
+ Partition Map for MMC device 0 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00000800 0x000107ff "SiFive bare-metal (or stage 2 loader"
+ attrs: 0x0000000000000000
+ type: 2e54b353-1271-4842-806f-e436d6af6985
+ guid: 3c9eabe1-b16b-4a2e-9b4e-f065c740bb86
+ 2 0x00040800 0x00ecdfde "Linux filesystem"
+ attrs: 0x0000000000000000
+ type: 0fc63daf-8483-4772-8e79-3d69d8477de4
+ guid: ad9309ff-d204-42f0-9f99-f3275a83f565
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage.
+
+.. code-block:: none
+
+ => setenv serverip 172.16.35.74
+ => setenv ipaddr 172.16.35.40
+ => tftpboot 0x83000000 fit.itb
+ ethernet at 10090000: PHY present at 0
+ ethernet at 10090000: Starting autonegotiation...
+ ethernet at 10090000: Autonegotiation complete
+ ethernet at 10090000: link up, 100Mbps full-duplex (lpa: 0x41e1)
+ Using ethernet at 10090000 device
+ TFTP from server 172.16.35.74; our IP address is 172.16.35.40
+ Filename 'fit.itb'.
+ Load address: 0x83000000
+ Loading: #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ ###################################
+ 945.3 KiB/s
+ done
+ Bytes transferred = 13823823 (d2ef4f hex)
+ => bootm 0x83000000
+ ## Loading kernel from FIT Image at 83000000 ...
+ Using 'config-1' configuration
+ Trying 'kernel at 1' kernel subimage
+ Description: Linux kernel
+ Type: Kernel Image
+ Compression: uncompressed
+ Data Start: 0x830000d8
+ Data Size: 9247260 Bytes = 8.8 MiB
+ Architecture: RISC-V
+ OS: Linux
+ Load Address: 0x80200000
+ Entry Point: 0x80200000
+ Verifying Hash Integrity ... OK
+ ## Loading ramdisk from FIT Image at 83000000 ...
+ Using 'config-1' configuration
+ Trying 'ramdisk at 1' ramdisk subimage
+ Description: ramdisk
+ Type: RAMDisk Image
+ Compression: gzip compressed
+ Data Start: 0x838d3378
+ Data Size: 4568674 Bytes = 4.4 MiB
+ Architecture: RISC-V
+ OS: Linux
+ Load Address: 0x82000000
+ Entry Point: unavailable
+ Verifying Hash Integrity ... OK
+ Loading ramdisk from 0x838d3378 to 0x82000000
+ WARNING: 'compression' nodes for ramdisks are deprecated, please fix your .its file!
+ ## Loading fdt from FIT Image at 83000000 ...
+ Using 'config-1' configuration
+ Trying 'fdt at 1' fdt subimage
+ Description: unavailable
+ Type: Flat Device Tree
+ Compression: uncompressed
+ Data Start: 0x838d1b80
+ Data Size: 6023 Bytes = 5.9 KiB
+ Architecture: RISC-V
+ Verifying Hash Integrity ... OK
+ Booting using the fdt blob at 0x838d1b80
+ Loading Kernel Image
+ Using Device Tree in place at 00000000838d1b80, end 00000000838d6306
+
+ Starting kernel ...
+
+ [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+ [ 0.000000] Linux version 5.3.0-13236-g97f9a3c4eee5 (pragneshp at sachinj2-OptiPlex-7010) (gcc version 8.2.0 (Buildroot 2018.11-rc2-00003-ga0787e9
+ [ 0.000000] earlycon: sifive0 at MMIO 0x0000000010010000 (options '')
+ [ 0.000000] printk: bootconsole [sifive0] enabled
+ [ 0.000000] Initial ramdisk at: 0x(____ptrval____) (4568674 bytes)
+ [ 0.000000] Zone ranges:
+ [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000ffffffff]
+ [ 0.000000] Normal [mem 0x0000000100000000-0x000000027fffffff]
+ [ 0.000000] Movable zone start for each node
+ [ 0.000000] Early memory node ranges
+ [ 0.000000] node 0: [mem 0x0000000080200000-0x000000027fffffff]
+ [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
+ [ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] elf_hwcap is 0x112d
+ [ 0.000000] percpu: Embedded 17 pages/cpu s30680 r8192 d30760 u69632
+ [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2067975
+ [ 0.000000] Kernel command line: earlycon=sifive,0x10010000 console=ttySIF0,115200
+ [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
+ [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
+ [ 0.000000] Sorting __ex_table...
+ [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+ [ 0.000000] Memory: 8179828K/8386560K available (6081K kernel code, 388K rwdata, 2025K rodata, 209K init, 307K bss, 206732K reserved, 0K cma-r)
+ [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+ [ 0.000000] rcu: Hierarchical RCU implementation.
+ [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+ [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+ [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+ [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+ [ 0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
+ [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [2]
+ [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
+ [ 0.000007] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+ [ 0.008471] Console: colour dummy device 80x25
+ [ 0.012818] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
+ [ 0.022844] pid_max: default: 32768 minimum: 301
+ [ 0.027915] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+ [ 0.035332] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+ [ 0.044789] rcu: Hierarchical SRCU implementation.
+ [ 0.049254] smp: Bringing up secondary CPUs ...
+ [ 0.055035] smp: Brought up 1 node, 4 CPUs
+ [ 0.059670] devtmpfs: initialized
+ [ 0.063825] random: get_random_u32 called from bucket_table_alloc.isra.29+0x4e/0x160 with crng_init=0
+ [ 0.072594] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+ [ 0.082007] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+ [ 0.089521] NET: Registered protocol family 16
+ [ 0.105923] vgaarb: loaded
+ [ 0.108174] SCSI subsystem initialized
+ [ 0.111961] usbcore: registered new interface driver usbfs
+ [ 0.117115] usbcore: registered new interface driver hub
+ [ 0.122495] usbcore: registered new device driver usb
+ [ 0.128086] clocksource: Switched to clocksource riscv_clocksource
+ [ 0.140287] NET: Registered protocol family 2
+ [ 0.144459] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
+ [ 0.152630] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
+ [ 0.162249] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
+ [ 0.172168] TCP: Hash tables configured (established 65536 bind 65536)
+ [ 0.178352] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
+ [ 0.185149] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
+ [ 0.192564] NET: Registered protocol family 1
+ [ 0.196791] RPC: Registered named UNIX socket transport module.
+ [ 0.202160] RPC: Registered udp transport module.
+ [ 0.206844] RPC: Registered tcp transport module.
+ [ 0.211519] RPC: Registered tcp NFSv4.1 backchannel transport module.
+ [ 0.217949] PCI: CLS 0 bytes, default 64
+ [ 0.222148] Unpacking initramfs...
+ [ 0.578819] Freeing initrd memory: 4460K
+ [ 0.582990] workingset: timestamp_bits=62 max_order=21 bucket_order=0
+ [ 0.596656] NFS: Registering the id_resolver key type
+ [ 0.600959] Key type id_resolver registered
+ [ 0.605146] Key type id_legacy registered
+ [ 0.609102] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+ [ 0.615940] 9p: Installing v9fs 9p2000 file system support
+ [ 0.621590] NET: Registered protocol family 38
+ [ 0.625711] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
+ [ 0.633062] io scheduler mq-deadline registered
+ [ 0.637570] io scheduler kyber registered
+ [ 0.685604] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+ [ 0.692195] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 4, base_baud = 0) is a SiFive UART v0
+ [ 0.700577] printk: console [ttySIF0] enabled
+ [ 0.700577] printk: console [ttySIF0] enabled
+ [ 0.709239] printk: bootconsole [sifive0] disabled
+ [ 0.709239] printk: bootconsole [sifive0] disabled
+ [ 0.719032] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 1, base_baud = 0) is a SiFive UART v0
+ [ 0.728378] [drm] radeon kernel modesetting enabled.
+ [ 0.745305] loop: module loaded
+ [ 0.748219] sifive_spi 10040000.spi: mapped; irq=3, cs=1
+ [ 0.753503] sifive_spi 10050000.spi: mapped; irq=5, cs=1
+ [ 0.758827] libphy: Fixed MDIO Bus: probed
+ [ 0.762901] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
+ [ 0.769657] macb: GEM doesn't support hardware ptp.
+ [ 0.774546] libphy: MACB_mii_bus: probed
+ [ 0.940370] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.et)
+ [ 0.954914] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 6 (ce:dc:0d:a4:e4:76)
+ [ 0.964717] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
+ [ 0.970437] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+ [ 0.976429] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+ [ 0.982853] ehci-pci: EHCI PCI platform driver
+ [ 0.987310] ehci-platform: EHCI generic platform driver
+ [ 0.992568] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+ [ 0.998668] ohci-pci: OHCI PCI platform driver
+ [ 1.003113] ohci-platform: OHCI generic platform driver
+ [ 1.008577] usbcore: registered new interface driver uas
+ [ 1.013639] usbcore: registered new interface driver usb-storage
+ [ 1.019716] mousedev: PS/2 mouse device common for all mice
+ [ 1.050586] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
+ [ 1.057730] usbcore: registered new interface driver usbhid
+ [ 1.063114] usbhid: USB HID core driver
+ [ 1.067825] NET: Registered protocol family 10
+ [ 1.072448] Segment Routing with IPv6
+ [ 1.075394] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+ [ 1.081770] NET: Registered protocol family 17
+ [ 1.085893] 9pnet: Installing 9P2000 support
+ [ 1.089981] Key type dns_resolver registered
+ [ 1.096414] Freeing unused kernel memory: 208K
+ [ 1.100094] This architecture does not have kernel memory protection.
+ [ 1.106509] Run /init as init process
+ Starting syslogd: OK
+ Starting klogd: OK
+ Starting mdev...
+ /etc/init.d/S10mdev: line 9: can't create /proc/sys/kernel/hotplug: nonexistent directory
+ [ 1.168422] mmc0: host does not support reading read-only switch, assuming write-enable
+ [ 1.175673] mmc0: new SDHC card on SPI
+ [ 1.180707] mmcblk0: mmc0:0000 SC16G 14.8 GiB
+ [ 1.215845] mmcblk0: p1 p2 p4
+ modprobe: can't change directory to '/lib/modules': No such file or directory
+ Initializing random number generator... [ 1.655294] random: dd: uninitialized urandom read (512 bytes read)
+ done.
+ Starting network: udhcpc: started, v1.29.3
+ udhcpc: sending discover
+ [ 3.724714] macb 10090000.ethernet eth0: link up (100/Full)
+ [ 3.729531] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
+ udhcpc: sending discover
+ udhcpc: sending select for 172.16.35.100
+ udhcpc: sending select for 172.16.35.100
+ udhcpc: sending select for 172.16.35.100
+ udhcpc: lease of 172.16.35.100 obtained, lease time 28800
+ deleting routers
+ adding dns 172.16.34.150
+ adding dns 172.16.24.25
+ OK
+ Starting dropbear sshd: [ 10.289079] random: dropbear: uninitialized urandom read (32 bytes read)
+ OK
+
+ Welcome to Buildroot
+ buildroot login: root
+ Password:
+ #
--
2.17.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI
2020-01-24 5:50 ` [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
@ 2020-01-24 6:27 ` Jagan Teki
2020-01-24 8:06 ` Pragnesh Patel
0 siblings, 1 reply; 32+ messages in thread
From: Jagan Teki @ 2020-01-24 6:27 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> When build U-boot SPL, meet an issue of undefined reference to
> 'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
> CONFIG_MMC_SPI selected.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
> ---
> lib/Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/lib/Makefile b/lib/Makefile
> index 51eba80b89..d21e0a6b3a 100644
> --- a/lib/Makefile
> +++ b/lib/Makefile
> @@ -78,6 +78,7 @@ endif
>
> ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
> +obj-$(CONFIG_MMC_SPI) += crc7.o
It is invalid to mark crc7 to MMC_SPI, try to add Kconfig option for
CRC7. like this.
https://paste.ubuntu.com/p/kSnkDWpTgS/
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 01/10] misc: add driver for the Sifive otp controller
2020-01-24 5:50 ` [PATCH v3 01/10] misc: add driver for the Sifive otp controller Pragnesh Patel
@ 2020-01-24 6:41 ` Jagan Teki
2020-01-27 10:18 ` Pragnesh Patel
0 siblings, 1 reply; 32+ messages in thread
From: Jagan Teki @ 2020-01-24 6:41 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> Added a misc driver to handle OTP memory in FU540.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 13 ++
> .../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
> board/sifive/fu540/fu540.c | 113 ++++------
> configs/sifive_fu540_defconfig | 2 +
> drivers/misc/Kconfig | 7 +
> drivers/misc/Makefile | 1 +
> drivers/misc/ememory-otp.c | 207 ++++++++++++++++++
This patch need to break into
1. add sifive otp driver
2. enable the otp driver - board, dts, defconfig changes.
> 7 files changed, 276 insertions(+), 73 deletions(-)
> create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
> create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> create mode 100644 drivers/misc/ememory-otp.c
>
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> new file mode 100644
> index 0000000000..615a68c0e9
> --- /dev/null
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2019 SiFive, Inc
> + */
> +
> +/ {
> + soc {
> + otp: otp at 10070000 {
> + compatible = "sifive,fu540-otp";
> + reg = <0x0 0x10070000 0x0 0x0FFF>;
> + };
> + };
> +};
> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> new file mode 100644
> index 0000000000..bec0d19134
> --- /dev/null
> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 SiFive, Inc
> + */
> +
> +#include "fu540-c000-u-boot.dtsi"
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index 47a2090251..3a5e74f1fb 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -10,94 +10,61 @@
> #include <dm.h>
> #include <linux/delay.h>
> #include <linux/io.h>
> +#include <misc.h>
>
> -#ifdef CONFIG_MISC_INIT_R
> -
> -#define FU540_OTP_BASE_ADDR 0x10070000
> -
> -struct fu540_otp_regs {
> - u32 pa; /* Address input */
> - u32 paio; /* Program address input */
> - u32 pas; /* Program redundancy cell selection input */
> - u32 pce; /* OTP Macro enable input */
> - u32 pclk; /* Clock input */
> - u32 pdin; /* Write data input */
> - u32 pdout; /* Read data output */
> - u32 pdstb; /* Deep standby mode enable input (active low) */
> - u32 pprog; /* Program mode enable input */
> - u32 ptc; /* Test column enable input */
> - u32 ptm; /* Test mode enable input */
> - u32 ptm_rep;/* Repair function test mode enable input */
> - u32 ptr; /* Test row enable input */
> - u32 ptrim; /* Repair function enable input */
> - u32 pwe; /* Write enable input (defines program cycle) */
> -} __packed;
> -
> -#define BYTES_PER_FUSE 4
> -#define NUM_FUSES 0x1000
> -
> -static int fu540_otp_read(int offset, void *buf, int size)
> -{
> - struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
> - unsigned int i;
> - int fuseidx = offset / BYTES_PER_FUSE;
> - int fusecount = size / BYTES_PER_FUSE;
> - u32 fusebuf[fusecount];
> -
> - /* check bounds */
> - if (offset < 0 || size < 0)
> - return -EINVAL;
> - if (fuseidx >= NUM_FUSES)
> - return -EINVAL;
> - if ((fuseidx + fusecount) > NUM_FUSES)
> - return -EINVAL;
> -
> - /* init OTP */
> - writel(0x01, ®s->pdstb); /* wake up from stand-by */
> - writel(0x01, ®s->ptrim); /* enable repair function */
> - writel(0x01, ®s->pce); /* enable input */
> -
> - /* read all requested fuses */
> - for (i = 0; i < fusecount; i++, fuseidx++) {
> - writel(fuseidx, ®s->pa);
> -
> - /* cycle clock to read */
> - writel(0x01, ®s->pclk);
> - mdelay(1);
> - writel(0x00, ®s->pclk);
> - mdelay(1);
> -
> - /* read the value */
> - fusebuf[i] = readl(®s->pdout);
> - }
> -
> - /* shut down */
> - writel(0, ®s->pce);
> - writel(0, ®s->ptrim);
> - writel(0, ®s->pdstb);
> -
> - /* copy out */
> - memcpy(buf, fusebuf, size);
> +/*
> + * This define is a value used for error/unknown serial.
> + * If we really care about distinguishing errors and 0 is
> + * valid, we'll need a different one.
> + */
> +#define ERROR_READING_SERIAL_NUMBER 0
>
> - return 0;
> -}
> +#ifdef CONFIG_MISC_INIT_R
>
> -static u32 fu540_read_serialnum(void)
> +#if CONFIG_IS_ENABLED(EMEMORY_OTP)
> +static u32 otp_read_serialnum(struct udevice *dev)
> {
> int ret;
> u32 serial[2] = {0};
>
> for (int i = 0xfe * 4; i > 0; i -= 8) {
> - ret = fu540_otp_read(i, serial, sizeof(serial));
> + ret = misc_read(dev, i, serial, sizeof(serial));
> +
> if (ret) {
> - printf("%s: error reading from OTP\n", __func__);
> + printf("%s: error reading serial from OTP\n", __func__);
> break;
> }
> +
> if (serial[0] == ~serial[1])
> return serial[0];
> }
>
> - return 0;
> + return ERROR_READING_SERIAL_NUMBER;
> +}
> +#endif
> +
> +static u32 fu540_read_serialnum(void)
> +{
> + u32 serial = ERROR_READING_SERIAL_NUMBER;
> +
> +#if CONFIG_IS_ENABLED(EMEMORY_OTP)
> + struct udevice *dev;
> + int ret;
> +
> + // init OTP
> + ret = uclass_get_device_by_driver(UCLASS_MISC,
> + DM_GET_DRIVER(hifive_otp), &dev);
> +
> + if (ret) {
> + debug("%s: could not find otp device\n", __func__);
> + return serial;
> + }
> +
> + // read serial from OTP and set env var
> + serial = otp_read_serialnum(dev);
> +#endif
> +
> + return serial;
> }
>
> static void fu540_setup_macaddr(u32 serialnum)
> diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
> index 6d61e6c960..40e78f12a2 100644
> --- a/configs/sifive_fu540_defconfig
> +++ b/configs/sifive_fu540_defconfig
> @@ -6,6 +6,8 @@ CONFIG_ARCH_RV64I=y
> CONFIG_RISCV_SMODE=y
> CONFIG_DISTRO_DEFAULTS=y
> CONFIG_FIT=y
> +CONFIG_MISC=y
> +CONFIG_EMEMORY_OTP=y
Look like this opt is needed global to SiFive, If so select MISC in
arch Kconfig.
> CONFIG_MISC_INIT_R=y
> CONFIG_DISPLAY_CPUINFO=y
> CONFIG_DISPLAY_BOARDINFO=y
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index f18aa8f7ba..cbda0deb14 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -68,6 +68,13 @@ config ROCKCHIP_OTP
> addressing and a length or through child-nodes that are generated
> based on the e-fuse map retrieved from the DTS.
>
> +config EMEMORY_OTP
What about SIFIVE_OTP or SIFIVE_EMEM_OTP or similar?
> + bool "Sifive Ememory OTP driver"
> + depends on RISCV && MISC
> + help
> + Enable support for reading the Ememory OTP on the HiFive Unleashed
> + OTP storage.
> +
> config VEXPRESS_CONFIG
> bool "Enable support for Arm Versatile Express config bus"
> depends on MISC
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index 2b843de93c..dcf9b628c8 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
> obj-$(CONFIG_QFW) += qfw.o
> obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
> obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
> +obj-$(CONFIG_EMEMORY_OTP) += ememory-otp.o
> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
> obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
> diff --git a/drivers/misc/ememory-otp.c b/drivers/misc/ememory-otp.c
> new file mode 100644
> index 0000000000..73e7af496a
> --- /dev/null
> +++ b/drivers/misc/ememory-otp.c
Again file name, would have platform or soc naming convention.
> @@ -0,0 +1,207 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
> + * One-Time-Programmable (OTP) memory used within the SiFive FU540.
> + * It is documented in the FU540 manual here:
> + * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
> + *
> + * Copyright (C) 2018 Philipp Hug <philipp@hug.cx>
> + * Copyright (C) 2018 Joey Hewitt <joey@joeyhewitt.com>
> + *
> + * Copyright (C) 2020 SiFive, Inc
> + */
> +
> +/*
> + * The FU540 stores 4096x32 bit (16KiB) values.
> + * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
> + */
Sorry, I didn't understand this comments. If it is memory map detail
that occupy otp, try to elaborate more by giving full details. Would
helpful to understand anyone in future.
> +
> +#include <common.h>
> +#include <dm/device.h>
> +#include <dm/read.h>
> +#include <linux/io.h>
> +#include <misc.h>
> +
> +struct hifive_otp_regs {
> + u32 pa; /* Address input */
> + u32 paio; /* Program address input */
> + u32 pas; /* Program redundancy cell selection input */
> + u32 pce; /* OTP Macro enable input */
> + u32 pclk; /* Clock input */
> + u32 pdin; /* Write data input */
> + u32 pdout; /* Read data output */
> + u32 pdstb; /* Deep standby mode enable input (active low) */
> + u32 pprog; /* Program mode enable input */
> + u32 ptc; /* Test column enable input */
> + u32 ptm; /* Test mode enable input */
> + u32 ptm_rep;/* Repair function test mode enable input */
> + u32 ptr; /* Test row enable input */
> + u32 ptrim; /* Repair function enable input */
> + u32 pwe; /* Write enable input (defines program cycle) */
> +} __packed;
> +
> +struct hifive_otp_platdata {
hifive here represent the board name, butter use soc name that has this otp.
> + struct hifive_otp_regs __iomem *regs;
> +};
> +
> +typedef u32 fuse_value_t;
No typdef please.
No global variables(unless it really need)
> +#define BYTES_PER_FUSE 4
> +
> +#define NUM_FUSES 0x1000
May be use dt properties.
> +
> +/*
> + * offset and size are assumed aligned to the size of the fuses (32bit).
> + */
> +static int hifive_otp_read(struct udevice *dev, int offset,
> + void *buf, int size)
> +{
> + struct hifive_otp_platdata *plat = dev_get_platdata(dev);
> + struct hifive_otp_regs *regs = (struct hifive_otp_regs *)plat->regs;
> +
> + int fuseidx = offset / BYTES_PER_FUSE;
> + int fusecount = size / BYTES_PER_FUSE;
> + fuse_value_t fusebuf[fusecount];
> +
> + // check bounds
use proper comment style.
> + if (offset < 0 || size < 0)
> + return -EINVAL;
> + if (fuseidx >= NUM_FUSES)
> + return -EINVAL;
> + if ((fuseidx + fusecount) > NUM_FUSES)
> + return -EINVAL;
> +
> + // init OTP
> + iowrite32(0x01, ®s->pdstb); // wake up from stand-by
> + iowrite32(0x01, ®s->ptrim); // enable repair function
> + iowrite32(0x01, ®s->pce); // enable input
use macros with proper bit names, like 0x01 would have proper macro.
> +
> + // read all requested fuses
> + for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
> + iowrite32(fuseidx, ®s->pa);
> +
> + // cycle clock to read
> + iowrite32(0x01, ®s->pclk);
> + mdelay(1);
> + iowrite32(0x00, ®s->pclk);
> + mdelay(1);
> +
> + // read the value
> + fusebuf[i] = ioread32(®s->pdout);
> + }
> +
> + // shut down
> + iowrite32(0, ®s->pce);
> + iowrite32(0, ®s->ptrim);
> + iowrite32(0, ®s->pdstb);
> +
> + // copy out
> + memcpy(buf, fusebuf, size);
> +
> + return 0;
> +}
> +
> +/*
> + * Caution:
> + * OTP can be write only once, so use carefully.
can be written
> + *
> + * offset and size are assumed aligned to the size of the fuses (32bit).
> + */
> +static int hifive_otp_write(struct udevice *dev, int offset,
> + const void *buf, int size)
> +{
> + struct hifive_otp_platdata *plat = dev_get_platdata(dev);
> + struct hifive_otp_regs *regs = (struct hifive_otp_regs *)plat->regs;
> +
> + int fuseidx = offset / BYTES_PER_FUSE;
> + int fusecount = size / BYTES_PER_FUSE;
> + u32 *write_buf = (u32 *)buf;
> + u32 write_data;
> + int i, pas, bit;
> +
> + // check bounds
> + if (offset < 0 || size < 0)
> + return -EINVAL;
> + if (fuseidx >= NUM_FUSES)
> + return -EINVAL;
> + if ((fuseidx + fusecount) > NUM_FUSES)
> + return -EINVAL;
We have lib functions to do this bound, would you please try to use that.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 02/10] riscv: Add _image_binary_end for SPL
2020-01-24 5:50 ` [PATCH v3 02/10] riscv: Add _image_binary_end for SPL Pragnesh Patel
@ 2020-01-24 6:44 ` Jagan Teki
0 siblings, 0 replies; 32+ messages in thread
From: Jagan Teki @ 2020-01-24 6:44 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/cpu/u-boot-spl.lds | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
> index 955dd3106d..d0495ce248 100644
> --- a/arch/riscv/cpu/u-boot-spl.lds
> +++ b/arch/riscv/cpu/u-boot-spl.lds
> @@ -72,6 +72,7 @@ SECTIONS
> . = ALIGN(4);
>
> _end = .;
> + _image_binary_end = .;
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
2020-01-24 5:50 ` [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL Pragnesh Patel
@ 2020-01-24 6:50 ` Jagan Teki
2020-01-25 8:41 ` Anup Patel
2020-01-27 6:50 ` Pragnesh Patel
0 siblings, 2 replies; 32+ messages in thread
From: Jagan Teki @ 2020-01-24 6:50 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> With sifive_fu540_spl_defconfig:
>
> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
> image u-boot.itb from 1st partition of SD card (replace fw_payload.bin
> with u-boot.itb) into RAM.
>
> U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD
> card irrespective of GUID
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
I'm thinking we don't need any separate config for SPL. Say if we have
single config that creates both SPL and U-Boot proper and give
feasibility to the user to use
1) SPL + U-Boot proper
2) SiFive SPL + U-Boot proper
We are using a similar approach for other platforms, I guess the same
will valid here, any comments?
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI
2020-01-24 6:27 ` Jagan Teki
@ 2020-01-24 8:06 ` Pragnesh Patel
2020-01-27 7:58 ` Jagan Teki
0 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-24 8:06 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 24 January 2020 11:58
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
>Kadam <sagar.kadam@sifive.com>; Simon Glass <sjg@chromium.org>;
>AKASHI Takahiro <takahiro.akashi@linaro.org>; Marek Behún
><marek.behun@nic.cz>; Philippe Reynes <philippe.reynes@softathome.com>;
>Alexander Graf <agraf@csgraf.de>; Peng Fan <peng.fan@nxp.com>
>Subject: Re: [PATCH v3 03/10] lib: Makefile: build crc7.c when
>CONFIG_MMC_SPI
>
>On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> When build U-boot SPL, meet an issue of undefined reference to 'crc7'
>> for drivers/mmc/mmc_spi.c, so let's compile crc7.c when CONFIG_MMC_SPI
>> selected.
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> Reviewed-by: Anup Patel <anup.patel@wdc.com>
>> ---
>> lib/Makefile | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/lib/Makefile b/lib/Makefile index 51eba80b89..d21e0a6b3a
>> 100644
>> --- a/lib/Makefile
>> +++ b/lib/Makefile
>> @@ -78,6 +78,7 @@ endif
>>
>> ifdef CONFIG_SPL_BUILD
>> obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
>> +obj-$(CONFIG_MMC_SPI) += crc7.o
>
>It is invalid to mark crc7 to MMC_SPI, try to add Kconfig option for CRC7. like
>this.
>https://paste.ubuntu.com/p/kSnkDWpTgS/
Thanks for pointing me. How about if I will add like this:
config SPL_CRC7_SUPPORT
bool "Support CRC7 hashing drivers"
default y if MMC_SPI
help
Enable CRC7 hashing for drivers which are using in SPL.
Any comments?
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info
2020-01-24 5:50 ` [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info Pragnesh Patel
@ 2020-01-25 8:31 ` Anup Patel
2020-01-27 7:51 ` Jagan Teki
1 sibling, 0 replies; 32+ messages in thread
From: Anup Patel @ 2020-01-25 8:31 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 5:49 PM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> Add ddr4 controller and phy related files
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
> board/sifive/fu540/Makefile | 4 +
> board/sifive/fu540/ddr.c | 868 ++++++++++++++++++++
> board/sifive/fu540/regconfig-ctl.h | 270 ++++++
> board/sifive/fu540/regconfig-phy.h | 1220 ++++++++++++++++++++++++++++
> board/sifive/fu540/ux00ddr.h | 45 +
> 5 files changed, 2407 insertions(+)
> create mode 100644 board/sifive/fu540/ddr.c
> create mode 100644 board/sifive/fu540/regconfig-ctl.h
> create mode 100644 board/sifive/fu540/regconfig-phy.h
> create mode 100644 board/sifive/fu540/ux00ddr.h
>
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index 6e1862c475..e4e76e1de3 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,3 +3,7 @@
> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
> obj-y += fu540.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += ddr.o
> +endif
> diff --git a/board/sifive/fu540/ddr.c b/board/sifive/fu540/ddr.c
> new file mode 100644
> index 0000000000..a4a86b1173
> --- /dev/null
> +++ b/board/sifive/fu540/ddr.c
> @@ -0,0 +1,868 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#include <common.h>
> +
> +#include "regconfig-ctl.h"
> +#include "regconfig-phy.h"
> +
> +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
> +
> +#define DRAM_CLASS_OFFSET 8
> +#define OPTIMAL_RMODW_EN_OFFSET 0
> +#define DISABLE_RD_INTERLEAVE_OFFSET 16
> +#define OUT_OF_RANGE_OFFSET 1
> +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
> +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
> +#define MC_INIT_COMPLETE_OFFSET 8
> +#define LEVELING_OPERATION_COMPLETED_OFFSET 22
> +#define DFI_PHY_WRLELV_MODE_OFFSET 24
> +#define DFI_PHY_RDLVL_MODE_OFFSET 24
> +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
> +#define VREF_EN_OFFSET 24
> +#define PORT_ADDR_PROTECTION_EN_OFFSET 0
> +#define AXI0_ADDRESS_RANGE_ENABLE 8
> +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
> +#define RDLVL_EN_OFFSET 16
> +#define RDLVL_GATE_EN_OFFSET 24
> +#define WRLVL_EN_OFFSET 0
> +
> +#define PHY_RX_CAL_DQ0_0_OFFSET 0
> +#define PHY_RX_CAL_DQ1_0_OFFSET 16
> +
> +static void phy_reset(u32 *ddrphyreg, const
> + u32 *physettings)
> +{
> + unsigned int i;
> +
> + for (i = 1152; i <= 1214; i++) {
> + u32 physet = physettings[i];
> + /*if (physet!=0)*/ ddrphyreg[i] = physet;
> + }
> +
> + for (i = 0; i <= 1151; i++) {
> + u32 physet = physettings[i];
> + /*if (physet!=0)*/ ddrphyreg[i] = physet;
> + }
> +}
> +
> +void ux00ddr_writeregmap(size_t ahbregaddr, const
> + u32 *ctlsettings, const u32 *physettings)
> +{
> + u32 *ddrctlreg = (u32 *)ahbregaddr;
> + u32 *ddrphyreg = ((u32 *)ahbregaddr) +
> + (0x2000 / sizeof(u32));
> +
> + unsigned int i;
> +
> + for (i = 0; i <= 264; i++) {
> + u32 ctlset = ctlsettings[i];
> + /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset;
> + }
> +
> + phy_reset(ddrphyreg, physettings);
> +}
> +
> +void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend)
> +{
> + // START register at ddrctl register base offset 0
> + u32 regdata = _REG32(0 << 2, ahbregaddr);
> +
> + regdata |= 0x1;
> + _REG32(0 << 2, ahbregaddr) = regdata;
> +
> + /*
> + * WAIT for initialization complete : bit 8 of INT_STATUS
> + * (DENALI_CTL_132) 0x210
> + */
> + while ((_REG32(132 << 2, ahbregaddr) & (1 <<
> + MC_INIT_COMPLETE_OFFSET)) == 0) {
> + }
> +
> + // Disable the BusBlocker in front of the controller AXI slave ports
> + u64 *filterreg = (u64 *)filteraddr;
> +
> + filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
> +}
> +
> +void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr)
> +{
> + /*
> + * Mask off Bit 8 of Interrupt Status
> + * Bit [8] The MC initialization has been completed
> + */
> +
> + _REG32(136 << 2, ahbregaddr) |= (1 << MC_INIT_COMPLETE_OFFSET);
> +}
> +
> +void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr)
> +{
> + /*
> + * Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status
> + * Bit [2] Multiple accesses outside the defined PHYSICAL memory
> + * space have occurred
> + * Bit [1] A memory access outside the defined PHYSICAL memory
> + * space has occurred
> + */
> +
> + _REG32(136 << 2, ahbregaddr) |= ((1 << OUT_OF_RANGE_OFFSET) | (1 <<
> + MULTIPLE_OUT_OF_RANGE_OFFSET));
> +}
> +
> +void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr)
> +{
> + /*
> + * Mask off Bit 7 of Interrupt Status
> + * Bit [7] An error occurred on the port command channel
> + */
> +
> + _REG32(136 << 2, ahbregaddr) |= (1 <<
> + PORT_COMMAND_CHANNEL_ERROR_OFFSET);
> +}
> +
> +void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr)
> +{
> + /*
> + * Mask off Bit 22 of Interrupt Status
> + * Bit [22] The leveling operation has completed
> + */
> +
> + _REG32(136 << 2, ahbregaddr) |= (1 <<
> + LEVELING_OPERATION_COMPLETED_OFFSET);
> +}
> +
> +void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr)
> +{
> + _REG32(209 << 2, ahbregaddr) = 0x0;
> + size_t end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
> +
> + _REG32(210 << 2, ahbregaddr) = ((u32)end_addr_16kblocks);
> + _REG32(212 << 2, ahbregaddr) = 0x0;
> + _REG32(214 << 2, ahbregaddr) = 0x0;
> + _REG32(216 << 2, ahbregaddr) = 0x0;
> + _REG32(224 << 2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
> + _REG32(225 << 2, ahbregaddr) = 0xFFFFFFFF;
> + _REG32(208 << 2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
> + _REG32(208 << 2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
> +}
> +
> +void ux00ddr_disableaxireadinterleave(size_t ahbregaddr)
> +{
> + _REG32(120 << 2, ahbregaddr) |= (1 << DISABLE_RD_INTERLEAVE_OFFSET);
> +}
> +
> +void ux00ddr_disableoptimalrmodw(size_t ahbregaddr)
> +{
> + _REG32(21 << 2, ahbregaddr) &= (~(1 << OPTIMAL_RMODW_EN_OFFSET));
> +}
> +
> +void ux00ddr_enablewriteleveling(size_t ahbregaddr)
> +{
> + _REG32(170 << 2, ahbregaddr) |= ((1 << WRLVL_EN_OFFSET) | (1 <<
> + DFI_PHY_WRLELV_MODE_OFFSET));
> +}
> +
> +void ux00ddr_enablereadleveling(size_t ahbregaddr)
> +{
> + _REG32(181 << 2, ahbregaddr) |= (1 << DFI_PHY_RDLVL_MODE_OFFSET);
> + _REG32(260 << 2, ahbregaddr) |= (1 << RDLVL_EN_OFFSET);
> +}
> +
> +void ux00ddr_enablereadlevelinggate(size_t ahbregaddr)
> +{
> + _REG32(260 << 2, ahbregaddr) |= (1 << RDLVL_GATE_EN_OFFSET);
> + _REG32(182 << 2, ahbregaddr) |= (1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
> +}
> +
> +void ux00ddr_enablevreftraining(size_t ahbregaddr)
> +{
> + _REG32(184 << 2, ahbregaddr) |= (1 << VREF_EN_OFFSET);
> +}
> +
> +u32 ux00ddr_getdramclass(size_t ahbregaddr)
> +{
> + return((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF);
> +}
> +
> +u64 ux00ddr_phy_fixup(size_t ahbregaddr)
> +{
> + // return bitmask of failed lanes
> +
> + size_t ddrphyreg = ahbregaddr + 0x2000;
> +
> + u64 fails = 0;
> + u32 slicebase = 0;
> + u32 dq = 0;
> +
> + // check errata condition
> + for (u32 slice = 0; slice < 8; slice++) {
> + u32 regbase = slicebase + 34;
> +
> + for (u32 reg = 0; reg < 4; reg++) {
> + u32 updownreg = _REG32((regbase + reg) << 2,
> + ddrphyreg);
> +
> + for (u32 bit = 0; bit < 2; bit++) {
> + u32 phy_rx_cal_dqn_0_offset;
> +
> + if (bit == 0) {
> + phy_rx_cal_dqn_0_offset =
> + PHY_RX_CAL_DQ0_0_OFFSET;
> + } else {
> + phy_rx_cal_dqn_0_offset =
> + PHY_RX_CAL_DQ1_0_OFFSET;
> + }
> +
> + u32 down = (updownreg >>
> + phy_rx_cal_dqn_0_offset) & 0x3F;
> + u32 up = (updownreg >>
> + (phy_rx_cal_dqn_0_offset + 6)) &
> + 0x3F;
> +
> + u8 failc0 = ((down == 0) && (up == 0x3F));
> + u8 failc1 = ((up == 0) && (down == 0x3F));
> +
> + // print error message on failure
> + if (failc0 || failc1) {
> + if (fails == 0)
> + printf("DDR error in fixing up\n");
> +
> + fails |= (1 << dq);
> +
> + char slicelsc = '0';
> + char slicemsc = '0';
> +
> + slicelsc += (dq % 10);
> + slicemsc += (dq / 10);
> + printf("S ");
> + printf("%c", slicemsc);
> + printf("%c", slicelsc);
> +
> + if (failc0)
> + printf("U");
> + else
> + printf("D");
> +
> + printf("\n");
> + }
> + dq++;
> + }
> + }
> + slicebase += 128;
> + }
> + return(0);
> +}
> +
> +u32 ddr_phy_settings[1215] = {
> + DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, DENALI_PHY_02_DATA,
> + DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, DENALI_PHY_05_DATA,
> + DENALI_PHY_06_DATA, DENALI_PHY_07_DATA, DENALI_PHY_08_DATA,
> + DENALI_PHY_09_DATA,
> + DENALI_PHY_10_DATA, DENALI_PHY_11_DATA, DENALI_PHY_12_DATA,
> + DENALI_PHY_13_DATA, DENALI_PHY_14_DATA, DENALI_PHY_15_DATA,
> + DENALI_PHY_16_DATA, DENALI_PHY_17_DATA, DENALI_PHY_18_DATA,
> + DENALI_PHY_19_DATA,
> + DENALI_PHY_20_DATA, DENALI_PHY_21_DATA, DENALI_PHY_22_DATA,
> + DENALI_PHY_23_DATA, DENALI_PHY_24_DATA, DENALI_PHY_25_DATA,
> + DENALI_PHY_26_DATA, DENALI_PHY_27_DATA, DENALI_PHY_28_DATA,
> + DENALI_PHY_29_DATA,
> + DENALI_PHY_30_DATA, DENALI_PHY_31_DATA, DENALI_PHY_32_DATA,
> + DENALI_PHY_33_DATA, DENALI_PHY_34_DATA, DENALI_PHY_35_DATA,
> + DENALI_PHY_36_DATA, DENALI_PHY_37_DATA, DENALI_PHY_38_DATA,
> + DENALI_PHY_39_DATA,
> + DENALI_PHY_40_DATA, DENALI_PHY_41_DATA, DENALI_PHY_42_DATA,
> + DENALI_PHY_43_DATA, DENALI_PHY_44_DATA, DENALI_PHY_45_DATA,
> + DENALI_PHY_46_DATA, DENALI_PHY_47_DATA, DENALI_PHY_48_DATA,
> + DENALI_PHY_49_DATA,
> + DENALI_PHY_50_DATA, DENALI_PHY_51_DATA, DENALI_PHY_52_DATA,
> + DENALI_PHY_53_DATA, DENALI_PHY_54_DATA, DENALI_PHY_55_DATA,
> + DENALI_PHY_56_DATA, DENALI_PHY_57_DATA, DENALI_PHY_58_DATA,
> + DENALI_PHY_59_DATA,
> + DENALI_PHY_60_DATA, DENALI_PHY_61_DATA, DENALI_PHY_62_DATA,
> + DENALI_PHY_63_DATA, DENALI_PHY_64_DATA, DENALI_PHY_65_DATA,
> + DENALI_PHY_66_DATA, DENALI_PHY_67_DATA, DENALI_PHY_68_DATA,
> + DENALI_PHY_69_DATA,
> + DENALI_PHY_70_DATA, DENALI_PHY_71_DATA, DENALI_PHY_72_DATA,
> + DENALI_PHY_73_DATA, DENALI_PHY_74_DATA, DENALI_PHY_75_DATA,
> + DENALI_PHY_76_DATA, DENALI_PHY_77_DATA, DENALI_PHY_78_DATA,
> + DENALI_PHY_79_DATA,
> + DENALI_PHY_80_DATA, DENALI_PHY_81_DATA, DENALI_PHY_82_DATA,
> + DENALI_PHY_83_DATA, DENALI_PHY_84_DATA, DENALI_PHY_85_DATA,
> + DENALI_PHY_86_DATA, DENALI_PHY_87_DATA, DENALI_PHY_88_DATA,
> + DENALI_PHY_89_DATA,
> + DENALI_PHY_90_DATA, DENALI_PHY_91_DATA, DENALI_PHY_92_DATA,
> + DENALI_PHY_93_DATA, DENALI_PHY_94_DATA, DENALI_PHY_95_DATA,
> + DENALI_PHY_96_DATA, DENALI_PHY_97_DATA, DENALI_PHY_98_DATA,
> + DENALI_PHY_99_DATA,
> +
> + DENALI_PHY_100_DATA, DENALI_PHY_101_DATA, DENALI_PHY_102_DATA,
> + DENALI_PHY_103_DATA, DENALI_PHY_104_DATA, DENALI_PHY_105_DATA,
> + DENALI_PHY_106_DATA, DENALI_PHY_107_DATA, DENALI_PHY_108_DATA,
> + DENALI_PHY_109_DATA,
> + DENALI_PHY_110_DATA, DENALI_PHY_111_DATA, DENALI_PHY_112_DATA,
> + DENALI_PHY_113_DATA, DENALI_PHY_114_DATA, DENALI_PHY_115_DATA,
> + DENALI_PHY_116_DATA, DENALI_PHY_117_DATA, DENALI_PHY_118_DATA,
> + DENALI_PHY_119_DATA,
> + DENALI_PHY_120_DATA, DENALI_PHY_121_DATA, DENALI_PHY_122_DATA,
> + DENALI_PHY_123_DATA, DENALI_PHY_124_DATA, DENALI_PHY_125_DATA,
> + DENALI_PHY_126_DATA, DENALI_PHY_127_DATA, DENALI_PHY_128_DATA,
> + DENALI_PHY_129_DATA,
> + DENALI_PHY_130_DATA, DENALI_PHY_131_DATA, DENALI_PHY_132_DATA,
> + DENALI_PHY_133_DATA, DENALI_PHY_134_DATA, DENALI_PHY_135_DATA,
> + DENALI_PHY_136_DATA, DENALI_PHY_137_DATA, DENALI_PHY_138_DATA,
> + DENALI_PHY_139_DATA,
> + DENALI_PHY_140_DATA, DENALI_PHY_141_DATA, DENALI_PHY_142_DATA,
> + DENALI_PHY_143_DATA, DENALI_PHY_144_DATA, DENALI_PHY_145_DATA,
> + DENALI_PHY_146_DATA, DENALI_PHY_147_DATA, DENALI_PHY_148_DATA,
> + DENALI_PHY_149_DATA,
> + DENALI_PHY_150_DATA, DENALI_PHY_151_DATA, DENALI_PHY_152_DATA,
> + DENALI_PHY_153_DATA, DENALI_PHY_154_DATA, DENALI_PHY_155_DATA,
> + DENALI_PHY_156_DATA, DENALI_PHY_157_DATA, DENALI_PHY_158_DATA,
> + DENALI_PHY_159_DATA,
> + DENALI_PHY_160_DATA, DENALI_PHY_161_DATA, DENALI_PHY_162_DATA,
> + DENALI_PHY_163_DATA, DENALI_PHY_164_DATA, DENALI_PHY_165_DATA,
> + DENALI_PHY_166_DATA, DENALI_PHY_167_DATA, DENALI_PHY_168_DATA,
> + DENALI_PHY_169_DATA,
> + DENALI_PHY_170_DATA, DENALI_PHY_171_DATA, DENALI_PHY_172_DATA,
> + DENALI_PHY_173_DATA, DENALI_PHY_174_DATA, DENALI_PHY_175_DATA,
> + DENALI_PHY_176_DATA, DENALI_PHY_177_DATA, DENALI_PHY_178_DATA,
> + DENALI_PHY_179_DATA,
> + DENALI_PHY_180_DATA, DENALI_PHY_181_DATA, DENALI_PHY_182_DATA,
> + DENALI_PHY_183_DATA, DENALI_PHY_184_DATA, DENALI_PHY_185_DATA,
> + DENALI_PHY_186_DATA, DENALI_PHY_187_DATA, DENALI_PHY_188_DATA,
> + DENALI_PHY_189_DATA,
> + DENALI_PHY_190_DATA, DENALI_PHY_191_DATA, DENALI_PHY_192_DATA,
> + DENALI_PHY_193_DATA, DENALI_PHY_194_DATA, DENALI_PHY_195_DATA,
> + DENALI_PHY_196_DATA, DENALI_PHY_197_DATA, DENALI_PHY_198_DATA,
> + DENALI_PHY_199_DATA,
> +
> + DENALI_PHY_200_DATA, DENALI_PHY_201_DATA, DENALI_PHY_202_DATA,
> + DENALI_PHY_203_DATA, DENALI_PHY_204_DATA, DENALI_PHY_205_DATA,
> + DENALI_PHY_206_DATA, DENALI_PHY_207_DATA, DENALI_PHY_208_DATA,
> + DENALI_PHY_209_DATA,
> + DENALI_PHY_210_DATA, DENALI_PHY_211_DATA, DENALI_PHY_212_DATA,
> + DENALI_PHY_213_DATA, DENALI_PHY_214_DATA, DENALI_PHY_215_DATA,
> + DENALI_PHY_216_DATA, DENALI_PHY_217_DATA, DENALI_PHY_218_DATA,
> + DENALI_PHY_219_DATA,
> + DENALI_PHY_220_DATA, DENALI_PHY_221_DATA, DENALI_PHY_222_DATA,
> + DENALI_PHY_223_DATA, DENALI_PHY_224_DATA, DENALI_PHY_225_DATA,
> + DENALI_PHY_226_DATA, DENALI_PHY_227_DATA, DENALI_PHY_228_DATA,
> + DENALI_PHY_229_DATA,
> + DENALI_PHY_230_DATA, DENALI_PHY_231_DATA, DENALI_PHY_232_DATA,
> + DENALI_PHY_233_DATA, DENALI_PHY_234_DATA, DENALI_PHY_235_DATA,
> + DENALI_PHY_236_DATA, DENALI_PHY_237_DATA, DENALI_PHY_238_DATA,
> + DENALI_PHY_239_DATA,
> + DENALI_PHY_240_DATA, DENALI_PHY_241_DATA, DENALI_PHY_242_DATA,
> + DENALI_PHY_243_DATA, DENALI_PHY_244_DATA, DENALI_PHY_245_DATA,
> + DENALI_PHY_246_DATA, DENALI_PHY_247_DATA, DENALI_PHY_248_DATA,
> + DENALI_PHY_249_DATA,
> + DENALI_PHY_250_DATA, DENALI_PHY_251_DATA, DENALI_PHY_252_DATA,
> + DENALI_PHY_253_DATA, DENALI_PHY_254_DATA, DENALI_PHY_255_DATA,
> + DENALI_PHY_256_DATA, DENALI_PHY_257_DATA, DENALI_PHY_258_DATA,
> + DENALI_PHY_259_DATA,
> + DENALI_PHY_260_DATA, DENALI_PHY_261_DATA, DENALI_PHY_262_DATA,
> + DENALI_PHY_263_DATA, DENALI_PHY_264_DATA, DENALI_PHY_265_DATA,
> + DENALI_PHY_266_DATA, DENALI_PHY_267_DATA, DENALI_PHY_268_DATA,
> + DENALI_PHY_269_DATA,
> + DENALI_PHY_270_DATA, DENALI_PHY_271_DATA, DENALI_PHY_272_DATA,
> + DENALI_PHY_273_DATA, DENALI_PHY_274_DATA, DENALI_PHY_275_DATA,
> + DENALI_PHY_276_DATA, DENALI_PHY_277_DATA, DENALI_PHY_278_DATA,
> + DENALI_PHY_279_DATA,
> + DENALI_PHY_280_DATA, DENALI_PHY_281_DATA, DENALI_PHY_282_DATA,
> + DENALI_PHY_283_DATA, DENALI_PHY_284_DATA, DENALI_PHY_285_DATA,
> + DENALI_PHY_286_DATA, DENALI_PHY_287_DATA, DENALI_PHY_288_DATA,
> + DENALI_PHY_289_DATA,
> + DENALI_PHY_290_DATA, DENALI_PHY_291_DATA, DENALI_PHY_292_DATA,
> + DENALI_PHY_293_DATA, DENALI_PHY_294_DATA, DENALI_PHY_295_DATA,
> + DENALI_PHY_296_DATA, DENALI_PHY_297_DATA, DENALI_PHY_298_DATA,
> + DENALI_PHY_299_DATA,
> +
> + DENALI_PHY_300_DATA, DENALI_PHY_301_DATA, DENALI_PHY_302_DATA,
> + DENALI_PHY_303_DATA, DENALI_PHY_304_DATA, DENALI_PHY_305_DATA,
> + DENALI_PHY_306_DATA, DENALI_PHY_307_DATA, DENALI_PHY_308_DATA,
> + DENALI_PHY_309_DATA,
> + DENALI_PHY_310_DATA, DENALI_PHY_311_DATA, DENALI_PHY_312_DATA,
> + DENALI_PHY_313_DATA, DENALI_PHY_314_DATA, DENALI_PHY_315_DATA,
> + DENALI_PHY_316_DATA, DENALI_PHY_317_DATA, DENALI_PHY_318_DATA,
> + DENALI_PHY_319_DATA,
> + DENALI_PHY_320_DATA, DENALI_PHY_321_DATA, DENALI_PHY_322_DATA,
> + DENALI_PHY_323_DATA, DENALI_PHY_324_DATA, DENALI_PHY_325_DATA,
> + DENALI_PHY_326_DATA, DENALI_PHY_327_DATA, DENALI_PHY_328_DATA,
> + DENALI_PHY_329_DATA,
> + DENALI_PHY_330_DATA, DENALI_PHY_331_DATA, DENALI_PHY_332_DATA,
> + DENALI_PHY_333_DATA, DENALI_PHY_334_DATA, DENALI_PHY_335_DATA,
> + DENALI_PHY_336_DATA, DENALI_PHY_337_DATA, DENALI_PHY_338_DATA,
> + DENALI_PHY_339_DATA,
> + DENALI_PHY_340_DATA, DENALI_PHY_341_DATA, DENALI_PHY_342_DATA,
> + DENALI_PHY_343_DATA, DENALI_PHY_344_DATA, DENALI_PHY_345_DATA,
> + DENALI_PHY_346_DATA, DENALI_PHY_347_DATA, DENALI_PHY_348_DATA,
> + DENALI_PHY_349_DATA,
> + DENALI_PHY_350_DATA, DENALI_PHY_351_DATA, DENALI_PHY_352_DATA,
> + DENALI_PHY_353_DATA, DENALI_PHY_354_DATA, DENALI_PHY_355_DATA,
> + DENALI_PHY_356_DATA, DENALI_PHY_357_DATA, DENALI_PHY_358_DATA,
> + DENALI_PHY_359_DATA,
> + DENALI_PHY_360_DATA, DENALI_PHY_361_DATA, DENALI_PHY_362_DATA,
> + DENALI_PHY_363_DATA, DENALI_PHY_364_DATA, DENALI_PHY_365_DATA,
> + DENALI_PHY_366_DATA, DENALI_PHY_367_DATA, DENALI_PHY_368_DATA,
> + DENALI_PHY_369_DATA,
> + DENALI_PHY_370_DATA, DENALI_PHY_371_DATA, DENALI_PHY_372_DATA,
> + DENALI_PHY_373_DATA, DENALI_PHY_374_DATA, DENALI_PHY_375_DATA,
> + DENALI_PHY_376_DATA, DENALI_PHY_377_DATA, DENALI_PHY_378_DATA,
> + DENALI_PHY_379_DATA,
> + DENALI_PHY_380_DATA, DENALI_PHY_381_DATA, DENALI_PHY_382_DATA,
> + DENALI_PHY_383_DATA, DENALI_PHY_384_DATA, DENALI_PHY_385_DATA,
> + DENALI_PHY_386_DATA, DENALI_PHY_387_DATA, DENALI_PHY_388_DATA,
> + DENALI_PHY_389_DATA,
> + DENALI_PHY_390_DATA, DENALI_PHY_391_DATA, DENALI_PHY_392_DATA,
> + DENALI_PHY_393_DATA, DENALI_PHY_394_DATA, DENALI_PHY_395_DATA,
> + DENALI_PHY_396_DATA, DENALI_PHY_397_DATA, DENALI_PHY_398_DATA,
> + DENALI_PHY_399_DATA,
> +
> + DENALI_PHY_400_DATA, DENALI_PHY_401_DATA, DENALI_PHY_402_DATA,
> + DENALI_PHY_403_DATA, DENALI_PHY_404_DATA, DENALI_PHY_405_DATA,
> + DENALI_PHY_406_DATA, DENALI_PHY_407_DATA, DENALI_PHY_408_DATA,
> + DENALI_PHY_409_DATA,
> + DENALI_PHY_410_DATA, DENALI_PHY_411_DATA, DENALI_PHY_412_DATA,
> + DENALI_PHY_413_DATA, DENALI_PHY_414_DATA, DENALI_PHY_415_DATA,
> + DENALI_PHY_416_DATA, DENALI_PHY_417_DATA, DENALI_PHY_418_DATA,
> + DENALI_PHY_419_DATA,
> + DENALI_PHY_420_DATA, DENALI_PHY_421_DATA, DENALI_PHY_422_DATA,
> + DENALI_PHY_423_DATA, DENALI_PHY_424_DATA, DENALI_PHY_425_DATA,
> + DENALI_PHY_426_DATA, DENALI_PHY_427_DATA, DENALI_PHY_428_DATA,
> + DENALI_PHY_429_DATA,
> + DENALI_PHY_430_DATA, DENALI_PHY_431_DATA, DENALI_PHY_432_DATA,
> + DENALI_PHY_433_DATA, DENALI_PHY_434_DATA, DENALI_PHY_435_DATA,
> + DENALI_PHY_436_DATA, DENALI_PHY_437_DATA, DENALI_PHY_438_DATA,
> + DENALI_PHY_439_DATA,
> + DENALI_PHY_440_DATA, DENALI_PHY_441_DATA, DENALI_PHY_442_DATA,
> + DENALI_PHY_443_DATA, DENALI_PHY_444_DATA, DENALI_PHY_445_DATA,
> + DENALI_PHY_446_DATA, DENALI_PHY_447_DATA, DENALI_PHY_448_DATA,
> + DENALI_PHY_449_DATA,
> + DENALI_PHY_450_DATA, DENALI_PHY_451_DATA, DENALI_PHY_452_DATA,
> + DENALI_PHY_453_DATA, DENALI_PHY_454_DATA, DENALI_PHY_455_DATA,
> + DENALI_PHY_456_DATA, DENALI_PHY_457_DATA, DENALI_PHY_458_DATA,
> + DENALI_PHY_459_DATA,
> + DENALI_PHY_460_DATA, DENALI_PHY_461_DATA, DENALI_PHY_462_DATA,
> + DENALI_PHY_463_DATA, DENALI_PHY_464_DATA, DENALI_PHY_465_DATA,
> + DENALI_PHY_466_DATA, DENALI_PHY_467_DATA, DENALI_PHY_468_DATA,
> + DENALI_PHY_469_DATA,
> + DENALI_PHY_470_DATA, DENALI_PHY_471_DATA, DENALI_PHY_472_DATA,
> + DENALI_PHY_473_DATA, DENALI_PHY_474_DATA, DENALI_PHY_475_DATA,
> + DENALI_PHY_476_DATA, DENALI_PHY_477_DATA, DENALI_PHY_478_DATA,
> + DENALI_PHY_479_DATA,
> + DENALI_PHY_480_DATA, DENALI_PHY_481_DATA, DENALI_PHY_482_DATA,
> + DENALI_PHY_483_DATA, DENALI_PHY_484_DATA, DENALI_PHY_485_DATA,
> + DENALI_PHY_486_DATA, DENALI_PHY_487_DATA, DENALI_PHY_488_DATA,
> + DENALI_PHY_489_DATA,
> + DENALI_PHY_490_DATA, DENALI_PHY_491_DATA, DENALI_PHY_492_DATA,
> + DENALI_PHY_493_DATA, DENALI_PHY_494_DATA, DENALI_PHY_495_DATA,
> + DENALI_PHY_496_DATA, DENALI_PHY_497_DATA, DENALI_PHY_498_DATA,
> + DENALI_PHY_499_DATA,
> +
> + DENALI_PHY_500_DATA, DENALI_PHY_501_DATA, DENALI_PHY_502_DATA,
> + DENALI_PHY_503_DATA, DENALI_PHY_504_DATA, DENALI_PHY_505_DATA,
> + DENALI_PHY_506_DATA, DENALI_PHY_507_DATA, DENALI_PHY_508_DATA,
> + DENALI_PHY_509_DATA,
> + DENALI_PHY_510_DATA, DENALI_PHY_511_DATA, DENALI_PHY_512_DATA,
> + DENALI_PHY_513_DATA, DENALI_PHY_514_DATA, DENALI_PHY_515_DATA,
> + DENALI_PHY_516_DATA, DENALI_PHY_517_DATA, DENALI_PHY_518_DATA,
> + DENALI_PHY_519_DATA,
> + DENALI_PHY_520_DATA, DENALI_PHY_521_DATA, DENALI_PHY_522_DATA,
> + DENALI_PHY_523_DATA, DENALI_PHY_524_DATA, DENALI_PHY_525_DATA,
> + DENALI_PHY_526_DATA, DENALI_PHY_527_DATA, DENALI_PHY_528_DATA,
> + DENALI_PHY_529_DATA,
> + DENALI_PHY_530_DATA, DENALI_PHY_531_DATA, DENALI_PHY_532_DATA,
> + DENALI_PHY_533_DATA, DENALI_PHY_534_DATA, DENALI_PHY_535_DATA,
> + DENALI_PHY_536_DATA, DENALI_PHY_537_DATA, DENALI_PHY_538_DATA,
> + DENALI_PHY_539_DATA,
> + DENALI_PHY_540_DATA, DENALI_PHY_541_DATA, DENALI_PHY_542_DATA,
> + DENALI_PHY_543_DATA, DENALI_PHY_544_DATA, DENALI_PHY_545_DATA,
> + DENALI_PHY_546_DATA, DENALI_PHY_547_DATA, DENALI_PHY_548_DATA,
> + DENALI_PHY_549_DATA,
> + DENALI_PHY_550_DATA, DENALI_PHY_551_DATA, DENALI_PHY_552_DATA,
> + DENALI_PHY_553_DATA, DENALI_PHY_554_DATA, DENALI_PHY_555_DATA,
> + DENALI_PHY_556_DATA, DENALI_PHY_557_DATA, DENALI_PHY_558_DATA,
> + DENALI_PHY_559_DATA,
> + DENALI_PHY_560_DATA, DENALI_PHY_561_DATA, DENALI_PHY_562_DATA,
> + DENALI_PHY_563_DATA, DENALI_PHY_564_DATA, DENALI_PHY_565_DATA,
> + DENALI_PHY_566_DATA, DENALI_PHY_567_DATA, DENALI_PHY_568_DATA,
> + DENALI_PHY_569_DATA,
> + DENALI_PHY_570_DATA, DENALI_PHY_571_DATA, DENALI_PHY_572_DATA,
> + DENALI_PHY_573_DATA, DENALI_PHY_574_DATA, DENALI_PHY_575_DATA,
> + DENALI_PHY_576_DATA, DENALI_PHY_577_DATA, DENALI_PHY_578_DATA,
> + DENALI_PHY_579_DATA,
> + DENALI_PHY_580_DATA, DENALI_PHY_581_DATA, DENALI_PHY_582_DATA,
> + DENALI_PHY_583_DATA, DENALI_PHY_584_DATA, DENALI_PHY_585_DATA,
> + DENALI_PHY_586_DATA, DENALI_PHY_587_DATA, DENALI_PHY_588_DATA,
> + DENALI_PHY_589_DATA,
> + DENALI_PHY_590_DATA, DENALI_PHY_591_DATA, DENALI_PHY_592_DATA,
> + DENALI_PHY_593_DATA, DENALI_PHY_594_DATA, DENALI_PHY_595_DATA,
> + DENALI_PHY_596_DATA, DENALI_PHY_597_DATA, DENALI_PHY_598_DATA,
> + DENALI_PHY_599_DATA,
> +
> + DENALI_PHY_600_DATA, DENALI_PHY_601_DATA, DENALI_PHY_602_DATA,
> + DENALI_PHY_603_DATA, DENALI_PHY_604_DATA, DENALI_PHY_605_DATA,
> + DENALI_PHY_606_DATA, DENALI_PHY_607_DATA, DENALI_PHY_608_DATA,
> + DENALI_PHY_609_DATA,
> + DENALI_PHY_610_DATA, DENALI_PHY_611_DATA, DENALI_PHY_612_DATA,
> + DENALI_PHY_613_DATA, DENALI_PHY_614_DATA, DENALI_PHY_615_DATA,
> + DENALI_PHY_616_DATA, DENALI_PHY_617_DATA, DENALI_PHY_618_DATA,
> + DENALI_PHY_619_DATA,
> + DENALI_PHY_620_DATA, DENALI_PHY_621_DATA, DENALI_PHY_622_DATA,
> + DENALI_PHY_623_DATA, DENALI_PHY_624_DATA, DENALI_PHY_625_DATA,
> + DENALI_PHY_626_DATA, DENALI_PHY_627_DATA, DENALI_PHY_628_DATA,
> + DENALI_PHY_629_DATA,
> + DENALI_PHY_630_DATA, DENALI_PHY_631_DATA, DENALI_PHY_632_DATA,
> + DENALI_PHY_633_DATA, DENALI_PHY_634_DATA, DENALI_PHY_635_DATA,
> + DENALI_PHY_636_DATA, DENALI_PHY_637_DATA, DENALI_PHY_638_DATA,
> + DENALI_PHY_639_DATA,
> + DENALI_PHY_640_DATA, DENALI_PHY_641_DATA, DENALI_PHY_642_DATA,
> + DENALI_PHY_643_DATA, DENALI_PHY_644_DATA, DENALI_PHY_645_DATA,
> + DENALI_PHY_646_DATA, DENALI_PHY_647_DATA, DENALI_PHY_648_DATA,
> + DENALI_PHY_649_DATA,
> + DENALI_PHY_650_DATA, DENALI_PHY_651_DATA, DENALI_PHY_652_DATA,
> + DENALI_PHY_653_DATA, DENALI_PHY_654_DATA, DENALI_PHY_655_DATA,
> + DENALI_PHY_656_DATA, DENALI_PHY_657_DATA, DENALI_PHY_658_DATA,
> + DENALI_PHY_659_DATA,
> + DENALI_PHY_660_DATA, DENALI_PHY_661_DATA, DENALI_PHY_662_DATA,
> + DENALI_PHY_663_DATA, DENALI_PHY_664_DATA, DENALI_PHY_665_DATA,
> + DENALI_PHY_666_DATA, DENALI_PHY_667_DATA, DENALI_PHY_668_DATA,
> + DENALI_PHY_669_DATA,
> + DENALI_PHY_670_DATA, DENALI_PHY_671_DATA, DENALI_PHY_672_DATA,
> + DENALI_PHY_673_DATA, DENALI_PHY_674_DATA, DENALI_PHY_675_DATA,
> + DENALI_PHY_676_DATA, DENALI_PHY_677_DATA, DENALI_PHY_678_DATA,
> + DENALI_PHY_679_DATA,
> + DENALI_PHY_680_DATA, DENALI_PHY_681_DATA, DENALI_PHY_682_DATA,
> + DENALI_PHY_683_DATA, DENALI_PHY_684_DATA, DENALI_PHY_685_DATA,
> + DENALI_PHY_686_DATA, DENALI_PHY_687_DATA, DENALI_PHY_688_DATA,
> + DENALI_PHY_689_DATA,
> + DENALI_PHY_690_DATA, DENALI_PHY_691_DATA, DENALI_PHY_692_DATA,
> + DENALI_PHY_693_DATA, DENALI_PHY_694_DATA, DENALI_PHY_695_DATA,
> + DENALI_PHY_696_DATA, DENALI_PHY_697_DATA, DENALI_PHY_698_DATA,
> + DENALI_PHY_699_DATA,
> +
> + DENALI_PHY_700_DATA, DENALI_PHY_701_DATA, DENALI_PHY_702_DATA,
> + DENALI_PHY_703_DATA, DENALI_PHY_704_DATA, DENALI_PHY_705_DATA,
> + DENALI_PHY_706_DATA, DENALI_PHY_707_DATA, DENALI_PHY_708_DATA,
> + DENALI_PHY_709_DATA,
> + DENALI_PHY_710_DATA, DENALI_PHY_711_DATA, DENALI_PHY_712_DATA,
> + DENALI_PHY_713_DATA, DENALI_PHY_714_DATA, DENALI_PHY_715_DATA,
> + DENALI_PHY_716_DATA, DENALI_PHY_717_DATA, DENALI_PHY_718_DATA,
> + DENALI_PHY_719_DATA,
> + DENALI_PHY_720_DATA, DENALI_PHY_721_DATA, DENALI_PHY_722_DATA,
> + DENALI_PHY_723_DATA, DENALI_PHY_724_DATA, DENALI_PHY_725_DATA,
> + DENALI_PHY_726_DATA, DENALI_PHY_727_DATA, DENALI_PHY_728_DATA,
> + DENALI_PHY_729_DATA,
> + DENALI_PHY_730_DATA, DENALI_PHY_731_DATA, DENALI_PHY_732_DATA,
> + DENALI_PHY_733_DATA, DENALI_PHY_734_DATA, DENALI_PHY_735_DATA,
> + DENALI_PHY_736_DATA, DENALI_PHY_737_DATA, DENALI_PHY_738_DATA,
> + DENALI_PHY_739_DATA,
> + DENALI_PHY_740_DATA, DENALI_PHY_741_DATA, DENALI_PHY_742_DATA,
> + DENALI_PHY_743_DATA, DENALI_PHY_744_DATA, DENALI_PHY_745_DATA,
> + DENALI_PHY_746_DATA, DENALI_PHY_747_DATA, DENALI_PHY_748_DATA,
> + DENALI_PHY_749_DATA,
> + DENALI_PHY_750_DATA, DENALI_PHY_751_DATA, DENALI_PHY_752_DATA,
> + DENALI_PHY_753_DATA, DENALI_PHY_754_DATA, DENALI_PHY_755_DATA,
> + DENALI_PHY_756_DATA, DENALI_PHY_757_DATA, DENALI_PHY_758_DATA,
> + DENALI_PHY_759_DATA,
> + DENALI_PHY_760_DATA, DENALI_PHY_761_DATA, DENALI_PHY_762_DATA,
> + DENALI_PHY_763_DATA, DENALI_PHY_764_DATA, DENALI_PHY_765_DATA,
> + DENALI_PHY_766_DATA, DENALI_PHY_767_DATA, DENALI_PHY_768_DATA,
> + DENALI_PHY_769_DATA,
> + DENALI_PHY_770_DATA, DENALI_PHY_771_DATA, DENALI_PHY_772_DATA,
> + DENALI_PHY_773_DATA, DENALI_PHY_774_DATA, DENALI_PHY_775_DATA,
> + DENALI_PHY_776_DATA, DENALI_PHY_777_DATA, DENALI_PHY_778_DATA,
> + DENALI_PHY_779_DATA,
> + DENALI_PHY_780_DATA, DENALI_PHY_781_DATA, DENALI_PHY_782_DATA,
> + DENALI_PHY_783_DATA, DENALI_PHY_784_DATA, DENALI_PHY_785_DATA,
> + DENALI_PHY_786_DATA, DENALI_PHY_787_DATA, DENALI_PHY_788_DATA,
> + DENALI_PHY_789_DATA,
> + DENALI_PHY_790_DATA, DENALI_PHY_791_DATA, DENALI_PHY_792_DATA,
> + DENALI_PHY_793_DATA, DENALI_PHY_794_DATA, DENALI_PHY_795_DATA,
> + DENALI_PHY_796_DATA, DENALI_PHY_797_DATA, DENALI_PHY_798_DATA,
> + DENALI_PHY_799_DATA,
> +
> + DENALI_PHY_800_DATA, DENALI_PHY_801_DATA, DENALI_PHY_802_DATA,
> + DENALI_PHY_803_DATA, DENALI_PHY_804_DATA, DENALI_PHY_805_DATA,
> + DENALI_PHY_806_DATA, DENALI_PHY_807_DATA, DENALI_PHY_808_DATA,
> + DENALI_PHY_809_DATA,
> + DENALI_PHY_810_DATA, DENALI_PHY_811_DATA, DENALI_PHY_812_DATA,
> + DENALI_PHY_813_DATA, DENALI_PHY_814_DATA, DENALI_PHY_815_DATA,
> + DENALI_PHY_816_DATA, DENALI_PHY_817_DATA, DENALI_PHY_818_DATA,
> + DENALI_PHY_819_DATA,
> + DENALI_PHY_820_DATA, DENALI_PHY_821_DATA, DENALI_PHY_822_DATA,
> + DENALI_PHY_823_DATA, DENALI_PHY_824_DATA, DENALI_PHY_825_DATA,
> + DENALI_PHY_826_DATA, DENALI_PHY_827_DATA, DENALI_PHY_828_DATA,
> + DENALI_PHY_829_DATA,
> + DENALI_PHY_830_DATA, DENALI_PHY_831_DATA, DENALI_PHY_832_DATA,
> + DENALI_PHY_833_DATA, DENALI_PHY_834_DATA, DENALI_PHY_835_DATA,
> + DENALI_PHY_836_DATA, DENALI_PHY_837_DATA, DENALI_PHY_838_DATA,
> + DENALI_PHY_839_DATA,
> + DENALI_PHY_840_DATA, DENALI_PHY_841_DATA, DENALI_PHY_842_DATA,
> + DENALI_PHY_843_DATA, DENALI_PHY_844_DATA, DENALI_PHY_845_DATA,
> + DENALI_PHY_846_DATA, DENALI_PHY_847_DATA, DENALI_PHY_848_DATA,
> + DENALI_PHY_849_DATA,
> + DENALI_PHY_850_DATA, DENALI_PHY_851_DATA, DENALI_PHY_852_DATA,
> + DENALI_PHY_853_DATA, DENALI_PHY_854_DATA, DENALI_PHY_855_DATA,
> + DENALI_PHY_856_DATA, DENALI_PHY_857_DATA, DENALI_PHY_858_DATA,
> + DENALI_PHY_859_DATA,
> + DENALI_PHY_860_DATA, DENALI_PHY_861_DATA, DENALI_PHY_862_DATA,
> + DENALI_PHY_863_DATA, DENALI_PHY_864_DATA, DENALI_PHY_865_DATA,
> + DENALI_PHY_866_DATA, DENALI_PHY_867_DATA, DENALI_PHY_868_DATA,
> + DENALI_PHY_869_DATA,
> + DENALI_PHY_870_DATA, DENALI_PHY_871_DATA, DENALI_PHY_872_DATA,
> + DENALI_PHY_873_DATA, DENALI_PHY_874_DATA, DENALI_PHY_875_DATA,
> + DENALI_PHY_876_DATA, DENALI_PHY_877_DATA, DENALI_PHY_878_DATA,
> + DENALI_PHY_879_DATA,
> + DENALI_PHY_880_DATA, DENALI_PHY_881_DATA, DENALI_PHY_882_DATA,
> + DENALI_PHY_883_DATA, DENALI_PHY_884_DATA, DENALI_PHY_885_DATA,
> + DENALI_PHY_886_DATA, DENALI_PHY_887_DATA, DENALI_PHY_888_DATA,
> + DENALI_PHY_889_DATA,
> + DENALI_PHY_890_DATA, DENALI_PHY_891_DATA, DENALI_PHY_892_DATA,
> + DENALI_PHY_893_DATA, DENALI_PHY_894_DATA, DENALI_PHY_895_DATA,
> + DENALI_PHY_896_DATA, DENALI_PHY_897_DATA, DENALI_PHY_898_DATA,
> + DENALI_PHY_899_DATA,
> +
> + DENALI_PHY_900_DATA, DENALI_PHY_901_DATA, DENALI_PHY_902_DATA,
> + DENALI_PHY_903_DATA, DENALI_PHY_904_DATA, DENALI_PHY_905_DATA,
> + DENALI_PHY_906_DATA, DENALI_PHY_907_DATA, DENALI_PHY_908_DATA,
> + DENALI_PHY_909_DATA,
> + DENALI_PHY_910_DATA, DENALI_PHY_911_DATA, DENALI_PHY_912_DATA,
> + DENALI_PHY_913_DATA, DENALI_PHY_914_DATA, DENALI_PHY_915_DATA,
> + DENALI_PHY_916_DATA, DENALI_PHY_917_DATA, DENALI_PHY_918_DATA,
> + DENALI_PHY_919_DATA,
> + DENALI_PHY_920_DATA, DENALI_PHY_921_DATA, DENALI_PHY_922_DATA,
> + DENALI_PHY_923_DATA, DENALI_PHY_924_DATA, DENALI_PHY_925_DATA,
> + DENALI_PHY_926_DATA, DENALI_PHY_927_DATA, DENALI_PHY_928_DATA,
> + DENALI_PHY_929_DATA,
> + DENALI_PHY_930_DATA, DENALI_PHY_931_DATA, DENALI_PHY_932_DATA,
> + DENALI_PHY_933_DATA, DENALI_PHY_934_DATA, DENALI_PHY_935_DATA,
> + DENALI_PHY_936_DATA, DENALI_PHY_937_DATA, DENALI_PHY_938_DATA,
> + DENALI_PHY_939_DATA,
> + DENALI_PHY_940_DATA, DENALI_PHY_941_DATA, DENALI_PHY_942_DATA,
> + DENALI_PHY_943_DATA, DENALI_PHY_944_DATA, DENALI_PHY_945_DATA,
> + DENALI_PHY_946_DATA, DENALI_PHY_947_DATA, DENALI_PHY_948_DATA,
> + DENALI_PHY_949_DATA,
> + DENALI_PHY_950_DATA, DENALI_PHY_951_DATA, DENALI_PHY_952_DATA,
> + DENALI_PHY_953_DATA, DENALI_PHY_954_DATA, DENALI_PHY_955_DATA,
> + DENALI_PHY_956_DATA, DENALI_PHY_957_DATA, DENALI_PHY_958_DATA,
> + DENALI_PHY_959_DATA,
> + DENALI_PHY_960_DATA, DENALI_PHY_961_DATA, DENALI_PHY_962_DATA,
> + DENALI_PHY_963_DATA, DENALI_PHY_964_DATA, DENALI_PHY_965_DATA,
> + DENALI_PHY_966_DATA, DENALI_PHY_967_DATA, DENALI_PHY_968_DATA,
> + DENALI_PHY_969_DATA,
> + DENALI_PHY_970_DATA, DENALI_PHY_971_DATA, DENALI_PHY_972_DATA,
> + DENALI_PHY_973_DATA, DENALI_PHY_974_DATA, DENALI_PHY_975_DATA,
> + DENALI_PHY_976_DATA, DENALI_PHY_977_DATA, DENALI_PHY_978_DATA,
> + DENALI_PHY_979_DATA,
> + DENALI_PHY_980_DATA, DENALI_PHY_981_DATA, DENALI_PHY_982_DATA,
> + DENALI_PHY_983_DATA, DENALI_PHY_984_DATA, DENALI_PHY_985_DATA,
> + DENALI_PHY_986_DATA, DENALI_PHY_987_DATA, DENALI_PHY_988_DATA,
> + DENALI_PHY_989_DATA,
> + DENALI_PHY_990_DATA, DENALI_PHY_991_DATA, DENALI_PHY_992_DATA,
> + DENALI_PHY_993_DATA, DENALI_PHY_994_DATA, DENALI_PHY_995_DATA,
> + DENALI_PHY_996_DATA, DENALI_PHY_997_DATA, DENALI_PHY_998_DATA,
> + DENALI_PHY_999_DATA,
> +
> + DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA, DENALI_PHY_1002_DATA,
> + DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA, DENALI_PHY_1005_DATA,
> + DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA, DENALI_PHY_1008_DATA,
> + DENALI_PHY_1009_DATA,
> + DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA, DENALI_PHY_1012_DATA,
> + DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA, DENALI_PHY_1015_DATA,
> + DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA, DENALI_PHY_1018_DATA,
> + DENALI_PHY_1019_DATA,
> + DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA, DENALI_PHY_1022_DATA,
> + DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA, DENALI_PHY_1025_DATA,
> + DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA, DENALI_PHY_1028_DATA,
> + DENALI_PHY_1029_DATA,
> + DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA, DENALI_PHY_1032_DATA,
> + DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA, DENALI_PHY_1035_DATA,
> + DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA, DENALI_PHY_1038_DATA,
> + DENALI_PHY_1039_DATA,
> + DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA, DENALI_PHY_1042_DATA,
> + DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA, DENALI_PHY_1045_DATA,
> + DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA, DENALI_PHY_1048_DATA,
> + DENALI_PHY_1049_DATA,
> + DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA, DENALI_PHY_1052_DATA,
> + DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA, DENALI_PHY_1055_DATA,
> + DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA, DENALI_PHY_1058_DATA,
> + DENALI_PHY_1059_DATA,
> + DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA, DENALI_PHY_1062_DATA,
> + DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA, DENALI_PHY_1065_DATA,
> + DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA, DENALI_PHY_1068_DATA,
> + DENALI_PHY_1069_DATA,
> + DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA, DENALI_PHY_1072_DATA,
> + DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA, DENALI_PHY_1075_DATA,
> + DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA, DENALI_PHY_1078_DATA,
> + DENALI_PHY_1079_DATA,
> + DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA, DENALI_PHY_1082_DATA,
> + DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA, DENALI_PHY_1085_DATA,
> + DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA, DENALI_PHY_1088_DATA,
> + DENALI_PHY_1089_DATA,
> + DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA, DENALI_PHY_1092_DATA,
> + DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA, DENALI_PHY_1095_DATA,
> + DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA, DENALI_PHY_1098_DATA,
> + DENALI_PHY_1099_DATA,
> +
> + DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA, DENALI_PHY_1102_DATA,
> + DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA, DENALI_PHY_1105_DATA,
> + DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA, DENALI_PHY_1108_DATA,
> + DENALI_PHY_1109_DATA,
> + DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA, DENALI_PHY_1112_DATA,
> + DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA, DENALI_PHY_1115_DATA,
> + DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA, DENALI_PHY_1118_DATA,
> + DENALI_PHY_1119_DATA,
> + DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA, DENALI_PHY_1122_DATA,
> + DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA, DENALI_PHY_1125_DATA,
> + DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA, DENALI_PHY_1128_DATA,
> + DENALI_PHY_1129_DATA,
> + DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA, DENALI_PHY_1132_DATA,
> + DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA, DENALI_PHY_1135_DATA,
> + DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA, DENALI_PHY_1138_DATA,
> + DENALI_PHY_1139_DATA,
> + DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA, DENALI_PHY_1142_DATA,
> + DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA, DENALI_PHY_1145_DATA,
> + DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA, DENALI_PHY_1148_DATA,
> + DENALI_PHY_1149_DATA,
> + DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA, DENALI_PHY_1152_DATA,
> + DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA, DENALI_PHY_1155_DATA,
> + DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA, DENALI_PHY_1158_DATA,
> + DENALI_PHY_1159_DATA,
> + DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA, DENALI_PHY_1162_DATA,
> + DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA, DENALI_PHY_1165_DATA,
> + DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA, DENALI_PHY_1168_DATA,
> + DENALI_PHY_1169_DATA,
> + DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA, DENALI_PHY_1172_DATA,
> + DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA, DENALI_PHY_1175_DATA,
> + DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA, DENALI_PHY_1178_DATA,
> + DENALI_PHY_1179_DATA,
> + DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA, DENALI_PHY_1182_DATA,
> + DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA, DENALI_PHY_1185_DATA,
> + DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA, DENALI_PHY_1188_DATA,
> + DENALI_PHY_1189_DATA,
> + DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA, DENALI_PHY_1192_DATA,
> + DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA, DENALI_PHY_1195_DATA,
> + DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA, DENALI_PHY_1198_DATA,
> + DENALI_PHY_1199_DATA,
> +
> + DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA,
> + DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA,
> + DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA,
> + DENALI_PHY_1209_DATA,
> + DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA,
> + DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA
> +};
> +
> +u32 ddr_ctl_settings[265] = {
> + DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA,
> + DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA,
> + DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA,
> + DENALI_CTL_09_DATA,
> + DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA,
> + DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA,
> + DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA,
> + DENALI_CTL_19_DATA,
> + DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA,
> + DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA,
> + DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA,
> + DENALI_CTL_29_DATA,
> + DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA,
> + DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA,
> + DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA,
> + DENALI_CTL_39_DATA,
> + DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA,
> + DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA,
> + DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA,
> + DENALI_CTL_49_DATA,
> + DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA,
> + DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA,
> + DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA,
> + DENALI_CTL_59_DATA,
> + DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA,
> + DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA,
> + DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA,
> + DENALI_CTL_69_DATA,
> + DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA,
> + DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA,
> + DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA,
> + DENALI_CTL_79_DATA,
> + DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA,
> + DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA,
> + DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA,
> + DENALI_CTL_89_DATA,
> + DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA,
> + DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA,
> + DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA,
> + DENALI_CTL_99_DATA,
> +
> + DENALI_CTL_100_DATA, DENALI_CTL_101_DATA, DENALI_CTL_102_DATA,
> + DENALI_CTL_103_DATA, DENALI_CTL_104_DATA, DENALI_CTL_105_DATA,
> + DENALI_CTL_106_DATA, DENALI_CTL_107_DATA, DENALI_CTL_108_DATA,
> + DENALI_CTL_109_DATA,
> + DENALI_CTL_110_DATA, DENALI_CTL_111_DATA, DENALI_CTL_112_DATA,
> + DENALI_CTL_113_DATA, DENALI_CTL_114_DATA, DENALI_CTL_115_DATA,
> + DENALI_CTL_116_DATA, DENALI_CTL_117_DATA, DENALI_CTL_118_DATA,
> + DENALI_CTL_119_DATA,
> + DENALI_CTL_120_DATA, DENALI_CTL_121_DATA, DENALI_CTL_122_DATA,
> + DENALI_CTL_123_DATA, DENALI_CTL_124_DATA, DENALI_CTL_125_DATA,
> + DENALI_CTL_126_DATA, DENALI_CTL_127_DATA, DENALI_CTL_128_DATA,
> + DENALI_CTL_129_DATA,
> + DENALI_CTL_130_DATA, DENALI_CTL_131_DATA, DENALI_CTL_132_DATA,
> + DENALI_CTL_133_DATA, DENALI_CTL_134_DATA, DENALI_CTL_135_DATA,
> + DENALI_CTL_136_DATA, DENALI_CTL_137_DATA, DENALI_CTL_138_DATA,
> + DENALI_CTL_139_DATA,
> + DENALI_CTL_140_DATA, DENALI_CTL_141_DATA, DENALI_CTL_142_DATA,
> + DENALI_CTL_143_DATA, DENALI_CTL_144_DATA, DENALI_CTL_145_DATA,
> + DENALI_CTL_146_DATA, DENALI_CTL_147_DATA, DENALI_CTL_148_DATA,
> + DENALI_CTL_149_DATA,
> + DENALI_CTL_150_DATA, DENALI_CTL_151_DATA, DENALI_CTL_152_DATA,
> + DENALI_CTL_153_DATA, DENALI_CTL_154_DATA, DENALI_CTL_155_DATA,
> + DENALI_CTL_156_DATA, DENALI_CTL_157_DATA, DENALI_CTL_158_DATA,
> + DENALI_CTL_159_DATA,
> + DENALI_CTL_160_DATA, DENALI_CTL_161_DATA, DENALI_CTL_162_DATA,
> + DENALI_CTL_163_DATA, DENALI_CTL_164_DATA, DENALI_CTL_165_DATA,
> + DENALI_CTL_166_DATA, DENALI_CTL_167_DATA, DENALI_CTL_168_DATA,
> + DENALI_CTL_169_DATA,
> + DENALI_CTL_170_DATA, DENALI_CTL_171_DATA, DENALI_CTL_172_DATA,
> + DENALI_CTL_173_DATA, DENALI_CTL_174_DATA, DENALI_CTL_175_DATA,
> + DENALI_CTL_176_DATA, DENALI_CTL_177_DATA, DENALI_CTL_178_DATA,
> + DENALI_CTL_179_DATA,
> + DENALI_CTL_180_DATA, DENALI_CTL_181_DATA, DENALI_CTL_182_DATA,
> + DENALI_CTL_183_DATA, DENALI_CTL_184_DATA, DENALI_CTL_185_DATA,
> + DENALI_CTL_186_DATA, DENALI_CTL_187_DATA, DENALI_CTL_188_DATA,
> + DENALI_CTL_189_DATA,
> + DENALI_CTL_190_DATA, DENALI_CTL_191_DATA, DENALI_CTL_192_DATA,
> + DENALI_CTL_193_DATA, DENALI_CTL_194_DATA, DENALI_CTL_195_DATA,
> + DENALI_CTL_196_DATA, DENALI_CTL_197_DATA, DENALI_CTL_198_DATA,
> + DENALI_CTL_199_DATA,
> +
> + DENALI_CTL_200_DATA, DENALI_CTL_201_DATA, DENALI_CTL_202_DATA,
> + DENALI_CTL_203_DATA, DENALI_CTL_204_DATA, DENALI_CTL_205_DATA,
> + DENALI_CTL_206_DATA, DENALI_CTL_207_DATA, DENALI_CTL_208_DATA,
> + DENALI_CTL_209_DATA,
> + DENALI_CTL_210_DATA, DENALI_CTL_211_DATA, DENALI_CTL_212_DATA,
> + DENALI_CTL_213_DATA, DENALI_CTL_214_DATA, DENALI_CTL_215_DATA,
> + DENALI_CTL_216_DATA, DENALI_CTL_217_DATA, DENALI_CTL_218_DATA,
> + DENALI_CTL_219_DATA,
> + DENALI_CTL_220_DATA, DENALI_CTL_221_DATA, DENALI_CTL_222_DATA,
> + DENALI_CTL_223_DATA, DENALI_CTL_224_DATA, DENALI_CTL_225_DATA,
> + DENALI_CTL_226_DATA, DENALI_CTL_227_DATA, DENALI_CTL_228_DATA,
> + DENALI_CTL_229_DATA,
> + DENALI_CTL_230_DATA, DENALI_CTL_231_DATA, DENALI_CTL_232_DATA,
> + DENALI_CTL_233_DATA, DENALI_CTL_234_DATA, DENALI_CTL_235_DATA,
> + DENALI_CTL_236_DATA, DENALI_CTL_237_DATA, DENALI_CTL_238_DATA,
> + DENALI_CTL_239_DATA,
> + DENALI_CTL_240_DATA, DENALI_CTL_241_DATA, DENALI_CTL_242_DATA,
> + DENALI_CTL_243_DATA, DENALI_CTL_244_DATA, DENALI_CTL_245_DATA,
> + DENALI_CTL_246_DATA, DENALI_CTL_247_DATA, DENALI_CTL_248_DATA,
> + DENALI_CTL_249_DATA,
> + DENALI_CTL_250_DATA, DENALI_CTL_251_DATA, DENALI_CTL_252_DATA,
> + DENALI_CTL_253_DATA, DENALI_CTL_254_DATA, DENALI_CTL_255_DATA,
> + DENALI_CTL_256_DATA, DENALI_CTL_257_DATA, DENALI_CTL_258_DATA,
> + DENALI_CTL_259_DATA,
> + DENALI_CTL_260_DATA, DENALI_CTL_261_DATA, DENALI_CTL_262_DATA,
> + DENALI_CTL_263_DATA, DENALI_CTL_264_DATA
> +};
> diff --git a/board/sifive/fu540/regconfig-ctl.h b/board/sifive/fu540/regconfig-ctl.h
> new file mode 100644
> index 0000000000..b8f50f5b35
> --- /dev/null
> +++ b/board/sifive/fu540/regconfig-ctl.h
> @@ -0,0 +1,270 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#define DENALI_CTL_00_DATA 0x00000a00
> +#define DENALI_CTL_01_DATA 0x00000000
> +#define DENALI_CTL_02_DATA 0x00000000
> +#define DENALI_CTL_03_DATA 0x00000000
> +#define DENALI_CTL_04_DATA 0x00000000
> +#define DENALI_CTL_05_DATA 0x00000000
> +#define DENALI_CTL_06_DATA 0x0000000a
> +#define DENALI_CTL_07_DATA 0x0002d362
> +#define DENALI_CTL_08_DATA 0x00071073
> +#define DENALI_CTL_09_DATA 0x0a1c0255
> +#define DENALI_CTL_10_DATA 0x1c1c0400
> +#define DENALI_CTL_11_DATA 0x0404990b
> +#define DENALI_CTL_12_DATA 0x2b050405
> +#define DENALI_CTL_13_DATA 0x0e0c081e
> +#define DENALI_CTL_14_DATA 0x08090914
> +#define DENALI_CTL_15_DATA 0x00fde718
> +#define DENALI_CTL_16_DATA 0x00180a05
> +#define DENALI_CTL_17_DATA 0x008b130e
> +#define DENALI_CTL_18_DATA 0x01000118
> +#define DENALI_CTL_19_DATA 0x0e032101
> +#define DENALI_CTL_20_DATA 0x00000000
> +#define DENALI_CTL_21_DATA 0x00000101
> +#define DENALI_CTL_22_DATA 0x00000000
> +#define DENALI_CTL_23_DATA 0x0a000000
> +#define DENALI_CTL_24_DATA 0x00000000
> +#define DENALI_CTL_25_DATA 0x01450100
> +#define DENALI_CTL_26_DATA 0x00001c36
> +#define DENALI_CTL_27_DATA 0x00000005
> +#define DENALI_CTL_28_DATA 0x00170006
> +#define DENALI_CTL_29_DATA 0x014e0300
> +#define DENALI_CTL_30_DATA 0x03010000
> +#define DENALI_CTL_31_DATA 0x000a0e00
> +#define DENALI_CTL_32_DATA 0x04030200
> +#define DENALI_CTL_33_DATA 0x0000031f
> +#define DENALI_CTL_34_DATA 0x00070004
> +#define DENALI_CTL_35_DATA 0x00000000
> +#define DENALI_CTL_36_DATA 0x00000000
> +#define DENALI_CTL_37_DATA 0x00000000
> +#define DENALI_CTL_38_DATA 0x00000000
> +#define DENALI_CTL_39_DATA 0x00000000
> +#define DENALI_CTL_40_DATA 0x00000000
> +#define DENALI_CTL_41_DATA 0x00000000
> +#define DENALI_CTL_42_DATA 0x00000000
> +#define DENALI_CTL_43_DATA 0x00000000
> +#define DENALI_CTL_44_DATA 0x00000000
> +#define DENALI_CTL_45_DATA 0x00000000
> +#define DENALI_CTL_46_DATA 0x00000000
> +#define DENALI_CTL_47_DATA 0x00000000
> +#define DENALI_CTL_48_DATA 0x00000000
> +#define DENALI_CTL_49_DATA 0x00000000
> +#define DENALI_CTL_50_DATA 0x00000000
> +#define DENALI_CTL_51_DATA 0x00000000
> +#define DENALI_CTL_52_DATA 0x00000000
> +#define DENALI_CTL_53_DATA 0x00000000
> +#define DENALI_CTL_54_DATA 0x00000000
> +#define DENALI_CTL_55_DATA 0x00000000
> +#define DENALI_CTL_56_DATA 0x00000000
> +#define DENALI_CTL_57_DATA 0x00000000
> +#define DENALI_CTL_58_DATA 0x00000000
> +#define DENALI_CTL_59_DATA 0x00000000
> +#define DENALI_CTL_60_DATA 0x00000424
> +#define DENALI_CTL_61_DATA 0x00000201
> +#define DENALI_CTL_62_DATA 0x00001008
> +#define DENALI_CTL_63_DATA 0x00000000
> +#define DENALI_CTL_64_DATA 0x00000200
> +#define DENALI_CTL_65_DATA 0x00000000
> +#define DENALI_CTL_66_DATA 0x00000481
> +#define DENALI_CTL_67_DATA 0x00000400
> +#define DENALI_CTL_68_DATA 0x00000424
> +#define DENALI_CTL_69_DATA 0x00000201
> +#define DENALI_CTL_70_DATA 0x00001008
> +#define DENALI_CTL_71_DATA 0x00000000
> +#define DENALI_CTL_72_DATA 0x00000200
> +#define DENALI_CTL_73_DATA 0x00000000
> +#define DENALI_CTL_74_DATA 0x00000481
> +#define DENALI_CTL_75_DATA 0x00000400
> +#define DENALI_CTL_76_DATA 0x01010000
> +#define DENALI_CTL_77_DATA 0x00000000
> +#define DENALI_CTL_78_DATA 0x00000000
> +#define DENALI_CTL_79_DATA 0x00000000
> +#define DENALI_CTL_80_DATA 0x00000000
> +#define DENALI_CTL_81_DATA 0x00000000
> +#define DENALI_CTL_82_DATA 0x00000000
> +#define DENALI_CTL_83_DATA 0x00000000
> +#define DENALI_CTL_84_DATA 0x00000000
> +#define DENALI_CTL_85_DATA 0x00000000
> +#define DENALI_CTL_86_DATA 0x00000000
> +#define DENALI_CTL_87_DATA 0x00000000
> +#define DENALI_CTL_88_DATA 0x00000000
> +#define DENALI_CTL_89_DATA 0x00000000
> +#define DENALI_CTL_90_DATA 0x00000000
> +#define DENALI_CTL_91_DATA 0x00000000
> +#define DENALI_CTL_92_DATA 0x00000000
> +#define DENALI_CTL_93_DATA 0x00000000
> +#define DENALI_CTL_94_DATA 0x00000000
> +#define DENALI_CTL_95_DATA 0x00000000
> +#define DENALI_CTL_96_DATA 0x00000000
> +#define DENALI_CTL_97_DATA 0x00000000
> +#define DENALI_CTL_98_DATA 0x00000000
> +#define DENALI_CTL_99_DATA 0x00000000
> +#define DENALI_CTL_100_DATA 0x00000000
> +#define DENALI_CTL_101_DATA 0x00000000
> +#define DENALI_CTL_102_DATA 0x00000000
> +#define DENALI_CTL_103_DATA 0x00000000
> +#define DENALI_CTL_104_DATA 0x00000000
> +#define DENALI_CTL_105_DATA 0x00000003
> +#define DENALI_CTL_106_DATA 0x00000000
> +#define DENALI_CTL_107_DATA 0x00000000
> +#define DENALI_CTL_108_DATA 0x00000000
> +#define DENALI_CTL_109_DATA 0x00000000
> +#define DENALI_CTL_110_DATA 0x01000000
> +#define DENALI_CTL_111_DATA 0x00040000
> +#define DENALI_CTL_112_DATA 0x00800200
> +#define DENALI_CTL_113_DATA 0x00000200
> +#define DENALI_CTL_114_DATA 0x00000040
> +#define DENALI_CTL_115_DATA 0x01000100
> +#define DENALI_CTL_116_DATA 0x0a000002
> +#define DENALI_CTL_117_DATA 0x0101ffff
> +#define DENALI_CTL_118_DATA 0x01010101
> +#define DENALI_CTL_119_DATA 0x01010101
> +#define DENALI_CTL_120_DATA 0x0000010b
> +#define DENALI_CTL_121_DATA 0x00000c01
> +#define DENALI_CTL_122_DATA 0x00000000
> +#define DENALI_CTL_123_DATA 0x00000000
> +#define DENALI_CTL_124_DATA 0x00000000
> +#define DENALI_CTL_125_DATA 0x00000000
> +#define DENALI_CTL_126_DATA 0x00030300
> +#define DENALI_CTL_127_DATA 0x00000000
> +#define DENALI_CTL_128_DATA 0x00010001
> +#define DENALI_CTL_129_DATA 0x00000000
> +#define DENALI_CTL_130_DATA 0x00000000
> +#define DENALI_CTL_131_DATA 0x00000000
> +#define DENALI_CTL_132_DATA 0x00000000
> +#define DENALI_CTL_133_DATA 0x00000000
> +#define DENALI_CTL_134_DATA 0x00000000
> +#define DENALI_CTL_135_DATA 0x00000000
> +#define DENALI_CTL_136_DATA 0x00000000
> +#define DENALI_CTL_137_DATA 0x00000000
> +#define DENALI_CTL_138_DATA 0x00000000
> +#define DENALI_CTL_139_DATA 0x00000000
> +#define DENALI_CTL_140_DATA 0x00000000
> +#define DENALI_CTL_141_DATA 0x00000000
> +#define DENALI_CTL_142_DATA 0x00000000
> +#define DENALI_CTL_143_DATA 0x00000000
> +#define DENALI_CTL_144_DATA 0x00000000
> +#define DENALI_CTL_145_DATA 0x00000000
> +#define DENALI_CTL_146_DATA 0x00000000
> +#define DENALI_CTL_147_DATA 0x00000000
> +#define DENALI_CTL_148_DATA 0x00000000
> +#define DENALI_CTL_149_DATA 0x00000000
> +#define DENALI_CTL_150_DATA 0x00000000
> +#define DENALI_CTL_151_DATA 0x00000000
> +#define DENALI_CTL_152_DATA 0x00000000
> +#define DENALI_CTL_153_DATA 0x00000000
> +#define DENALI_CTL_154_DATA 0x00000000
> +#define DENALI_CTL_155_DATA 0x00000000
> +#define DENALI_CTL_156_DATA 0x00000000
> +#define DENALI_CTL_157_DATA 0x00000000
> +#define DENALI_CTL_158_DATA 0x00000000
> +#define DENALI_CTL_159_DATA 0x00000000
> +#define DENALI_CTL_160_DATA 0x00000000
> +#define DENALI_CTL_161_DATA 0x02010102
> +#define DENALI_CTL_162_DATA 0x0107070d
> +#define DENALI_CTL_163_DATA 0x04040400
> +#define DENALI_CTL_164_DATA 0x03000503
> +#define DENALI_CTL_165_DATA 0x00000000
> +#define DENALI_CTL_166_DATA 0x00000000
> +#define DENALI_CTL_167_DATA 0x00000000
> +#define DENALI_CTL_168_DATA 0x00000000
> +#define DENALI_CTL_169_DATA 0x280d0000
> +#define DENALI_CTL_170_DATA 0x01000000
> +#define DENALI_CTL_171_DATA 0x00000000
> +#define DENALI_CTL_172_DATA 0x00010001
> +#define DENALI_CTL_173_DATA 0x00000000
> +#define DENALI_CTL_174_DATA 0x00000000
> +#define DENALI_CTL_175_DATA 0x00000000
> +#define DENALI_CTL_176_DATA 0x00000000
> +#define DENALI_CTL_177_DATA 0x00000000
> +#define DENALI_CTL_178_DATA 0x00000000
> +#define DENALI_CTL_179_DATA 0x00000000
> +#define DENALI_CTL_180_DATA 0x00000000
> +#define DENALI_CTL_181_DATA 0x01000000
> +#define DENALI_CTL_182_DATA 0x00000001
> +#define DENALI_CTL_183_DATA 0x00000100
> +#define DENALI_CTL_184_DATA 0x00000101
> +#define DENALI_CTL_185_DATA 0x67676701
> +#define DENALI_CTL_186_DATA 0x67676767
> +#define DENALI_CTL_187_DATA 0x67676767
> +#define DENALI_CTL_188_DATA 0x67676767
> +#define DENALI_CTL_189_DATA 0x67676767
> +#define DENALI_CTL_190_DATA 0x67676767
> +#define DENALI_CTL_191_DATA 0x67676767
> +#define DENALI_CTL_192_DATA 0x67676767
> +#define DENALI_CTL_193_DATA 0x67676767
> +#define DENALI_CTL_194_DATA 0x01000067
> +#define DENALI_CTL_195_DATA 0x00000001
> +#define DENALI_CTL_196_DATA 0x00000101
> +#define DENALI_CTL_197_DATA 0x00000000
> +#define DENALI_CTL_198_DATA 0x00000000
> +#define DENALI_CTL_199_DATA 0x00000000
> +#define DENALI_CTL_200_DATA 0x00000000
> +#define DENALI_CTL_201_DATA 0x00000000
> +#define DENALI_CTL_202_DATA 0x00000000
> +#define DENALI_CTL_203_DATA 0x00000000
> +#define DENALI_CTL_204_DATA 0x00000000
> +#define DENALI_CTL_205_DATA 0x00000000
> +#define DENALI_CTL_206_DATA 0x00000000
> +#define DENALI_CTL_207_DATA 0x00000000
> +#define DENALI_CTL_208_DATA 0x00000001
> +#define DENALI_CTL_209_DATA 0x00000000
> +#define DENALI_CTL_210_DATA 0x007fffff
> +#define DENALI_CTL_211_DATA 0x00000000
> +#define DENALI_CTL_212_DATA 0x007fffff
> +#define DENALI_CTL_213_DATA 0x00000000
> +#define DENALI_CTL_214_DATA 0x007fffff
> +#define DENALI_CTL_215_DATA 0x00000000
> +#define DENALI_CTL_216_DATA 0x007fffff
> +#define DENALI_CTL_217_DATA 0x00000000
> +#define DENALI_CTL_218_DATA 0x007fffff
> +#define DENALI_CTL_219_DATA 0x00000000
> +#define DENALI_CTL_220_DATA 0x007fffff
> +#define DENALI_CTL_221_DATA 0x00000000
> +#define DENALI_CTL_222_DATA 0x007fffff
> +#define DENALI_CTL_223_DATA 0x00000000
> +#define DENALI_CTL_224_DATA 0x037fffff
> +#define DENALI_CTL_225_DATA 0xffffffff
> +#define DENALI_CTL_226_DATA 0x000f000f
> +#define DENALI_CTL_227_DATA 0x00ffff03
> +#define DENALI_CTL_228_DATA 0x000fffff
> +#define DENALI_CTL_229_DATA 0x0003000f
> +#define DENALI_CTL_230_DATA 0xffffffff
> +#define DENALI_CTL_231_DATA 0x000f000f
> +#define DENALI_CTL_232_DATA 0x00ffff03
> +#define DENALI_CTL_233_DATA 0x000fffff
> +#define DENALI_CTL_234_DATA 0x0003000f
> +#define DENALI_CTL_235_DATA 0xffffffff
> +#define DENALI_CTL_236_DATA 0x000f000f
> +#define DENALI_CTL_237_DATA 0x00ffff03
> +#define DENALI_CTL_238_DATA 0x000fffff
> +#define DENALI_CTL_239_DATA 0x0003000f
> +#define DENALI_CTL_240_DATA 0xffffffff
> +#define DENALI_CTL_241_DATA 0x000f000f
> +#define DENALI_CTL_242_DATA 0x00ffff03
> +#define DENALI_CTL_243_DATA 0x000fffff
> +#define DENALI_CTL_244_DATA 0x6407000f
> +#define DENALI_CTL_245_DATA 0x01640001
> +#define DENALI_CTL_246_DATA 0x00000000
> +#define DENALI_CTL_247_DATA 0x00000000
> +#define DENALI_CTL_248_DATA 0x00001700
> +#define DENALI_CTL_249_DATA 0x00386c05
> +#define DENALI_CTL_250_DATA 0x02000200
> +#define DENALI_CTL_251_DATA 0x02000200
> +#define DENALI_CTL_252_DATA 0x0000386c
> +#define DENALI_CTL_253_DATA 0x00023438
> +#define DENALI_CTL_254_DATA 0x02020d10
> +#define DENALI_CTL_255_DATA 0x00140303
> +#define DENALI_CTL_256_DATA 0x00000000
> +#define DENALI_CTL_257_DATA 0x00000000
> +#define DENALI_CTL_258_DATA 0x00001403
> +#define DENALI_CTL_259_DATA 0x00000000
> +#define DENALI_CTL_260_DATA 0x00000000
> +#define DENALI_CTL_261_DATA 0x00000000
> +#define DENALI_CTL_262_DATA 0x00000000
> +#define DENALI_CTL_263_DATA 0x0d010000
> +#define DENALI_CTL_264_DATA 0x00000008
> diff --git a/board/sifive/fu540/regconfig-phy.h b/board/sifive/fu540/regconfig-phy.h
> new file mode 100644
> index 0000000000..62163290b9
> --- /dev/null
> +++ b/board/sifive/fu540/regconfig-phy.h
> @@ -0,0 +1,1220 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#define DENALI_PHY_00_DATA 0x31706542
> +#define DENALI_PHY_01_DATA 0x0004c008
> +#define DENALI_PHY_02_DATA 0x000000da
> +#define DENALI_PHY_03_DATA 0x00000000
> +#define DENALI_PHY_04_DATA 0x00000000
> +#define DENALI_PHY_05_DATA 0x00010000
> +#define DENALI_PHY_06_DATA 0x01DDDD90
> +#define DENALI_PHY_07_DATA 0x01DDDD90
> +#define DENALI_PHY_08_DATA 0x01030000
> +#define DENALI_PHY_09_DATA 0x01000000
> +#define DENALI_PHY_10_DATA 0x00c00000
> +#define DENALI_PHY_11_DATA 0x00000007
> +#define DENALI_PHY_12_DATA 0x00000000
> +#define DENALI_PHY_13_DATA 0x00000000
> +#define DENALI_PHY_14_DATA 0x04000408
> +#define DENALI_PHY_15_DATA 0x00000408
> +#define DENALI_PHY_16_DATA 0x00e4e400
> +#define DENALI_PHY_17_DATA 0x00000000
> +#define DENALI_PHY_18_DATA 0x00000000
> +#define DENALI_PHY_19_DATA 0x00000000
> +#define DENALI_PHY_20_DATA 0x00000000
> +#define DENALI_PHY_21_DATA 0x00000000
> +#define DENALI_PHY_22_DATA 0x00000000
> +#define DENALI_PHY_23_DATA 0x00000000
> +#define DENALI_PHY_24_DATA 0x00000000
> +#define DENALI_PHY_25_DATA 0x00000000
> +#define DENALI_PHY_26_DATA 0x00000000
> +#define DENALI_PHY_27_DATA 0x00000000
> +#define DENALI_PHY_28_DATA 0x00000000
> +#define DENALI_PHY_29_DATA 0x00000000
> +#define DENALI_PHY_30_DATA 0x00000000
> +#define DENALI_PHY_31_DATA 0x00000000
> +#define DENALI_PHY_32_DATA 0x00000000
> +#define DENALI_PHY_33_DATA 0x00200000
> +#define DENALI_PHY_34_DATA 0x00000000
> +#define DENALI_PHY_35_DATA 0x00000000
> +#define DENALI_PHY_36_DATA 0x00000000
> +#define DENALI_PHY_37_DATA 0x00000000
> +#define DENALI_PHY_38_DATA 0x00000000
> +#define DENALI_PHY_39_DATA 0x00000000
> +#define DENALI_PHY_40_DATA 0x02800280
> +#define DENALI_PHY_41_DATA 0x02800280
> +#define DENALI_PHY_42_DATA 0x02800280
> +#define DENALI_PHY_43_DATA 0x02800280
> +#define DENALI_PHY_44_DATA 0x00000280
> +#define DENALI_PHY_45_DATA 0x00000000
> +#define DENALI_PHY_46_DATA 0x00000000
> +#define DENALI_PHY_47_DATA 0x00000000
> +#define DENALI_PHY_48_DATA 0x00000000
> +#define DENALI_PHY_49_DATA 0x00000000
> +#define DENALI_PHY_50_DATA 0x00800080
> +#define DENALI_PHY_51_DATA 0x00800080
> +#define DENALI_PHY_52_DATA 0x00800080
> +#define DENALI_PHY_53_DATA 0x00800080
> +#define DENALI_PHY_54_DATA 0x00800080
> +#define DENALI_PHY_55_DATA 0x00800080
> +#define DENALI_PHY_56_DATA 0x00800080
> +#define DENALI_PHY_57_DATA 0x00800080
> +#define DENALI_PHY_58_DATA 0x00800080
> +#define DENALI_PHY_59_DATA 0x000100da
> +#define DENALI_PHY_60_DATA 0x01000200
> +#define DENALI_PHY_61_DATA 0x00000000
> +#define DENALI_PHY_62_DATA 0x00000000
> +#define DENALI_PHY_63_DATA 0x00000002
> +#define DENALI_PHY_64_DATA 0x51313152
> +#define DENALI_PHY_65_DATA 0x80013130
> +#define DENALI_PHY_66_DATA 0x02000080
> +#define DENALI_PHY_67_DATA 0x00100001
> +#define DENALI_PHY_68_DATA 0x0c064208
> +#define DENALI_PHY_69_DATA 0x000f0c0f
> +#define DENALI_PHY_70_DATA 0x01000140
> +#define DENALI_PHY_71_DATA 0x0000000c
> +#define DENALI_PHY_72_DATA 0x00000000
> +#define DENALI_PHY_73_DATA 0x00000000
> +#define DENALI_PHY_74_DATA 0x00000000
> +#define DENALI_PHY_75_DATA 0x00000000
> +#define DENALI_PHY_76_DATA 0x00000000
> +#define DENALI_PHY_77_DATA 0x00000000
> +#define DENALI_PHY_78_DATA 0x00000000
> +#define DENALI_PHY_79_DATA 0x00000000
> +#define DENALI_PHY_80_DATA 0x00000000
> +#define DENALI_PHY_81_DATA 0x00000000
> +#define DENALI_PHY_82_DATA 0x00000000
> +#define DENALI_PHY_83_DATA 0x00000000
> +#define DENALI_PHY_84_DATA 0x00000000
> +#define DENALI_PHY_85_DATA 0x00000000
> +#define DENALI_PHY_86_DATA 0x00000000
> +#define DENALI_PHY_87_DATA 0x00000000
> +#define DENALI_PHY_88_DATA 0x00000000
> +#define DENALI_PHY_89_DATA 0x00000000
> +#define DENALI_PHY_90_DATA 0x00000000
> +#define DENALI_PHY_91_DATA 0x00000000
> +#define DENALI_PHY_92_DATA 0x00000000
> +#define DENALI_PHY_93_DATA 0x00000000
> +#define DENALI_PHY_94_DATA 0x00000000
> +#define DENALI_PHY_95_DATA 0x00000000
> +#define DENALI_PHY_96_DATA 0x00000000
> +#define DENALI_PHY_97_DATA 0x00000000
> +#define DENALI_PHY_98_DATA 0x00000000
> +#define DENALI_PHY_99_DATA 0x00000000
> +#define DENALI_PHY_100_DATA 0x00000000
> +#define DENALI_PHY_101_DATA 0x00000000
> +#define DENALI_PHY_102_DATA 0x00000000
> +#define DENALI_PHY_103_DATA 0x00000000
> +#define DENALI_PHY_104_DATA 0x00000000
> +#define DENALI_PHY_105_DATA 0x00000000
> +#define DENALI_PHY_106_DATA 0x00000000
> +#define DENALI_PHY_107_DATA 0x00000000
> +#define DENALI_PHY_108_DATA 0x00000000
> +#define DENALI_PHY_109_DATA 0x00000000
> +#define DENALI_PHY_110_DATA 0x00000000
> +#define DENALI_PHY_111_DATA 0x00000000
> +#define DENALI_PHY_112_DATA 0x00000000
> +#define DENALI_PHY_113_DATA 0x00000000
> +#define DENALI_PHY_114_DATA 0x00000000
> +#define DENALI_PHY_115_DATA 0x00000000
> +#define DENALI_PHY_116_DATA 0x00000000
> +#define DENALI_PHY_117_DATA 0x00000000
> +#define DENALI_PHY_118_DATA 0x00000000
> +#define DENALI_PHY_119_DATA 0x00000000
> +#define DENALI_PHY_120_DATA 0x00000000
> +#define DENALI_PHY_121_DATA 0x00000000
> +#define DENALI_PHY_122_DATA 0x00000000
> +#define DENALI_PHY_123_DATA 0x00000000
> +#define DENALI_PHY_124_DATA 0x00000000
> +#define DENALI_PHY_125_DATA 0x00000000
> +#define DENALI_PHY_126_DATA 0x00000000
> +#define DENALI_PHY_127_DATA 0x00000000
> +#define DENALI_PHY_128_DATA 0x40263571
> +#define DENALI_PHY_129_DATA 0x0004c008
> +#define DENALI_PHY_130_DATA 0x000000da
> +#define DENALI_PHY_131_DATA 0x00000000
> +#define DENALI_PHY_132_DATA 0x00000000
> +#define DENALI_PHY_133_DATA 0x00010000
> +#define DENALI_PHY_134_DATA 0x01DDDD90
> +#define DENALI_PHY_135_DATA 0x01DDDD90
> +#define DENALI_PHY_136_DATA 0x01030000
> +#define DENALI_PHY_137_DATA 0x01000000
> +#define DENALI_PHY_138_DATA 0x00c00000
> +#define DENALI_PHY_139_DATA 0x00000007
> +#define DENALI_PHY_140_DATA 0x00000000
> +#define DENALI_PHY_141_DATA 0x00000000
> +#define DENALI_PHY_142_DATA 0x04000408
> +#define DENALI_PHY_143_DATA 0x00000408
> +#define DENALI_PHY_144_DATA 0x00e4e400
> +#define DENALI_PHY_145_DATA 0x00000000
> +#define DENALI_PHY_146_DATA 0x00000000
> +#define DENALI_PHY_147_DATA 0x00000000
> +#define DENALI_PHY_148_DATA 0x00000000
> +#define DENALI_PHY_149_DATA 0x00000000
> +#define DENALI_PHY_150_DATA 0x00000000
> +#define DENALI_PHY_151_DATA 0x00000000
> +#define DENALI_PHY_152_DATA 0x00000000
> +#define DENALI_PHY_153_DATA 0x00000000
> +#define DENALI_PHY_154_DATA 0x00000000
> +#define DENALI_PHY_155_DATA 0x00000000
> +#define DENALI_PHY_156_DATA 0x00000000
> +#define DENALI_PHY_157_DATA 0x00000000
> +#define DENALI_PHY_158_DATA 0x00000000
> +#define DENALI_PHY_159_DATA 0x00000000
> +#define DENALI_PHY_160_DATA 0x00000000
> +#define DENALI_PHY_161_DATA 0x00200000
> +#define DENALI_PHY_162_DATA 0x00000000
> +#define DENALI_PHY_163_DATA 0x00000000
> +#define DENALI_PHY_164_DATA 0x00000000
> +#define DENALI_PHY_165_DATA 0x00000000
> +#define DENALI_PHY_166_DATA 0x00000000
> +#define DENALI_PHY_167_DATA 0x00000000
> +#define DENALI_PHY_168_DATA 0x02800280
> +#define DENALI_PHY_169_DATA 0x02800280
> +#define DENALI_PHY_170_DATA 0x02800280
> +#define DENALI_PHY_171_DATA 0x02800280
> +#define DENALI_PHY_172_DATA 0x00000280
> +#define DENALI_PHY_173_DATA 0x00000000
> +#define DENALI_PHY_174_DATA 0x00000000
> +#define DENALI_PHY_175_DATA 0x00000000
> +#define DENALI_PHY_176_DATA 0x00000000
> +#define DENALI_PHY_177_DATA 0x00000000
> +#define DENALI_PHY_178_DATA 0x00800080
> +#define DENALI_PHY_179_DATA 0x00800080
> +#define DENALI_PHY_180_DATA 0x00800080
> +#define DENALI_PHY_181_DATA 0x00800080
> +#define DENALI_PHY_182_DATA 0x00800080
> +#define DENALI_PHY_183_DATA 0x00800080
> +#define DENALI_PHY_184_DATA 0x00800080
> +#define DENALI_PHY_185_DATA 0x00800080
> +#define DENALI_PHY_186_DATA 0x00800080
> +#define DENALI_PHY_187_DATA 0x000100da
> +#define DENALI_PHY_188_DATA 0x01000200
> +#define DENALI_PHY_189_DATA 0x00000000
> +#define DENALI_PHY_190_DATA 0x00000000
> +#define DENALI_PHY_191_DATA 0x00000002
> +#define DENALI_PHY_192_DATA 0x51313152
> +#define DENALI_PHY_193_DATA 0x80013130
> +#define DENALI_PHY_194_DATA 0x02000080
> +#define DENALI_PHY_195_DATA 0x00100001
> +#define DENALI_PHY_196_DATA 0x0c064208
> +#define DENALI_PHY_197_DATA 0x000f0c0f
> +#define DENALI_PHY_198_DATA 0x01000140
> +#define DENALI_PHY_199_DATA 0x0000000c
> +#define DENALI_PHY_200_DATA 0x00000000
> +#define DENALI_PHY_201_DATA 0x00000000
> +#define DENALI_PHY_202_DATA 0x00000000
> +#define DENALI_PHY_203_DATA 0x00000000
> +#define DENALI_PHY_204_DATA 0x00000000
> +#define DENALI_PHY_205_DATA 0x00000000
> +#define DENALI_PHY_206_DATA 0x00000000
> +#define DENALI_PHY_207_DATA 0x00000000
> +#define DENALI_PHY_208_DATA 0x00000000
> +#define DENALI_PHY_209_DATA 0x00000000
> +#define DENALI_PHY_210_DATA 0x00000000
> +#define DENALI_PHY_211_DATA 0x00000000
> +#define DENALI_PHY_212_DATA 0x00000000
> +#define DENALI_PHY_213_DATA 0x00000000
> +#define DENALI_PHY_214_DATA 0x00000000
> +#define DENALI_PHY_215_DATA 0x00000000
> +#define DENALI_PHY_216_DATA 0x00000000
> +#define DENALI_PHY_217_DATA 0x00000000
> +#define DENALI_PHY_218_DATA 0x00000000
> +#define DENALI_PHY_219_DATA 0x00000000
> +#define DENALI_PHY_220_DATA 0x00000000
> +#define DENALI_PHY_221_DATA 0x00000000
> +#define DENALI_PHY_222_DATA 0x00000000
> +#define DENALI_PHY_223_DATA 0x00000000
> +#define DENALI_PHY_224_DATA 0x00000000
> +#define DENALI_PHY_225_DATA 0x00000000
> +#define DENALI_PHY_226_DATA 0x00000000
> +#define DENALI_PHY_227_DATA 0x00000000
> +#define DENALI_PHY_228_DATA 0x00000000
> +#define DENALI_PHY_229_DATA 0x00000000
> +#define DENALI_PHY_230_DATA 0x00000000
> +#define DENALI_PHY_231_DATA 0x00000000
> +#define DENALI_PHY_232_DATA 0x00000000
> +#define DENALI_PHY_233_DATA 0x00000000
> +#define DENALI_PHY_234_DATA 0x00000000
> +#define DENALI_PHY_235_DATA 0x00000000
> +#define DENALI_PHY_236_DATA 0x00000000
> +#define DENALI_PHY_237_DATA 0x00000000
> +#define DENALI_PHY_238_DATA 0x00000000
> +#define DENALI_PHY_239_DATA 0x00000000
> +#define DENALI_PHY_240_DATA 0x00000000
> +#define DENALI_PHY_241_DATA 0x00000000
> +#define DENALI_PHY_242_DATA 0x00000000
> +#define DENALI_PHY_243_DATA 0x00000000
> +#define DENALI_PHY_244_DATA 0x00000000
> +#define DENALI_PHY_245_DATA 0x00000000
> +#define DENALI_PHY_246_DATA 0x00000000
> +#define DENALI_PHY_247_DATA 0x00000000
> +#define DENALI_PHY_248_DATA 0x00000000
> +#define DENALI_PHY_249_DATA 0x00000000
> +#define DENALI_PHY_250_DATA 0x00000000
> +#define DENALI_PHY_251_DATA 0x00000000
> +#define DENALI_PHY_252_DATA 0x00000000
> +#define DENALI_PHY_253_DATA 0x00000000
> +#define DENALI_PHY_254_DATA 0x00000000
> +#define DENALI_PHY_255_DATA 0x00000000
> +#define DENALI_PHY_256_DATA 0x46052371
> +#define DENALI_PHY_257_DATA 0x0004c008
> +#define DENALI_PHY_258_DATA 0x000000da
> +#define DENALI_PHY_259_DATA 0x00000000
> +#define DENALI_PHY_260_DATA 0x00000000
> +#define DENALI_PHY_261_DATA 0x00010000
> +#define DENALI_PHY_262_DATA 0x01DDDD90
> +#define DENALI_PHY_263_DATA 0x01DDDD90
> +#define DENALI_PHY_264_DATA 0x01030000
> +#define DENALI_PHY_265_DATA 0x01000000
> +#define DENALI_PHY_266_DATA 0x00c00000
> +#define DENALI_PHY_267_DATA 0x00000007
> +#define DENALI_PHY_268_DATA 0x00000000
> +#define DENALI_PHY_269_DATA 0x00000000
> +#define DENALI_PHY_270_DATA 0x04000408
> +#define DENALI_PHY_271_DATA 0x00000408
> +#define DENALI_PHY_272_DATA 0x00e4e400
> +#define DENALI_PHY_273_DATA 0x00000000
> +#define DENALI_PHY_274_DATA 0x00000000
> +#define DENALI_PHY_275_DATA 0x00000000
> +#define DENALI_PHY_276_DATA 0x00000000
> +#define DENALI_PHY_277_DATA 0x00000000
> +#define DENALI_PHY_278_DATA 0x00000000
> +#define DENALI_PHY_279_DATA 0x00000000
> +#define DENALI_PHY_280_DATA 0x00000000
> +#define DENALI_PHY_281_DATA 0x00000000
> +#define DENALI_PHY_282_DATA 0x00000000
> +#define DENALI_PHY_283_DATA 0x00000000
> +#define DENALI_PHY_284_DATA 0x00000000
> +#define DENALI_PHY_285_DATA 0x00000000
> +#define DENALI_PHY_286_DATA 0x00000000
> +#define DENALI_PHY_287_DATA 0x00000000
> +#define DENALI_PHY_288_DATA 0x00000000
> +#define DENALI_PHY_289_DATA 0x00200000
> +#define DENALI_PHY_290_DATA 0x00000000
> +#define DENALI_PHY_291_DATA 0x00000000
> +#define DENALI_PHY_292_DATA 0x00000000
> +#define DENALI_PHY_293_DATA 0x00000000
> +#define DENALI_PHY_294_DATA 0x00000000
> +#define DENALI_PHY_295_DATA 0x00000000
> +#define DENALI_PHY_296_DATA 0x02800280
> +#define DENALI_PHY_297_DATA 0x02800280
> +#define DENALI_PHY_298_DATA 0x02800280
> +#define DENALI_PHY_299_DATA 0x02800280
> +#define DENALI_PHY_300_DATA 0x00000280
> +#define DENALI_PHY_301_DATA 0x00000000
> +#define DENALI_PHY_302_DATA 0x00000000
> +#define DENALI_PHY_303_DATA 0x00000000
> +#define DENALI_PHY_304_DATA 0x00000000
> +#define DENALI_PHY_305_DATA 0x00000000
> +#define DENALI_PHY_306_DATA 0x00800080
> +#define DENALI_PHY_307_DATA 0x00800080
> +#define DENALI_PHY_308_DATA 0x00800080
> +#define DENALI_PHY_309_DATA 0x00800080
> +#define DENALI_PHY_310_DATA 0x00800080
> +#define DENALI_PHY_311_DATA 0x00800080
> +#define DENALI_PHY_312_DATA 0x00800080
> +#define DENALI_PHY_313_DATA 0x00800080
> +#define DENALI_PHY_314_DATA 0x00800080
> +#define DENALI_PHY_315_DATA 0x000100da
> +#define DENALI_PHY_316_DATA 0x00000200
> +#define DENALI_PHY_317_DATA 0x00000000
> +#define DENALI_PHY_318_DATA 0x00000000
> +#define DENALI_PHY_319_DATA 0x00000002
> +#define DENALI_PHY_320_DATA 0x51313152
> +#define DENALI_PHY_321_DATA 0x80013130
> +#define DENALI_PHY_322_DATA 0x02000080
> +#define DENALI_PHY_323_DATA 0x00100001
> +#define DENALI_PHY_324_DATA 0x0c064208
> +#define DENALI_PHY_325_DATA 0x000f0c0f
> +#define DENALI_PHY_326_DATA 0x01000140
> +#define DENALI_PHY_327_DATA 0x0000000c
> +#define DENALI_PHY_328_DATA 0x00000000
> +#define DENALI_PHY_329_DATA 0x00000000
> +#define DENALI_PHY_330_DATA 0x00000000
> +#define DENALI_PHY_331_DATA 0x00000000
> +#define DENALI_PHY_332_DATA 0x00000000
> +#define DENALI_PHY_333_DATA 0x00000000
> +#define DENALI_PHY_334_DATA 0x00000000
> +#define DENALI_PHY_335_DATA 0x00000000
> +#define DENALI_PHY_336_DATA 0x00000000
> +#define DENALI_PHY_337_DATA 0x00000000
> +#define DENALI_PHY_338_DATA 0x00000000
> +#define DENALI_PHY_339_DATA 0x00000000
> +#define DENALI_PHY_340_DATA 0x00000000
> +#define DENALI_PHY_341_DATA 0x00000000
> +#define DENALI_PHY_342_DATA 0x00000000
> +#define DENALI_PHY_343_DATA 0x00000000
> +#define DENALI_PHY_344_DATA 0x00000000
> +#define DENALI_PHY_345_DATA 0x00000000
> +#define DENALI_PHY_346_DATA 0x00000000
> +#define DENALI_PHY_347_DATA 0x00000000
> +#define DENALI_PHY_348_DATA 0x00000000
> +#define DENALI_PHY_349_DATA 0x00000000
> +#define DENALI_PHY_350_DATA 0x00000000
> +#define DENALI_PHY_351_DATA 0x00000000
> +#define DENALI_PHY_352_DATA 0x00000000
> +#define DENALI_PHY_353_DATA 0x00000000
> +#define DENALI_PHY_354_DATA 0x00000000
> +#define DENALI_PHY_355_DATA 0x00000000
> +#define DENALI_PHY_356_DATA 0x00000000
> +#define DENALI_PHY_357_DATA 0x00000000
> +#define DENALI_PHY_358_DATA 0x00000000
> +#define DENALI_PHY_359_DATA 0x00000000
> +#define DENALI_PHY_360_DATA 0x00000000
> +#define DENALI_PHY_361_DATA 0x00000000
> +#define DENALI_PHY_362_DATA 0x00000000
> +#define DENALI_PHY_363_DATA 0x00000000
> +#define DENALI_PHY_364_DATA 0x00000000
> +#define DENALI_PHY_365_DATA 0x00000000
> +#define DENALI_PHY_366_DATA 0x00000000
> +#define DENALI_PHY_367_DATA 0x00000000
> +#define DENALI_PHY_368_DATA 0x00000000
> +#define DENALI_PHY_369_DATA 0x00000000
> +#define DENALI_PHY_370_DATA 0x00000000
> +#define DENALI_PHY_371_DATA 0x00000000
> +#define DENALI_PHY_372_DATA 0x00000000
> +#define DENALI_PHY_373_DATA 0x00000000
> +#define DENALI_PHY_374_DATA 0x00000000
> +#define DENALI_PHY_375_DATA 0x00000000
> +#define DENALI_PHY_376_DATA 0x00000000
> +#define DENALI_PHY_377_DATA 0x00000000
> +#define DENALI_PHY_378_DATA 0x00000000
> +#define DENALI_PHY_379_DATA 0x00000000
> +#define DENALI_PHY_380_DATA 0x00000000
> +#define DENALI_PHY_381_DATA 0x00000000
> +#define DENALI_PHY_382_DATA 0x00000000
> +#define DENALI_PHY_383_DATA 0x00000000
> +#define DENALI_PHY_384_DATA 0x37654120
> +#define DENALI_PHY_385_DATA 0x0004c008
> +#define DENALI_PHY_386_DATA 0x000000da
> +#define DENALI_PHY_387_DATA 0x00000000
> +#define DENALI_PHY_388_DATA 0x00000000
> +#define DENALI_PHY_389_DATA 0x00010000
> +#define DENALI_PHY_390_DATA 0x01DDDD90
> +#define DENALI_PHY_391_DATA 0x01DDDD90
> +#define DENALI_PHY_392_DATA 0x01030000
> +#define DENALI_PHY_393_DATA 0x01000000
> +#define DENALI_PHY_394_DATA 0x00c00000
> +#define DENALI_PHY_395_DATA 0x00000007
> +#define DENALI_PHY_396_DATA 0x00000000
> +#define DENALI_PHY_397_DATA 0x00000000
> +#define DENALI_PHY_398_DATA 0x04000408
> +#define DENALI_PHY_399_DATA 0x00000408
> +#define DENALI_PHY_400_DATA 0x00e4e400
> +#define DENALI_PHY_401_DATA 0x00000000
> +#define DENALI_PHY_402_DATA 0x00000000
> +#define DENALI_PHY_403_DATA 0x00000000
> +#define DENALI_PHY_404_DATA 0x00000000
> +#define DENALI_PHY_405_DATA 0x00000000
> +#define DENALI_PHY_406_DATA 0x00000000
> +#define DENALI_PHY_407_DATA 0x00000000
> +#define DENALI_PHY_408_DATA 0x00000000
> +#define DENALI_PHY_409_DATA 0x00000000
> +#define DENALI_PHY_410_DATA 0x00000000
> +#define DENALI_PHY_411_DATA 0x00000000
> +#define DENALI_PHY_412_DATA 0x00000000
> +#define DENALI_PHY_413_DATA 0x00000000
> +#define DENALI_PHY_414_DATA 0x00000000
> +#define DENALI_PHY_415_DATA 0x00000000
> +#define DENALI_PHY_416_DATA 0x00000000
> +#define DENALI_PHY_417_DATA 0x00200000
> +#define DENALI_PHY_418_DATA 0x00000000
> +#define DENALI_PHY_419_DATA 0x00000000
> +#define DENALI_PHY_420_DATA 0x00000000
> +#define DENALI_PHY_421_DATA 0x00000000
> +#define DENALI_PHY_422_DATA 0x00000000
> +#define DENALI_PHY_423_DATA 0x00000000
> +#define DENALI_PHY_424_DATA 0x02800280
> +#define DENALI_PHY_425_DATA 0x02800280
> +#define DENALI_PHY_426_DATA 0x02800280
> +#define DENALI_PHY_427_DATA 0x02800280
> +#define DENALI_PHY_428_DATA 0x00000280
> +#define DENALI_PHY_429_DATA 0x00000000
> +#define DENALI_PHY_430_DATA 0x00000000
> +#define DENALI_PHY_431_DATA 0x00000000
> +#define DENALI_PHY_432_DATA 0x00000000
> +#define DENALI_PHY_433_DATA 0x00000000
> +#define DENALI_PHY_434_DATA 0x00800080
> +#define DENALI_PHY_435_DATA 0x00800080
> +#define DENALI_PHY_436_DATA 0x00800080
> +#define DENALI_PHY_437_DATA 0x00800080
> +#define DENALI_PHY_438_DATA 0x00800080
> +#define DENALI_PHY_439_DATA 0x00800080
> +#define DENALI_PHY_440_DATA 0x00800080
> +#define DENALI_PHY_441_DATA 0x00800080
> +#define DENALI_PHY_442_DATA 0x00800080
> +#define DENALI_PHY_443_DATA 0x000100da
> +#define DENALI_PHY_444_DATA 0x00000200
> +#define DENALI_PHY_445_DATA 0x00000000
> +#define DENALI_PHY_446_DATA 0x00000000
> +#define DENALI_PHY_447_DATA 0x00000002
> +#define DENALI_PHY_448_DATA 0x51313152
> +#define DENALI_PHY_449_DATA 0x80013130
> +#define DENALI_PHY_450_DATA 0x02000080
> +#define DENALI_PHY_451_DATA 0x00100001
> +#define DENALI_PHY_452_DATA 0x0c064208
> +#define DENALI_PHY_453_DATA 0x000f0c0f
> +#define DENALI_PHY_454_DATA 0x01000140
> +#define DENALI_PHY_455_DATA 0x0000000c
> +#define DENALI_PHY_456_DATA 0x00000000
> +#define DENALI_PHY_457_DATA 0x00000000
> +#define DENALI_PHY_458_DATA 0x00000000
> +#define DENALI_PHY_459_DATA 0x00000000
> +#define DENALI_PHY_460_DATA 0x00000000
> +#define DENALI_PHY_461_DATA 0x00000000
> +#define DENALI_PHY_462_DATA 0x00000000
> +#define DENALI_PHY_463_DATA 0x00000000
> +#define DENALI_PHY_464_DATA 0x00000000
> +#define DENALI_PHY_465_DATA 0x00000000
> +#define DENALI_PHY_466_DATA 0x00000000
> +#define DENALI_PHY_467_DATA 0x00000000
> +#define DENALI_PHY_468_DATA 0x00000000
> +#define DENALI_PHY_469_DATA 0x00000000
> +#define DENALI_PHY_470_DATA 0x00000000
> +#define DENALI_PHY_471_DATA 0x00000000
> +#define DENALI_PHY_472_DATA 0x00000000
> +#define DENALI_PHY_473_DATA 0x00000000
> +#define DENALI_PHY_474_DATA 0x00000000
> +#define DENALI_PHY_475_DATA 0x00000000
> +#define DENALI_PHY_476_DATA 0x00000000
> +#define DENALI_PHY_477_DATA 0x00000000
> +#define DENALI_PHY_478_DATA 0x00000000
> +#define DENALI_PHY_479_DATA 0x00000000
> +#define DENALI_PHY_480_DATA 0x00000000
> +#define DENALI_PHY_481_DATA 0x00000000
> +#define DENALI_PHY_482_DATA 0x00000000
> +#define DENALI_PHY_483_DATA 0x00000000
> +#define DENALI_PHY_484_DATA 0x00000000
> +#define DENALI_PHY_485_DATA 0x00000000
> +#define DENALI_PHY_486_DATA 0x00000000
> +#define DENALI_PHY_487_DATA 0x00000000
> +#define DENALI_PHY_488_DATA 0x00000000
> +#define DENALI_PHY_489_DATA 0x00000000
> +#define DENALI_PHY_490_DATA 0x00000000
> +#define DENALI_PHY_491_DATA 0x00000000
> +#define DENALI_PHY_492_DATA 0x00000000
> +#define DENALI_PHY_493_DATA 0x00000000
> +#define DENALI_PHY_494_DATA 0x00000000
> +#define DENALI_PHY_495_DATA 0x00000000
> +#define DENALI_PHY_496_DATA 0x00000000
> +#define DENALI_PHY_497_DATA 0x00000000
> +#define DENALI_PHY_498_DATA 0x00000000
> +#define DENALI_PHY_499_DATA 0x00000000
> +#define DENALI_PHY_500_DATA 0x00000000
> +#define DENALI_PHY_501_DATA 0x00000000
> +#define DENALI_PHY_502_DATA 0x00000000
> +#define DENALI_PHY_503_DATA 0x00000000
> +#define DENALI_PHY_504_DATA 0x00000000
> +#define DENALI_PHY_505_DATA 0x00000000
> +#define DENALI_PHY_506_DATA 0x00000000
> +#define DENALI_PHY_507_DATA 0x00000000
> +#define DENALI_PHY_508_DATA 0x00000000
> +#define DENALI_PHY_509_DATA 0x00000000
> +#define DENALI_PHY_510_DATA 0x00000000
> +#define DENALI_PHY_511_DATA 0x00000000
> +#define DENALI_PHY_512_DATA 0x24316750
> +#define DENALI_PHY_513_DATA 0x0004c008
> +#define DENALI_PHY_514_DATA 0x000000da
> +#define DENALI_PHY_515_DATA 0x00000000
> +#define DENALI_PHY_516_DATA 0x00000000
> +#define DENALI_PHY_517_DATA 0x00010000
> +#define DENALI_PHY_518_DATA 0x01DDDD90
> +#define DENALI_PHY_519_DATA 0x01DDDD90
> +#define DENALI_PHY_520_DATA 0x01030000
> +#define DENALI_PHY_521_DATA 0x01000000
> +#define DENALI_PHY_522_DATA 0x00c00000
> +#define DENALI_PHY_523_DATA 0x00000007
> +#define DENALI_PHY_524_DATA 0x00000000
> +#define DENALI_PHY_525_DATA 0x00000000
> +#define DENALI_PHY_526_DATA 0x04000408
> +#define DENALI_PHY_527_DATA 0x00000408
> +#define DENALI_PHY_528_DATA 0x00e4e400
> +#define DENALI_PHY_529_DATA 0x00000000
> +#define DENALI_PHY_530_DATA 0x00000000
> +#define DENALI_PHY_531_DATA 0x00000000
> +#define DENALI_PHY_532_DATA 0x00000000
> +#define DENALI_PHY_533_DATA 0x00000000
> +#define DENALI_PHY_534_DATA 0x00000000
> +#define DENALI_PHY_535_DATA 0x00000000
> +#define DENALI_PHY_536_DATA 0x00000000
> +#define DENALI_PHY_537_DATA 0x00000000
> +#define DENALI_PHY_538_DATA 0x00000000
> +#define DENALI_PHY_539_DATA 0x00000000
> +#define DENALI_PHY_540_DATA 0x00000000
> +#define DENALI_PHY_541_DATA 0x00000000
> +#define DENALI_PHY_542_DATA 0x00000000
> +#define DENALI_PHY_543_DATA 0x00000000
> +#define DENALI_PHY_544_DATA 0x00000000
> +#define DENALI_PHY_545_DATA 0x00200000
> +#define DENALI_PHY_546_DATA 0x00000000
> +#define DENALI_PHY_547_DATA 0x00000000
> +#define DENALI_PHY_548_DATA 0x00000000
> +#define DENALI_PHY_549_DATA 0x00000000
> +#define DENALI_PHY_550_DATA 0x00000000
> +#define DENALI_PHY_551_DATA 0x00000000
> +#define DENALI_PHY_552_DATA 0x02800280
> +#define DENALI_PHY_553_DATA 0x02800280
> +#define DENALI_PHY_554_DATA 0x02800280
> +#define DENALI_PHY_555_DATA 0x02800280
> +#define DENALI_PHY_556_DATA 0x00000280
> +#define DENALI_PHY_557_DATA 0x00000000
> +#define DENALI_PHY_558_DATA 0x00000000
> +#define DENALI_PHY_559_DATA 0x00000000
> +#define DENALI_PHY_560_DATA 0x00000000
> +#define DENALI_PHY_561_DATA 0x00000000
> +#define DENALI_PHY_562_DATA 0x00800080
> +#define DENALI_PHY_563_DATA 0x00800080
> +#define DENALI_PHY_564_DATA 0x00800080
> +#define DENALI_PHY_565_DATA 0x00800080
> +#define DENALI_PHY_566_DATA 0x00800080
> +#define DENALI_PHY_567_DATA 0x00800080
> +#define DENALI_PHY_568_DATA 0x00800080
> +#define DENALI_PHY_569_DATA 0x00800080
> +#define DENALI_PHY_570_DATA 0x00800080
> +#define DENALI_PHY_571_DATA 0x000100da
> +#define DENALI_PHY_572_DATA 0x00000200
> +#define DENALI_PHY_573_DATA 0x00000000
> +#define DENALI_PHY_574_DATA 0x00000000
> +#define DENALI_PHY_575_DATA 0x00000002
> +#define DENALI_PHY_576_DATA 0x51313152
> +#define DENALI_PHY_577_DATA 0x80013130
> +#define DENALI_PHY_578_DATA 0x02000080
> +#define DENALI_PHY_579_DATA 0x00100001
> +#define DENALI_PHY_580_DATA 0x0c064208
> +#define DENALI_PHY_581_DATA 0x000f0c0f
> +#define DENALI_PHY_582_DATA 0x01000140
> +#define DENALI_PHY_583_DATA 0x0000000c
> +#define DENALI_PHY_584_DATA 0x00000000
> +#define DENALI_PHY_585_DATA 0x00000000
> +#define DENALI_PHY_586_DATA 0x00000000
> +#define DENALI_PHY_587_DATA 0x00000000
> +#define DENALI_PHY_588_DATA 0x00000000
> +#define DENALI_PHY_589_DATA 0x00000000
> +#define DENALI_PHY_590_DATA 0x00000000
> +#define DENALI_PHY_591_DATA 0x00000000
> +#define DENALI_PHY_592_DATA 0x00000000
> +#define DENALI_PHY_593_DATA 0x00000000
> +#define DENALI_PHY_594_DATA 0x00000000
> +#define DENALI_PHY_595_DATA 0x00000000
> +#define DENALI_PHY_596_DATA 0x00000000
> +#define DENALI_PHY_597_DATA 0x00000000
> +#define DENALI_PHY_598_DATA 0x00000000
> +#define DENALI_PHY_599_DATA 0x00000000
> +#define DENALI_PHY_600_DATA 0x00000000
> +#define DENALI_PHY_601_DATA 0x00000000
> +#define DENALI_PHY_602_DATA 0x00000000
> +#define DENALI_PHY_603_DATA 0x00000000
> +#define DENALI_PHY_604_DATA 0x00000000
> +#define DENALI_PHY_605_DATA 0x00000000
> +#define DENALI_PHY_606_DATA 0x00000000
> +#define DENALI_PHY_607_DATA 0x00000000
> +#define DENALI_PHY_608_DATA 0x00000000
> +#define DENALI_PHY_609_DATA 0x00000000
> +#define DENALI_PHY_610_DATA 0x00000000
> +#define DENALI_PHY_611_DATA 0x00000000
> +#define DENALI_PHY_612_DATA 0x00000000
> +#define DENALI_PHY_613_DATA 0x00000000
> +#define DENALI_PHY_614_DATA 0x00000000
> +#define DENALI_PHY_615_DATA 0x00000000
> +#define DENALI_PHY_616_DATA 0x00000000
> +#define DENALI_PHY_617_DATA 0x00000000
> +#define DENALI_PHY_618_DATA 0x00000000
> +#define DENALI_PHY_619_DATA 0x00000000
> +#define DENALI_PHY_620_DATA 0x00000000
> +#define DENALI_PHY_621_DATA 0x00000000
> +#define DENALI_PHY_622_DATA 0x00000000
> +#define DENALI_PHY_623_DATA 0x00000000
> +#define DENALI_PHY_624_DATA 0x00000000
> +#define DENALI_PHY_625_DATA 0x00000000
> +#define DENALI_PHY_626_DATA 0x00000000
> +#define DENALI_PHY_627_DATA 0x00000000
> +#define DENALI_PHY_628_DATA 0x00000000
> +#define DENALI_PHY_629_DATA 0x00000000
> +#define DENALI_PHY_630_DATA 0x00000000
> +#define DENALI_PHY_631_DATA 0x00000000
> +#define DENALI_PHY_632_DATA 0x00000000
> +#define DENALI_PHY_633_DATA 0x00000000
> +#define DENALI_PHY_634_DATA 0x00000000
> +#define DENALI_PHY_635_DATA 0x00000000
> +#define DENALI_PHY_636_DATA 0x00000000
> +#define DENALI_PHY_637_DATA 0x00000000
> +#define DENALI_PHY_638_DATA 0x00000000
> +#define DENALI_PHY_639_DATA 0x00000000
> +#define DENALI_PHY_640_DATA 0x35174620
> +#define DENALI_PHY_641_DATA 0x0004c008
> +#define DENALI_PHY_642_DATA 0x000000da
> +#define DENALI_PHY_643_DATA 0x00000000
> +#define DENALI_PHY_644_DATA 0x00000000
> +#define DENALI_PHY_645_DATA 0x00010000
> +#define DENALI_PHY_646_DATA 0x01DDDD90
> +#define DENALI_PHY_647_DATA 0x01DDDD90
> +#define DENALI_PHY_648_DATA 0x01030000
> +#define DENALI_PHY_649_DATA 0x01000000
> +#define DENALI_PHY_650_DATA 0x00c00000
> +#define DENALI_PHY_651_DATA 0x00000007
> +#define DENALI_PHY_652_DATA 0x00000000
> +#define DENALI_PHY_653_DATA 0x00000000
> +#define DENALI_PHY_654_DATA 0x04000408
> +#define DENALI_PHY_655_DATA 0x00000408
> +#define DENALI_PHY_656_DATA 0x00e4e400
> +#define DENALI_PHY_657_DATA 0x00000000
> +#define DENALI_PHY_658_DATA 0x00000000
> +#define DENALI_PHY_659_DATA 0x00000000
> +#define DENALI_PHY_660_DATA 0x00000000
> +#define DENALI_PHY_661_DATA 0x00000000
> +#define DENALI_PHY_662_DATA 0x00000000
> +#define DENALI_PHY_663_DATA 0x00000000
> +#define DENALI_PHY_664_DATA 0x00000000
> +#define DENALI_PHY_665_DATA 0x00000000
> +#define DENALI_PHY_666_DATA 0x00000000
> +#define DENALI_PHY_667_DATA 0x00000000
> +#define DENALI_PHY_668_DATA 0x00000000
> +#define DENALI_PHY_669_DATA 0x00000000
> +#define DENALI_PHY_670_DATA 0x00000000
> +#define DENALI_PHY_671_DATA 0x00000000
> +#define DENALI_PHY_672_DATA 0x00000000
> +#define DENALI_PHY_673_DATA 0x00200000
> +#define DENALI_PHY_674_DATA 0x00000000
> +#define DENALI_PHY_675_DATA 0x00000000
> +#define DENALI_PHY_676_DATA 0x00000000
> +#define DENALI_PHY_677_DATA 0x00000000
> +#define DENALI_PHY_678_DATA 0x00000000
> +#define DENALI_PHY_679_DATA 0x00000000
> +#define DENALI_PHY_680_DATA 0x02800280
> +#define DENALI_PHY_681_DATA 0x02800280
> +#define DENALI_PHY_682_DATA 0x02800280
> +#define DENALI_PHY_683_DATA 0x02800280
> +#define DENALI_PHY_684_DATA 0x00000280
> +#define DENALI_PHY_685_DATA 0x00000000
> +#define DENALI_PHY_686_DATA 0x00000000
> +#define DENALI_PHY_687_DATA 0x00000000
> +#define DENALI_PHY_688_DATA 0x00000000
> +#define DENALI_PHY_689_DATA 0x00000000
> +#define DENALI_PHY_690_DATA 0x00800080
> +#define DENALI_PHY_691_DATA 0x00800080
> +#define DENALI_PHY_692_DATA 0x00800080
> +#define DENALI_PHY_693_DATA 0x00800080
> +#define DENALI_PHY_694_DATA 0x00800080
> +#define DENALI_PHY_695_DATA 0x00800080
> +#define DENALI_PHY_696_DATA 0x00800080
> +#define DENALI_PHY_697_DATA 0x00800080
> +#define DENALI_PHY_698_DATA 0x00800080
> +#define DENALI_PHY_699_DATA 0x000100da
> +#define DENALI_PHY_700_DATA 0x00000200
> +#define DENALI_PHY_701_DATA 0x00000000
> +#define DENALI_PHY_702_DATA 0x00000000
> +#define DENALI_PHY_703_DATA 0x00000002
> +#define DENALI_PHY_704_DATA 0x51313152
> +#define DENALI_PHY_705_DATA 0x80013130
> +#define DENALI_PHY_706_DATA 0x02000080
> +#define DENALI_PHY_707_DATA 0x00100001
> +#define DENALI_PHY_708_DATA 0x0c064208
> +#define DENALI_PHY_709_DATA 0x000f0c0f
> +#define DENALI_PHY_710_DATA 0x01000140
> +#define DENALI_PHY_711_DATA 0x0000000c
> +#define DENALI_PHY_712_DATA 0x00000000
> +#define DENALI_PHY_713_DATA 0x00000000
> +#define DENALI_PHY_714_DATA 0x00000000
> +#define DENALI_PHY_715_DATA 0x00000000
> +#define DENALI_PHY_716_DATA 0x00000000
> +#define DENALI_PHY_717_DATA 0x00000000
> +#define DENALI_PHY_718_DATA 0x00000000
> +#define DENALI_PHY_719_DATA 0x00000000
> +#define DENALI_PHY_720_DATA 0x00000000
> +#define DENALI_PHY_721_DATA 0x00000000
> +#define DENALI_PHY_722_DATA 0x00000000
> +#define DENALI_PHY_723_DATA 0x00000000
> +#define DENALI_PHY_724_DATA 0x00000000
> +#define DENALI_PHY_725_DATA 0x00000000
> +#define DENALI_PHY_726_DATA 0x00000000
> +#define DENALI_PHY_727_DATA 0x00000000
> +#define DENALI_PHY_728_DATA 0x00000000
> +#define DENALI_PHY_729_DATA 0x00000000
> +#define DENALI_PHY_730_DATA 0x00000000
> +#define DENALI_PHY_731_DATA 0x00000000
> +#define DENALI_PHY_732_DATA 0x00000000
> +#define DENALI_PHY_733_DATA 0x00000000
> +#define DENALI_PHY_734_DATA 0x00000000
> +#define DENALI_PHY_735_DATA 0x00000000
> +#define DENALI_PHY_736_DATA 0x00000000
> +#define DENALI_PHY_737_DATA 0x00000000
> +#define DENALI_PHY_738_DATA 0x00000000
> +#define DENALI_PHY_739_DATA 0x00000000
> +#define DENALI_PHY_740_DATA 0x00000000
> +#define DENALI_PHY_741_DATA 0x00000000
> +#define DENALI_PHY_742_DATA 0x00000000
> +#define DENALI_PHY_743_DATA 0x00000000
> +#define DENALI_PHY_744_DATA 0x00000000
> +#define DENALI_PHY_745_DATA 0x00000000
> +#define DENALI_PHY_746_DATA 0x00000000
> +#define DENALI_PHY_747_DATA 0x00000000
> +#define DENALI_PHY_748_DATA 0x00000000
> +#define DENALI_PHY_749_DATA 0x00000000
> +#define DENALI_PHY_750_DATA 0x00000000
> +#define DENALI_PHY_751_DATA 0x00000000
> +#define DENALI_PHY_752_DATA 0x00000000
> +#define DENALI_PHY_753_DATA 0x00000000
> +#define DENALI_PHY_754_DATA 0x00000000
> +#define DENALI_PHY_755_DATA 0x00000000
> +#define DENALI_PHY_756_DATA 0x00000000
> +#define DENALI_PHY_757_DATA 0x00000000
> +#define DENALI_PHY_758_DATA 0x00000000
> +#define DENALI_PHY_759_DATA 0x00000000
> +#define DENALI_PHY_760_DATA 0x00000000
> +#define DENALI_PHY_761_DATA 0x00000000
> +#define DENALI_PHY_762_DATA 0x00000000
> +#define DENALI_PHY_763_DATA 0x00000000
> +#define DENALI_PHY_764_DATA 0x00000000
> +#define DENALI_PHY_765_DATA 0x00000000
> +#define DENALI_PHY_766_DATA 0x00000000
> +#define DENALI_PHY_767_DATA 0x00000000
> +#define DENALI_PHY_768_DATA 0x15203476
> +#define DENALI_PHY_769_DATA 0x0004c008
> +#define DENALI_PHY_770_DATA 0x000000da
> +#define DENALI_PHY_771_DATA 0x00000000
> +#define DENALI_PHY_772_DATA 0x00000000
> +#define DENALI_PHY_773_DATA 0x00010000
> +#define DENALI_PHY_774_DATA 0x01DDDD90
> +#define DENALI_PHY_775_DATA 0x01DDDD90
> +#define DENALI_PHY_776_DATA 0x01030000
> +#define DENALI_PHY_777_DATA 0x01000000
> +#define DENALI_PHY_778_DATA 0x00c00000
> +#define DENALI_PHY_779_DATA 0x00000007
> +#define DENALI_PHY_780_DATA 0x00000000
> +#define DENALI_PHY_781_DATA 0x00000000
> +#define DENALI_PHY_782_DATA 0x04000408
> +#define DENALI_PHY_783_DATA 0x00000408
> +#define DENALI_PHY_784_DATA 0x00e4e400
> +#define DENALI_PHY_785_DATA 0x00000000
> +#define DENALI_PHY_786_DATA 0x00000000
> +#define DENALI_PHY_787_DATA 0x00000000
> +#define DENALI_PHY_788_DATA 0x00000000
> +#define DENALI_PHY_789_DATA 0x00000000
> +#define DENALI_PHY_790_DATA 0x00000000
> +#define DENALI_PHY_791_DATA 0x00000000
> +#define DENALI_PHY_792_DATA 0x00000000
> +#define DENALI_PHY_793_DATA 0x00000000
> +#define DENALI_PHY_794_DATA 0x00000000
> +#define DENALI_PHY_795_DATA 0x00000000
> +#define DENALI_PHY_796_DATA 0x00000000
> +#define DENALI_PHY_797_DATA 0x00000000
> +#define DENALI_PHY_798_DATA 0x00000000
> +#define DENALI_PHY_799_DATA 0x00000000
> +#define DENALI_PHY_800_DATA 0x00000000
> +#define DENALI_PHY_801_DATA 0x00200000
> +#define DENALI_PHY_802_DATA 0x00000000
> +#define DENALI_PHY_803_DATA 0x00000000
> +#define DENALI_PHY_804_DATA 0x00000000
> +#define DENALI_PHY_805_DATA 0x00000000
> +#define DENALI_PHY_806_DATA 0x00000000
> +#define DENALI_PHY_807_DATA 0x00000000
> +#define DENALI_PHY_808_DATA 0x02800280
> +#define DENALI_PHY_809_DATA 0x02800280
> +#define DENALI_PHY_810_DATA 0x02800280
> +#define DENALI_PHY_811_DATA 0x02800280
> +#define DENALI_PHY_812_DATA 0x00000280
> +#define DENALI_PHY_813_DATA 0x00000000
> +#define DENALI_PHY_814_DATA 0x00000000
> +#define DENALI_PHY_815_DATA 0x00000000
> +#define DENALI_PHY_816_DATA 0x00000000
> +#define DENALI_PHY_817_DATA 0x00000000
> +#define DENALI_PHY_818_DATA 0x00800080
> +#define DENALI_PHY_819_DATA 0x00800080
> +#define DENALI_PHY_820_DATA 0x00800080
> +#define DENALI_PHY_821_DATA 0x00800080
> +#define DENALI_PHY_822_DATA 0x00800080
> +#define DENALI_PHY_823_DATA 0x00800080
> +#define DENALI_PHY_824_DATA 0x00800080
> +#define DENALI_PHY_825_DATA 0x00800080
> +#define DENALI_PHY_826_DATA 0x00800080
> +#define DENALI_PHY_827_DATA 0x000100da
> +#define DENALI_PHY_828_DATA 0x00000200
> +#define DENALI_PHY_829_DATA 0x00000000
> +#define DENALI_PHY_830_DATA 0x00000000
> +#define DENALI_PHY_831_DATA 0x00000002
> +#define DENALI_PHY_832_DATA 0x51313152
> +#define DENALI_PHY_833_DATA 0x80013130
> +#define DENALI_PHY_834_DATA 0x02000080
> +#define DENALI_PHY_835_DATA 0x00100001
> +#define DENALI_PHY_836_DATA 0x0c064208
> +#define DENALI_PHY_837_DATA 0x000f0c0f
> +#define DENALI_PHY_838_DATA 0x01000140
> +#define DENALI_PHY_839_DATA 0x0000000c
> +#define DENALI_PHY_840_DATA 0x00000000
> +#define DENALI_PHY_841_DATA 0x00000000
> +#define DENALI_PHY_842_DATA 0x00000000
> +#define DENALI_PHY_843_DATA 0x00000000
> +#define DENALI_PHY_844_DATA 0x00000000
> +#define DENALI_PHY_845_DATA 0x00000000
> +#define DENALI_PHY_846_DATA 0x00000000
> +#define DENALI_PHY_847_DATA 0x00000000
> +#define DENALI_PHY_848_DATA 0x00000000
> +#define DENALI_PHY_849_DATA 0x00000000
> +#define DENALI_PHY_850_DATA 0x00000000
> +#define DENALI_PHY_851_DATA 0x00000000
> +#define DENALI_PHY_852_DATA 0x00000000
> +#define DENALI_PHY_853_DATA 0x00000000
> +#define DENALI_PHY_854_DATA 0x00000000
> +#define DENALI_PHY_855_DATA 0x00000000
> +#define DENALI_PHY_856_DATA 0x00000000
> +#define DENALI_PHY_857_DATA 0x00000000
> +#define DENALI_PHY_858_DATA 0x00000000
> +#define DENALI_PHY_859_DATA 0x00000000
> +#define DENALI_PHY_860_DATA 0x00000000
> +#define DENALI_PHY_861_DATA 0x00000000
> +#define DENALI_PHY_862_DATA 0x00000000
> +#define DENALI_PHY_863_DATA 0x00000000
> +#define DENALI_PHY_864_DATA 0x00000000
> +#define DENALI_PHY_865_DATA 0x00000000
> +#define DENALI_PHY_866_DATA 0x00000000
> +#define DENALI_PHY_867_DATA 0x00000000
> +#define DENALI_PHY_868_DATA 0x00000000
> +#define DENALI_PHY_869_DATA 0x00000000
> +#define DENALI_PHY_870_DATA 0x00000000
> +#define DENALI_PHY_871_DATA 0x00000000
> +#define DENALI_PHY_872_DATA 0x00000000
> +#define DENALI_PHY_873_DATA 0x00000000
> +#define DENALI_PHY_874_DATA 0x00000000
> +#define DENALI_PHY_875_DATA 0x00000000
> +#define DENALI_PHY_876_DATA 0x00000000
> +#define DENALI_PHY_877_DATA 0x00000000
> +#define DENALI_PHY_878_DATA 0x00000000
> +#define DENALI_PHY_879_DATA 0x00000000
> +#define DENALI_PHY_880_DATA 0x00000000
> +#define DENALI_PHY_881_DATA 0x00000000
> +#define DENALI_PHY_882_DATA 0x00000000
> +#define DENALI_PHY_883_DATA 0x00000000
> +#define DENALI_PHY_884_DATA 0x00000000
> +#define DENALI_PHY_885_DATA 0x00000000
> +#define DENALI_PHY_886_DATA 0x00000000
> +#define DENALI_PHY_887_DATA 0x00000000
> +#define DENALI_PHY_888_DATA 0x00000000
> +#define DENALI_PHY_889_DATA 0x00000000
> +#define DENALI_PHY_890_DATA 0x00000000
> +#define DENALI_PHY_891_DATA 0x00000000
> +#define DENALI_PHY_892_DATA 0x00000000
> +#define DENALI_PHY_893_DATA 0x00000000
> +#define DENALI_PHY_894_DATA 0x00000000
> +#define DENALI_PHY_895_DATA 0x00000000
> +#define DENALI_PHY_896_DATA 0x41753206
> +#define DENALI_PHY_897_DATA 0x0004c008
> +#define DENALI_PHY_898_DATA 0x000000da
> +#define DENALI_PHY_899_DATA 0x00000000
> +#define DENALI_PHY_900_DATA 0x00000000
> +#define DENALI_PHY_901_DATA 0x00010000
> +#define DENALI_PHY_902_DATA 0x01DDDD90
> +#define DENALI_PHY_903_DATA 0x01DDDD90
> +#define DENALI_PHY_904_DATA 0x01030000
> +#define DENALI_PHY_905_DATA 0x01000000
> +#define DENALI_PHY_906_DATA 0x00c00000
> +#define DENALI_PHY_907_DATA 0x00000007
> +#define DENALI_PHY_908_DATA 0x00000000
> +#define DENALI_PHY_909_DATA 0x00000000
> +#define DENALI_PHY_910_DATA 0x04000408
> +#define DENALI_PHY_911_DATA 0x00000408
> +#define DENALI_PHY_912_DATA 0x00e4e400
> +#define DENALI_PHY_913_DATA 0x00000000
> +#define DENALI_PHY_914_DATA 0x00000000
> +#define DENALI_PHY_915_DATA 0x00000000
> +#define DENALI_PHY_916_DATA 0x00000000
> +#define DENALI_PHY_917_DATA 0x00000000
> +#define DENALI_PHY_918_DATA 0x00000000
> +#define DENALI_PHY_919_DATA 0x00000000
> +#define DENALI_PHY_920_DATA 0x00000000
> +#define DENALI_PHY_921_DATA 0x00000000
> +#define DENALI_PHY_922_DATA 0x00000000
> +#define DENALI_PHY_923_DATA 0x00000000
> +#define DENALI_PHY_924_DATA 0x00000000
> +#define DENALI_PHY_925_DATA 0x00000000
> +#define DENALI_PHY_926_DATA 0x00000000
> +#define DENALI_PHY_927_DATA 0x00000000
> +#define DENALI_PHY_928_DATA 0x00000000
> +#define DENALI_PHY_929_DATA 0x00200000
> +#define DENALI_PHY_930_DATA 0x00000000
> +#define DENALI_PHY_931_DATA 0x00000000
> +#define DENALI_PHY_932_DATA 0x00000000
> +#define DENALI_PHY_933_DATA 0x00000000
> +#define DENALI_PHY_934_DATA 0x00000000
> +#define DENALI_PHY_935_DATA 0x00000000
> +#define DENALI_PHY_936_DATA 0x02800280
> +#define DENALI_PHY_937_DATA 0x02800280
> +#define DENALI_PHY_938_DATA 0x02800280
> +#define DENALI_PHY_939_DATA 0x02800280
> +#define DENALI_PHY_940_DATA 0x00000280
> +#define DENALI_PHY_941_DATA 0x00000000
> +#define DENALI_PHY_942_DATA 0x00000000
> +#define DENALI_PHY_943_DATA 0x00000000
> +#define DENALI_PHY_944_DATA 0x00000000
> +#define DENALI_PHY_945_DATA 0x00000000
> +#define DENALI_PHY_946_DATA 0x00800080
> +#define DENALI_PHY_947_DATA 0x00800080
> +#define DENALI_PHY_948_DATA 0x00800080
> +#define DENALI_PHY_949_DATA 0x00800080
> +#define DENALI_PHY_950_DATA 0x00800080
> +#define DENALI_PHY_951_DATA 0x00800080
> +#define DENALI_PHY_952_DATA 0x00800080
> +#define DENALI_PHY_953_DATA 0x00800080
> +#define DENALI_PHY_954_DATA 0x00800080
> +#define DENALI_PHY_955_DATA 0x000100da
> +#define DENALI_PHY_956_DATA 0x00000200
> +#define DENALI_PHY_957_DATA 0x00000000
> +#define DENALI_PHY_958_DATA 0x00000000
> +#define DENALI_PHY_959_DATA 0x00000002
> +#define DENALI_PHY_960_DATA 0x51313152
> +#define DENALI_PHY_961_DATA 0x80013130
> +#define DENALI_PHY_962_DATA 0x02000080
> +#define DENALI_PHY_963_DATA 0x00100001
> +#define DENALI_PHY_964_DATA 0x0c064208
> +#define DENALI_PHY_965_DATA 0x000f0c0f
> +#define DENALI_PHY_966_DATA 0x01000140
> +#define DENALI_PHY_967_DATA 0x0000000c
> +#define DENALI_PHY_968_DATA 0x00000000
> +#define DENALI_PHY_969_DATA 0x00000000
> +#define DENALI_PHY_970_DATA 0x00000000
> +#define DENALI_PHY_971_DATA 0x00000000
> +#define DENALI_PHY_972_DATA 0x00000000
> +#define DENALI_PHY_973_DATA 0x00000000
> +#define DENALI_PHY_974_DATA 0x00000000
> +#define DENALI_PHY_975_DATA 0x00000000
> +#define DENALI_PHY_976_DATA 0x00000000
> +#define DENALI_PHY_977_DATA 0x00000000
> +#define DENALI_PHY_978_DATA 0x00000000
> +#define DENALI_PHY_979_DATA 0x00000000
> +#define DENALI_PHY_980_DATA 0x00000000
> +#define DENALI_PHY_981_DATA 0x00000000
> +#define DENALI_PHY_982_DATA 0x00000000
> +#define DENALI_PHY_983_DATA 0x00000000
> +#define DENALI_PHY_984_DATA 0x00000000
> +#define DENALI_PHY_985_DATA 0x00000000
> +#define DENALI_PHY_986_DATA 0x00000000
> +#define DENALI_PHY_987_DATA 0x00000000
> +#define DENALI_PHY_988_DATA 0x00000000
> +#define DENALI_PHY_989_DATA 0x00000000
> +#define DENALI_PHY_990_DATA 0x00000000
> +#define DENALI_PHY_991_DATA 0x00000000
> +#define DENALI_PHY_992_DATA 0x00000000
> +#define DENALI_PHY_993_DATA 0x00000000
> +#define DENALI_PHY_994_DATA 0x00000000
> +#define DENALI_PHY_995_DATA 0x00000000
> +#define DENALI_PHY_996_DATA 0x00000000
> +#define DENALI_PHY_997_DATA 0x00000000
> +#define DENALI_PHY_998_DATA 0x00000000
> +#define DENALI_PHY_999_DATA 0x00000000
> +#define DENALI_PHY_1000_DATA 0x00000000
> +#define DENALI_PHY_1001_DATA 0x00000000
> +#define DENALI_PHY_1002_DATA 0x00000000
> +#define DENALI_PHY_1003_DATA 0x00000000
> +#define DENALI_PHY_1004_DATA 0x00000000
> +#define DENALI_PHY_1005_DATA 0x00000000
> +#define DENALI_PHY_1006_DATA 0x00000000
> +#define DENALI_PHY_1007_DATA 0x00000000
> +#define DENALI_PHY_1008_DATA 0x00000000
> +#define DENALI_PHY_1009_DATA 0x00000000
> +#define DENALI_PHY_1010_DATA 0x00000000
> +#define DENALI_PHY_1011_DATA 0x00000000
> +#define DENALI_PHY_1012_DATA 0x00000000
> +#define DENALI_PHY_1013_DATA 0x00000000
> +#define DENALI_PHY_1014_DATA 0x00000000
> +#define DENALI_PHY_1015_DATA 0x00000000
> +#define DENALI_PHY_1016_DATA 0x00000000
> +#define DENALI_PHY_1017_DATA 0x00000000
> +#define DENALI_PHY_1018_DATA 0x00000000
> +#define DENALI_PHY_1019_DATA 0x00000000
> +#define DENALI_PHY_1020_DATA 0x00000000
> +#define DENALI_PHY_1021_DATA 0x00000000
> +#define DENALI_PHY_1022_DATA 0x00000000
> +#define DENALI_PHY_1023_DATA 0x00000000
> +#define DENALI_PHY_1024_DATA 0x36025174
> +#define DENALI_PHY_1025_DATA 0x0004c008
> +#define DENALI_PHY_1026_DATA 0x000000da
> +#define DENALI_PHY_1027_DATA 0x00000000
> +#define DENALI_PHY_1028_DATA 0x00000000
> +#define DENALI_PHY_1029_DATA 0x00010000
> +#define DENALI_PHY_1030_DATA 0x01DDDD90
> +#define DENALI_PHY_1031_DATA 0x01DDDD90
> +#define DENALI_PHY_1032_DATA 0x01030000
> +#define DENALI_PHY_1033_DATA 0x01000000
> +#define DENALI_PHY_1034_DATA 0x00c00000
> +#define DENALI_PHY_1035_DATA 0x00000007
> +#define DENALI_PHY_1036_DATA 0x00000000
> +#define DENALI_PHY_1037_DATA 0x00000000
> +#define DENALI_PHY_1038_DATA 0x04000408
> +#define DENALI_PHY_1039_DATA 0x00000408
> +#define DENALI_PHY_1040_DATA 0x00e4e400
> +#define DENALI_PHY_1041_DATA 0x00000000
> +#define DENALI_PHY_1042_DATA 0x00000000
> +#define DENALI_PHY_1043_DATA 0x00000000
> +#define DENALI_PHY_1044_DATA 0x00000000
> +#define DENALI_PHY_1045_DATA 0x00000000
> +#define DENALI_PHY_1046_DATA 0x00000000
> +#define DENALI_PHY_1047_DATA 0x00000000
> +#define DENALI_PHY_1048_DATA 0x00000000
> +#define DENALI_PHY_1049_DATA 0x00000000
> +#define DENALI_PHY_1050_DATA 0x00000000
> +#define DENALI_PHY_1051_DATA 0x00000000
> +#define DENALI_PHY_1052_DATA 0x00000000
> +#define DENALI_PHY_1053_DATA 0x00000000
> +#define DENALI_PHY_1054_DATA 0x00000000
> +#define DENALI_PHY_1055_DATA 0x00000000
> +#define DENALI_PHY_1056_DATA 0x00000000
> +#define DENALI_PHY_1057_DATA 0x00200000
> +#define DENALI_PHY_1058_DATA 0x00000000
> +#define DENALI_PHY_1059_DATA 0x00000000
> +#define DENALI_PHY_1060_DATA 0x00000000
> +#define DENALI_PHY_1061_DATA 0x00000000
> +#define DENALI_PHY_1062_DATA 0x00000000
> +#define DENALI_PHY_1063_DATA 0x00000000
> +#define DENALI_PHY_1064_DATA 0x02800280
> +#define DENALI_PHY_1065_DATA 0x02800280
> +#define DENALI_PHY_1066_DATA 0x02800280
> +#define DENALI_PHY_1067_DATA 0x02800280
> +#define DENALI_PHY_1068_DATA 0x00000280
> +#define DENALI_PHY_1069_DATA 0x00000000
> +#define DENALI_PHY_1070_DATA 0x00000000
> +#define DENALI_PHY_1071_DATA 0x00000000
> +#define DENALI_PHY_1072_DATA 0x00000000
> +#define DENALI_PHY_1073_DATA 0x00000000
> +#define DENALI_PHY_1074_DATA 0x00800080
> +#define DENALI_PHY_1075_DATA 0x00800080
> +#define DENALI_PHY_1076_DATA 0x00800080
> +#define DENALI_PHY_1077_DATA 0x00800080
> +#define DENALI_PHY_1078_DATA 0x00800080
> +#define DENALI_PHY_1079_DATA 0x00800080
> +#define DENALI_PHY_1080_DATA 0x00800080
> +#define DENALI_PHY_1081_DATA 0x00800080
> +#define DENALI_PHY_1082_DATA 0x00800080
> +#define DENALI_PHY_1083_DATA 0x000100da
> +#define DENALI_PHY_1084_DATA 0x00000200
> +#define DENALI_PHY_1085_DATA 0x00000000
> +#define DENALI_PHY_1086_DATA 0x00000000
> +#define DENALI_PHY_1087_DATA 0x00000002
> +#define DENALI_PHY_1088_DATA 0x51313152
> +#define DENALI_PHY_1089_DATA 0x80013130
> +#define DENALI_PHY_1090_DATA 0x02000080
> +#define DENALI_PHY_1091_DATA 0x00100001
> +#define DENALI_PHY_1092_DATA 0x0c064208
> +#define DENALI_PHY_1093_DATA 0x000f0c0f
> +#define DENALI_PHY_1094_DATA 0x01000140
> +#define DENALI_PHY_1095_DATA 0x0000000c
> +#define DENALI_PHY_1096_DATA 0x00000000
> +#define DENALI_PHY_1097_DATA 0x00000000
> +#define DENALI_PHY_1098_DATA 0x00000000
> +#define DENALI_PHY_1099_DATA 0x00000000
> +#define DENALI_PHY_1100_DATA 0x00000000
> +#define DENALI_PHY_1101_DATA 0x00000000
> +#define DENALI_PHY_1102_DATA 0x00000000
> +#define DENALI_PHY_1103_DATA 0x00000000
> +#define DENALI_PHY_1104_DATA 0x00000000
> +#define DENALI_PHY_1105_DATA 0x00000000
> +#define DENALI_PHY_1106_DATA 0x00000000
> +#define DENALI_PHY_1107_DATA 0x00000000
> +#define DENALI_PHY_1108_DATA 0x00000000
> +#define DENALI_PHY_1109_DATA 0x00000000
> +#define DENALI_PHY_1110_DATA 0x00000000
> +#define DENALI_PHY_1111_DATA 0x00000000
> +#define DENALI_PHY_1112_DATA 0x00000000
> +#define DENALI_PHY_1113_DATA 0x00000000
> +#define DENALI_PHY_1114_DATA 0x00000000
> +#define DENALI_PHY_1115_DATA 0x00000000
> +#define DENALI_PHY_1116_DATA 0x00000000
> +#define DENALI_PHY_1117_DATA 0x00000000
> +#define DENALI_PHY_1118_DATA 0x00000000
> +#define DENALI_PHY_1119_DATA 0x00000000
> +#define DENALI_PHY_1120_DATA 0x00000000
> +#define DENALI_PHY_1121_DATA 0x00000000
> +#define DENALI_PHY_1122_DATA 0x00000000
> +#define DENALI_PHY_1123_DATA 0x00000000
> +#define DENALI_PHY_1124_DATA 0x00000000
> +#define DENALI_PHY_1125_DATA 0x00000000
> +#define DENALI_PHY_1126_DATA 0x00000000
> +#define DENALI_PHY_1127_DATA 0x00000000
> +#define DENALI_PHY_1128_DATA 0x00000000
> +#define DENALI_PHY_1129_DATA 0x00000000
> +#define DENALI_PHY_1130_DATA 0x00000000
> +#define DENALI_PHY_1131_DATA 0x00000000
> +#define DENALI_PHY_1132_DATA 0x00000000
> +#define DENALI_PHY_1133_DATA 0x00000000
> +#define DENALI_PHY_1134_DATA 0x00000000
> +#define DENALI_PHY_1135_DATA 0x00000000
> +#define DENALI_PHY_1136_DATA 0x00000000
> +#define DENALI_PHY_1137_DATA 0x00000000
> +#define DENALI_PHY_1138_DATA 0x00000000
> +#define DENALI_PHY_1139_DATA 0x00000000
> +#define DENALI_PHY_1140_DATA 0x00000000
> +#define DENALI_PHY_1141_DATA 0x00000000
> +#define DENALI_PHY_1142_DATA 0x00000000
> +#define DENALI_PHY_1143_DATA 0x00000000
> +#define DENALI_PHY_1144_DATA 0x00000000
> +#define DENALI_PHY_1145_DATA 0x00000000
> +#define DENALI_PHY_1146_DATA 0x00000000
> +#define DENALI_PHY_1147_DATA 0x00000000
> +#define DENALI_PHY_1148_DATA 0x00000000
> +#define DENALI_PHY_1149_DATA 0x00000000
> +#define DENALI_PHY_1150_DATA 0x00000000
> +#define DENALI_PHY_1151_DATA 0x00000000
> +#define DENALI_PHY_1152_DATA 0x00000000
> +#define DENALI_PHY_1153_DATA 0x00000000
> +#define DENALI_PHY_1154_DATA 0x00050000
> +#define DENALI_PHY_1155_DATA 0x00000000
> +#define DENALI_PHY_1156_DATA 0x00000000
> +#define DENALI_PHY_1157_DATA 0x00000000
> +#define DENALI_PHY_1158_DATA 0x00000100
> +#define DENALI_PHY_1159_DATA 0x00000000
> +#define DENALI_PHY_1160_DATA 0x00000000
> +#define DENALI_PHY_1161_DATA 0x00506401
> +#define DENALI_PHY_1162_DATA 0x01221102
> +#define DENALI_PHY_1163_DATA 0x00000122
> +#define DENALI_PHY_1164_DATA 0x00000000
> +#define DENALI_PHY_1165_DATA 0x000B1F00
> +#define DENALI_PHY_1166_DATA 0x0B1F0B1F
> +#define DENALI_PHY_1167_DATA 0x0B1F0B1B
> +#define DENALI_PHY_1168_DATA 0x0B1F0B1F
> +#define DENALI_PHY_1169_DATA 0x0B1F0B1F
> +#define DENALI_PHY_1170_DATA 0x00000B00
> +#define DENALI_PHY_1171_DATA 0x42080010
> +#define DENALI_PHY_1172_DATA 0x01000100
> +#define DENALI_PHY_1173_DATA 0x01000100
> +#define DENALI_PHY_1174_DATA 0x01000100
> +#define DENALI_PHY_1175_DATA 0x01000100
> +#define DENALI_PHY_1176_DATA 0x00000000
> +#define DENALI_PHY_1177_DATA 0x00000000
> +#define DENALI_PHY_1178_DATA 0x00000000
> +#define DENALI_PHY_1179_DATA 0x00000000
> +#define DENALI_PHY_1180_DATA 0x00000000
> +#define DENALI_PHY_1181_DATA 0x00000803
> +#define DENALI_PHY_1182_DATA 0x223FFF00
> +#define DENALI_PHY_1183_DATA 0x000008FF
> +#define DENALI_PHY_1184_DATA 0x0000057F
> +#define DENALI_PHY_1185_DATA 0x0000057F
> +#define DENALI_PHY_1186_DATA 0x00037FFF
> +#define DENALI_PHY_1187_DATA 0x00037FFF
> +#define DENALI_PHY_1188_DATA 0x00004410
> +#define DENALI_PHY_1189_DATA 0x00004410
> +#define DENALI_PHY_1190_DATA 0x00004410
> +#define DENALI_PHY_1191_DATA 0x00004410
> +#define DENALI_PHY_1192_DATA 0x00004410
> +#define DENALI_PHY_1193_DATA 0x00037FFF
> +#define DENALI_PHY_1194_DATA 0x00037FFF
> +#define DENALI_PHY_1195_DATA 0x00000000
> +#define DENALI_PHY_1196_DATA 0x00000000
> +#define DENALI_PHY_1197_DATA 0x00000000
> +#define DENALI_PHY_1198_DATA 0x04000000
> +#define DENALI_PHY_1199_DATA 0x00000000
> +#define DENALI_PHY_1200_DATA 0x00000000
> +#define DENALI_PHY_1201_DATA 0x00000108
> +#define DENALI_PHY_1202_DATA 0x00000000
> +#define DENALI_PHY_1203_DATA 0x00000000
> +#define DENALI_PHY_1204_DATA 0x00000000
> +#define DENALI_PHY_1205_DATA 0x00000001
> +#define DENALI_PHY_1206_DATA 0x00000000
> +#define DENALI_PHY_1207_DATA 0x00000000
> +#define DENALI_PHY_1208_DATA 0x00000000
> +#define DENALI_PHY_1209_DATA 0x00000000
> +#define DENALI_PHY_1210_DATA 0x00000000
> +#define DENALI_PHY_1211_DATA 0x00000000
> +#define DENALI_PHY_1212_DATA 0x00020100
> +#define DENALI_PHY_1213_DATA 0x00000000
> +#define DENALI_PHY_1214_DATA 0x00000000
> diff --git a/board/sifive/fu540/ux00ddr.h b/board/sifive/fu540/ux00ddr.h
> new file mode 100644
> index 0000000000..6c18db251a
> --- /dev/null
> +++ b/board/sifive/fu540/ux00ddr.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#ifndef FU540_UX00DDR_H
> +#define FU540_UX00DDR_H
> +
> +#define DRAM_CLASS_DDR4 0xA
> +
> +extern u32 ddr_phy_settings[1215];
> +extern u32 ddr_ctl_settings[265];
> +
> +void ux00ddr_writeregmap(size_t ahbregaddr, const
> + u32 *ctlsettings, const u32 *physettings);
> +
> +void ux00ddr_disableaxireadinterleave(size_t ahbregaddr);
> +
> +void ux00ddr_disableoptimalrmodw(size_t ahbregaddr);
> +
> +void ux00ddr_enablewriteleveling(size_t ahbregaddr);
> +
> +void ux00ddr_enablereadleveling(size_t ahbregaddr);
> +
> +void ux00ddr_enablereadlevelinggate(size_t ahbregaddr);
> +
> +void ux00ddr_enablevreftraining(size_t ahbregaddr);
> +
> +u32 ux00ddr_getdramclass(size_t ahbregaddr);
> +
> +void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr);
> +
> +void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr);
> +
> +void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr);
> +
> +void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr);
> +
> +void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr);
> +
> +void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend);
> +
> +u64 ux00ddr_phy_fixup(size_t ahbregaddr);
> +
> +#endif /* FU540_UX00DDR_H */
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 06/10] riscv: sifive: fu540: add SPL configuration
2020-01-24 5:50 ` [PATCH v3 06/10] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
@ 2020-01-25 8:35 ` Anup Patel
0 siblings, 0 replies; 32+ messages in thread
From: Anup Patel @ 2020-01-25 8:35 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
> then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware
> and U-Boot proper images from 1st partition of MMC boot devices.
>
> SPL related code is leverage from FSBL
> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
> board/sifive/fu540/Kconfig | 8 +
> board/sifive/fu540/Makefile | 1 +
> board/sifive/fu540/fu540-memory-map.h | 33 ++++
> board/sifive/fu540/fu540.c | 24 +++
> board/sifive/fu540/spl.c | 252 ++++++++++++++++++++++++++
> board/sifive/fu540/ux00prci.h | 56 ++++++
> include/configs/sifive-fu540.h | 18 ++
> 7 files changed, 392 insertions(+)
> create mode 100644 board/sifive/fu540/fu540-memory-map.h
> create mode 100644 board/sifive/fu540/spl.c
> create mode 100644 board/sifive/fu540/ux00prci.h
>
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> index 5ca21474de..edb224ed7a 100644
> --- a/board/sifive/fu540/Kconfig
> +++ b/board/sifive/fu540/Kconfig
> @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
> default "sifive-fu540"
>
> config SYS_TEXT_BASE
> + default 0x80200000 if SPL
> default 0x80000000 if !RISCV_SMODE
> default 0x80200000 if RISCV_SMODE
>
> +config SPL_TEXT_BASE
> + default 0x08000000
> +
> +config SPL_OPENSBI_LOAD_ADDR
> + default 0x80000000
> +
> config BOARD_SPECIFIC_OPTIONS # dummy
> def_bool y
> select GENERIC_RISCV
> + select SUPPORT_SPL
> imply CMD_DHCP
> imply CMD_EXT2
> imply CMD_EXT4
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index e4e76e1de3..cdcf894ade 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -5,5 +5,6 @@
> obj-y += fu540.o
>
> ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> obj-y += ddr.o
> endif
> diff --git a/board/sifive/fu540/fu540-memory-map.h b/board/sifive/fu540/fu540-memory-map.h
> new file mode 100644
> index 0000000000..c65203726b
> --- /dev/null
> +++ b/board/sifive/fu540/fu540-memory-map.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#ifndef FU540_MEMORY_MAP
> +#define FU540_MEMORY_MAP
> +
> +#include <asm/arch/gpio.h>
> +#include "ux00prci.h"
> +
> +/****************************************************************************
> + * Platform definitions
> + *****************************************************************************/
> +
> +/* Memory map */
> +#define GPIO_CTRL_ADDR _AC(0x10060000, UL)
> +
> +#define PHYSICAL_FILTER_CTRL_ADDR _AC(0x100b8000, UL)
> +
> +#define UX00DDR_CTRL_ADDR _AC(0x100b0000, UL)
> +#define UX00PRCI_CTRL_ADDR _AC(0x10000000, UL)
> +
> +/* Helper functions */
> +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
> +
> +#define UX00PRCI_REG(offset) \
> + _REG32(UX00PRCI_CTRL_ADDR, \
> + offset)
> +
> +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
> +
> +#endif /* FU540_MEMORY_MAP */
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index 3a5e74f1fb..b81003aa6f 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -11,6 +11,7 @@
> #include <linux/delay.h>
> #include <linux/io.h>
> #include <misc.h>
> +#include <spl.h>
>
> /*
> * This define is a value used for error/unknown serial.
> @@ -114,3 +115,26 @@ int board_init(void)
>
> return 0;
> }
> +
> +#ifdef CONFIG_SPL
> +void board_boot_order(u32 *spl_boot_list)
> +{
> + u8 i;
> + u32 boot_devices[] = {
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> + BOOT_DEVICE_MMC1,
> +#endif
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
> + spl_boot_list[i] = boot_devices[i];
> +}
> +#endif
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> + /* boot using first FIT config */
> + return 0;
> +}
> +#endif
> diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
> new file mode 100644
> index 0000000000..c7ae4aa292
> --- /dev/null
> +++ b/board/sifive/fu540/spl.c
> @@ -0,0 +1,252 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <misc.h>
> +
> +#include "ux00ddr.h"
> +#include "fu540-memory-map.h"
> +
> +#define DDR_SIZE (8UL * 1024UL * 1024UL * 1024UL)
> +#define DDRCTLPLL_F 55
> +#define DDRCTLPLL_Q 2
> +
> +#define PHY_NRESET 0x1000
> +
> +static inline int ux00prci_select_corepll(volatile u32 *coreclkselreg,
> + volatile u32 *corepllcfg,
> + volatile u32 *corepllout,
> + u32 pllconfigval)
> +{
> + (*corepllcfg) = pllconfigval;
> +
> + // Wait for lock
> + while (((*corepllcfg) & (PLL_LOCK(1))) == 0)
> + ;
> +
> + u32 core_out =
> + (PLLOUT_DIV(PLLOUT_DIV_default)) |
> + (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
> + (PLLOUT_CLK_EN(1));
> + (*corepllout) = core_out;
> +
> + // Set CORECLKSELREG to select COREPLL
> + (*coreclkselreg) = PLL_CORECLKSEL_COREPLL;
> +
> + return 0;
> +}
> +
> +static inline int ux00prci_select_corepll_500mhz(volatile u32 *coreclkselreg,
> + volatile u32 *corepllcfg,
> + volatile u32 *corepllout)
> +{
> + /*
> + * CORE pll init
> + * Set corepll 33MHz -> 1GHz
> + */
> +
> + u32 core500mhz =
> + (PLL_R(0)) |
> + (PLL_F(59)) | // 4000MHz VCO
> + (PLL_Q(3)) | /* /8 Output divider */
> + (PLL_RANGE(0x4)) |
> + (PLL_BYPASS(0)) |
> + (PLL_FSE(1));
> +
> + return ux00prci_select_corepll(coreclkselreg, corepllcfg, corepllout,
> + core500mhz);
> +}
> +
> +static inline int ux00prci_select_corepll_1ghz(volatile u32 *coreclkselreg,
> + volatile u32 *corepllcfg,
> + volatile u32 *corepllout)
> +{
> + /*
> + * CORE pll init
> + * Set corepll 33MHz -> 1GHz
> + */
> +
> + u32 core1ghz =
> + (PLL_R(0)) |
> + (PLL_F(59)) | // 4000MHz VCO
> + (PLL_Q(2)) | /* /4 Output divider */
> + (PLL_RANGE(0x4)) |
> + (PLL_BYPASS(0)) |
> + (PLL_FSE(1));
> +
> + return ux00prci_select_corepll(coreclkselreg, corepllcfg, corepllout,
> + core1ghz);
> +}
> +
> +long nsec_per_cyc = 300; // 33.333MHz
> +void nsleep(long nsec)
> +{
> + long step = nsec_per_cyc * 2;
> +
> + while (nsec > 0)
> + nsec -= step;
> +}
> +
> +void init_clk_and_ddr(void)
> +{
> + // PRCI init
> +
> + // Check Reset Values (lock don't care)
> + u32 pll_default =
> + (PLL_R(PLL_R_default)) |
> + (PLL_F(PLL_F_default)) |
> + (PLL_Q(PLL_Q_default)) |
> + (PLL_RANGE(PLL_RANGE_default)) |
> + (PLL_BYPASS(PLL_BYPASS_default)) |
> + (PLL_FSE(PLL_FSE_default));
> + u32 lockmask = ~PLL_LOCK(1);
> + u32 pllout_default =
> + (PLLOUT_DIV(PLLOUT_DIV_default)) |
> + (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
> + (PLLOUT_CLK_EN(PLLOUT_CLK_EN_default));
> +
> + if ((UX00PRCI_REG(UX00PRCI_COREPLLCFG) ^ pll_default) & lockmask)
> + return;
> + if ((UX00PRCI_REG(UX00PRCI_COREPLLOUT) ^ pllout_default))
> + return;
> + if ((UX00PRCI_REG(UX00PRCI_DDRPLLCFG) ^ pll_default) & lockmask)
> + return;
> + if ((UX00PRCI_REG(UX00PRCI_DDRPLLOUT) ^ pllout_default))
> + return;
> + if (((UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG)) ^ pll_default) & lockmask)
> + return;
> + if (((UX00PRCI_REG(UX00PRCI_GEMGXLPLLOUT)) ^ pllout_default))
> + return;
> +
> + /* CORE pll init
> + * If tlclksel is set for 2:1 operation,
> + * Set corepll 33Mhz -> 1GHz
> + * Otherwise, set corepll 33MHz -> 500MHz.
> + */
> +
> + if (UX00PRCI_REG(UX00PRCI_CLKMUXSTATUSREG) & CLKMUX_STATUS_TLCLKSEL) {
> + ux00prci_select_corepll_500mhz
> + (&UX00PRCI_REG(UX00PRCI_CORECLKSELREG),
> + &UX00PRCI_REG(UX00PRCI_COREPLLCFG),
> + &UX00PRCI_REG(UX00PRCI_COREPLLOUT));
> + } else {
> + ux00prci_select_corepll_1ghz
> + (&UX00PRCI_REG(UX00PRCI_CORECLKSELREG),
> + &UX00PRCI_REG(UX00PRCI_COREPLLCFG),
> + &UX00PRCI_REG(UX00PRCI_COREPLLOUT));
> + }
> +
> + //DDR init
> + u32 ddrctlmhz =
> + (PLL_R(0)) |
> + (PLL_F(DDRCTLPLL_F)) |
> + (PLL_Q(DDRCTLPLL_Q)) |
> + (PLL_RANGE(0x4)) |
> + (PLL_BYPASS(0)) |
> + (PLL_FSE(1));
> + UX00PRCI_REG(UX00PRCI_DDRPLLCFG) = ddrctlmhz;
> +
> + // Wait for lock
> + while ((UX00PRCI_REG(UX00PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0)
> + ;
> +
> + u32 ddrctl_out =
> + (PLLOUT_DIV(PLLOUT_DIV_default)) |
> + (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
> + (PLLOUT_CLK_EN(1));
> + (UX00PRCI_REG(UX00PRCI_DDRPLLOUT)) = ddrctl_out;
> +
> + //Release DDR reset.
> + UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |=
> + DEVICESRESET_DDR_CTRL_RST_N(1);
> +
> + // HACK to get the '1 full controller clock cycle'.
> + asm volatile ("fence");
> + UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |= DEVICESRESET_DDR_AXI_RST_N(1)
> + | DEVICESRESET_DDR_AHB_RST_N(1) | DEVICESRESET_DDR_PHY_RST_N(1);
> + // HACK to get the '1 full controller clock cycle'.
> + asm volatile ("fence");
> +
> + /* These take like 16 cycles to actually propagate. We can't go sending
> + * stuff before they come out of reset. So wait. (TODO: Add a register
> + * to read the current reset states, or DDR Control device?)
> + */
> + for (int i = 0; i < 256; i++)
> + asm volatile ("nop");
> +
> + ux00ddr_writeregmap(UX00DDR_CTRL_ADDR, ddr_ctl_settings,
> + ddr_phy_settings);
> + ux00ddr_disableaxireadinterleave(UX00DDR_CTRL_ADDR);
> +
> + ux00ddr_disableoptimalrmodw(UX00DDR_CTRL_ADDR);
> +
> + ux00ddr_enablewriteleveling(UX00DDR_CTRL_ADDR);
> + ux00ddr_enablereadleveling(UX00DDR_CTRL_ADDR);
> + ux00ddr_enablereadlevelinggate(UX00DDR_CTRL_ADDR);
> + if (ux00ddr_getdramclass(UX00DDR_CTRL_ADDR) == DRAM_CLASS_DDR4)
> + ux00ddr_enablevreftraining(UX00DDR_CTRL_ADDR);
> + //mask off interrupts for leveling completion
> + ux00ddr_mask_leveling_completed_interrupt(UX00DDR_CTRL_ADDR);
> +
> + ux00ddr_mask_mc_init_complete_interrupt(UX00DDR_CTRL_ADDR);
> + ux00ddr_mask_outofrange_interrupts(UX00DDR_CTRL_ADDR);
> + ux00ddr_setuprangeprotection(UX00DDR_CTRL_ADDR, DDR_SIZE);
> + ux00ddr_mask_port_command_error_interrupt(UX00DDR_CTRL_ADDR);
> +
> + const u64 ddr_size = DDR_SIZE;
> + const u64 ddr_end = CONFIG_SYS_SDRAM_BASE + ddr_size;
> +
> + ux00ddr_start(UX00DDR_CTRL_ADDR, PHYSICAL_FILTER_CTRL_ADDR, ddr_end);
> + ux00ddr_phy_fixup(UX00DDR_CTRL_ADDR);
> +
> + //GEMGXL init
> + u32 gemgxl125mhz =
> + (PLL_R(0)) |
> + (PLL_F(59)) | //4000Mhz VCO
> + (PLL_Q(5)) | /* /32 */
> + (PLL_RANGE(0x4)) |
> + (PLL_BYPASS(0)) |
> + (PLL_FSE(1));
> + UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG) = gemgxl125mhz;
> +
> + // Wait for lock
> + while ((UX00PRCI_REG(UX00PRCI_GEMGXLPLLCFG) & PLL_LOCK(1)) == 0)
> + ;
> +
> + u32 gemgxlctl_out =
> + (PLLOUT_DIV(PLLOUT_DIV_default)) |
> + (PLLOUT_DIV_BY_1(PLLOUT_DIV_BY_1_default)) |
> + (PLLOUT_CLK_EN(1));
> + UX00PRCI_REG(UX00PRCI_GEMGXLPLLOUT) = gemgxlctl_out;
> +
> + //Release GEMGXL reset (set bit DEVICESRESET_GEMGXL to 1)
> + UX00PRCI_REG(UX00PRCI_DEVICESRESETREG) |= DEVICESRESET_GEMGXL_RST_N(1);
> +
> + // VSC8541 PHY reset sequence; leave pull-down active for 2ms
> + nsleep(2000000);
> + // Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1
> + GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET;
> + GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET;
> + nsleep(100);
> +
> + // Procmon => core clock
> + UX00PRCI_REG(UX00PRCI_PROCMONCFG) = 0x1 << 24;
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + int ret;
> +
> + ret = spl_early_init();
> + if (ret)
> + panic("spl_early_init() failed: %d\n", ret);
> +
> + arch_cpu_init_dm();
> +
> + init_clk_and_ddr();
> +
> + preloader_console_init();
> +}
> diff --git a/board/sifive/fu540/ux00prci.h b/board/sifive/fu540/ux00prci.h
> new file mode 100644
> index 0000000000..90ca3cd258
> --- /dev/null
> +++ b/board/sifive/fu540/ux00prci.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#ifndef _SIFIVE_UX00PRCI_H
> +#define _SIFIVE_UX00PRCI_H
> +
> +/* Register offsets */
> +#define UX00PRCI_HFROSCCFG (0x0000)
> +#define UX00PRCI_COREPLLCFG (0x0004)
> +#define UX00PRCI_COREPLLOUT (0x0008)
> +#define UX00PRCI_DDRPLLCFG (0x000C)
> +#define UX00PRCI_DDRPLLOUT (0x0010)
> +#define UX00PRCI_GEMGXLPLLCFG (0x001C)
> +#define UX00PRCI_GEMGXLPLLOUT (0x0020)
> +#define UX00PRCI_CORECLKSELREG (0x0024)
> +#define UX00PRCI_DEVICESRESETREG (0x0028)
> +#define UX00PRCI_CLKMUXSTATUSREG (0x002C)
> +#define UX00PRCI_PROCMONCFG (0x00F0)
> +
> +#define PLL_R(x) (((x) & 0x3F) << 0)
> +#define PLL_F(x) (((x) & 0x1FF) << 6)
> +#define PLL_Q(x) (((x) & 0x7) << 15)
> +#define PLL_RANGE(x) (((x) & 0x7) << 18)
> +#define PLL_BYPASS(x) (((x) & 0x1) << 24)
> +#define PLL_FSE(x) (((x) & 0x1) << 25)
> +#define PLL_LOCK(x) (((x) & 0x1) << 31)
> +
> +#define PLLOUT_DIV(x) (((x) & 0x7F) << 0)
> +#define PLLOUT_DIV_BY_1(x) (((x) & 0x1) << 8)
> +#define PLLOUT_CLK_EN(x) (((x) & 0x1) << 31)
> +
> +#define PLL_R_default 0x1
> +#define PLL_F_default 0x1F
> +#define PLL_Q_default 0x3
> +#define PLL_RANGE_default 0x0
> +#define PLL_BYPASS_default 0x1
> +#define PLL_FSE_default 0x1
> +
> +#define PLLOUT_DIV_default 0x0
> +#define PLLOUT_DIV_BY_1_default 0x0
> +#define PLLOUT_CLK_EN_default 0x0
> +
> +#define PLL_CORECLKSEL_HFXIN 0x1
> +#define PLL_CORECLKSEL_COREPLL 0x0
> +
> +#define DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1) << 0)
> +#define DEVICESRESET_DDR_AXI_RST_N(x) (((x) & 0x1) << 1)
> +#define DEVICESRESET_DDR_AHB_RST_N(x) (((x) & 0x1) << 2)
> +#define DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3)
> +#define DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)
> +
> +#define CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
> +
> +#endif // _SIFIVE_UX00PRCI_H
> diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
> index 2756ed5a77..ef3ae9b650 100644
> --- a/include/configs/sifive-fu540.h
> +++ b/include/configs/sifive-fu540.h
> @@ -11,6 +11,22 @@
>
> #include <linux/sizes.h>
>
> +#ifdef CONFIG_SPL
> +
> +#define CONFIG_SPL_MAX_SIZE 0x00100000
> +#define CONFIG_SPL_BSS_START_ADDR 0x85000000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
> +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
> + CONFIG_SPL_BSS_MAX_SIZE)
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
> +
> +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000
> +
> +#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \
> + GENERATED_GBL_DATA_SIZE)
> +
> +#endif
> +
> #define CONFIG_SYS_SDRAM_BASE 0x80000000
> #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
>
> @@ -24,6 +40,7 @@
>
> /* Environment options */
>
> +#ifndef CONFIG_SPL_BUILD
> #define BOOT_TARGET_DEVICES(func) \
> func(MMC, mmc, 0) \
> func(DHCP, dhcp, na)
> @@ -43,5 +60,6 @@
> #define CONFIG_PREBOOT \
> "setenv fdt_addr ${fdtcontroladdr};" \
> "fdt addr ${fdtcontroladdr};"
> +#endif
>
> #endif /* __CONFIG_H */
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 08/10] riscv: sifive: fu540: enable all cache ways from u-boot proper
2020-01-24 5:50 ` [PATCH v3 08/10] riscv: sifive: fu540: enable all cache ways from u-boot proper Pragnesh Patel
@ 2020-01-25 8:36 ` Anup Patel
0 siblings, 0 replies; 32+ messages in thread
From: Anup Patel @ 2020-01-25 8:36 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 11:22 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> This patch enables all cache ways from u-boot proper.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
> board/sifive/fu540/Makefile | 1 +
> board/sifive/fu540/cache.c | 30 ++++++++++++++++++++++++++++++
> board/sifive/fu540/cache.h | 13 +++++++++++++
> board/sifive/fu540/fu540.c | 6 ++++--
> 4 files changed, 48 insertions(+), 2 deletions(-)
> create mode 100644 board/sifive/fu540/cache.c
> create mode 100644 board/sifive/fu540/cache.h
>
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index cdcf894ade..a79928a0bf 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,6 +3,7 @@
> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
> obj-y += fu540.o
> +obj-y += cache.o
>
> ifdef CONFIG_SPL_BUILD
> obj-y += spl.o
> diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> new file mode 100644
> index 0000000000..c91728a678
> --- /dev/null
> +++ b/board/sifive/fu540/cache.c
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +#include <stdint.h>
> +#include <linux/types.h>
> +
> +/* Register offsets */
> +#define CACHE_ENABLE 0x008
> +
> +/* Block memory access until operation completed */
> +static void cache_barrier_0(void)
> +{
> + asm volatile("fence rw, io" : : : "memory");
> +}
> +
> +static void cache_barrier_1(void)
> +{
> + asm volatile("fence io, rw" : : : "memory");
> +}
> +
> +/* Enable ways; allow cache to use these ways */
> +void cache_enable_ways(u64 base_addr, u8 value)
> +{
> + volatile u32 *enable = (volatile u32 *)(base_addr +
> + CACHE_ENABLE);
> + cache_barrier_0();
> + (*enable) = value;
> + cache_barrier_1();
> +}
> diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> new file mode 100644
> index 0000000000..425124a23b
> --- /dev/null
> +++ b/board/sifive/fu540/cache.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#ifndef FU540_CACHE_H
> +#define FU540_CACHE_H
> +
> +#define CACHE_CTRL_ADDR _AC(0x2010000, UL)
> +
> +void cache_enable_ways(u64 base_addr, u8 value);
> +
> +#endif /* FU540_CACHE_H */
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index b81003aa6f..7fde881e72 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -13,6 +13,8 @@
> #include <misc.h>
> #include <spl.h>
>
> +#include "cache.h"
> +
> /*
> * This define is a value used for error/unknown serial.
> * If we really care about distinguishing errors and 0 is
> @@ -111,8 +113,8 @@ int misc_init_r(void)
>
> int board_init(void)
> {
> - /* For now nothing to do here. */
> -
> + /* enable all cache ways */
> + cache_enable_ways(CACHE_CTRL_ADDR, 15);
> return 0;
> }
>
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 09/10] sifive: fix palmer's email address and add sifive_fu540_spl_defconfig
2020-01-24 5:50 ` [PATCH v3 09/10] sifive: fix palmer's email address and add sifive_fu540_spl_defconfig Pragnesh Patel
@ 2020-01-25 8:37 ` Anup Patel
0 siblings, 0 replies; 32+ messages in thread
From: Anup Patel @ 2020-01-25 8:37 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 11:22 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> Fix Palmer's email address and add sifive_fu540_spl_defconfig
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
> board/sifive/fu540/MAINTAINERS | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
> index 702d803ad8..909a1bf300 100644
> --- a/board/sifive/fu540/MAINTAINERS
> +++ b/board/sifive/fu540/MAINTAINERS
> @@ -1,9 +1,10 @@
> SiFive FU540 BOARD
> M: Paul Walmsley <paul.walmsley@sifive.com>
> -M: Palmer Dabbelt <palmer@sifive.com>
> +M: Palmer Dabbelt <palmerdabbelt@google.com>
> M: Anup Patel <anup.patel@wdc.com>
> M: Atish Patra <atish.patra@wdc.com>
> S: Maintained
> F: board/sifive/fu540/
> F: include/configs/sifive-fu540.h
> F: configs/sifive_fu540_defconfig
> +F: configs/sifive_fu540_spl_defconfig
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
2020-01-24 6:50 ` Jagan Teki
@ 2020-01-25 8:41 ` Anup Patel
2020-01-27 7:49 ` Pragnesh Patel
2020-01-27 6:50 ` Pragnesh Patel
1 sibling, 1 reply; 32+ messages in thread
From: Anup Patel @ 2020-01-25 8:41 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 12:21 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
> <pragnesh.patel@sifive.com> wrote:
> >
> > With sifive_fu540_spl_defconfig:
> >
> > U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
> > u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
> > image u-boot.itb from 1st partition of SD card (replace fw_payload.bin
> > with u-boot.itb) into RAM.
> >
> > U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD
> > card irrespective of GUID
> >
> > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> > ---
>
> I'm thinking we don't need any separate config for SPL. Say if we have
> single config that creates both SPL and U-Boot proper and give
> feasibility to the user to use
> 1) SPL + U-Boot proper
> 2) SiFive SPL + U-Boot proper
>
> We are using a similar approach for other platforms, I guess the same
> will valid here, any comments?
I agree with Jagan.
We can augment all required SPL related config options directly
in sifive_fu540_defconfig but we have to ensure that u-boot.bin
created with updated sifive_fu540_defconfig works fine with
OpenSBI FW_PAYLOAD.
Regards,
Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
2020-01-24 6:50 ` Jagan Teki
2020-01-25 8:41 ` Anup Patel
@ 2020-01-27 6:50 ` Pragnesh Patel
2020-01-27 7:38 ` Anup Patel
1 sibling, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-27 6:50 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 24 January 2020 12:21
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
>Kadam <sagar.kadam@sifive.com>
>Subject: Re: [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
>
>On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> With sifive_fu540_spl_defconfig:
>>
>> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
>> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
>> image u-boot.itb from 1st partition of SD card (replace fw_payload.bin
>> with u-boot.itb) into RAM.
>>
>> U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD
>> card irrespective of GUID
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> ---
>
>I'm thinking we don't need any separate config for SPL. Say if we have single
>config that creates both SPL and U-Boot proper and give feasibility to the user
>to use
>1) SPL + U-Boot proper
>2) SiFive SPL + U-Boot proper
Sifive SPL ?
>
>We are using a similar approach for other platforms, I guess the same will
>valid here, any comments?
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
2020-01-27 6:50 ` Pragnesh Patel
@ 2020-01-27 7:38 ` Anup Patel
2020-01-27 7:41 ` Pragnesh Patel
0 siblings, 1 reply; 32+ messages in thread
From: Anup Patel @ 2020-01-27 7:38 UTC (permalink / raw)
To: u-boot
On Mon, Jan 27, 2020 at 12:20 PM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
>
> >-----Original Message-----
> >From: Jagan Teki <jagan@amarulasolutions.com>
> >Sent: 24 January 2020 12:21
> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
> ><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
> ><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
> ><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
> ><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
> >Kadam <sagar.kadam@sifive.com>
> >Subject: Re: [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
> >
> >On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel <pragnesh.patel@sifive.com>
> >wrote:
> >>
> >> With sifive_fu540_spl_defconfig:
> >>
> >> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
> >> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
> >> image u-boot.itb from 1st partition of SD card (replace fw_payload.bin
> >> with u-boot.itb) into RAM.
> >>
> >> U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD
> >> card irrespective of GUID
> >>
> >> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> >> ---
> >
> >I'm thinking we don't need any separate config for SPL. Say if we have single
> >config that creates both SPL and U-Boot proper and give feasibility to the user
> >to use
> >1) SPL + U-Boot proper
> >2) SiFive SPL + U-Boot proper
>
> Sifive SPL ?
I think what Jagan meant was:
1) U-Boot SPL + OpenSBI FW_DYNAMIC + U-Boot proper
2) FSBL + OpenSBI FW_PAYLOAD + U-Boot proper
So "SiFive SPL" is actually "FSBL"
Regards,
Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
2020-01-27 7:38 ` Anup Patel
@ 2020-01-27 7:41 ` Pragnesh Patel
0 siblings, 0 replies; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-27 7:41 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Anup Patel <anup@brainfault.org>
>Sent: 27 January 2020 13:09
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: Jagan Teki <jagan@amarulasolutions.com>; Atish Patra
><atish.patra@wdc.com>; palmerdabbelt at google.com; U-Boot-Denx <u-
>boot at lists.denx.de>
>Subject: Re: [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
>
>On Mon, Jan 27, 2020 at 12:20 PM Pragnesh Patel
><pragnesh.patel@sifive.com> wrote:
>>
>>
>> >-----Original Message-----
>> >From: Jagan Teki <jagan@amarulasolutions.com>
>> >Sent: 24 January 2020 12:21
>> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
>> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
>> ><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
>> ><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
>> ><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
>> ><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
>> >Kadam <sagar.kadam@sifive.com>
>> >Subject: Re: [PATCH v3 07/10] configs: fu540: Add config file for
>> >U-boot SPL
>> >
>> >On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
>> ><pragnesh.patel@sifive.com>
>> >wrote:
>> >>
>> >> With sifive_fu540_spl_defconfig:
>> >>
>> >> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin
>> >> with
>> >> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load
>> >> FIT image u-boot.itb from 1st partition of SD card (replace
>> >> fw_payload.bin with u-boot.itb) into RAM.
>> >>
>> >> U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD
>> >> card irrespective of GUID
>> >>
>> >> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> >> ---
>> >
>> >I'm thinking we don't need any separate config for SPL. Say if we
>> >have single config that creates both SPL and U-Boot proper and give
>> >feasibility to the user to use
>> >1) SPL + U-Boot proper
>> >2) SiFive SPL + U-Boot proper
>>
>> Sifive SPL ?
>
>I think what Jagan meant was:
>
>1) U-Boot SPL + OpenSBI FW_DYNAMIC + U-Boot proper
>2) FSBL + OpenSBI FW_PAYLOAD + U-Boot proper
>
>So "SiFive SPL" is actually "FSBL"
Ok, Thanks for the clarification.
>
>Regards,
>Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
2020-01-25 8:41 ` Anup Patel
@ 2020-01-27 7:49 ` Pragnesh Patel
2020-01-27 12:45 ` Anup Patel
0 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-27 7:49 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Anup Patel <anup@brainfault.org>
>Sent: 25 January 2020 14:12
>To: Jagan Teki <jagan@amarulasolutions.com>
>Cc: Pragnesh Patel <pragnesh.patel@sifive.com>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; U-
>Boot-Denx <u-boot@lists.denx.de>
>Subject: Re: [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
>
>On Fri, Jan 24, 2020 at 12:21 PM Jagan Teki <jagan@amarulasolutions.com>
>wrote:
>>
>> On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
>> <pragnesh.patel@sifive.com> wrote:
>> >
>> > With sifive_fu540_spl_defconfig:
>> >
>> > U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin
>> > with
>> > u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
>> > image u-boot.itb from 1st partition of SD card (replace
>> > fw_payload.bin with u-boot.itb) into RAM.
>> >
>> > U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD
>> > card irrespective of GUID
>> >
>> > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> > ---
>>
>> I'm thinking we don't need any separate config for SPL. Say if we have
>> single config that creates both SPL and U-Boot proper and give
>> feasibility to the user to use
>> 1) SPL + U-Boot proper
>> 2) SiFive SPL + U-Boot proper
>>
>> We are using a similar approach for other platforms, I guess the same
>> will valid here, any comments?
>
>I agree with Jagan.
>
>We can augment all required SPL related config options directly in
>sifive_fu540_defconfig but we have to ensure that u-boot.bin created with
>updated sifive_fu540_defconfig works fine with OpenSBI FW_PAYLOAD.
If SPL related configs will be included in sifive_fu540_defconfig then the generated
u-boot.bin works fine with OpenSBI FW_PAYLOAD.
There are 2 cases:
1) Without U-boot SPL -
FSBL + OpenSBI fw_payload + U-boot proper works.
2) With U-boot SPL -
SPL + FW_DYNAMIC + U-boot proper works.
Will include SPL related configs in sifive_fu540_defconfig in v4.
Any comments?
>
>Regards,
>Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info
2020-01-24 5:50 ` [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info Pragnesh Patel
2020-01-25 8:31 ` Anup Patel
@ 2020-01-27 7:51 ` Jagan Teki
2020-01-28 6:41 ` Pragnesh Patel
1 sibling, 1 reply; 32+ messages in thread
From: Jagan Teki @ 2020-01-27 7:51 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
> Add ddr4 controller and phy related files
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> ---
> board/sifive/fu540/Makefile | 4 +
> board/sifive/fu540/ddr.c | 868 ++++++++++++++++++++
> board/sifive/fu540/regconfig-ctl.h | 270 ++++++
> board/sifive/fu540/regconfig-phy.h | 1220 ++++++++++++++++++++++++++++
> board/sifive/fu540/ux00ddr.h | 45 +
> 5 files changed, 2407 insertions(+)
> create mode 100644 board/sifive/fu540/ddr.c
> create mode 100644 board/sifive/fu540/regconfig-ctl.h
> create mode 100644 board/sifive/fu540/regconfig-phy.h
> create mode 100644 board/sifive/fu540/ux00ddr.h
>
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index 6e1862c475..e4e76e1de3 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,3 +3,7 @@
> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
> obj-y += fu540.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += ddr.o
> +endif
> diff --git a/board/sifive/fu540/ddr.c b/board/sifive/fu540/ddr.c
> new file mode 100644
> index 0000000000..a4a86b1173
> --- /dev/null
> +++ b/board/sifive/fu540/ddr.c
> @@ -0,0 +1,868 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#include <common.h>
> +
> +#include "regconfig-ctl.h"
> +#include "regconfig-phy.h"
> +
> +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
> +
> +#define DRAM_CLASS_OFFSET 8
> +#define OPTIMAL_RMODW_EN_OFFSET 0
> +#define DISABLE_RD_INTERLEAVE_OFFSET 16
> +#define OUT_OF_RANGE_OFFSET 1
> +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
> +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
> +#define MC_INIT_COMPLETE_OFFSET 8
> +#define LEVELING_OPERATION_COMPLETED_OFFSET 22
> +#define DFI_PHY_WRLELV_MODE_OFFSET 24
> +#define DFI_PHY_RDLVL_MODE_OFFSET 24
> +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
> +#define VREF_EN_OFFSET 24
> +#define PORT_ADDR_PROTECTION_EN_OFFSET 0
> +#define AXI0_ADDRESS_RANGE_ENABLE 8
> +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
> +#define RDLVL_EN_OFFSET 16
> +#define RDLVL_GATE_EN_OFFSET 24
> +#define WRLVL_EN_OFFSET 0
> +
> +#define PHY_RX_CAL_DQ0_0_OFFSET 0
> +#define PHY_RX_CAL_DQ1_0_OFFSET 16
> +
> +static void phy_reset(u32 *ddrphyreg, const
> + u32 *physettings)
> +{
> + unsigned int i;
> +
> + for (i = 1152; i <= 1214; i++) {
> + u32 physet = physettings[i];
> + /*if (physet!=0)*/ ddrphyreg[i] = physet;
> + }
> +
> + for (i = 0; i <= 1151; i++) {
> + u32 physet = physettings[i];
> + /*if (physet!=0)*/ ddrphyreg[i] = physet;
> + }
> +}
> +
> +void ux00ddr_writeregmap(size_t ahbregaddr, const
> + u32 *ctlsettings, const u32 *physettings)
> +{
> + u32 *ddrctlreg = (u32 *)ahbregaddr;
> + u32 *ddrphyreg = ((u32 *)ahbregaddr) +
> + (0x2000 / sizeof(u32));
> +
> + unsigned int i;
> +
> + for (i = 0; i <= 264; i++) {
> + u32 ctlset = ctlsettings[i];
> + /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset;
> + }
> +
> + phy_reset(ddrphyreg, physettings);
> +}
> +
> +void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend)
> +{
> + // START register at ddrctl register base offset 0
> + u32 regdata = _REG32(0 << 2, ahbregaddr);
> +
> + regdata |= 0x1;
> + _REG32(0 << 2, ahbregaddr) = regdata;
> +
> + /*
> + * WAIT for initialization complete : bit 8 of INT_STATUS
> + * (DENALI_CTL_132) 0x210
> + */
> + while ((_REG32(132 << 2, ahbregaddr) & (1 <<
> + MC_INIT_COMPLETE_OFFSET)) == 0) {
> + }
> +
> + // Disable the BusBlocker in front of the controller AXI slave ports
> + u64 *filterreg = (u64 *)filteraddr;
> +
> + filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
> +}
> +
> +void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr)
> +{
> + /*
> + * Mask off Bit 8 of Interrupt Status
> + * Bit [8] The MC initialization has been completed
> + */
> +
> + _REG32(136 << 2, ahbregaddr) |= (1 << MC_INIT_COMPLETE_OFFSET);
> +}
> +
> +void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr)
> +{
> + /*
> + * Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status
> + * Bit [2] Multiple accesses outside the defined PHYSICAL memory
> + * space have occurred
> + * Bit [1] A memory access outside the defined PHYSICAL memory
> + * space has occurred
> + */
> +
> + _REG32(136 << 2, ahbregaddr) |= ((1 << OUT_OF_RANGE_OFFSET) | (1 <<
> + MULTIPLE_OUT_OF_RANGE_OFFSET));
> +}
> +
> +void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr)
> +{
> + /*
> + * Mask off Bit 7 of Interrupt Status
> + * Bit [7] An error occurred on the port command channel
> + */
> +
> + _REG32(136 << 2, ahbregaddr) |= (1 <<
> + PORT_COMMAND_CHANNEL_ERROR_OFFSET);
> +}
> +
> +void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr)
> +{
> + /*
> + * Mask off Bit 22 of Interrupt Status
> + * Bit [22] The leveling operation has completed
> + */
> +
> + _REG32(136 << 2, ahbregaddr) |= (1 <<
> + LEVELING_OPERATION_COMPLETED_OFFSET);
> +}
> +
> +void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr)
> +{
> + _REG32(209 << 2, ahbregaddr) = 0x0;
> + size_t end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
> +
> + _REG32(210 << 2, ahbregaddr) = ((u32)end_addr_16kblocks);
> + _REG32(212 << 2, ahbregaddr) = 0x0;
> + _REG32(214 << 2, ahbregaddr) = 0x0;
> + _REG32(216 << 2, ahbregaddr) = 0x0;
> + _REG32(224 << 2, ahbregaddr) |= (0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
> + _REG32(225 << 2, ahbregaddr) = 0xFFFFFFFF;
> + _REG32(208 << 2, ahbregaddr) |= (1 << AXI0_ADDRESS_RANGE_ENABLE);
> + _REG32(208 << 2, ahbregaddr) |= (1 << PORT_ADDR_PROTECTION_EN_OFFSET);
> +}
> +
> +void ux00ddr_disableaxireadinterleave(size_t ahbregaddr)
> +{
> + _REG32(120 << 2, ahbregaddr) |= (1 << DISABLE_RD_INTERLEAVE_OFFSET);
> +}
> +
> +void ux00ddr_disableoptimalrmodw(size_t ahbregaddr)
> +{
> + _REG32(21 << 2, ahbregaddr) &= (~(1 << OPTIMAL_RMODW_EN_OFFSET));
> +}
> +
> +void ux00ddr_enablewriteleveling(size_t ahbregaddr)
> +{
> + _REG32(170 << 2, ahbregaddr) |= ((1 << WRLVL_EN_OFFSET) | (1 <<
> + DFI_PHY_WRLELV_MODE_OFFSET));
> +}
> +
> +void ux00ddr_enablereadleveling(size_t ahbregaddr)
> +{
> + _REG32(181 << 2, ahbregaddr) |= (1 << DFI_PHY_RDLVL_MODE_OFFSET);
> + _REG32(260 << 2, ahbregaddr) |= (1 << RDLVL_EN_OFFSET);
> +}
> +
> +void ux00ddr_enablereadlevelinggate(size_t ahbregaddr)
> +{
> + _REG32(260 << 2, ahbregaddr) |= (1 << RDLVL_GATE_EN_OFFSET);
> + _REG32(182 << 2, ahbregaddr) |= (1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
> +}
> +
> +void ux00ddr_enablevreftraining(size_t ahbregaddr)
> +{
> + _REG32(184 << 2, ahbregaddr) |= (1 << VREF_EN_OFFSET);
> +}
> +
> +u32 ux00ddr_getdramclass(size_t ahbregaddr)
> +{
> + return((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF);
> +}
> +
> +u64 ux00ddr_phy_fixup(size_t ahbregaddr)
> +{
> + // return bitmask of failed lanes
> +
> + size_t ddrphyreg = ahbregaddr + 0x2000;
> +
> + u64 fails = 0;
> + u32 slicebase = 0;
> + u32 dq = 0;
> +
> + // check errata condition
> + for (u32 slice = 0; slice < 8; slice++) {
> + u32 regbase = slicebase + 34;
> +
> + for (u32 reg = 0; reg < 4; reg++) {
> + u32 updownreg = _REG32((regbase + reg) << 2,
> + ddrphyreg);
> +
> + for (u32 bit = 0; bit < 2; bit++) {
> + u32 phy_rx_cal_dqn_0_offset;
> +
> + if (bit == 0) {
> + phy_rx_cal_dqn_0_offset =
> + PHY_RX_CAL_DQ0_0_OFFSET;
> + } else {
> + phy_rx_cal_dqn_0_offset =
> + PHY_RX_CAL_DQ1_0_OFFSET;
> + }
> +
> + u32 down = (updownreg >>
> + phy_rx_cal_dqn_0_offset) & 0x3F;
> + u32 up = (updownreg >>
> + (phy_rx_cal_dqn_0_offset + 6)) &
> + 0x3F;
> +
> + u8 failc0 = ((down == 0) && (up == 0x3F));
> + u8 failc1 = ((up == 0) && (down == 0x3F));
> +
> + // print error message on failure
> + if (failc0 || failc1) {
> + if (fails == 0)
> + printf("DDR error in fixing up\n");
> +
> + fails |= (1 << dq);
> +
> + char slicelsc = '0';
> + char slicemsc = '0';
> +
> + slicelsc += (dq % 10);
> + slicemsc += (dq / 10);
> + printf("S ");
> + printf("%c", slicemsc);
> + printf("%c", slicelsc);
> +
> + if (failc0)
> + printf("U");
> + else
> + printf("D");
> +
> + printf("\n");
> + }
> + dq++;
> + }
> + }
> + slicebase += 128;
> + }
> + return(0);
> +}
> +
> +u32 ddr_phy_settings[1215] = {
> + DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, DENALI_PHY_02_DATA,
> + DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, DENALI_PHY_05_DATA,
> + DENALI_PHY_06_DATA, DENALI_PHY_07_DATA, DENALI_PHY_08_DATA,
> + DENALI_PHY_09_DATA,
> + DENALI_PHY_10_DATA, DENALI_PHY_11_DATA, DENALI_PHY_12_DATA,
> + DENALI_PHY_13_DATA, DENALI_PHY_14_DATA, DENALI_PHY_15_DATA,
> + DENALI_PHY_16_DATA, DENALI_PHY_17_DATA, DENALI_PHY_18_DATA,
> + DENALI_PHY_19_DATA,
> + DENALI_PHY_20_DATA, DENALI_PHY_21_DATA, DENALI_PHY_22_DATA,
> + DENALI_PHY_23_DATA, DENALI_PHY_24_DATA, DENALI_PHY_25_DATA,
> + DENALI_PHY_26_DATA, DENALI_PHY_27_DATA, DENALI_PHY_28_DATA,
> + DENALI_PHY_29_DATA,
> + DENALI_PHY_30_DATA, DENALI_PHY_31_DATA, DENALI_PHY_32_DATA,
> + DENALI_PHY_33_DATA, DENALI_PHY_34_DATA, DENALI_PHY_35_DATA,
> + DENALI_PHY_36_DATA, DENALI_PHY_37_DATA, DENALI_PHY_38_DATA,
> + DENALI_PHY_39_DATA,
> + DENALI_PHY_40_DATA, DENALI_PHY_41_DATA, DENALI_PHY_42_DATA,
> + DENALI_PHY_43_DATA, DENALI_PHY_44_DATA, DENALI_PHY_45_DATA,
> + DENALI_PHY_46_DATA, DENALI_PHY_47_DATA, DENALI_PHY_48_DATA,
> + DENALI_PHY_49_DATA,
> + DENALI_PHY_50_DATA, DENALI_PHY_51_DATA, DENALI_PHY_52_DATA,
> + DENALI_PHY_53_DATA, DENALI_PHY_54_DATA, DENALI_PHY_55_DATA,
> + DENALI_PHY_56_DATA, DENALI_PHY_57_DATA, DENALI_PHY_58_DATA,
> + DENALI_PHY_59_DATA,
> + DENALI_PHY_60_DATA, DENALI_PHY_61_DATA, DENALI_PHY_62_DATA,
> + DENALI_PHY_63_DATA, DENALI_PHY_64_DATA, DENALI_PHY_65_DATA,
> + DENALI_PHY_66_DATA, DENALI_PHY_67_DATA, DENALI_PHY_68_DATA,
> + DENALI_PHY_69_DATA,
> + DENALI_PHY_70_DATA, DENALI_PHY_71_DATA, DENALI_PHY_72_DATA,
> + DENALI_PHY_73_DATA, DENALI_PHY_74_DATA, DENALI_PHY_75_DATA,
> + DENALI_PHY_76_DATA, DENALI_PHY_77_DATA, DENALI_PHY_78_DATA,
> + DENALI_PHY_79_DATA,
> + DENALI_PHY_80_DATA, DENALI_PHY_81_DATA, DENALI_PHY_82_DATA,
> + DENALI_PHY_83_DATA, DENALI_PHY_84_DATA, DENALI_PHY_85_DATA,
> + DENALI_PHY_86_DATA, DENALI_PHY_87_DATA, DENALI_PHY_88_DATA,
> + DENALI_PHY_89_DATA,
> + DENALI_PHY_90_DATA, DENALI_PHY_91_DATA, DENALI_PHY_92_DATA,
> + DENALI_PHY_93_DATA, DENALI_PHY_94_DATA, DENALI_PHY_95_DATA,
> + DENALI_PHY_96_DATA, DENALI_PHY_97_DATA, DENALI_PHY_98_DATA,
> + DENALI_PHY_99_DATA,
> +
> + DENALI_PHY_100_DATA, DENALI_PHY_101_DATA, DENALI_PHY_102_DATA,
> + DENALI_PHY_103_DATA, DENALI_PHY_104_DATA, DENALI_PHY_105_DATA,
> + DENALI_PHY_106_DATA, DENALI_PHY_107_DATA, DENALI_PHY_108_DATA,
> + DENALI_PHY_109_DATA,
> + DENALI_PHY_110_DATA, DENALI_PHY_111_DATA, DENALI_PHY_112_DATA,
> + DENALI_PHY_113_DATA, DENALI_PHY_114_DATA, DENALI_PHY_115_DATA,
> + DENALI_PHY_116_DATA, DENALI_PHY_117_DATA, DENALI_PHY_118_DATA,
> + DENALI_PHY_119_DATA,
> + DENALI_PHY_120_DATA, DENALI_PHY_121_DATA, DENALI_PHY_122_DATA,
> + DENALI_PHY_123_DATA, DENALI_PHY_124_DATA, DENALI_PHY_125_DATA,
> + DENALI_PHY_126_DATA, DENALI_PHY_127_DATA, DENALI_PHY_128_DATA,
> + DENALI_PHY_129_DATA,
> + DENALI_PHY_130_DATA, DENALI_PHY_131_DATA, DENALI_PHY_132_DATA,
> + DENALI_PHY_133_DATA, DENALI_PHY_134_DATA, DENALI_PHY_135_DATA,
> + DENALI_PHY_136_DATA, DENALI_PHY_137_DATA, DENALI_PHY_138_DATA,
> + DENALI_PHY_139_DATA,
> + DENALI_PHY_140_DATA, DENALI_PHY_141_DATA, DENALI_PHY_142_DATA,
> + DENALI_PHY_143_DATA, DENALI_PHY_144_DATA, DENALI_PHY_145_DATA,
> + DENALI_PHY_146_DATA, DENALI_PHY_147_DATA, DENALI_PHY_148_DATA,
> + DENALI_PHY_149_DATA,
> + DENALI_PHY_150_DATA, DENALI_PHY_151_DATA, DENALI_PHY_152_DATA,
> + DENALI_PHY_153_DATA, DENALI_PHY_154_DATA, DENALI_PHY_155_DATA,
> + DENALI_PHY_156_DATA, DENALI_PHY_157_DATA, DENALI_PHY_158_DATA,
> + DENALI_PHY_159_DATA,
> + DENALI_PHY_160_DATA, DENALI_PHY_161_DATA, DENALI_PHY_162_DATA,
> + DENALI_PHY_163_DATA, DENALI_PHY_164_DATA, DENALI_PHY_165_DATA,
> + DENALI_PHY_166_DATA, DENALI_PHY_167_DATA, DENALI_PHY_168_DATA,
> + DENALI_PHY_169_DATA,
> + DENALI_PHY_170_DATA, DENALI_PHY_171_DATA, DENALI_PHY_172_DATA,
> + DENALI_PHY_173_DATA, DENALI_PHY_174_DATA, DENALI_PHY_175_DATA,
> + DENALI_PHY_176_DATA, DENALI_PHY_177_DATA, DENALI_PHY_178_DATA,
> + DENALI_PHY_179_DATA,
> + DENALI_PHY_180_DATA, DENALI_PHY_181_DATA, DENALI_PHY_182_DATA,
> + DENALI_PHY_183_DATA, DENALI_PHY_184_DATA, DENALI_PHY_185_DATA,
> + DENALI_PHY_186_DATA, DENALI_PHY_187_DATA, DENALI_PHY_188_DATA,
> + DENALI_PHY_189_DATA,
> + DENALI_PHY_190_DATA, DENALI_PHY_191_DATA, DENALI_PHY_192_DATA,
> + DENALI_PHY_193_DATA, DENALI_PHY_194_DATA, DENALI_PHY_195_DATA,
> + DENALI_PHY_196_DATA, DENALI_PHY_197_DATA, DENALI_PHY_198_DATA,
> + DENALI_PHY_199_DATA,
> +
> + DENALI_PHY_200_DATA, DENALI_PHY_201_DATA, DENALI_PHY_202_DATA,
> + DENALI_PHY_203_DATA, DENALI_PHY_204_DATA, DENALI_PHY_205_DATA,
> + DENALI_PHY_206_DATA, DENALI_PHY_207_DATA, DENALI_PHY_208_DATA,
> + DENALI_PHY_209_DATA,
> + DENALI_PHY_210_DATA, DENALI_PHY_211_DATA, DENALI_PHY_212_DATA,
> + DENALI_PHY_213_DATA, DENALI_PHY_214_DATA, DENALI_PHY_215_DATA,
> + DENALI_PHY_216_DATA, DENALI_PHY_217_DATA, DENALI_PHY_218_DATA,
> + DENALI_PHY_219_DATA,
> + DENALI_PHY_220_DATA, DENALI_PHY_221_DATA, DENALI_PHY_222_DATA,
> + DENALI_PHY_223_DATA, DENALI_PHY_224_DATA, DENALI_PHY_225_DATA,
> + DENALI_PHY_226_DATA, DENALI_PHY_227_DATA, DENALI_PHY_228_DATA,
> + DENALI_PHY_229_DATA,
> + DENALI_PHY_230_DATA, DENALI_PHY_231_DATA, DENALI_PHY_232_DATA,
> + DENALI_PHY_233_DATA, DENALI_PHY_234_DATA, DENALI_PHY_235_DATA,
> + DENALI_PHY_236_DATA, DENALI_PHY_237_DATA, DENALI_PHY_238_DATA,
> + DENALI_PHY_239_DATA,
> + DENALI_PHY_240_DATA, DENALI_PHY_241_DATA, DENALI_PHY_242_DATA,
> + DENALI_PHY_243_DATA, DENALI_PHY_244_DATA, DENALI_PHY_245_DATA,
> + DENALI_PHY_246_DATA, DENALI_PHY_247_DATA, DENALI_PHY_248_DATA,
> + DENALI_PHY_249_DATA,
> + DENALI_PHY_250_DATA, DENALI_PHY_251_DATA, DENALI_PHY_252_DATA,
> + DENALI_PHY_253_DATA, DENALI_PHY_254_DATA, DENALI_PHY_255_DATA,
> + DENALI_PHY_256_DATA, DENALI_PHY_257_DATA, DENALI_PHY_258_DATA,
> + DENALI_PHY_259_DATA,
> + DENALI_PHY_260_DATA, DENALI_PHY_261_DATA, DENALI_PHY_262_DATA,
> + DENALI_PHY_263_DATA, DENALI_PHY_264_DATA, DENALI_PHY_265_DATA,
> + DENALI_PHY_266_DATA, DENALI_PHY_267_DATA, DENALI_PHY_268_DATA,
> + DENALI_PHY_269_DATA,
> + DENALI_PHY_270_DATA, DENALI_PHY_271_DATA, DENALI_PHY_272_DATA,
> + DENALI_PHY_273_DATA, DENALI_PHY_274_DATA, DENALI_PHY_275_DATA,
> + DENALI_PHY_276_DATA, DENALI_PHY_277_DATA, DENALI_PHY_278_DATA,
> + DENALI_PHY_279_DATA,
> + DENALI_PHY_280_DATA, DENALI_PHY_281_DATA, DENALI_PHY_282_DATA,
> + DENALI_PHY_283_DATA, DENALI_PHY_284_DATA, DENALI_PHY_285_DATA,
> + DENALI_PHY_286_DATA, DENALI_PHY_287_DATA, DENALI_PHY_288_DATA,
> + DENALI_PHY_289_DATA,
> + DENALI_PHY_290_DATA, DENALI_PHY_291_DATA, DENALI_PHY_292_DATA,
> + DENALI_PHY_293_DATA, DENALI_PHY_294_DATA, DENALI_PHY_295_DATA,
> + DENALI_PHY_296_DATA, DENALI_PHY_297_DATA, DENALI_PHY_298_DATA,
> + DENALI_PHY_299_DATA,
> +
> + DENALI_PHY_300_DATA, DENALI_PHY_301_DATA, DENALI_PHY_302_DATA,
> + DENALI_PHY_303_DATA, DENALI_PHY_304_DATA, DENALI_PHY_305_DATA,
> + DENALI_PHY_306_DATA, DENALI_PHY_307_DATA, DENALI_PHY_308_DATA,
> + DENALI_PHY_309_DATA,
> + DENALI_PHY_310_DATA, DENALI_PHY_311_DATA, DENALI_PHY_312_DATA,
> + DENALI_PHY_313_DATA, DENALI_PHY_314_DATA, DENALI_PHY_315_DATA,
> + DENALI_PHY_316_DATA, DENALI_PHY_317_DATA, DENALI_PHY_318_DATA,
> + DENALI_PHY_319_DATA,
> + DENALI_PHY_320_DATA, DENALI_PHY_321_DATA, DENALI_PHY_322_DATA,
> + DENALI_PHY_323_DATA, DENALI_PHY_324_DATA, DENALI_PHY_325_DATA,
> + DENALI_PHY_326_DATA, DENALI_PHY_327_DATA, DENALI_PHY_328_DATA,
> + DENALI_PHY_329_DATA,
> + DENALI_PHY_330_DATA, DENALI_PHY_331_DATA, DENALI_PHY_332_DATA,
> + DENALI_PHY_333_DATA, DENALI_PHY_334_DATA, DENALI_PHY_335_DATA,
> + DENALI_PHY_336_DATA, DENALI_PHY_337_DATA, DENALI_PHY_338_DATA,
> + DENALI_PHY_339_DATA,
> + DENALI_PHY_340_DATA, DENALI_PHY_341_DATA, DENALI_PHY_342_DATA,
> + DENALI_PHY_343_DATA, DENALI_PHY_344_DATA, DENALI_PHY_345_DATA,
> + DENALI_PHY_346_DATA, DENALI_PHY_347_DATA, DENALI_PHY_348_DATA,
> + DENALI_PHY_349_DATA,
> + DENALI_PHY_350_DATA, DENALI_PHY_351_DATA, DENALI_PHY_352_DATA,
> + DENALI_PHY_353_DATA, DENALI_PHY_354_DATA, DENALI_PHY_355_DATA,
> + DENALI_PHY_356_DATA, DENALI_PHY_357_DATA, DENALI_PHY_358_DATA,
> + DENALI_PHY_359_DATA,
> + DENALI_PHY_360_DATA, DENALI_PHY_361_DATA, DENALI_PHY_362_DATA,
> + DENALI_PHY_363_DATA, DENALI_PHY_364_DATA, DENALI_PHY_365_DATA,
> + DENALI_PHY_366_DATA, DENALI_PHY_367_DATA, DENALI_PHY_368_DATA,
> + DENALI_PHY_369_DATA,
> + DENALI_PHY_370_DATA, DENALI_PHY_371_DATA, DENALI_PHY_372_DATA,
> + DENALI_PHY_373_DATA, DENALI_PHY_374_DATA, DENALI_PHY_375_DATA,
> + DENALI_PHY_376_DATA, DENALI_PHY_377_DATA, DENALI_PHY_378_DATA,
> + DENALI_PHY_379_DATA,
> + DENALI_PHY_380_DATA, DENALI_PHY_381_DATA, DENALI_PHY_382_DATA,
> + DENALI_PHY_383_DATA, DENALI_PHY_384_DATA, DENALI_PHY_385_DATA,
> + DENALI_PHY_386_DATA, DENALI_PHY_387_DATA, DENALI_PHY_388_DATA,
> + DENALI_PHY_389_DATA,
> + DENALI_PHY_390_DATA, DENALI_PHY_391_DATA, DENALI_PHY_392_DATA,
> + DENALI_PHY_393_DATA, DENALI_PHY_394_DATA, DENALI_PHY_395_DATA,
> + DENALI_PHY_396_DATA, DENALI_PHY_397_DATA, DENALI_PHY_398_DATA,
> + DENALI_PHY_399_DATA,
> +
> + DENALI_PHY_400_DATA, DENALI_PHY_401_DATA, DENALI_PHY_402_DATA,
> + DENALI_PHY_403_DATA, DENALI_PHY_404_DATA, DENALI_PHY_405_DATA,
> + DENALI_PHY_406_DATA, DENALI_PHY_407_DATA, DENALI_PHY_408_DATA,
> + DENALI_PHY_409_DATA,
> + DENALI_PHY_410_DATA, DENALI_PHY_411_DATA, DENALI_PHY_412_DATA,
> + DENALI_PHY_413_DATA, DENALI_PHY_414_DATA, DENALI_PHY_415_DATA,
> + DENALI_PHY_416_DATA, DENALI_PHY_417_DATA, DENALI_PHY_418_DATA,
> + DENALI_PHY_419_DATA,
> + DENALI_PHY_420_DATA, DENALI_PHY_421_DATA, DENALI_PHY_422_DATA,
> + DENALI_PHY_423_DATA, DENALI_PHY_424_DATA, DENALI_PHY_425_DATA,
> + DENALI_PHY_426_DATA, DENALI_PHY_427_DATA, DENALI_PHY_428_DATA,
> + DENALI_PHY_429_DATA,
> + DENALI_PHY_430_DATA, DENALI_PHY_431_DATA, DENALI_PHY_432_DATA,
> + DENALI_PHY_433_DATA, DENALI_PHY_434_DATA, DENALI_PHY_435_DATA,
> + DENALI_PHY_436_DATA, DENALI_PHY_437_DATA, DENALI_PHY_438_DATA,
> + DENALI_PHY_439_DATA,
> + DENALI_PHY_440_DATA, DENALI_PHY_441_DATA, DENALI_PHY_442_DATA,
> + DENALI_PHY_443_DATA, DENALI_PHY_444_DATA, DENALI_PHY_445_DATA,
> + DENALI_PHY_446_DATA, DENALI_PHY_447_DATA, DENALI_PHY_448_DATA,
> + DENALI_PHY_449_DATA,
> + DENALI_PHY_450_DATA, DENALI_PHY_451_DATA, DENALI_PHY_452_DATA,
> + DENALI_PHY_453_DATA, DENALI_PHY_454_DATA, DENALI_PHY_455_DATA,
> + DENALI_PHY_456_DATA, DENALI_PHY_457_DATA, DENALI_PHY_458_DATA,
> + DENALI_PHY_459_DATA,
> + DENALI_PHY_460_DATA, DENALI_PHY_461_DATA, DENALI_PHY_462_DATA,
> + DENALI_PHY_463_DATA, DENALI_PHY_464_DATA, DENALI_PHY_465_DATA,
> + DENALI_PHY_466_DATA, DENALI_PHY_467_DATA, DENALI_PHY_468_DATA,
> + DENALI_PHY_469_DATA,
> + DENALI_PHY_470_DATA, DENALI_PHY_471_DATA, DENALI_PHY_472_DATA,
> + DENALI_PHY_473_DATA, DENALI_PHY_474_DATA, DENALI_PHY_475_DATA,
> + DENALI_PHY_476_DATA, DENALI_PHY_477_DATA, DENALI_PHY_478_DATA,
> + DENALI_PHY_479_DATA,
> + DENALI_PHY_480_DATA, DENALI_PHY_481_DATA, DENALI_PHY_482_DATA,
> + DENALI_PHY_483_DATA, DENALI_PHY_484_DATA, DENALI_PHY_485_DATA,
> + DENALI_PHY_486_DATA, DENALI_PHY_487_DATA, DENALI_PHY_488_DATA,
> + DENALI_PHY_489_DATA,
> + DENALI_PHY_490_DATA, DENALI_PHY_491_DATA, DENALI_PHY_492_DATA,
> + DENALI_PHY_493_DATA, DENALI_PHY_494_DATA, DENALI_PHY_495_DATA,
> + DENALI_PHY_496_DATA, DENALI_PHY_497_DATA, DENALI_PHY_498_DATA,
> + DENALI_PHY_499_DATA,
> +
> + DENALI_PHY_500_DATA, DENALI_PHY_501_DATA, DENALI_PHY_502_DATA,
> + DENALI_PHY_503_DATA, DENALI_PHY_504_DATA, DENALI_PHY_505_DATA,
> + DENALI_PHY_506_DATA, DENALI_PHY_507_DATA, DENALI_PHY_508_DATA,
> + DENALI_PHY_509_DATA,
> + DENALI_PHY_510_DATA, DENALI_PHY_511_DATA, DENALI_PHY_512_DATA,
> + DENALI_PHY_513_DATA, DENALI_PHY_514_DATA, DENALI_PHY_515_DATA,
> + DENALI_PHY_516_DATA, DENALI_PHY_517_DATA, DENALI_PHY_518_DATA,
> + DENALI_PHY_519_DATA,
> + DENALI_PHY_520_DATA, DENALI_PHY_521_DATA, DENALI_PHY_522_DATA,
> + DENALI_PHY_523_DATA, DENALI_PHY_524_DATA, DENALI_PHY_525_DATA,
> + DENALI_PHY_526_DATA, DENALI_PHY_527_DATA, DENALI_PHY_528_DATA,
> + DENALI_PHY_529_DATA,
> + DENALI_PHY_530_DATA, DENALI_PHY_531_DATA, DENALI_PHY_532_DATA,
> + DENALI_PHY_533_DATA, DENALI_PHY_534_DATA, DENALI_PHY_535_DATA,
> + DENALI_PHY_536_DATA, DENALI_PHY_537_DATA, DENALI_PHY_538_DATA,
> + DENALI_PHY_539_DATA,
> + DENALI_PHY_540_DATA, DENALI_PHY_541_DATA, DENALI_PHY_542_DATA,
> + DENALI_PHY_543_DATA, DENALI_PHY_544_DATA, DENALI_PHY_545_DATA,
> + DENALI_PHY_546_DATA, DENALI_PHY_547_DATA, DENALI_PHY_548_DATA,
> + DENALI_PHY_549_DATA,
> + DENALI_PHY_550_DATA, DENALI_PHY_551_DATA, DENALI_PHY_552_DATA,
> + DENALI_PHY_553_DATA, DENALI_PHY_554_DATA, DENALI_PHY_555_DATA,
> + DENALI_PHY_556_DATA, DENALI_PHY_557_DATA, DENALI_PHY_558_DATA,
> + DENALI_PHY_559_DATA,
> + DENALI_PHY_560_DATA, DENALI_PHY_561_DATA, DENALI_PHY_562_DATA,
> + DENALI_PHY_563_DATA, DENALI_PHY_564_DATA, DENALI_PHY_565_DATA,
> + DENALI_PHY_566_DATA, DENALI_PHY_567_DATA, DENALI_PHY_568_DATA,
> + DENALI_PHY_569_DATA,
> + DENALI_PHY_570_DATA, DENALI_PHY_571_DATA, DENALI_PHY_572_DATA,
> + DENALI_PHY_573_DATA, DENALI_PHY_574_DATA, DENALI_PHY_575_DATA,
> + DENALI_PHY_576_DATA, DENALI_PHY_577_DATA, DENALI_PHY_578_DATA,
> + DENALI_PHY_579_DATA,
> + DENALI_PHY_580_DATA, DENALI_PHY_581_DATA, DENALI_PHY_582_DATA,
> + DENALI_PHY_583_DATA, DENALI_PHY_584_DATA, DENALI_PHY_585_DATA,
> + DENALI_PHY_586_DATA, DENALI_PHY_587_DATA, DENALI_PHY_588_DATA,
> + DENALI_PHY_589_DATA,
> + DENALI_PHY_590_DATA, DENALI_PHY_591_DATA, DENALI_PHY_592_DATA,
> + DENALI_PHY_593_DATA, DENALI_PHY_594_DATA, DENALI_PHY_595_DATA,
> + DENALI_PHY_596_DATA, DENALI_PHY_597_DATA, DENALI_PHY_598_DATA,
> + DENALI_PHY_599_DATA,
> +
> + DENALI_PHY_600_DATA, DENALI_PHY_601_DATA, DENALI_PHY_602_DATA,
> + DENALI_PHY_603_DATA, DENALI_PHY_604_DATA, DENALI_PHY_605_DATA,
> + DENALI_PHY_606_DATA, DENALI_PHY_607_DATA, DENALI_PHY_608_DATA,
> + DENALI_PHY_609_DATA,
> + DENALI_PHY_610_DATA, DENALI_PHY_611_DATA, DENALI_PHY_612_DATA,
> + DENALI_PHY_613_DATA, DENALI_PHY_614_DATA, DENALI_PHY_615_DATA,
> + DENALI_PHY_616_DATA, DENALI_PHY_617_DATA, DENALI_PHY_618_DATA,
> + DENALI_PHY_619_DATA,
> + DENALI_PHY_620_DATA, DENALI_PHY_621_DATA, DENALI_PHY_622_DATA,
> + DENALI_PHY_623_DATA, DENALI_PHY_624_DATA, DENALI_PHY_625_DATA,
> + DENALI_PHY_626_DATA, DENALI_PHY_627_DATA, DENALI_PHY_628_DATA,
> + DENALI_PHY_629_DATA,
> + DENALI_PHY_630_DATA, DENALI_PHY_631_DATA, DENALI_PHY_632_DATA,
> + DENALI_PHY_633_DATA, DENALI_PHY_634_DATA, DENALI_PHY_635_DATA,
> + DENALI_PHY_636_DATA, DENALI_PHY_637_DATA, DENALI_PHY_638_DATA,
> + DENALI_PHY_639_DATA,
> + DENALI_PHY_640_DATA, DENALI_PHY_641_DATA, DENALI_PHY_642_DATA,
> + DENALI_PHY_643_DATA, DENALI_PHY_644_DATA, DENALI_PHY_645_DATA,
> + DENALI_PHY_646_DATA, DENALI_PHY_647_DATA, DENALI_PHY_648_DATA,
> + DENALI_PHY_649_DATA,
> + DENALI_PHY_650_DATA, DENALI_PHY_651_DATA, DENALI_PHY_652_DATA,
> + DENALI_PHY_653_DATA, DENALI_PHY_654_DATA, DENALI_PHY_655_DATA,
> + DENALI_PHY_656_DATA, DENALI_PHY_657_DATA, DENALI_PHY_658_DATA,
> + DENALI_PHY_659_DATA,
> + DENALI_PHY_660_DATA, DENALI_PHY_661_DATA, DENALI_PHY_662_DATA,
> + DENALI_PHY_663_DATA, DENALI_PHY_664_DATA, DENALI_PHY_665_DATA,
> + DENALI_PHY_666_DATA, DENALI_PHY_667_DATA, DENALI_PHY_668_DATA,
> + DENALI_PHY_669_DATA,
> + DENALI_PHY_670_DATA, DENALI_PHY_671_DATA, DENALI_PHY_672_DATA,
> + DENALI_PHY_673_DATA, DENALI_PHY_674_DATA, DENALI_PHY_675_DATA,
> + DENALI_PHY_676_DATA, DENALI_PHY_677_DATA, DENALI_PHY_678_DATA,
> + DENALI_PHY_679_DATA,
> + DENALI_PHY_680_DATA, DENALI_PHY_681_DATA, DENALI_PHY_682_DATA,
> + DENALI_PHY_683_DATA, DENALI_PHY_684_DATA, DENALI_PHY_685_DATA,
> + DENALI_PHY_686_DATA, DENALI_PHY_687_DATA, DENALI_PHY_688_DATA,
> + DENALI_PHY_689_DATA,
> + DENALI_PHY_690_DATA, DENALI_PHY_691_DATA, DENALI_PHY_692_DATA,
> + DENALI_PHY_693_DATA, DENALI_PHY_694_DATA, DENALI_PHY_695_DATA,
> + DENALI_PHY_696_DATA, DENALI_PHY_697_DATA, DENALI_PHY_698_DATA,
> + DENALI_PHY_699_DATA,
> +
> + DENALI_PHY_700_DATA, DENALI_PHY_701_DATA, DENALI_PHY_702_DATA,
> + DENALI_PHY_703_DATA, DENALI_PHY_704_DATA, DENALI_PHY_705_DATA,
> + DENALI_PHY_706_DATA, DENALI_PHY_707_DATA, DENALI_PHY_708_DATA,
> + DENALI_PHY_709_DATA,
> + DENALI_PHY_710_DATA, DENALI_PHY_711_DATA, DENALI_PHY_712_DATA,
> + DENALI_PHY_713_DATA, DENALI_PHY_714_DATA, DENALI_PHY_715_DATA,
> + DENALI_PHY_716_DATA, DENALI_PHY_717_DATA, DENALI_PHY_718_DATA,
> + DENALI_PHY_719_DATA,
> + DENALI_PHY_720_DATA, DENALI_PHY_721_DATA, DENALI_PHY_722_DATA,
> + DENALI_PHY_723_DATA, DENALI_PHY_724_DATA, DENALI_PHY_725_DATA,
> + DENALI_PHY_726_DATA, DENALI_PHY_727_DATA, DENALI_PHY_728_DATA,
> + DENALI_PHY_729_DATA,
> + DENALI_PHY_730_DATA, DENALI_PHY_731_DATA, DENALI_PHY_732_DATA,
> + DENALI_PHY_733_DATA, DENALI_PHY_734_DATA, DENALI_PHY_735_DATA,
> + DENALI_PHY_736_DATA, DENALI_PHY_737_DATA, DENALI_PHY_738_DATA,
> + DENALI_PHY_739_DATA,
> + DENALI_PHY_740_DATA, DENALI_PHY_741_DATA, DENALI_PHY_742_DATA,
> + DENALI_PHY_743_DATA, DENALI_PHY_744_DATA, DENALI_PHY_745_DATA,
> + DENALI_PHY_746_DATA, DENALI_PHY_747_DATA, DENALI_PHY_748_DATA,
> + DENALI_PHY_749_DATA,
> + DENALI_PHY_750_DATA, DENALI_PHY_751_DATA, DENALI_PHY_752_DATA,
> + DENALI_PHY_753_DATA, DENALI_PHY_754_DATA, DENALI_PHY_755_DATA,
> + DENALI_PHY_756_DATA, DENALI_PHY_757_DATA, DENALI_PHY_758_DATA,
> + DENALI_PHY_759_DATA,
> + DENALI_PHY_760_DATA, DENALI_PHY_761_DATA, DENALI_PHY_762_DATA,
> + DENALI_PHY_763_DATA, DENALI_PHY_764_DATA, DENALI_PHY_765_DATA,
> + DENALI_PHY_766_DATA, DENALI_PHY_767_DATA, DENALI_PHY_768_DATA,
> + DENALI_PHY_769_DATA,
> + DENALI_PHY_770_DATA, DENALI_PHY_771_DATA, DENALI_PHY_772_DATA,
> + DENALI_PHY_773_DATA, DENALI_PHY_774_DATA, DENALI_PHY_775_DATA,
> + DENALI_PHY_776_DATA, DENALI_PHY_777_DATA, DENALI_PHY_778_DATA,
> + DENALI_PHY_779_DATA,
> + DENALI_PHY_780_DATA, DENALI_PHY_781_DATA, DENALI_PHY_782_DATA,
> + DENALI_PHY_783_DATA, DENALI_PHY_784_DATA, DENALI_PHY_785_DATA,
> + DENALI_PHY_786_DATA, DENALI_PHY_787_DATA, DENALI_PHY_788_DATA,
> + DENALI_PHY_789_DATA,
> + DENALI_PHY_790_DATA, DENALI_PHY_791_DATA, DENALI_PHY_792_DATA,
> + DENALI_PHY_793_DATA, DENALI_PHY_794_DATA, DENALI_PHY_795_DATA,
> + DENALI_PHY_796_DATA, DENALI_PHY_797_DATA, DENALI_PHY_798_DATA,
> + DENALI_PHY_799_DATA,
> +
> + DENALI_PHY_800_DATA, DENALI_PHY_801_DATA, DENALI_PHY_802_DATA,
> + DENALI_PHY_803_DATA, DENALI_PHY_804_DATA, DENALI_PHY_805_DATA,
> + DENALI_PHY_806_DATA, DENALI_PHY_807_DATA, DENALI_PHY_808_DATA,
> + DENALI_PHY_809_DATA,
> + DENALI_PHY_810_DATA, DENALI_PHY_811_DATA, DENALI_PHY_812_DATA,
> + DENALI_PHY_813_DATA, DENALI_PHY_814_DATA, DENALI_PHY_815_DATA,
> + DENALI_PHY_816_DATA, DENALI_PHY_817_DATA, DENALI_PHY_818_DATA,
> + DENALI_PHY_819_DATA,
> + DENALI_PHY_820_DATA, DENALI_PHY_821_DATA, DENALI_PHY_822_DATA,
> + DENALI_PHY_823_DATA, DENALI_PHY_824_DATA, DENALI_PHY_825_DATA,
> + DENALI_PHY_826_DATA, DENALI_PHY_827_DATA, DENALI_PHY_828_DATA,
> + DENALI_PHY_829_DATA,
> + DENALI_PHY_830_DATA, DENALI_PHY_831_DATA, DENALI_PHY_832_DATA,
> + DENALI_PHY_833_DATA, DENALI_PHY_834_DATA, DENALI_PHY_835_DATA,
> + DENALI_PHY_836_DATA, DENALI_PHY_837_DATA, DENALI_PHY_838_DATA,
> + DENALI_PHY_839_DATA,
> + DENALI_PHY_840_DATA, DENALI_PHY_841_DATA, DENALI_PHY_842_DATA,
> + DENALI_PHY_843_DATA, DENALI_PHY_844_DATA, DENALI_PHY_845_DATA,
> + DENALI_PHY_846_DATA, DENALI_PHY_847_DATA, DENALI_PHY_848_DATA,
> + DENALI_PHY_849_DATA,
> + DENALI_PHY_850_DATA, DENALI_PHY_851_DATA, DENALI_PHY_852_DATA,
> + DENALI_PHY_853_DATA, DENALI_PHY_854_DATA, DENALI_PHY_855_DATA,
> + DENALI_PHY_856_DATA, DENALI_PHY_857_DATA, DENALI_PHY_858_DATA,
> + DENALI_PHY_859_DATA,
> + DENALI_PHY_860_DATA, DENALI_PHY_861_DATA, DENALI_PHY_862_DATA,
> + DENALI_PHY_863_DATA, DENALI_PHY_864_DATA, DENALI_PHY_865_DATA,
> + DENALI_PHY_866_DATA, DENALI_PHY_867_DATA, DENALI_PHY_868_DATA,
> + DENALI_PHY_869_DATA,
> + DENALI_PHY_870_DATA, DENALI_PHY_871_DATA, DENALI_PHY_872_DATA,
> + DENALI_PHY_873_DATA, DENALI_PHY_874_DATA, DENALI_PHY_875_DATA,
> + DENALI_PHY_876_DATA, DENALI_PHY_877_DATA, DENALI_PHY_878_DATA,
> + DENALI_PHY_879_DATA,
> + DENALI_PHY_880_DATA, DENALI_PHY_881_DATA, DENALI_PHY_882_DATA,
> + DENALI_PHY_883_DATA, DENALI_PHY_884_DATA, DENALI_PHY_885_DATA,
> + DENALI_PHY_886_DATA, DENALI_PHY_887_DATA, DENALI_PHY_888_DATA,
> + DENALI_PHY_889_DATA,
> + DENALI_PHY_890_DATA, DENALI_PHY_891_DATA, DENALI_PHY_892_DATA,
> + DENALI_PHY_893_DATA, DENALI_PHY_894_DATA, DENALI_PHY_895_DATA,
> + DENALI_PHY_896_DATA, DENALI_PHY_897_DATA, DENALI_PHY_898_DATA,
> + DENALI_PHY_899_DATA,
> +
> + DENALI_PHY_900_DATA, DENALI_PHY_901_DATA, DENALI_PHY_902_DATA,
> + DENALI_PHY_903_DATA, DENALI_PHY_904_DATA, DENALI_PHY_905_DATA,
> + DENALI_PHY_906_DATA, DENALI_PHY_907_DATA, DENALI_PHY_908_DATA,
> + DENALI_PHY_909_DATA,
> + DENALI_PHY_910_DATA, DENALI_PHY_911_DATA, DENALI_PHY_912_DATA,
> + DENALI_PHY_913_DATA, DENALI_PHY_914_DATA, DENALI_PHY_915_DATA,
> + DENALI_PHY_916_DATA, DENALI_PHY_917_DATA, DENALI_PHY_918_DATA,
> + DENALI_PHY_919_DATA,
> + DENALI_PHY_920_DATA, DENALI_PHY_921_DATA, DENALI_PHY_922_DATA,
> + DENALI_PHY_923_DATA, DENALI_PHY_924_DATA, DENALI_PHY_925_DATA,
> + DENALI_PHY_926_DATA, DENALI_PHY_927_DATA, DENALI_PHY_928_DATA,
> + DENALI_PHY_929_DATA,
> + DENALI_PHY_930_DATA, DENALI_PHY_931_DATA, DENALI_PHY_932_DATA,
> + DENALI_PHY_933_DATA, DENALI_PHY_934_DATA, DENALI_PHY_935_DATA,
> + DENALI_PHY_936_DATA, DENALI_PHY_937_DATA, DENALI_PHY_938_DATA,
> + DENALI_PHY_939_DATA,
> + DENALI_PHY_940_DATA, DENALI_PHY_941_DATA, DENALI_PHY_942_DATA,
> + DENALI_PHY_943_DATA, DENALI_PHY_944_DATA, DENALI_PHY_945_DATA,
> + DENALI_PHY_946_DATA, DENALI_PHY_947_DATA, DENALI_PHY_948_DATA,
> + DENALI_PHY_949_DATA,
> + DENALI_PHY_950_DATA, DENALI_PHY_951_DATA, DENALI_PHY_952_DATA,
> + DENALI_PHY_953_DATA, DENALI_PHY_954_DATA, DENALI_PHY_955_DATA,
> + DENALI_PHY_956_DATA, DENALI_PHY_957_DATA, DENALI_PHY_958_DATA,
> + DENALI_PHY_959_DATA,
> + DENALI_PHY_960_DATA, DENALI_PHY_961_DATA, DENALI_PHY_962_DATA,
> + DENALI_PHY_963_DATA, DENALI_PHY_964_DATA, DENALI_PHY_965_DATA,
> + DENALI_PHY_966_DATA, DENALI_PHY_967_DATA, DENALI_PHY_968_DATA,
> + DENALI_PHY_969_DATA,
> + DENALI_PHY_970_DATA, DENALI_PHY_971_DATA, DENALI_PHY_972_DATA,
> + DENALI_PHY_973_DATA, DENALI_PHY_974_DATA, DENALI_PHY_975_DATA,
> + DENALI_PHY_976_DATA, DENALI_PHY_977_DATA, DENALI_PHY_978_DATA,
> + DENALI_PHY_979_DATA,
> + DENALI_PHY_980_DATA, DENALI_PHY_981_DATA, DENALI_PHY_982_DATA,
> + DENALI_PHY_983_DATA, DENALI_PHY_984_DATA, DENALI_PHY_985_DATA,
> + DENALI_PHY_986_DATA, DENALI_PHY_987_DATA, DENALI_PHY_988_DATA,
> + DENALI_PHY_989_DATA,
> + DENALI_PHY_990_DATA, DENALI_PHY_991_DATA, DENALI_PHY_992_DATA,
> + DENALI_PHY_993_DATA, DENALI_PHY_994_DATA, DENALI_PHY_995_DATA,
> + DENALI_PHY_996_DATA, DENALI_PHY_997_DATA, DENALI_PHY_998_DATA,
> + DENALI_PHY_999_DATA,
> +
> + DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA, DENALI_PHY_1002_DATA,
> + DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA, DENALI_PHY_1005_DATA,
> + DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA, DENALI_PHY_1008_DATA,
> + DENALI_PHY_1009_DATA,
> + DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA, DENALI_PHY_1012_DATA,
> + DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA, DENALI_PHY_1015_DATA,
> + DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA, DENALI_PHY_1018_DATA,
> + DENALI_PHY_1019_DATA,
> + DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA, DENALI_PHY_1022_DATA,
> + DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA, DENALI_PHY_1025_DATA,
> + DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA, DENALI_PHY_1028_DATA,
> + DENALI_PHY_1029_DATA,
> + DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA, DENALI_PHY_1032_DATA,
> + DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA, DENALI_PHY_1035_DATA,
> + DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA, DENALI_PHY_1038_DATA,
> + DENALI_PHY_1039_DATA,
> + DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA, DENALI_PHY_1042_DATA,
> + DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA, DENALI_PHY_1045_DATA,
> + DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA, DENALI_PHY_1048_DATA,
> + DENALI_PHY_1049_DATA,
> + DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA, DENALI_PHY_1052_DATA,
> + DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA, DENALI_PHY_1055_DATA,
> + DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA, DENALI_PHY_1058_DATA,
> + DENALI_PHY_1059_DATA,
> + DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA, DENALI_PHY_1062_DATA,
> + DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA, DENALI_PHY_1065_DATA,
> + DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA, DENALI_PHY_1068_DATA,
> + DENALI_PHY_1069_DATA,
> + DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA, DENALI_PHY_1072_DATA,
> + DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA, DENALI_PHY_1075_DATA,
> + DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA, DENALI_PHY_1078_DATA,
> + DENALI_PHY_1079_DATA,
> + DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA, DENALI_PHY_1082_DATA,
> + DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA, DENALI_PHY_1085_DATA,
> + DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA, DENALI_PHY_1088_DATA,
> + DENALI_PHY_1089_DATA,
> + DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA, DENALI_PHY_1092_DATA,
> + DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA, DENALI_PHY_1095_DATA,
> + DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA, DENALI_PHY_1098_DATA,
> + DENALI_PHY_1099_DATA,
> +
> + DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA, DENALI_PHY_1102_DATA,
> + DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA, DENALI_PHY_1105_DATA,
> + DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA, DENALI_PHY_1108_DATA,
> + DENALI_PHY_1109_DATA,
> + DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA, DENALI_PHY_1112_DATA,
> + DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA, DENALI_PHY_1115_DATA,
> + DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA, DENALI_PHY_1118_DATA,
> + DENALI_PHY_1119_DATA,
> + DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA, DENALI_PHY_1122_DATA,
> + DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA, DENALI_PHY_1125_DATA,
> + DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA, DENALI_PHY_1128_DATA,
> + DENALI_PHY_1129_DATA,
> + DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA, DENALI_PHY_1132_DATA,
> + DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA, DENALI_PHY_1135_DATA,
> + DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA, DENALI_PHY_1138_DATA,
> + DENALI_PHY_1139_DATA,
> + DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA, DENALI_PHY_1142_DATA,
> + DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA, DENALI_PHY_1145_DATA,
> + DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA, DENALI_PHY_1148_DATA,
> + DENALI_PHY_1149_DATA,
> + DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA, DENALI_PHY_1152_DATA,
> + DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA, DENALI_PHY_1155_DATA,
> + DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA, DENALI_PHY_1158_DATA,
> + DENALI_PHY_1159_DATA,
> + DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA, DENALI_PHY_1162_DATA,
> + DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA, DENALI_PHY_1165_DATA,
> + DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA, DENALI_PHY_1168_DATA,
> + DENALI_PHY_1169_DATA,
> + DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA, DENALI_PHY_1172_DATA,
> + DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA, DENALI_PHY_1175_DATA,
> + DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA, DENALI_PHY_1178_DATA,
> + DENALI_PHY_1179_DATA,
> + DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA, DENALI_PHY_1182_DATA,
> + DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA, DENALI_PHY_1185_DATA,
> + DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA, DENALI_PHY_1188_DATA,
> + DENALI_PHY_1189_DATA,
> + DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA, DENALI_PHY_1192_DATA,
> + DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA, DENALI_PHY_1195_DATA,
> + DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA, DENALI_PHY_1198_DATA,
> + DENALI_PHY_1199_DATA,
> +
> + DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA,
> + DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA,
> + DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA,
> + DENALI_PHY_1209_DATA,
> + DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA,
> + DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA
> +};
> +
> +u32 ddr_ctl_settings[265] = {
> + DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA,
> + DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA,
> + DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA,
> + DENALI_CTL_09_DATA,
> + DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA,
> + DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA,
> + DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA,
> + DENALI_CTL_19_DATA,
> + DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA,
> + DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA,
> + DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA,
> + DENALI_CTL_29_DATA,
> + DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA,
> + DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA,
> + DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA,
> + DENALI_CTL_39_DATA,
> + DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA,
> + DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA,
> + DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA,
> + DENALI_CTL_49_DATA,
> + DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA,
> + DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA,
> + DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA,
> + DENALI_CTL_59_DATA,
> + DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA,
> + DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA,
> + DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA,
> + DENALI_CTL_69_DATA,
> + DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA,
> + DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA,
> + DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA,
> + DENALI_CTL_79_DATA,
> + DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA,
> + DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA,
> + DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA,
> + DENALI_CTL_89_DATA,
> + DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA,
> + DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA,
> + DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA,
> + DENALI_CTL_99_DATA,
> +
> + DENALI_CTL_100_DATA, DENALI_CTL_101_DATA, DENALI_CTL_102_DATA,
> + DENALI_CTL_103_DATA, DENALI_CTL_104_DATA, DENALI_CTL_105_DATA,
> + DENALI_CTL_106_DATA, DENALI_CTL_107_DATA, DENALI_CTL_108_DATA,
> + DENALI_CTL_109_DATA,
> + DENALI_CTL_110_DATA, DENALI_CTL_111_DATA, DENALI_CTL_112_DATA,
> + DENALI_CTL_113_DATA, DENALI_CTL_114_DATA, DENALI_CTL_115_DATA,
> + DENALI_CTL_116_DATA, DENALI_CTL_117_DATA, DENALI_CTL_118_DATA,
> + DENALI_CTL_119_DATA,
> + DENALI_CTL_120_DATA, DENALI_CTL_121_DATA, DENALI_CTL_122_DATA,
> + DENALI_CTL_123_DATA, DENALI_CTL_124_DATA, DENALI_CTL_125_DATA,
> + DENALI_CTL_126_DATA, DENALI_CTL_127_DATA, DENALI_CTL_128_DATA,
> + DENALI_CTL_129_DATA,
> + DENALI_CTL_130_DATA, DENALI_CTL_131_DATA, DENALI_CTL_132_DATA,
> + DENALI_CTL_133_DATA, DENALI_CTL_134_DATA, DENALI_CTL_135_DATA,
> + DENALI_CTL_136_DATA, DENALI_CTL_137_DATA, DENALI_CTL_138_DATA,
> + DENALI_CTL_139_DATA,
> + DENALI_CTL_140_DATA, DENALI_CTL_141_DATA, DENALI_CTL_142_DATA,
> + DENALI_CTL_143_DATA, DENALI_CTL_144_DATA, DENALI_CTL_145_DATA,
> + DENALI_CTL_146_DATA, DENALI_CTL_147_DATA, DENALI_CTL_148_DATA,
> + DENALI_CTL_149_DATA,
> + DENALI_CTL_150_DATA, DENALI_CTL_151_DATA, DENALI_CTL_152_DATA,
> + DENALI_CTL_153_DATA, DENALI_CTL_154_DATA, DENALI_CTL_155_DATA,
> + DENALI_CTL_156_DATA, DENALI_CTL_157_DATA, DENALI_CTL_158_DATA,
> + DENALI_CTL_159_DATA,
> + DENALI_CTL_160_DATA, DENALI_CTL_161_DATA, DENALI_CTL_162_DATA,
> + DENALI_CTL_163_DATA, DENALI_CTL_164_DATA, DENALI_CTL_165_DATA,
> + DENALI_CTL_166_DATA, DENALI_CTL_167_DATA, DENALI_CTL_168_DATA,
> + DENALI_CTL_169_DATA,
> + DENALI_CTL_170_DATA, DENALI_CTL_171_DATA, DENALI_CTL_172_DATA,
> + DENALI_CTL_173_DATA, DENALI_CTL_174_DATA, DENALI_CTL_175_DATA,
> + DENALI_CTL_176_DATA, DENALI_CTL_177_DATA, DENALI_CTL_178_DATA,
> + DENALI_CTL_179_DATA,
> + DENALI_CTL_180_DATA, DENALI_CTL_181_DATA, DENALI_CTL_182_DATA,
> + DENALI_CTL_183_DATA, DENALI_CTL_184_DATA, DENALI_CTL_185_DATA,
> + DENALI_CTL_186_DATA, DENALI_CTL_187_DATA, DENALI_CTL_188_DATA,
> + DENALI_CTL_189_DATA,
> + DENALI_CTL_190_DATA, DENALI_CTL_191_DATA, DENALI_CTL_192_DATA,
> + DENALI_CTL_193_DATA, DENALI_CTL_194_DATA, DENALI_CTL_195_DATA,
> + DENALI_CTL_196_DATA, DENALI_CTL_197_DATA, DENALI_CTL_198_DATA,
> + DENALI_CTL_199_DATA,
> +
> + DENALI_CTL_200_DATA, DENALI_CTL_201_DATA, DENALI_CTL_202_DATA,
> + DENALI_CTL_203_DATA, DENALI_CTL_204_DATA, DENALI_CTL_205_DATA,
> + DENALI_CTL_206_DATA, DENALI_CTL_207_DATA, DENALI_CTL_208_DATA,
> + DENALI_CTL_209_DATA,
> + DENALI_CTL_210_DATA, DENALI_CTL_211_DATA, DENALI_CTL_212_DATA,
> + DENALI_CTL_213_DATA, DENALI_CTL_214_DATA, DENALI_CTL_215_DATA,
> + DENALI_CTL_216_DATA, DENALI_CTL_217_DATA, DENALI_CTL_218_DATA,
> + DENALI_CTL_219_DATA,
> + DENALI_CTL_220_DATA, DENALI_CTL_221_DATA, DENALI_CTL_222_DATA,
> + DENALI_CTL_223_DATA, DENALI_CTL_224_DATA, DENALI_CTL_225_DATA,
> + DENALI_CTL_226_DATA, DENALI_CTL_227_DATA, DENALI_CTL_228_DATA,
> + DENALI_CTL_229_DATA,
> + DENALI_CTL_230_DATA, DENALI_CTL_231_DATA, DENALI_CTL_232_DATA,
> + DENALI_CTL_233_DATA, DENALI_CTL_234_DATA, DENALI_CTL_235_DATA,
> + DENALI_CTL_236_DATA, DENALI_CTL_237_DATA, DENALI_CTL_238_DATA,
> + DENALI_CTL_239_DATA,
> + DENALI_CTL_240_DATA, DENALI_CTL_241_DATA, DENALI_CTL_242_DATA,
> + DENALI_CTL_243_DATA, DENALI_CTL_244_DATA, DENALI_CTL_245_DATA,
> + DENALI_CTL_246_DATA, DENALI_CTL_247_DATA, DENALI_CTL_248_DATA,
> + DENALI_CTL_249_DATA,
> + DENALI_CTL_250_DATA, DENALI_CTL_251_DATA, DENALI_CTL_252_DATA,
> + DENALI_CTL_253_DATA, DENALI_CTL_254_DATA, DENALI_CTL_255_DATA,
> + DENALI_CTL_256_DATA, DENALI_CTL_257_DATA, DENALI_CTL_258_DATA,
> + DENALI_CTL_259_DATA,
> + DENALI_CTL_260_DATA, DENALI_CTL_261_DATA, DENALI_CTL_262_DATA,
> + DENALI_CTL_263_DATA, DENALI_CTL_264_DATA
> +};
> diff --git a/board/sifive/fu540/regconfig-ctl.h b/board/sifive/fu540/regconfig-ctl.h
> new file mode 100644
> index 0000000000..b8f50f5b35
> --- /dev/null
> +++ b/board/sifive/fu540/regconfig-ctl.h
> @@ -0,0 +1,270 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#define DENALI_CTL_00_DATA 0x00000a00
> +#define DENALI_CTL_01_DATA 0x00000000
> +#define DENALI_CTL_02_DATA 0x00000000
> +#define DENALI_CTL_03_DATA 0x00000000
> +#define DENALI_CTL_04_DATA 0x00000000
> +#define DENALI_CTL_05_DATA 0x00000000
> +#define DENALI_CTL_06_DATA 0x0000000a
> +#define DENALI_CTL_07_DATA 0x0002d362
> +#define DENALI_CTL_08_DATA 0x00071073
> +#define DENALI_CTL_09_DATA 0x0a1c0255
> +#define DENALI_CTL_10_DATA 0x1c1c0400
> +#define DENALI_CTL_11_DATA 0x0404990b
> +#define DENALI_CTL_12_DATA 0x2b050405
> +#define DENALI_CTL_13_DATA 0x0e0c081e
> +#define DENALI_CTL_14_DATA 0x08090914
> +#define DENALI_CTL_15_DATA 0x00fde718
> +#define DENALI_CTL_16_DATA 0x00180a05
> +#define DENALI_CTL_17_DATA 0x008b130e
> +#define DENALI_CTL_18_DATA 0x01000118
> +#define DENALI_CTL_19_DATA 0x0e032101
> +#define DENALI_CTL_20_DATA 0x00000000
> +#define DENALI_CTL_21_DATA 0x00000101
> +#define DENALI_CTL_22_DATA 0x00000000
> +#define DENALI_CTL_23_DATA 0x0a000000
> +#define DENALI_CTL_24_DATA 0x00000000
> +#define DENALI_CTL_25_DATA 0x01450100
> +#define DENALI_CTL_26_DATA 0x00001c36
> +#define DENALI_CTL_27_DATA 0x00000005
> +#define DENALI_CTL_28_DATA 0x00170006
> +#define DENALI_CTL_29_DATA 0x014e0300
> +#define DENALI_CTL_30_DATA 0x03010000
> +#define DENALI_CTL_31_DATA 0x000a0e00
> +#define DENALI_CTL_32_DATA 0x04030200
> +#define DENALI_CTL_33_DATA 0x0000031f
> +#define DENALI_CTL_34_DATA 0x00070004
> +#define DENALI_CTL_35_DATA 0x00000000
> +#define DENALI_CTL_36_DATA 0x00000000
> +#define DENALI_CTL_37_DATA 0x00000000
> +#define DENALI_CTL_38_DATA 0x00000000
> +#define DENALI_CTL_39_DATA 0x00000000
> +#define DENALI_CTL_40_DATA 0x00000000
> +#define DENALI_CTL_41_DATA 0x00000000
> +#define DENALI_CTL_42_DATA 0x00000000
> +#define DENALI_CTL_43_DATA 0x00000000
> +#define DENALI_CTL_44_DATA 0x00000000
> +#define DENALI_CTL_45_DATA 0x00000000
> +#define DENALI_CTL_46_DATA 0x00000000
> +#define DENALI_CTL_47_DATA 0x00000000
> +#define DENALI_CTL_48_DATA 0x00000000
> +#define DENALI_CTL_49_DATA 0x00000000
> +#define DENALI_CTL_50_DATA 0x00000000
> +#define DENALI_CTL_51_DATA 0x00000000
> +#define DENALI_CTL_52_DATA 0x00000000
> +#define DENALI_CTL_53_DATA 0x00000000
> +#define DENALI_CTL_54_DATA 0x00000000
> +#define DENALI_CTL_55_DATA 0x00000000
> +#define DENALI_CTL_56_DATA 0x00000000
> +#define DENALI_CTL_57_DATA 0x00000000
> +#define DENALI_CTL_58_DATA 0x00000000
> +#define DENALI_CTL_59_DATA 0x00000000
> +#define DENALI_CTL_60_DATA 0x00000424
> +#define DENALI_CTL_61_DATA 0x00000201
> +#define DENALI_CTL_62_DATA 0x00001008
> +#define DENALI_CTL_63_DATA 0x00000000
> +#define DENALI_CTL_64_DATA 0x00000200
> +#define DENALI_CTL_65_DATA 0x00000000
> +#define DENALI_CTL_66_DATA 0x00000481
> +#define DENALI_CTL_67_DATA 0x00000400
> +#define DENALI_CTL_68_DATA 0x00000424
> +#define DENALI_CTL_69_DATA 0x00000201
> +#define DENALI_CTL_70_DATA 0x00001008
> +#define DENALI_CTL_71_DATA 0x00000000
> +#define DENALI_CTL_72_DATA 0x00000200
> +#define DENALI_CTL_73_DATA 0x00000000
> +#define DENALI_CTL_74_DATA 0x00000481
> +#define DENALI_CTL_75_DATA 0x00000400
> +#define DENALI_CTL_76_DATA 0x01010000
> +#define DENALI_CTL_77_DATA 0x00000000
> +#define DENALI_CTL_78_DATA 0x00000000
> +#define DENALI_CTL_79_DATA 0x00000000
> +#define DENALI_CTL_80_DATA 0x00000000
> +#define DENALI_CTL_81_DATA 0x00000000
> +#define DENALI_CTL_82_DATA 0x00000000
> +#define DENALI_CTL_83_DATA 0x00000000
> +#define DENALI_CTL_84_DATA 0x00000000
> +#define DENALI_CTL_85_DATA 0x00000000
> +#define DENALI_CTL_86_DATA 0x00000000
> +#define DENALI_CTL_87_DATA 0x00000000
> +#define DENALI_CTL_88_DATA 0x00000000
> +#define DENALI_CTL_89_DATA 0x00000000
> +#define DENALI_CTL_90_DATA 0x00000000
> +#define DENALI_CTL_91_DATA 0x00000000
> +#define DENALI_CTL_92_DATA 0x00000000
> +#define DENALI_CTL_93_DATA 0x00000000
> +#define DENALI_CTL_94_DATA 0x00000000
> +#define DENALI_CTL_95_DATA 0x00000000
> +#define DENALI_CTL_96_DATA 0x00000000
> +#define DENALI_CTL_97_DATA 0x00000000
> +#define DENALI_CTL_98_DATA 0x00000000
> +#define DENALI_CTL_99_DATA 0x00000000
> +#define DENALI_CTL_100_DATA 0x00000000
> +#define DENALI_CTL_101_DATA 0x00000000
> +#define DENALI_CTL_102_DATA 0x00000000
> +#define DENALI_CTL_103_DATA 0x00000000
> +#define DENALI_CTL_104_DATA 0x00000000
> +#define DENALI_CTL_105_DATA 0x00000003
> +#define DENALI_CTL_106_DATA 0x00000000
> +#define DENALI_CTL_107_DATA 0x00000000
> +#define DENALI_CTL_108_DATA 0x00000000
> +#define DENALI_CTL_109_DATA 0x00000000
> +#define DENALI_CTL_110_DATA 0x01000000
> +#define DENALI_CTL_111_DATA 0x00040000
> +#define DENALI_CTL_112_DATA 0x00800200
> +#define DENALI_CTL_113_DATA 0x00000200
> +#define DENALI_CTL_114_DATA 0x00000040
> +#define DENALI_CTL_115_DATA 0x01000100
> +#define DENALI_CTL_116_DATA 0x0a000002
> +#define DENALI_CTL_117_DATA 0x0101ffff
> +#define DENALI_CTL_118_DATA 0x01010101
> +#define DENALI_CTL_119_DATA 0x01010101
> +#define DENALI_CTL_120_DATA 0x0000010b
> +#define DENALI_CTL_121_DATA 0x00000c01
> +#define DENALI_CTL_122_DATA 0x00000000
> +#define DENALI_CTL_123_DATA 0x00000000
> +#define DENALI_CTL_124_DATA 0x00000000
> +#define DENALI_CTL_125_DATA 0x00000000
> +#define DENALI_CTL_126_DATA 0x00030300
> +#define DENALI_CTL_127_DATA 0x00000000
> +#define DENALI_CTL_128_DATA 0x00010001
> +#define DENALI_CTL_129_DATA 0x00000000
> +#define DENALI_CTL_130_DATA 0x00000000
> +#define DENALI_CTL_131_DATA 0x00000000
> +#define DENALI_CTL_132_DATA 0x00000000
> +#define DENALI_CTL_133_DATA 0x00000000
> +#define DENALI_CTL_134_DATA 0x00000000
> +#define DENALI_CTL_135_DATA 0x00000000
> +#define DENALI_CTL_136_DATA 0x00000000
> +#define DENALI_CTL_137_DATA 0x00000000
> +#define DENALI_CTL_138_DATA 0x00000000
> +#define DENALI_CTL_139_DATA 0x00000000
> +#define DENALI_CTL_140_DATA 0x00000000
> +#define DENALI_CTL_141_DATA 0x00000000
> +#define DENALI_CTL_142_DATA 0x00000000
> +#define DENALI_CTL_143_DATA 0x00000000
> +#define DENALI_CTL_144_DATA 0x00000000
> +#define DENALI_CTL_145_DATA 0x00000000
> +#define DENALI_CTL_146_DATA 0x00000000
> +#define DENALI_CTL_147_DATA 0x00000000
> +#define DENALI_CTL_148_DATA 0x00000000
> +#define DENALI_CTL_149_DATA 0x00000000
> +#define DENALI_CTL_150_DATA 0x00000000
> +#define DENALI_CTL_151_DATA 0x00000000
> +#define DENALI_CTL_152_DATA 0x00000000
> +#define DENALI_CTL_153_DATA 0x00000000
> +#define DENALI_CTL_154_DATA 0x00000000
> +#define DENALI_CTL_155_DATA 0x00000000
> +#define DENALI_CTL_156_DATA 0x00000000
> +#define DENALI_CTL_157_DATA 0x00000000
> +#define DENALI_CTL_158_DATA 0x00000000
> +#define DENALI_CTL_159_DATA 0x00000000
> +#define DENALI_CTL_160_DATA 0x00000000
> +#define DENALI_CTL_161_DATA 0x02010102
> +#define DENALI_CTL_162_DATA 0x0107070d
> +#define DENALI_CTL_163_DATA 0x04040400
> +#define DENALI_CTL_164_DATA 0x03000503
> +#define DENALI_CTL_165_DATA 0x00000000
> +#define DENALI_CTL_166_DATA 0x00000000
> +#define DENALI_CTL_167_DATA 0x00000000
> +#define DENALI_CTL_168_DATA 0x00000000
> +#define DENALI_CTL_169_DATA 0x280d0000
> +#define DENALI_CTL_170_DATA 0x01000000
> +#define DENALI_CTL_171_DATA 0x00000000
> +#define DENALI_CTL_172_DATA 0x00010001
> +#define DENALI_CTL_173_DATA 0x00000000
> +#define DENALI_CTL_174_DATA 0x00000000
> +#define DENALI_CTL_175_DATA 0x00000000
> +#define DENALI_CTL_176_DATA 0x00000000
> +#define DENALI_CTL_177_DATA 0x00000000
> +#define DENALI_CTL_178_DATA 0x00000000
> +#define DENALI_CTL_179_DATA 0x00000000
> +#define DENALI_CTL_180_DATA 0x00000000
> +#define DENALI_CTL_181_DATA 0x01000000
> +#define DENALI_CTL_182_DATA 0x00000001
> +#define DENALI_CTL_183_DATA 0x00000100
> +#define DENALI_CTL_184_DATA 0x00000101
> +#define DENALI_CTL_185_DATA 0x67676701
> +#define DENALI_CTL_186_DATA 0x67676767
> +#define DENALI_CTL_187_DATA 0x67676767
> +#define DENALI_CTL_188_DATA 0x67676767
> +#define DENALI_CTL_189_DATA 0x67676767
> +#define DENALI_CTL_190_DATA 0x67676767
> +#define DENALI_CTL_191_DATA 0x67676767
> +#define DENALI_CTL_192_DATA 0x67676767
> +#define DENALI_CTL_193_DATA 0x67676767
> +#define DENALI_CTL_194_DATA 0x01000067
> +#define DENALI_CTL_195_DATA 0x00000001
> +#define DENALI_CTL_196_DATA 0x00000101
> +#define DENALI_CTL_197_DATA 0x00000000
> +#define DENALI_CTL_198_DATA 0x00000000
> +#define DENALI_CTL_199_DATA 0x00000000
> +#define DENALI_CTL_200_DATA 0x00000000
> +#define DENALI_CTL_201_DATA 0x00000000
> +#define DENALI_CTL_202_DATA 0x00000000
> +#define DENALI_CTL_203_DATA 0x00000000
> +#define DENALI_CTL_204_DATA 0x00000000
> +#define DENALI_CTL_205_DATA 0x00000000
> +#define DENALI_CTL_206_DATA 0x00000000
> +#define DENALI_CTL_207_DATA 0x00000000
> +#define DENALI_CTL_208_DATA 0x00000001
> +#define DENALI_CTL_209_DATA 0x00000000
> +#define DENALI_CTL_210_DATA 0x007fffff
> +#define DENALI_CTL_211_DATA 0x00000000
> +#define DENALI_CTL_212_DATA 0x007fffff
> +#define DENALI_CTL_213_DATA 0x00000000
> +#define DENALI_CTL_214_DATA 0x007fffff
> +#define DENALI_CTL_215_DATA 0x00000000
> +#define DENALI_CTL_216_DATA 0x007fffff
> +#define DENALI_CTL_217_DATA 0x00000000
> +#define DENALI_CTL_218_DATA 0x007fffff
> +#define DENALI_CTL_219_DATA 0x00000000
> +#define DENALI_CTL_220_DATA 0x007fffff
> +#define DENALI_CTL_221_DATA 0x00000000
> +#define DENALI_CTL_222_DATA 0x007fffff
> +#define DENALI_CTL_223_DATA 0x00000000
> +#define DENALI_CTL_224_DATA 0x037fffff
> +#define DENALI_CTL_225_DATA 0xffffffff
> +#define DENALI_CTL_226_DATA 0x000f000f
> +#define DENALI_CTL_227_DATA 0x00ffff03
> +#define DENALI_CTL_228_DATA 0x000fffff
> +#define DENALI_CTL_229_DATA 0x0003000f
> +#define DENALI_CTL_230_DATA 0xffffffff
> +#define DENALI_CTL_231_DATA 0x000f000f
> +#define DENALI_CTL_232_DATA 0x00ffff03
> +#define DENALI_CTL_233_DATA 0x000fffff
> +#define DENALI_CTL_234_DATA 0x0003000f
> +#define DENALI_CTL_235_DATA 0xffffffff
> +#define DENALI_CTL_236_DATA 0x000f000f
> +#define DENALI_CTL_237_DATA 0x00ffff03
> +#define DENALI_CTL_238_DATA 0x000fffff
> +#define DENALI_CTL_239_DATA 0x0003000f
> +#define DENALI_CTL_240_DATA 0xffffffff
> +#define DENALI_CTL_241_DATA 0x000f000f
> +#define DENALI_CTL_242_DATA 0x00ffff03
> +#define DENALI_CTL_243_DATA 0x000fffff
> +#define DENALI_CTL_244_DATA 0x6407000f
> +#define DENALI_CTL_245_DATA 0x01640001
> +#define DENALI_CTL_246_DATA 0x00000000
> +#define DENALI_CTL_247_DATA 0x00000000
> +#define DENALI_CTL_248_DATA 0x00001700
> +#define DENALI_CTL_249_DATA 0x00386c05
> +#define DENALI_CTL_250_DATA 0x02000200
> +#define DENALI_CTL_251_DATA 0x02000200
> +#define DENALI_CTL_252_DATA 0x0000386c
> +#define DENALI_CTL_253_DATA 0x00023438
> +#define DENALI_CTL_254_DATA 0x02020d10
> +#define DENALI_CTL_255_DATA 0x00140303
> +#define DENALI_CTL_256_DATA 0x00000000
> +#define DENALI_CTL_257_DATA 0x00000000
> +#define DENALI_CTL_258_DATA 0x00001403
> +#define DENALI_CTL_259_DATA 0x00000000
> +#define DENALI_CTL_260_DATA 0x00000000
> +#define DENALI_CTL_261_DATA 0x00000000
> +#define DENALI_CTL_262_DATA 0x00000000
> +#define DENALI_CTL_263_DATA 0x0d010000
> +#define DENALI_CTL_264_DATA 0x00000008
> diff --git a/board/sifive/fu540/regconfig-phy.h b/board/sifive/fu540/regconfig-phy.h
> new file mode 100644
> index 0000000000..62163290b9
> --- /dev/null
> +++ b/board/sifive/fu540/regconfig-phy.h
> @@ -0,0 +1,1220 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#define DENALI_PHY_00_DATA 0x31706542
> +#define DENALI_PHY_01_DATA 0x0004c008
> +#define DENALI_PHY_02_DATA 0x000000da
> +#define DENALI_PHY_03_DATA 0x00000000
> +#define DENALI_PHY_04_DATA 0x00000000
> +#define DENALI_PHY_05_DATA 0x00010000
> +#define DENALI_PHY_06_DATA 0x01DDDD90
> +#define DENALI_PHY_07_DATA 0x01DDDD90
> +#define DENALI_PHY_08_DATA 0x01030000
> +#define DENALI_PHY_09_DATA 0x01000000
> +#define DENALI_PHY_10_DATA 0x00c00000
> +#define DENALI_PHY_11_DATA 0x00000007
> +#define DENALI_PHY_12_DATA 0x00000000
> +#define DENALI_PHY_13_DATA 0x00000000
> +#define DENALI_PHY_14_DATA 0x04000408
> +#define DENALI_PHY_15_DATA 0x00000408
> +#define DENALI_PHY_16_DATA 0x00e4e400
> +#define DENALI_PHY_17_DATA 0x00000000
> +#define DENALI_PHY_18_DATA 0x00000000
> +#define DENALI_PHY_19_DATA 0x00000000
> +#define DENALI_PHY_20_DATA 0x00000000
> +#define DENALI_PHY_21_DATA 0x00000000
> +#define DENALI_PHY_22_DATA 0x00000000
> +#define DENALI_PHY_23_DATA 0x00000000
> +#define DENALI_PHY_24_DATA 0x00000000
> +#define DENALI_PHY_25_DATA 0x00000000
> +#define DENALI_PHY_26_DATA 0x00000000
> +#define DENALI_PHY_27_DATA 0x00000000
> +#define DENALI_PHY_28_DATA 0x00000000
> +#define DENALI_PHY_29_DATA 0x00000000
> +#define DENALI_PHY_30_DATA 0x00000000
> +#define DENALI_PHY_31_DATA 0x00000000
> +#define DENALI_PHY_32_DATA 0x00000000
> +#define DENALI_PHY_33_DATA 0x00200000
> +#define DENALI_PHY_34_DATA 0x00000000
> +#define DENALI_PHY_35_DATA 0x00000000
> +#define DENALI_PHY_36_DATA 0x00000000
> +#define DENALI_PHY_37_DATA 0x00000000
> +#define DENALI_PHY_38_DATA 0x00000000
> +#define DENALI_PHY_39_DATA 0x00000000
> +#define DENALI_PHY_40_DATA 0x02800280
> +#define DENALI_PHY_41_DATA 0x02800280
> +#define DENALI_PHY_42_DATA 0x02800280
> +#define DENALI_PHY_43_DATA 0x02800280
> +#define DENALI_PHY_44_DATA 0x00000280
> +#define DENALI_PHY_45_DATA 0x00000000
> +#define DENALI_PHY_46_DATA 0x00000000
> +#define DENALI_PHY_47_DATA 0x00000000
> +#define DENALI_PHY_48_DATA 0x00000000
> +#define DENALI_PHY_49_DATA 0x00000000
> +#define DENALI_PHY_50_DATA 0x00800080
> +#define DENALI_PHY_51_DATA 0x00800080
> +#define DENALI_PHY_52_DATA 0x00800080
> +#define DENALI_PHY_53_DATA 0x00800080
> +#define DENALI_PHY_54_DATA 0x00800080
> +#define DENALI_PHY_55_DATA 0x00800080
> +#define DENALI_PHY_56_DATA 0x00800080
> +#define DENALI_PHY_57_DATA 0x00800080
> +#define DENALI_PHY_58_DATA 0x00800080
> +#define DENALI_PHY_59_DATA 0x000100da
> +#define DENALI_PHY_60_DATA 0x01000200
> +#define DENALI_PHY_61_DATA 0x00000000
> +#define DENALI_PHY_62_DATA 0x00000000
> +#define DENALI_PHY_63_DATA 0x00000002
> +#define DENALI_PHY_64_DATA 0x51313152
> +#define DENALI_PHY_65_DATA 0x80013130
> +#define DENALI_PHY_66_DATA 0x02000080
> +#define DENALI_PHY_67_DATA 0x00100001
> +#define DENALI_PHY_68_DATA 0x0c064208
> +#define DENALI_PHY_69_DATA 0x000f0c0f
> +#define DENALI_PHY_70_DATA 0x01000140
> +#define DENALI_PHY_71_DATA 0x0000000c
> +#define DENALI_PHY_72_DATA 0x00000000
> +#define DENALI_PHY_73_DATA 0x00000000
> +#define DENALI_PHY_74_DATA 0x00000000
> +#define DENALI_PHY_75_DATA 0x00000000
> +#define DENALI_PHY_76_DATA 0x00000000
> +#define DENALI_PHY_77_DATA 0x00000000
> +#define DENALI_PHY_78_DATA 0x00000000
> +#define DENALI_PHY_79_DATA 0x00000000
> +#define DENALI_PHY_80_DATA 0x00000000
> +#define DENALI_PHY_81_DATA 0x00000000
> +#define DENALI_PHY_82_DATA 0x00000000
> +#define DENALI_PHY_83_DATA 0x00000000
> +#define DENALI_PHY_84_DATA 0x00000000
> +#define DENALI_PHY_85_DATA 0x00000000
> +#define DENALI_PHY_86_DATA 0x00000000
> +#define DENALI_PHY_87_DATA 0x00000000
> +#define DENALI_PHY_88_DATA 0x00000000
> +#define DENALI_PHY_89_DATA 0x00000000
> +#define DENALI_PHY_90_DATA 0x00000000
> +#define DENALI_PHY_91_DATA 0x00000000
> +#define DENALI_PHY_92_DATA 0x00000000
> +#define DENALI_PHY_93_DATA 0x00000000
> +#define DENALI_PHY_94_DATA 0x00000000
> +#define DENALI_PHY_95_DATA 0x00000000
> +#define DENALI_PHY_96_DATA 0x00000000
> +#define DENALI_PHY_97_DATA 0x00000000
> +#define DENALI_PHY_98_DATA 0x00000000
> +#define DENALI_PHY_99_DATA 0x00000000
> +#define DENALI_PHY_100_DATA 0x00000000
> +#define DENALI_PHY_101_DATA 0x00000000
> +#define DENALI_PHY_102_DATA 0x00000000
> +#define DENALI_PHY_103_DATA 0x00000000
> +#define DENALI_PHY_104_DATA 0x00000000
> +#define DENALI_PHY_105_DATA 0x00000000
> +#define DENALI_PHY_106_DATA 0x00000000
> +#define DENALI_PHY_107_DATA 0x00000000
> +#define DENALI_PHY_108_DATA 0x00000000
> +#define DENALI_PHY_109_DATA 0x00000000
> +#define DENALI_PHY_110_DATA 0x00000000
> +#define DENALI_PHY_111_DATA 0x00000000
> +#define DENALI_PHY_112_DATA 0x00000000
> +#define DENALI_PHY_113_DATA 0x00000000
> +#define DENALI_PHY_114_DATA 0x00000000
> +#define DENALI_PHY_115_DATA 0x00000000
> +#define DENALI_PHY_116_DATA 0x00000000
> +#define DENALI_PHY_117_DATA 0x00000000
> +#define DENALI_PHY_118_DATA 0x00000000
> +#define DENALI_PHY_119_DATA 0x00000000
> +#define DENALI_PHY_120_DATA 0x00000000
> +#define DENALI_PHY_121_DATA 0x00000000
> +#define DENALI_PHY_122_DATA 0x00000000
> +#define DENALI_PHY_123_DATA 0x00000000
> +#define DENALI_PHY_124_DATA 0x00000000
> +#define DENALI_PHY_125_DATA 0x00000000
> +#define DENALI_PHY_126_DATA 0x00000000
> +#define DENALI_PHY_127_DATA 0x00000000
> +#define DENALI_PHY_128_DATA 0x40263571
> +#define DENALI_PHY_129_DATA 0x0004c008
> +#define DENALI_PHY_130_DATA 0x000000da
> +#define DENALI_PHY_131_DATA 0x00000000
> +#define DENALI_PHY_132_DATA 0x00000000
> +#define DENALI_PHY_133_DATA 0x00010000
> +#define DENALI_PHY_134_DATA 0x01DDDD90
> +#define DENALI_PHY_135_DATA 0x01DDDD90
> +#define DENALI_PHY_136_DATA 0x01030000
> +#define DENALI_PHY_137_DATA 0x01000000
> +#define DENALI_PHY_138_DATA 0x00c00000
> +#define DENALI_PHY_139_DATA 0x00000007
> +#define DENALI_PHY_140_DATA 0x00000000
> +#define DENALI_PHY_141_DATA 0x00000000
> +#define DENALI_PHY_142_DATA 0x04000408
> +#define DENALI_PHY_143_DATA 0x00000408
> +#define DENALI_PHY_144_DATA 0x00e4e400
> +#define DENALI_PHY_145_DATA 0x00000000
> +#define DENALI_PHY_146_DATA 0x00000000
> +#define DENALI_PHY_147_DATA 0x00000000
> +#define DENALI_PHY_148_DATA 0x00000000
> +#define DENALI_PHY_149_DATA 0x00000000
> +#define DENALI_PHY_150_DATA 0x00000000
> +#define DENALI_PHY_151_DATA 0x00000000
> +#define DENALI_PHY_152_DATA 0x00000000
> +#define DENALI_PHY_153_DATA 0x00000000
> +#define DENALI_PHY_154_DATA 0x00000000
> +#define DENALI_PHY_155_DATA 0x00000000
> +#define DENALI_PHY_156_DATA 0x00000000
> +#define DENALI_PHY_157_DATA 0x00000000
> +#define DENALI_PHY_158_DATA 0x00000000
> +#define DENALI_PHY_159_DATA 0x00000000
> +#define DENALI_PHY_160_DATA 0x00000000
> +#define DENALI_PHY_161_DATA 0x00200000
> +#define DENALI_PHY_162_DATA 0x00000000
> +#define DENALI_PHY_163_DATA 0x00000000
> +#define DENALI_PHY_164_DATA 0x00000000
> +#define DENALI_PHY_165_DATA 0x00000000
> +#define DENALI_PHY_166_DATA 0x00000000
> +#define DENALI_PHY_167_DATA 0x00000000
> +#define DENALI_PHY_168_DATA 0x02800280
> +#define DENALI_PHY_169_DATA 0x02800280
> +#define DENALI_PHY_170_DATA 0x02800280
> +#define DENALI_PHY_171_DATA 0x02800280
> +#define DENALI_PHY_172_DATA 0x00000280
> +#define DENALI_PHY_173_DATA 0x00000000
> +#define DENALI_PHY_174_DATA 0x00000000
> +#define DENALI_PHY_175_DATA 0x00000000
> +#define DENALI_PHY_176_DATA 0x00000000
> +#define DENALI_PHY_177_DATA 0x00000000
> +#define DENALI_PHY_178_DATA 0x00800080
> +#define DENALI_PHY_179_DATA 0x00800080
> +#define DENALI_PHY_180_DATA 0x00800080
> +#define DENALI_PHY_181_DATA 0x00800080
> +#define DENALI_PHY_182_DATA 0x00800080
> +#define DENALI_PHY_183_DATA 0x00800080
> +#define DENALI_PHY_184_DATA 0x00800080
> +#define DENALI_PHY_185_DATA 0x00800080
> +#define DENALI_PHY_186_DATA 0x00800080
> +#define DENALI_PHY_187_DATA 0x000100da
> +#define DENALI_PHY_188_DATA 0x01000200
> +#define DENALI_PHY_189_DATA 0x00000000
> +#define DENALI_PHY_190_DATA 0x00000000
> +#define DENALI_PHY_191_DATA 0x00000002
> +#define DENALI_PHY_192_DATA 0x51313152
> +#define DENALI_PHY_193_DATA 0x80013130
> +#define DENALI_PHY_194_DATA 0x02000080
> +#define DENALI_PHY_195_DATA 0x00100001
> +#define DENALI_PHY_196_DATA 0x0c064208
> +#define DENALI_PHY_197_DATA 0x000f0c0f
> +#define DENALI_PHY_198_DATA 0x01000140
> +#define DENALI_PHY_199_DATA 0x0000000c
> +#define DENALI_PHY_200_DATA 0x00000000
> +#define DENALI_PHY_201_DATA 0x00000000
> +#define DENALI_PHY_202_DATA 0x00000000
> +#define DENALI_PHY_203_DATA 0x00000000
> +#define DENALI_PHY_204_DATA 0x00000000
> +#define DENALI_PHY_205_DATA 0x00000000
> +#define DENALI_PHY_206_DATA 0x00000000
> +#define DENALI_PHY_207_DATA 0x00000000
> +#define DENALI_PHY_208_DATA 0x00000000
> +#define DENALI_PHY_209_DATA 0x00000000
> +#define DENALI_PHY_210_DATA 0x00000000
> +#define DENALI_PHY_211_DATA 0x00000000
> +#define DENALI_PHY_212_DATA 0x00000000
> +#define DENALI_PHY_213_DATA 0x00000000
> +#define DENALI_PHY_214_DATA 0x00000000
> +#define DENALI_PHY_215_DATA 0x00000000
> +#define DENALI_PHY_216_DATA 0x00000000
> +#define DENALI_PHY_217_DATA 0x00000000
> +#define DENALI_PHY_218_DATA 0x00000000
> +#define DENALI_PHY_219_DATA 0x00000000
> +#define DENALI_PHY_220_DATA 0x00000000
> +#define DENALI_PHY_221_DATA 0x00000000
> +#define DENALI_PHY_222_DATA 0x00000000
> +#define DENALI_PHY_223_DATA 0x00000000
> +#define DENALI_PHY_224_DATA 0x00000000
> +#define DENALI_PHY_225_DATA 0x00000000
> +#define DENALI_PHY_226_DATA 0x00000000
> +#define DENALI_PHY_227_DATA 0x00000000
> +#define DENALI_PHY_228_DATA 0x00000000
> +#define DENALI_PHY_229_DATA 0x00000000
> +#define DENALI_PHY_230_DATA 0x00000000
> +#define DENALI_PHY_231_DATA 0x00000000
> +#define DENALI_PHY_232_DATA 0x00000000
> +#define DENALI_PHY_233_DATA 0x00000000
> +#define DENALI_PHY_234_DATA 0x00000000
> +#define DENALI_PHY_235_DATA 0x00000000
> +#define DENALI_PHY_236_DATA 0x00000000
> +#define DENALI_PHY_237_DATA 0x00000000
> +#define DENALI_PHY_238_DATA 0x00000000
> +#define DENALI_PHY_239_DATA 0x00000000
> +#define DENALI_PHY_240_DATA 0x00000000
> +#define DENALI_PHY_241_DATA 0x00000000
> +#define DENALI_PHY_242_DATA 0x00000000
> +#define DENALI_PHY_243_DATA 0x00000000
> +#define DENALI_PHY_244_DATA 0x00000000
> +#define DENALI_PHY_245_DATA 0x00000000
> +#define DENALI_PHY_246_DATA 0x00000000
> +#define DENALI_PHY_247_DATA 0x00000000
> +#define DENALI_PHY_248_DATA 0x00000000
> +#define DENALI_PHY_249_DATA 0x00000000
> +#define DENALI_PHY_250_DATA 0x00000000
> +#define DENALI_PHY_251_DATA 0x00000000
> +#define DENALI_PHY_252_DATA 0x00000000
> +#define DENALI_PHY_253_DATA 0x00000000
> +#define DENALI_PHY_254_DATA 0x00000000
> +#define DENALI_PHY_255_DATA 0x00000000
> +#define DENALI_PHY_256_DATA 0x46052371
> +#define DENALI_PHY_257_DATA 0x0004c008
> +#define DENALI_PHY_258_DATA 0x000000da
> +#define DENALI_PHY_259_DATA 0x00000000
> +#define DENALI_PHY_260_DATA 0x00000000
> +#define DENALI_PHY_261_DATA 0x00010000
> +#define DENALI_PHY_262_DATA 0x01DDDD90
> +#define DENALI_PHY_263_DATA 0x01DDDD90
> +#define DENALI_PHY_264_DATA 0x01030000
> +#define DENALI_PHY_265_DATA 0x01000000
> +#define DENALI_PHY_266_DATA 0x00c00000
> +#define DENALI_PHY_267_DATA 0x00000007
> +#define DENALI_PHY_268_DATA 0x00000000
> +#define DENALI_PHY_269_DATA 0x00000000
> +#define DENALI_PHY_270_DATA 0x04000408
> +#define DENALI_PHY_271_DATA 0x00000408
> +#define DENALI_PHY_272_DATA 0x00e4e400
> +#define DENALI_PHY_273_DATA 0x00000000
> +#define DENALI_PHY_274_DATA 0x00000000
> +#define DENALI_PHY_275_DATA 0x00000000
> +#define DENALI_PHY_276_DATA 0x00000000
> +#define DENALI_PHY_277_DATA 0x00000000
> +#define DENALI_PHY_278_DATA 0x00000000
> +#define DENALI_PHY_279_DATA 0x00000000
> +#define DENALI_PHY_280_DATA 0x00000000
> +#define DENALI_PHY_281_DATA 0x00000000
> +#define DENALI_PHY_282_DATA 0x00000000
> +#define DENALI_PHY_283_DATA 0x00000000
> +#define DENALI_PHY_284_DATA 0x00000000
> +#define DENALI_PHY_285_DATA 0x00000000
> +#define DENALI_PHY_286_DATA 0x00000000
> +#define DENALI_PHY_287_DATA 0x00000000
> +#define DENALI_PHY_288_DATA 0x00000000
> +#define DENALI_PHY_289_DATA 0x00200000
> +#define DENALI_PHY_290_DATA 0x00000000
> +#define DENALI_PHY_291_DATA 0x00000000
> +#define DENALI_PHY_292_DATA 0x00000000
> +#define DENALI_PHY_293_DATA 0x00000000
> +#define DENALI_PHY_294_DATA 0x00000000
> +#define DENALI_PHY_295_DATA 0x00000000
> +#define DENALI_PHY_296_DATA 0x02800280
> +#define DENALI_PHY_297_DATA 0x02800280
> +#define DENALI_PHY_298_DATA 0x02800280
> +#define DENALI_PHY_299_DATA 0x02800280
> +#define DENALI_PHY_300_DATA 0x00000280
> +#define DENALI_PHY_301_DATA 0x00000000
> +#define DENALI_PHY_302_DATA 0x00000000
> +#define DENALI_PHY_303_DATA 0x00000000
> +#define DENALI_PHY_304_DATA 0x00000000
> +#define DENALI_PHY_305_DATA 0x00000000
> +#define DENALI_PHY_306_DATA 0x00800080
> +#define DENALI_PHY_307_DATA 0x00800080
> +#define DENALI_PHY_308_DATA 0x00800080
> +#define DENALI_PHY_309_DATA 0x00800080
> +#define DENALI_PHY_310_DATA 0x00800080
> +#define DENALI_PHY_311_DATA 0x00800080
> +#define DENALI_PHY_312_DATA 0x00800080
> +#define DENALI_PHY_313_DATA 0x00800080
> +#define DENALI_PHY_314_DATA 0x00800080
> +#define DENALI_PHY_315_DATA 0x000100da
> +#define DENALI_PHY_316_DATA 0x00000200
> +#define DENALI_PHY_317_DATA 0x00000000
> +#define DENALI_PHY_318_DATA 0x00000000
> +#define DENALI_PHY_319_DATA 0x00000002
> +#define DENALI_PHY_320_DATA 0x51313152
> +#define DENALI_PHY_321_DATA 0x80013130
> +#define DENALI_PHY_322_DATA 0x02000080
> +#define DENALI_PHY_323_DATA 0x00100001
> +#define DENALI_PHY_324_DATA 0x0c064208
> +#define DENALI_PHY_325_DATA 0x000f0c0f
> +#define DENALI_PHY_326_DATA 0x01000140
> +#define DENALI_PHY_327_DATA 0x0000000c
> +#define DENALI_PHY_328_DATA 0x00000000
> +#define DENALI_PHY_329_DATA 0x00000000
> +#define DENALI_PHY_330_DATA 0x00000000
> +#define DENALI_PHY_331_DATA 0x00000000
> +#define DENALI_PHY_332_DATA 0x00000000
> +#define DENALI_PHY_333_DATA 0x00000000
> +#define DENALI_PHY_334_DATA 0x00000000
> +#define DENALI_PHY_335_DATA 0x00000000
> +#define DENALI_PHY_336_DATA 0x00000000
> +#define DENALI_PHY_337_DATA 0x00000000
> +#define DENALI_PHY_338_DATA 0x00000000
> +#define DENALI_PHY_339_DATA 0x00000000
> +#define DENALI_PHY_340_DATA 0x00000000
> +#define DENALI_PHY_341_DATA 0x00000000
> +#define DENALI_PHY_342_DATA 0x00000000
> +#define DENALI_PHY_343_DATA 0x00000000
> +#define DENALI_PHY_344_DATA 0x00000000
> +#define DENALI_PHY_345_DATA 0x00000000
> +#define DENALI_PHY_346_DATA 0x00000000
> +#define DENALI_PHY_347_DATA 0x00000000
> +#define DENALI_PHY_348_DATA 0x00000000
> +#define DENALI_PHY_349_DATA 0x00000000
> +#define DENALI_PHY_350_DATA 0x00000000
> +#define DENALI_PHY_351_DATA 0x00000000
> +#define DENALI_PHY_352_DATA 0x00000000
> +#define DENALI_PHY_353_DATA 0x00000000
> +#define DENALI_PHY_354_DATA 0x00000000
> +#define DENALI_PHY_355_DATA 0x00000000
> +#define DENALI_PHY_356_DATA 0x00000000
> +#define DENALI_PHY_357_DATA 0x00000000
> +#define DENALI_PHY_358_DATA 0x00000000
> +#define DENALI_PHY_359_DATA 0x00000000
> +#define DENALI_PHY_360_DATA 0x00000000
> +#define DENALI_PHY_361_DATA 0x00000000
> +#define DENALI_PHY_362_DATA 0x00000000
> +#define DENALI_PHY_363_DATA 0x00000000
> +#define DENALI_PHY_364_DATA 0x00000000
> +#define DENALI_PHY_365_DATA 0x00000000
> +#define DENALI_PHY_366_DATA 0x00000000
> +#define DENALI_PHY_367_DATA 0x00000000
> +#define DENALI_PHY_368_DATA 0x00000000
> +#define DENALI_PHY_369_DATA 0x00000000
> +#define DENALI_PHY_370_DATA 0x00000000
> +#define DENALI_PHY_371_DATA 0x00000000
> +#define DENALI_PHY_372_DATA 0x00000000
> +#define DENALI_PHY_373_DATA 0x00000000
> +#define DENALI_PHY_374_DATA 0x00000000
> +#define DENALI_PHY_375_DATA 0x00000000
> +#define DENALI_PHY_376_DATA 0x00000000
> +#define DENALI_PHY_377_DATA 0x00000000
> +#define DENALI_PHY_378_DATA 0x00000000
> +#define DENALI_PHY_379_DATA 0x00000000
> +#define DENALI_PHY_380_DATA 0x00000000
> +#define DENALI_PHY_381_DATA 0x00000000
> +#define DENALI_PHY_382_DATA 0x00000000
> +#define DENALI_PHY_383_DATA 0x00000000
> +#define DENALI_PHY_384_DATA 0x37654120
> +#define DENALI_PHY_385_DATA 0x0004c008
> +#define DENALI_PHY_386_DATA 0x000000da
> +#define DENALI_PHY_387_DATA 0x00000000
> +#define DENALI_PHY_388_DATA 0x00000000
> +#define DENALI_PHY_389_DATA 0x00010000
> +#define DENALI_PHY_390_DATA 0x01DDDD90
> +#define DENALI_PHY_391_DATA 0x01DDDD90
> +#define DENALI_PHY_392_DATA 0x01030000
> +#define DENALI_PHY_393_DATA 0x01000000
> +#define DENALI_PHY_394_DATA 0x00c00000
> +#define DENALI_PHY_395_DATA 0x00000007
> +#define DENALI_PHY_396_DATA 0x00000000
> +#define DENALI_PHY_397_DATA 0x00000000
> +#define DENALI_PHY_398_DATA 0x04000408
> +#define DENALI_PHY_399_DATA 0x00000408
> +#define DENALI_PHY_400_DATA 0x00e4e400
> +#define DENALI_PHY_401_DATA 0x00000000
> +#define DENALI_PHY_402_DATA 0x00000000
> +#define DENALI_PHY_403_DATA 0x00000000
> +#define DENALI_PHY_404_DATA 0x00000000
> +#define DENALI_PHY_405_DATA 0x00000000
> +#define DENALI_PHY_406_DATA 0x00000000
> +#define DENALI_PHY_407_DATA 0x00000000
> +#define DENALI_PHY_408_DATA 0x00000000
> +#define DENALI_PHY_409_DATA 0x00000000
> +#define DENALI_PHY_410_DATA 0x00000000
> +#define DENALI_PHY_411_DATA 0x00000000
> +#define DENALI_PHY_412_DATA 0x00000000
> +#define DENALI_PHY_413_DATA 0x00000000
> +#define DENALI_PHY_414_DATA 0x00000000
> +#define DENALI_PHY_415_DATA 0x00000000
> +#define DENALI_PHY_416_DATA 0x00000000
> +#define DENALI_PHY_417_DATA 0x00200000
> +#define DENALI_PHY_418_DATA 0x00000000
> +#define DENALI_PHY_419_DATA 0x00000000
> +#define DENALI_PHY_420_DATA 0x00000000
> +#define DENALI_PHY_421_DATA 0x00000000
> +#define DENALI_PHY_422_DATA 0x00000000
> +#define DENALI_PHY_423_DATA 0x00000000
> +#define DENALI_PHY_424_DATA 0x02800280
> +#define DENALI_PHY_425_DATA 0x02800280
> +#define DENALI_PHY_426_DATA 0x02800280
> +#define DENALI_PHY_427_DATA 0x02800280
> +#define DENALI_PHY_428_DATA 0x00000280
> +#define DENALI_PHY_429_DATA 0x00000000
> +#define DENALI_PHY_430_DATA 0x00000000
> +#define DENALI_PHY_431_DATA 0x00000000
> +#define DENALI_PHY_432_DATA 0x00000000
> +#define DENALI_PHY_433_DATA 0x00000000
> +#define DENALI_PHY_434_DATA 0x00800080
> +#define DENALI_PHY_435_DATA 0x00800080
> +#define DENALI_PHY_436_DATA 0x00800080
> +#define DENALI_PHY_437_DATA 0x00800080
> +#define DENALI_PHY_438_DATA 0x00800080
> +#define DENALI_PHY_439_DATA 0x00800080
> +#define DENALI_PHY_440_DATA 0x00800080
> +#define DENALI_PHY_441_DATA 0x00800080
> +#define DENALI_PHY_442_DATA 0x00800080
> +#define DENALI_PHY_443_DATA 0x000100da
> +#define DENALI_PHY_444_DATA 0x00000200
> +#define DENALI_PHY_445_DATA 0x00000000
> +#define DENALI_PHY_446_DATA 0x00000000
> +#define DENALI_PHY_447_DATA 0x00000002
> +#define DENALI_PHY_448_DATA 0x51313152
> +#define DENALI_PHY_449_DATA 0x80013130
> +#define DENALI_PHY_450_DATA 0x02000080
> +#define DENALI_PHY_451_DATA 0x00100001
> +#define DENALI_PHY_452_DATA 0x0c064208
> +#define DENALI_PHY_453_DATA 0x000f0c0f
> +#define DENALI_PHY_454_DATA 0x01000140
> +#define DENALI_PHY_455_DATA 0x0000000c
> +#define DENALI_PHY_456_DATA 0x00000000
> +#define DENALI_PHY_457_DATA 0x00000000
> +#define DENALI_PHY_458_DATA 0x00000000
> +#define DENALI_PHY_459_DATA 0x00000000
> +#define DENALI_PHY_460_DATA 0x00000000
> +#define DENALI_PHY_461_DATA 0x00000000
> +#define DENALI_PHY_462_DATA 0x00000000
> +#define DENALI_PHY_463_DATA 0x00000000
> +#define DENALI_PHY_464_DATA 0x00000000
> +#define DENALI_PHY_465_DATA 0x00000000
> +#define DENALI_PHY_466_DATA 0x00000000
> +#define DENALI_PHY_467_DATA 0x00000000
> +#define DENALI_PHY_468_DATA 0x00000000
> +#define DENALI_PHY_469_DATA 0x00000000
> +#define DENALI_PHY_470_DATA 0x00000000
> +#define DENALI_PHY_471_DATA 0x00000000
> +#define DENALI_PHY_472_DATA 0x00000000
> +#define DENALI_PHY_473_DATA 0x00000000
> +#define DENALI_PHY_474_DATA 0x00000000
> +#define DENALI_PHY_475_DATA 0x00000000
> +#define DENALI_PHY_476_DATA 0x00000000
> +#define DENALI_PHY_477_DATA 0x00000000
> +#define DENALI_PHY_478_DATA 0x00000000
> +#define DENALI_PHY_479_DATA 0x00000000
> +#define DENALI_PHY_480_DATA 0x00000000
> +#define DENALI_PHY_481_DATA 0x00000000
> +#define DENALI_PHY_482_DATA 0x00000000
> +#define DENALI_PHY_483_DATA 0x00000000
> +#define DENALI_PHY_484_DATA 0x00000000
> +#define DENALI_PHY_485_DATA 0x00000000
> +#define DENALI_PHY_486_DATA 0x00000000
> +#define DENALI_PHY_487_DATA 0x00000000
> +#define DENALI_PHY_488_DATA 0x00000000
> +#define DENALI_PHY_489_DATA 0x00000000
> +#define DENALI_PHY_490_DATA 0x00000000
> +#define DENALI_PHY_491_DATA 0x00000000
> +#define DENALI_PHY_492_DATA 0x00000000
> +#define DENALI_PHY_493_DATA 0x00000000
> +#define DENALI_PHY_494_DATA 0x00000000
> +#define DENALI_PHY_495_DATA 0x00000000
> +#define DENALI_PHY_496_DATA 0x00000000
> +#define DENALI_PHY_497_DATA 0x00000000
> +#define DENALI_PHY_498_DATA 0x00000000
> +#define DENALI_PHY_499_DATA 0x00000000
> +#define DENALI_PHY_500_DATA 0x00000000
> +#define DENALI_PHY_501_DATA 0x00000000
> +#define DENALI_PHY_502_DATA 0x00000000
> +#define DENALI_PHY_503_DATA 0x00000000
> +#define DENALI_PHY_504_DATA 0x00000000
> +#define DENALI_PHY_505_DATA 0x00000000
> +#define DENALI_PHY_506_DATA 0x00000000
> +#define DENALI_PHY_507_DATA 0x00000000
> +#define DENALI_PHY_508_DATA 0x00000000
> +#define DENALI_PHY_509_DATA 0x00000000
> +#define DENALI_PHY_510_DATA 0x00000000
> +#define DENALI_PHY_511_DATA 0x00000000
> +#define DENALI_PHY_512_DATA 0x24316750
> +#define DENALI_PHY_513_DATA 0x0004c008
> +#define DENALI_PHY_514_DATA 0x000000da
> +#define DENALI_PHY_515_DATA 0x00000000
> +#define DENALI_PHY_516_DATA 0x00000000
> +#define DENALI_PHY_517_DATA 0x00010000
> +#define DENALI_PHY_518_DATA 0x01DDDD90
> +#define DENALI_PHY_519_DATA 0x01DDDD90
> +#define DENALI_PHY_520_DATA 0x01030000
> +#define DENALI_PHY_521_DATA 0x01000000
> +#define DENALI_PHY_522_DATA 0x00c00000
> +#define DENALI_PHY_523_DATA 0x00000007
> +#define DENALI_PHY_524_DATA 0x00000000
> +#define DENALI_PHY_525_DATA 0x00000000
> +#define DENALI_PHY_526_DATA 0x04000408
> +#define DENALI_PHY_527_DATA 0x00000408
> +#define DENALI_PHY_528_DATA 0x00e4e400
> +#define DENALI_PHY_529_DATA 0x00000000
> +#define DENALI_PHY_530_DATA 0x00000000
> +#define DENALI_PHY_531_DATA 0x00000000
> +#define DENALI_PHY_532_DATA 0x00000000
> +#define DENALI_PHY_533_DATA 0x00000000
> +#define DENALI_PHY_534_DATA 0x00000000
> +#define DENALI_PHY_535_DATA 0x00000000
> +#define DENALI_PHY_536_DATA 0x00000000
> +#define DENALI_PHY_537_DATA 0x00000000
> +#define DENALI_PHY_538_DATA 0x00000000
> +#define DENALI_PHY_539_DATA 0x00000000
> +#define DENALI_PHY_540_DATA 0x00000000
> +#define DENALI_PHY_541_DATA 0x00000000
> +#define DENALI_PHY_542_DATA 0x00000000
> +#define DENALI_PHY_543_DATA 0x00000000
> +#define DENALI_PHY_544_DATA 0x00000000
> +#define DENALI_PHY_545_DATA 0x00200000
> +#define DENALI_PHY_546_DATA 0x00000000
> +#define DENALI_PHY_547_DATA 0x00000000
> +#define DENALI_PHY_548_DATA 0x00000000
> +#define DENALI_PHY_549_DATA 0x00000000
> +#define DENALI_PHY_550_DATA 0x00000000
> +#define DENALI_PHY_551_DATA 0x00000000
> +#define DENALI_PHY_552_DATA 0x02800280
> +#define DENALI_PHY_553_DATA 0x02800280
> +#define DENALI_PHY_554_DATA 0x02800280
> +#define DENALI_PHY_555_DATA 0x02800280
> +#define DENALI_PHY_556_DATA 0x00000280
> +#define DENALI_PHY_557_DATA 0x00000000
> +#define DENALI_PHY_558_DATA 0x00000000
> +#define DENALI_PHY_559_DATA 0x00000000
> +#define DENALI_PHY_560_DATA 0x00000000
> +#define DENALI_PHY_561_DATA 0x00000000
> +#define DENALI_PHY_562_DATA 0x00800080
> +#define DENALI_PHY_563_DATA 0x00800080
> +#define DENALI_PHY_564_DATA 0x00800080
> +#define DENALI_PHY_565_DATA 0x00800080
> +#define DENALI_PHY_566_DATA 0x00800080
> +#define DENALI_PHY_567_DATA 0x00800080
> +#define DENALI_PHY_568_DATA 0x00800080
> +#define DENALI_PHY_569_DATA 0x00800080
> +#define DENALI_PHY_570_DATA 0x00800080
> +#define DENALI_PHY_571_DATA 0x000100da
> +#define DENALI_PHY_572_DATA 0x00000200
> +#define DENALI_PHY_573_DATA 0x00000000
> +#define DENALI_PHY_574_DATA 0x00000000
> +#define DENALI_PHY_575_DATA 0x00000002
> +#define DENALI_PHY_576_DATA 0x51313152
> +#define DENALI_PHY_577_DATA 0x80013130
> +#define DENALI_PHY_578_DATA 0x02000080
> +#define DENALI_PHY_579_DATA 0x00100001
> +#define DENALI_PHY_580_DATA 0x0c064208
> +#define DENALI_PHY_581_DATA 0x000f0c0f
> +#define DENALI_PHY_582_DATA 0x01000140
> +#define DENALI_PHY_583_DATA 0x0000000c
> +#define DENALI_PHY_584_DATA 0x00000000
> +#define DENALI_PHY_585_DATA 0x00000000
> +#define DENALI_PHY_586_DATA 0x00000000
> +#define DENALI_PHY_587_DATA 0x00000000
> +#define DENALI_PHY_588_DATA 0x00000000
> +#define DENALI_PHY_589_DATA 0x00000000
> +#define DENALI_PHY_590_DATA 0x00000000
> +#define DENALI_PHY_591_DATA 0x00000000
> +#define DENALI_PHY_592_DATA 0x00000000
> +#define DENALI_PHY_593_DATA 0x00000000
> +#define DENALI_PHY_594_DATA 0x00000000
> +#define DENALI_PHY_595_DATA 0x00000000
> +#define DENALI_PHY_596_DATA 0x00000000
> +#define DENALI_PHY_597_DATA 0x00000000
> +#define DENALI_PHY_598_DATA 0x00000000
> +#define DENALI_PHY_599_DATA 0x00000000
> +#define DENALI_PHY_600_DATA 0x00000000
> +#define DENALI_PHY_601_DATA 0x00000000
> +#define DENALI_PHY_602_DATA 0x00000000
> +#define DENALI_PHY_603_DATA 0x00000000
> +#define DENALI_PHY_604_DATA 0x00000000
> +#define DENALI_PHY_605_DATA 0x00000000
> +#define DENALI_PHY_606_DATA 0x00000000
> +#define DENALI_PHY_607_DATA 0x00000000
> +#define DENALI_PHY_608_DATA 0x00000000
> +#define DENALI_PHY_609_DATA 0x00000000
> +#define DENALI_PHY_610_DATA 0x00000000
> +#define DENALI_PHY_611_DATA 0x00000000
> +#define DENALI_PHY_612_DATA 0x00000000
> +#define DENALI_PHY_613_DATA 0x00000000
> +#define DENALI_PHY_614_DATA 0x00000000
> +#define DENALI_PHY_615_DATA 0x00000000
> +#define DENALI_PHY_616_DATA 0x00000000
> +#define DENALI_PHY_617_DATA 0x00000000
> +#define DENALI_PHY_618_DATA 0x00000000
> +#define DENALI_PHY_619_DATA 0x00000000
> +#define DENALI_PHY_620_DATA 0x00000000
> +#define DENALI_PHY_621_DATA 0x00000000
> +#define DENALI_PHY_622_DATA 0x00000000
> +#define DENALI_PHY_623_DATA 0x00000000
> +#define DENALI_PHY_624_DATA 0x00000000
> +#define DENALI_PHY_625_DATA 0x00000000
> +#define DENALI_PHY_626_DATA 0x00000000
> +#define DENALI_PHY_627_DATA 0x00000000
> +#define DENALI_PHY_628_DATA 0x00000000
> +#define DENALI_PHY_629_DATA 0x00000000
> +#define DENALI_PHY_630_DATA 0x00000000
> +#define DENALI_PHY_631_DATA 0x00000000
> +#define DENALI_PHY_632_DATA 0x00000000
> +#define DENALI_PHY_633_DATA 0x00000000
> +#define DENALI_PHY_634_DATA 0x00000000
> +#define DENALI_PHY_635_DATA 0x00000000
> +#define DENALI_PHY_636_DATA 0x00000000
> +#define DENALI_PHY_637_DATA 0x00000000
> +#define DENALI_PHY_638_DATA 0x00000000
> +#define DENALI_PHY_639_DATA 0x00000000
> +#define DENALI_PHY_640_DATA 0x35174620
> +#define DENALI_PHY_641_DATA 0x0004c008
> +#define DENALI_PHY_642_DATA 0x000000da
> +#define DENALI_PHY_643_DATA 0x00000000
> +#define DENALI_PHY_644_DATA 0x00000000
> +#define DENALI_PHY_645_DATA 0x00010000
> +#define DENALI_PHY_646_DATA 0x01DDDD90
> +#define DENALI_PHY_647_DATA 0x01DDDD90
> +#define DENALI_PHY_648_DATA 0x01030000
> +#define DENALI_PHY_649_DATA 0x01000000
> +#define DENALI_PHY_650_DATA 0x00c00000
> +#define DENALI_PHY_651_DATA 0x00000007
> +#define DENALI_PHY_652_DATA 0x00000000
> +#define DENALI_PHY_653_DATA 0x00000000
> +#define DENALI_PHY_654_DATA 0x04000408
> +#define DENALI_PHY_655_DATA 0x00000408
> +#define DENALI_PHY_656_DATA 0x00e4e400
> +#define DENALI_PHY_657_DATA 0x00000000
> +#define DENALI_PHY_658_DATA 0x00000000
> +#define DENALI_PHY_659_DATA 0x00000000
> +#define DENALI_PHY_660_DATA 0x00000000
> +#define DENALI_PHY_661_DATA 0x00000000
> +#define DENALI_PHY_662_DATA 0x00000000
> +#define DENALI_PHY_663_DATA 0x00000000
> +#define DENALI_PHY_664_DATA 0x00000000
> +#define DENALI_PHY_665_DATA 0x00000000
> +#define DENALI_PHY_666_DATA 0x00000000
> +#define DENALI_PHY_667_DATA 0x00000000
> +#define DENALI_PHY_668_DATA 0x00000000
> +#define DENALI_PHY_669_DATA 0x00000000
> +#define DENALI_PHY_670_DATA 0x00000000
> +#define DENALI_PHY_671_DATA 0x00000000
> +#define DENALI_PHY_672_DATA 0x00000000
> +#define DENALI_PHY_673_DATA 0x00200000
> +#define DENALI_PHY_674_DATA 0x00000000
> +#define DENALI_PHY_675_DATA 0x00000000
> +#define DENALI_PHY_676_DATA 0x00000000
> +#define DENALI_PHY_677_DATA 0x00000000
> +#define DENALI_PHY_678_DATA 0x00000000
> +#define DENALI_PHY_679_DATA 0x00000000
> +#define DENALI_PHY_680_DATA 0x02800280
> +#define DENALI_PHY_681_DATA 0x02800280
> +#define DENALI_PHY_682_DATA 0x02800280
> +#define DENALI_PHY_683_DATA 0x02800280
> +#define DENALI_PHY_684_DATA 0x00000280
> +#define DENALI_PHY_685_DATA 0x00000000
> +#define DENALI_PHY_686_DATA 0x00000000
> +#define DENALI_PHY_687_DATA 0x00000000
> +#define DENALI_PHY_688_DATA 0x00000000
> +#define DENALI_PHY_689_DATA 0x00000000
> +#define DENALI_PHY_690_DATA 0x00800080
> +#define DENALI_PHY_691_DATA 0x00800080
> +#define DENALI_PHY_692_DATA 0x00800080
> +#define DENALI_PHY_693_DATA 0x00800080
> +#define DENALI_PHY_694_DATA 0x00800080
> +#define DENALI_PHY_695_DATA 0x00800080
> +#define DENALI_PHY_696_DATA 0x00800080
> +#define DENALI_PHY_697_DATA 0x00800080
> +#define DENALI_PHY_698_DATA 0x00800080
> +#define DENALI_PHY_699_DATA 0x000100da
> +#define DENALI_PHY_700_DATA 0x00000200
> +#define DENALI_PHY_701_DATA 0x00000000
> +#define DENALI_PHY_702_DATA 0x00000000
> +#define DENALI_PHY_703_DATA 0x00000002
> +#define DENALI_PHY_704_DATA 0x51313152
> +#define DENALI_PHY_705_DATA 0x80013130
> +#define DENALI_PHY_706_DATA 0x02000080
> +#define DENALI_PHY_707_DATA 0x00100001
> +#define DENALI_PHY_708_DATA 0x0c064208
> +#define DENALI_PHY_709_DATA 0x000f0c0f
> +#define DENALI_PHY_710_DATA 0x01000140
> +#define DENALI_PHY_711_DATA 0x0000000c
> +#define DENALI_PHY_712_DATA 0x00000000
> +#define DENALI_PHY_713_DATA 0x00000000
> +#define DENALI_PHY_714_DATA 0x00000000
> +#define DENALI_PHY_715_DATA 0x00000000
> +#define DENALI_PHY_716_DATA 0x00000000
> +#define DENALI_PHY_717_DATA 0x00000000
> +#define DENALI_PHY_718_DATA 0x00000000
> +#define DENALI_PHY_719_DATA 0x00000000
> +#define DENALI_PHY_720_DATA 0x00000000
> +#define DENALI_PHY_721_DATA 0x00000000
> +#define DENALI_PHY_722_DATA 0x00000000
> +#define DENALI_PHY_723_DATA 0x00000000
> +#define DENALI_PHY_724_DATA 0x00000000
> +#define DENALI_PHY_725_DATA 0x00000000
> +#define DENALI_PHY_726_DATA 0x00000000
> +#define DENALI_PHY_727_DATA 0x00000000
> +#define DENALI_PHY_728_DATA 0x00000000
> +#define DENALI_PHY_729_DATA 0x00000000
> +#define DENALI_PHY_730_DATA 0x00000000
> +#define DENALI_PHY_731_DATA 0x00000000
> +#define DENALI_PHY_732_DATA 0x00000000
> +#define DENALI_PHY_733_DATA 0x00000000
> +#define DENALI_PHY_734_DATA 0x00000000
> +#define DENALI_PHY_735_DATA 0x00000000
> +#define DENALI_PHY_736_DATA 0x00000000
> +#define DENALI_PHY_737_DATA 0x00000000
> +#define DENALI_PHY_738_DATA 0x00000000
> +#define DENALI_PHY_739_DATA 0x00000000
> +#define DENALI_PHY_740_DATA 0x00000000
> +#define DENALI_PHY_741_DATA 0x00000000
> +#define DENALI_PHY_742_DATA 0x00000000
> +#define DENALI_PHY_743_DATA 0x00000000
> +#define DENALI_PHY_744_DATA 0x00000000
> +#define DENALI_PHY_745_DATA 0x00000000
> +#define DENALI_PHY_746_DATA 0x00000000
> +#define DENALI_PHY_747_DATA 0x00000000
> +#define DENALI_PHY_748_DATA 0x00000000
> +#define DENALI_PHY_749_DATA 0x00000000
> +#define DENALI_PHY_750_DATA 0x00000000
> +#define DENALI_PHY_751_DATA 0x00000000
> +#define DENALI_PHY_752_DATA 0x00000000
> +#define DENALI_PHY_753_DATA 0x00000000
> +#define DENALI_PHY_754_DATA 0x00000000
> +#define DENALI_PHY_755_DATA 0x00000000
> +#define DENALI_PHY_756_DATA 0x00000000
> +#define DENALI_PHY_757_DATA 0x00000000
> +#define DENALI_PHY_758_DATA 0x00000000
> +#define DENALI_PHY_759_DATA 0x00000000
> +#define DENALI_PHY_760_DATA 0x00000000
> +#define DENALI_PHY_761_DATA 0x00000000
> +#define DENALI_PHY_762_DATA 0x00000000
> +#define DENALI_PHY_763_DATA 0x00000000
> +#define DENALI_PHY_764_DATA 0x00000000
> +#define DENALI_PHY_765_DATA 0x00000000
> +#define DENALI_PHY_766_DATA 0x00000000
> +#define DENALI_PHY_767_DATA 0x00000000
> +#define DENALI_PHY_768_DATA 0x15203476
> +#define DENALI_PHY_769_DATA 0x0004c008
> +#define DENALI_PHY_770_DATA 0x000000da
> +#define DENALI_PHY_771_DATA 0x00000000
> +#define DENALI_PHY_772_DATA 0x00000000
> +#define DENALI_PHY_773_DATA 0x00010000
> +#define DENALI_PHY_774_DATA 0x01DDDD90
> +#define DENALI_PHY_775_DATA 0x01DDDD90
> +#define DENALI_PHY_776_DATA 0x01030000
> +#define DENALI_PHY_777_DATA 0x01000000
> +#define DENALI_PHY_778_DATA 0x00c00000
> +#define DENALI_PHY_779_DATA 0x00000007
> +#define DENALI_PHY_780_DATA 0x00000000
> +#define DENALI_PHY_781_DATA 0x00000000
> +#define DENALI_PHY_782_DATA 0x04000408
> +#define DENALI_PHY_783_DATA 0x00000408
> +#define DENALI_PHY_784_DATA 0x00e4e400
> +#define DENALI_PHY_785_DATA 0x00000000
> +#define DENALI_PHY_786_DATA 0x00000000
> +#define DENALI_PHY_787_DATA 0x00000000
> +#define DENALI_PHY_788_DATA 0x00000000
> +#define DENALI_PHY_789_DATA 0x00000000
> +#define DENALI_PHY_790_DATA 0x00000000
> +#define DENALI_PHY_791_DATA 0x00000000
> +#define DENALI_PHY_792_DATA 0x00000000
> +#define DENALI_PHY_793_DATA 0x00000000
> +#define DENALI_PHY_794_DATA 0x00000000
> +#define DENALI_PHY_795_DATA 0x00000000
> +#define DENALI_PHY_796_DATA 0x00000000
> +#define DENALI_PHY_797_DATA 0x00000000
> +#define DENALI_PHY_798_DATA 0x00000000
> +#define DENALI_PHY_799_DATA 0x00000000
> +#define DENALI_PHY_800_DATA 0x00000000
> +#define DENALI_PHY_801_DATA 0x00200000
> +#define DENALI_PHY_802_DATA 0x00000000
> +#define DENALI_PHY_803_DATA 0x00000000
> +#define DENALI_PHY_804_DATA 0x00000000
> +#define DENALI_PHY_805_DATA 0x00000000
> +#define DENALI_PHY_806_DATA 0x00000000
> +#define DENALI_PHY_807_DATA 0x00000000
> +#define DENALI_PHY_808_DATA 0x02800280
> +#define DENALI_PHY_809_DATA 0x02800280
> +#define DENALI_PHY_810_DATA 0x02800280
> +#define DENALI_PHY_811_DATA 0x02800280
> +#define DENALI_PHY_812_DATA 0x00000280
> +#define DENALI_PHY_813_DATA 0x00000000
> +#define DENALI_PHY_814_DATA 0x00000000
> +#define DENALI_PHY_815_DATA 0x00000000
> +#define DENALI_PHY_816_DATA 0x00000000
> +#define DENALI_PHY_817_DATA 0x00000000
> +#define DENALI_PHY_818_DATA 0x00800080
> +#define DENALI_PHY_819_DATA 0x00800080
> +#define DENALI_PHY_820_DATA 0x00800080
> +#define DENALI_PHY_821_DATA 0x00800080
> +#define DENALI_PHY_822_DATA 0x00800080
> +#define DENALI_PHY_823_DATA 0x00800080
> +#define DENALI_PHY_824_DATA 0x00800080
> +#define DENALI_PHY_825_DATA 0x00800080
> +#define DENALI_PHY_826_DATA 0x00800080
> +#define DENALI_PHY_827_DATA 0x000100da
> +#define DENALI_PHY_828_DATA 0x00000200
> +#define DENALI_PHY_829_DATA 0x00000000
> +#define DENALI_PHY_830_DATA 0x00000000
> +#define DENALI_PHY_831_DATA 0x00000002
> +#define DENALI_PHY_832_DATA 0x51313152
> +#define DENALI_PHY_833_DATA 0x80013130
> +#define DENALI_PHY_834_DATA 0x02000080
> +#define DENALI_PHY_835_DATA 0x00100001
> +#define DENALI_PHY_836_DATA 0x0c064208
> +#define DENALI_PHY_837_DATA 0x000f0c0f
> +#define DENALI_PHY_838_DATA 0x01000140
> +#define DENALI_PHY_839_DATA 0x0000000c
> +#define DENALI_PHY_840_DATA 0x00000000
> +#define DENALI_PHY_841_DATA 0x00000000
> +#define DENALI_PHY_842_DATA 0x00000000
> +#define DENALI_PHY_843_DATA 0x00000000
> +#define DENALI_PHY_844_DATA 0x00000000
> +#define DENALI_PHY_845_DATA 0x00000000
> +#define DENALI_PHY_846_DATA 0x00000000
> +#define DENALI_PHY_847_DATA 0x00000000
> +#define DENALI_PHY_848_DATA 0x00000000
> +#define DENALI_PHY_849_DATA 0x00000000
> +#define DENALI_PHY_850_DATA 0x00000000
> +#define DENALI_PHY_851_DATA 0x00000000
> +#define DENALI_PHY_852_DATA 0x00000000
> +#define DENALI_PHY_853_DATA 0x00000000
> +#define DENALI_PHY_854_DATA 0x00000000
> +#define DENALI_PHY_855_DATA 0x00000000
> +#define DENALI_PHY_856_DATA 0x00000000
> +#define DENALI_PHY_857_DATA 0x00000000
> +#define DENALI_PHY_858_DATA 0x00000000
> +#define DENALI_PHY_859_DATA 0x00000000
> +#define DENALI_PHY_860_DATA 0x00000000
> +#define DENALI_PHY_861_DATA 0x00000000
> +#define DENALI_PHY_862_DATA 0x00000000
> +#define DENALI_PHY_863_DATA 0x00000000
> +#define DENALI_PHY_864_DATA 0x00000000
> +#define DENALI_PHY_865_DATA 0x00000000
> +#define DENALI_PHY_866_DATA 0x00000000
> +#define DENALI_PHY_867_DATA 0x00000000
> +#define DENALI_PHY_868_DATA 0x00000000
> +#define DENALI_PHY_869_DATA 0x00000000
> +#define DENALI_PHY_870_DATA 0x00000000
> +#define DENALI_PHY_871_DATA 0x00000000
> +#define DENALI_PHY_872_DATA 0x00000000
> +#define DENALI_PHY_873_DATA 0x00000000
> +#define DENALI_PHY_874_DATA 0x00000000
> +#define DENALI_PHY_875_DATA 0x00000000
> +#define DENALI_PHY_876_DATA 0x00000000
> +#define DENALI_PHY_877_DATA 0x00000000
> +#define DENALI_PHY_878_DATA 0x00000000
> +#define DENALI_PHY_879_DATA 0x00000000
> +#define DENALI_PHY_880_DATA 0x00000000
> +#define DENALI_PHY_881_DATA 0x00000000
> +#define DENALI_PHY_882_DATA 0x00000000
> +#define DENALI_PHY_883_DATA 0x00000000
> +#define DENALI_PHY_884_DATA 0x00000000
> +#define DENALI_PHY_885_DATA 0x00000000
> +#define DENALI_PHY_886_DATA 0x00000000
> +#define DENALI_PHY_887_DATA 0x00000000
> +#define DENALI_PHY_888_DATA 0x00000000
> +#define DENALI_PHY_889_DATA 0x00000000
> +#define DENALI_PHY_890_DATA 0x00000000
> +#define DENALI_PHY_891_DATA 0x00000000
> +#define DENALI_PHY_892_DATA 0x00000000
> +#define DENALI_PHY_893_DATA 0x00000000
> +#define DENALI_PHY_894_DATA 0x00000000
> +#define DENALI_PHY_895_DATA 0x00000000
> +#define DENALI_PHY_896_DATA 0x41753206
> +#define DENALI_PHY_897_DATA 0x0004c008
> +#define DENALI_PHY_898_DATA 0x000000da
> +#define DENALI_PHY_899_DATA 0x00000000
> +#define DENALI_PHY_900_DATA 0x00000000
> +#define DENALI_PHY_901_DATA 0x00010000
> +#define DENALI_PHY_902_DATA 0x01DDDD90
> +#define DENALI_PHY_903_DATA 0x01DDDD90
> +#define DENALI_PHY_904_DATA 0x01030000
> +#define DENALI_PHY_905_DATA 0x01000000
> +#define DENALI_PHY_906_DATA 0x00c00000
> +#define DENALI_PHY_907_DATA 0x00000007
> +#define DENALI_PHY_908_DATA 0x00000000
> +#define DENALI_PHY_909_DATA 0x00000000
> +#define DENALI_PHY_910_DATA 0x04000408
> +#define DENALI_PHY_911_DATA 0x00000408
> +#define DENALI_PHY_912_DATA 0x00e4e400
> +#define DENALI_PHY_913_DATA 0x00000000
> +#define DENALI_PHY_914_DATA 0x00000000
> +#define DENALI_PHY_915_DATA 0x00000000
> +#define DENALI_PHY_916_DATA 0x00000000
> +#define DENALI_PHY_917_DATA 0x00000000
> +#define DENALI_PHY_918_DATA 0x00000000
> +#define DENALI_PHY_919_DATA 0x00000000
> +#define DENALI_PHY_920_DATA 0x00000000
> +#define DENALI_PHY_921_DATA 0x00000000
> +#define DENALI_PHY_922_DATA 0x00000000
> +#define DENALI_PHY_923_DATA 0x00000000
> +#define DENALI_PHY_924_DATA 0x00000000
> +#define DENALI_PHY_925_DATA 0x00000000
> +#define DENALI_PHY_926_DATA 0x00000000
> +#define DENALI_PHY_927_DATA 0x00000000
> +#define DENALI_PHY_928_DATA 0x00000000
> +#define DENALI_PHY_929_DATA 0x00200000
> +#define DENALI_PHY_930_DATA 0x00000000
> +#define DENALI_PHY_931_DATA 0x00000000
> +#define DENALI_PHY_932_DATA 0x00000000
> +#define DENALI_PHY_933_DATA 0x00000000
> +#define DENALI_PHY_934_DATA 0x00000000
> +#define DENALI_PHY_935_DATA 0x00000000
> +#define DENALI_PHY_936_DATA 0x02800280
> +#define DENALI_PHY_937_DATA 0x02800280
> +#define DENALI_PHY_938_DATA 0x02800280
> +#define DENALI_PHY_939_DATA 0x02800280
> +#define DENALI_PHY_940_DATA 0x00000280
> +#define DENALI_PHY_941_DATA 0x00000000
> +#define DENALI_PHY_942_DATA 0x00000000
> +#define DENALI_PHY_943_DATA 0x00000000
> +#define DENALI_PHY_944_DATA 0x00000000
> +#define DENALI_PHY_945_DATA 0x00000000
> +#define DENALI_PHY_946_DATA 0x00800080
> +#define DENALI_PHY_947_DATA 0x00800080
> +#define DENALI_PHY_948_DATA 0x00800080
> +#define DENALI_PHY_949_DATA 0x00800080
> +#define DENALI_PHY_950_DATA 0x00800080
> +#define DENALI_PHY_951_DATA 0x00800080
> +#define DENALI_PHY_952_DATA 0x00800080
> +#define DENALI_PHY_953_DATA 0x00800080
> +#define DENALI_PHY_954_DATA 0x00800080
> +#define DENALI_PHY_955_DATA 0x000100da
> +#define DENALI_PHY_956_DATA 0x00000200
> +#define DENALI_PHY_957_DATA 0x00000000
> +#define DENALI_PHY_958_DATA 0x00000000
> +#define DENALI_PHY_959_DATA 0x00000002
> +#define DENALI_PHY_960_DATA 0x51313152
> +#define DENALI_PHY_961_DATA 0x80013130
> +#define DENALI_PHY_962_DATA 0x02000080
> +#define DENALI_PHY_963_DATA 0x00100001
> +#define DENALI_PHY_964_DATA 0x0c064208
> +#define DENALI_PHY_965_DATA 0x000f0c0f
> +#define DENALI_PHY_966_DATA 0x01000140
> +#define DENALI_PHY_967_DATA 0x0000000c
> +#define DENALI_PHY_968_DATA 0x00000000
> +#define DENALI_PHY_969_DATA 0x00000000
> +#define DENALI_PHY_970_DATA 0x00000000
> +#define DENALI_PHY_971_DATA 0x00000000
> +#define DENALI_PHY_972_DATA 0x00000000
> +#define DENALI_PHY_973_DATA 0x00000000
> +#define DENALI_PHY_974_DATA 0x00000000
> +#define DENALI_PHY_975_DATA 0x00000000
> +#define DENALI_PHY_976_DATA 0x00000000
> +#define DENALI_PHY_977_DATA 0x00000000
> +#define DENALI_PHY_978_DATA 0x00000000
> +#define DENALI_PHY_979_DATA 0x00000000
> +#define DENALI_PHY_980_DATA 0x00000000
> +#define DENALI_PHY_981_DATA 0x00000000
> +#define DENALI_PHY_982_DATA 0x00000000
> +#define DENALI_PHY_983_DATA 0x00000000
> +#define DENALI_PHY_984_DATA 0x00000000
> +#define DENALI_PHY_985_DATA 0x00000000
> +#define DENALI_PHY_986_DATA 0x00000000
> +#define DENALI_PHY_987_DATA 0x00000000
> +#define DENALI_PHY_988_DATA 0x00000000
> +#define DENALI_PHY_989_DATA 0x00000000
> +#define DENALI_PHY_990_DATA 0x00000000
> +#define DENALI_PHY_991_DATA 0x00000000
> +#define DENALI_PHY_992_DATA 0x00000000
> +#define DENALI_PHY_993_DATA 0x00000000
> +#define DENALI_PHY_994_DATA 0x00000000
> +#define DENALI_PHY_995_DATA 0x00000000
> +#define DENALI_PHY_996_DATA 0x00000000
> +#define DENALI_PHY_997_DATA 0x00000000
> +#define DENALI_PHY_998_DATA 0x00000000
> +#define DENALI_PHY_999_DATA 0x00000000
> +#define DENALI_PHY_1000_DATA 0x00000000
> +#define DENALI_PHY_1001_DATA 0x00000000
> +#define DENALI_PHY_1002_DATA 0x00000000
> +#define DENALI_PHY_1003_DATA 0x00000000
> +#define DENALI_PHY_1004_DATA 0x00000000
> +#define DENALI_PHY_1005_DATA 0x00000000
> +#define DENALI_PHY_1006_DATA 0x00000000
> +#define DENALI_PHY_1007_DATA 0x00000000
> +#define DENALI_PHY_1008_DATA 0x00000000
> +#define DENALI_PHY_1009_DATA 0x00000000
> +#define DENALI_PHY_1010_DATA 0x00000000
> +#define DENALI_PHY_1011_DATA 0x00000000
> +#define DENALI_PHY_1012_DATA 0x00000000
> +#define DENALI_PHY_1013_DATA 0x00000000
> +#define DENALI_PHY_1014_DATA 0x00000000
> +#define DENALI_PHY_1015_DATA 0x00000000
> +#define DENALI_PHY_1016_DATA 0x00000000
> +#define DENALI_PHY_1017_DATA 0x00000000
> +#define DENALI_PHY_1018_DATA 0x00000000
> +#define DENALI_PHY_1019_DATA 0x00000000
> +#define DENALI_PHY_1020_DATA 0x00000000
> +#define DENALI_PHY_1021_DATA 0x00000000
> +#define DENALI_PHY_1022_DATA 0x00000000
> +#define DENALI_PHY_1023_DATA 0x00000000
> +#define DENALI_PHY_1024_DATA 0x36025174
> +#define DENALI_PHY_1025_DATA 0x0004c008
> +#define DENALI_PHY_1026_DATA 0x000000da
> +#define DENALI_PHY_1027_DATA 0x00000000
> +#define DENALI_PHY_1028_DATA 0x00000000
> +#define DENALI_PHY_1029_DATA 0x00010000
> +#define DENALI_PHY_1030_DATA 0x01DDDD90
> +#define DENALI_PHY_1031_DATA 0x01DDDD90
> +#define DENALI_PHY_1032_DATA 0x01030000
> +#define DENALI_PHY_1033_DATA 0x01000000
> +#define DENALI_PHY_1034_DATA 0x00c00000
> +#define DENALI_PHY_1035_DATA 0x00000007
> +#define DENALI_PHY_1036_DATA 0x00000000
> +#define DENALI_PHY_1037_DATA 0x00000000
> +#define DENALI_PHY_1038_DATA 0x04000408
> +#define DENALI_PHY_1039_DATA 0x00000408
> +#define DENALI_PHY_1040_DATA 0x00e4e400
> +#define DENALI_PHY_1041_DATA 0x00000000
> +#define DENALI_PHY_1042_DATA 0x00000000
> +#define DENALI_PHY_1043_DATA 0x00000000
> +#define DENALI_PHY_1044_DATA 0x00000000
> +#define DENALI_PHY_1045_DATA 0x00000000
> +#define DENALI_PHY_1046_DATA 0x00000000
> +#define DENALI_PHY_1047_DATA 0x00000000
> +#define DENALI_PHY_1048_DATA 0x00000000
> +#define DENALI_PHY_1049_DATA 0x00000000
> +#define DENALI_PHY_1050_DATA 0x00000000
> +#define DENALI_PHY_1051_DATA 0x00000000
> +#define DENALI_PHY_1052_DATA 0x00000000
> +#define DENALI_PHY_1053_DATA 0x00000000
> +#define DENALI_PHY_1054_DATA 0x00000000
> +#define DENALI_PHY_1055_DATA 0x00000000
> +#define DENALI_PHY_1056_DATA 0x00000000
> +#define DENALI_PHY_1057_DATA 0x00200000
> +#define DENALI_PHY_1058_DATA 0x00000000
> +#define DENALI_PHY_1059_DATA 0x00000000
> +#define DENALI_PHY_1060_DATA 0x00000000
> +#define DENALI_PHY_1061_DATA 0x00000000
> +#define DENALI_PHY_1062_DATA 0x00000000
> +#define DENALI_PHY_1063_DATA 0x00000000
> +#define DENALI_PHY_1064_DATA 0x02800280
> +#define DENALI_PHY_1065_DATA 0x02800280
> +#define DENALI_PHY_1066_DATA 0x02800280
> +#define DENALI_PHY_1067_DATA 0x02800280
> +#define DENALI_PHY_1068_DATA 0x00000280
> +#define DENALI_PHY_1069_DATA 0x00000000
> +#define DENALI_PHY_1070_DATA 0x00000000
> +#define DENALI_PHY_1071_DATA 0x00000000
> +#define DENALI_PHY_1072_DATA 0x00000000
> +#define DENALI_PHY_1073_DATA 0x00000000
> +#define DENALI_PHY_1074_DATA 0x00800080
> +#define DENALI_PHY_1075_DATA 0x00800080
> +#define DENALI_PHY_1076_DATA 0x00800080
> +#define DENALI_PHY_1077_DATA 0x00800080
> +#define DENALI_PHY_1078_DATA 0x00800080
> +#define DENALI_PHY_1079_DATA 0x00800080
> +#define DENALI_PHY_1080_DATA 0x00800080
> +#define DENALI_PHY_1081_DATA 0x00800080
> +#define DENALI_PHY_1082_DATA 0x00800080
> +#define DENALI_PHY_1083_DATA 0x000100da
> +#define DENALI_PHY_1084_DATA 0x00000200
> +#define DENALI_PHY_1085_DATA 0x00000000
> +#define DENALI_PHY_1086_DATA 0x00000000
> +#define DENALI_PHY_1087_DATA 0x00000002
> +#define DENALI_PHY_1088_DATA 0x51313152
> +#define DENALI_PHY_1089_DATA 0x80013130
> +#define DENALI_PHY_1090_DATA 0x02000080
> +#define DENALI_PHY_1091_DATA 0x00100001
> +#define DENALI_PHY_1092_DATA 0x0c064208
> +#define DENALI_PHY_1093_DATA 0x000f0c0f
> +#define DENALI_PHY_1094_DATA 0x01000140
> +#define DENALI_PHY_1095_DATA 0x0000000c
> +#define DENALI_PHY_1096_DATA 0x00000000
> +#define DENALI_PHY_1097_DATA 0x00000000
> +#define DENALI_PHY_1098_DATA 0x00000000
> +#define DENALI_PHY_1099_DATA 0x00000000
> +#define DENALI_PHY_1100_DATA 0x00000000
> +#define DENALI_PHY_1101_DATA 0x00000000
> +#define DENALI_PHY_1102_DATA 0x00000000
> +#define DENALI_PHY_1103_DATA 0x00000000
> +#define DENALI_PHY_1104_DATA 0x00000000
> +#define DENALI_PHY_1105_DATA 0x00000000
> +#define DENALI_PHY_1106_DATA 0x00000000
> +#define DENALI_PHY_1107_DATA 0x00000000
> +#define DENALI_PHY_1108_DATA 0x00000000
> +#define DENALI_PHY_1109_DATA 0x00000000
> +#define DENALI_PHY_1110_DATA 0x00000000
> +#define DENALI_PHY_1111_DATA 0x00000000
> +#define DENALI_PHY_1112_DATA 0x00000000
> +#define DENALI_PHY_1113_DATA 0x00000000
> +#define DENALI_PHY_1114_DATA 0x00000000
> +#define DENALI_PHY_1115_DATA 0x00000000
> +#define DENALI_PHY_1116_DATA 0x00000000
> +#define DENALI_PHY_1117_DATA 0x00000000
> +#define DENALI_PHY_1118_DATA 0x00000000
> +#define DENALI_PHY_1119_DATA 0x00000000
> +#define DENALI_PHY_1120_DATA 0x00000000
> +#define DENALI_PHY_1121_DATA 0x00000000
> +#define DENALI_PHY_1122_DATA 0x00000000
> +#define DENALI_PHY_1123_DATA 0x00000000
> +#define DENALI_PHY_1124_DATA 0x00000000
> +#define DENALI_PHY_1125_DATA 0x00000000
> +#define DENALI_PHY_1126_DATA 0x00000000
> +#define DENALI_PHY_1127_DATA 0x00000000
> +#define DENALI_PHY_1128_DATA 0x00000000
> +#define DENALI_PHY_1129_DATA 0x00000000
> +#define DENALI_PHY_1130_DATA 0x00000000
> +#define DENALI_PHY_1131_DATA 0x00000000
> +#define DENALI_PHY_1132_DATA 0x00000000
> +#define DENALI_PHY_1133_DATA 0x00000000
> +#define DENALI_PHY_1134_DATA 0x00000000
> +#define DENALI_PHY_1135_DATA 0x00000000
> +#define DENALI_PHY_1136_DATA 0x00000000
> +#define DENALI_PHY_1137_DATA 0x00000000
> +#define DENALI_PHY_1138_DATA 0x00000000
> +#define DENALI_PHY_1139_DATA 0x00000000
> +#define DENALI_PHY_1140_DATA 0x00000000
> +#define DENALI_PHY_1141_DATA 0x00000000
> +#define DENALI_PHY_1142_DATA 0x00000000
> +#define DENALI_PHY_1143_DATA 0x00000000
> +#define DENALI_PHY_1144_DATA 0x00000000
> +#define DENALI_PHY_1145_DATA 0x00000000
> +#define DENALI_PHY_1146_DATA 0x00000000
> +#define DENALI_PHY_1147_DATA 0x00000000
> +#define DENALI_PHY_1148_DATA 0x00000000
> +#define DENALI_PHY_1149_DATA 0x00000000
> +#define DENALI_PHY_1150_DATA 0x00000000
> +#define DENALI_PHY_1151_DATA 0x00000000
> +#define DENALI_PHY_1152_DATA 0x00000000
> +#define DENALI_PHY_1153_DATA 0x00000000
> +#define DENALI_PHY_1154_DATA 0x00050000
> +#define DENALI_PHY_1155_DATA 0x00000000
> +#define DENALI_PHY_1156_DATA 0x00000000
> +#define DENALI_PHY_1157_DATA 0x00000000
> +#define DENALI_PHY_1158_DATA 0x00000100
> +#define DENALI_PHY_1159_DATA 0x00000000
> +#define DENALI_PHY_1160_DATA 0x00000000
> +#define DENALI_PHY_1161_DATA 0x00506401
> +#define DENALI_PHY_1162_DATA 0x01221102
> +#define DENALI_PHY_1163_DATA 0x00000122
> +#define DENALI_PHY_1164_DATA 0x00000000
> +#define DENALI_PHY_1165_DATA 0x000B1F00
> +#define DENALI_PHY_1166_DATA 0x0B1F0B1F
> +#define DENALI_PHY_1167_DATA 0x0B1F0B1B
> +#define DENALI_PHY_1168_DATA 0x0B1F0B1F
> +#define DENALI_PHY_1169_DATA 0x0B1F0B1F
> +#define DENALI_PHY_1170_DATA 0x00000B00
> +#define DENALI_PHY_1171_DATA 0x42080010
> +#define DENALI_PHY_1172_DATA 0x01000100
> +#define DENALI_PHY_1173_DATA 0x01000100
> +#define DENALI_PHY_1174_DATA 0x01000100
> +#define DENALI_PHY_1175_DATA 0x01000100
> +#define DENALI_PHY_1176_DATA 0x00000000
> +#define DENALI_PHY_1177_DATA 0x00000000
> +#define DENALI_PHY_1178_DATA 0x00000000
> +#define DENALI_PHY_1179_DATA 0x00000000
> +#define DENALI_PHY_1180_DATA 0x00000000
> +#define DENALI_PHY_1181_DATA 0x00000803
> +#define DENALI_PHY_1182_DATA 0x223FFF00
> +#define DENALI_PHY_1183_DATA 0x000008FF
> +#define DENALI_PHY_1184_DATA 0x0000057F
> +#define DENALI_PHY_1185_DATA 0x0000057F
> +#define DENALI_PHY_1186_DATA 0x00037FFF
> +#define DENALI_PHY_1187_DATA 0x00037FFF
> +#define DENALI_PHY_1188_DATA 0x00004410
> +#define DENALI_PHY_1189_DATA 0x00004410
> +#define DENALI_PHY_1190_DATA 0x00004410
> +#define DENALI_PHY_1191_DATA 0x00004410
> +#define DENALI_PHY_1192_DATA 0x00004410
> +#define DENALI_PHY_1193_DATA 0x00037FFF
> +#define DENALI_PHY_1194_DATA 0x00037FFF
> +#define DENALI_PHY_1195_DATA 0x00000000
> +#define DENALI_PHY_1196_DATA 0x00000000
> +#define DENALI_PHY_1197_DATA 0x00000000
> +#define DENALI_PHY_1198_DATA 0x04000000
> +#define DENALI_PHY_1199_DATA 0x00000000
> +#define DENALI_PHY_1200_DATA 0x00000000
> +#define DENALI_PHY_1201_DATA 0x00000108
> +#define DENALI_PHY_1202_DATA 0x00000000
> +#define DENALI_PHY_1203_DATA 0x00000000
> +#define DENALI_PHY_1204_DATA 0x00000000
> +#define DENALI_PHY_1205_DATA 0x00000001
> +#define DENALI_PHY_1206_DATA 0x00000000
> +#define DENALI_PHY_1207_DATA 0x00000000
> +#define DENALI_PHY_1208_DATA 0x00000000
> +#define DENALI_PHY_1209_DATA 0x00000000
> +#define DENALI_PHY_1210_DATA 0x00000000
> +#define DENALI_PHY_1211_DATA 0x00000000
> +#define DENALI_PHY_1212_DATA 0x00020100
> +#define DENALI_PHY_1213_DATA 0x00000000
> +#define DENALI_PHY_1214_DATA 0x00000000
Sorry, this entire ddr code look very difficult to undestand or
review. I understand it is driven from the vendor blog or so but it is
not in proper shape to mege it on mainline, IMHO. But I'm sure if we
have a close attenetion then it would definetly a ready peice for
mainline and readable for future proof.
Suggestions would be try to differentiate the code into driver and
timings, so we can write drivers/ram and the timings would be some
sort of dtsi or script or platdata would centainly ddr chip depenent.
I can help here, based on my experince with rockchip ddr, if you need any?
Jagan.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI
2020-01-24 8:06 ` Pragnesh Patel
@ 2020-01-27 7:58 ` Jagan Teki
0 siblings, 0 replies; 32+ messages in thread
From: Jagan Teki @ 2020-01-27 7:58 UTC (permalink / raw)
To: u-boot
On Fri, Jan 24, 2020 at 1:36 PM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
>
> >-----Original Message-----
> >From: Jagan Teki <jagan@amarulasolutions.com>
> >Sent: 24 January 2020 11:58
> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
> ><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
> ><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
> ><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
> ><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
> >Kadam <sagar.kadam@sifive.com>; Simon Glass <sjg@chromium.org>;
> >AKASHI Takahiro <takahiro.akashi@linaro.org>; Marek Behún
> ><marek.behun@nic.cz>; Philippe Reynes <philippe.reynes@softathome.com>;
> >Alexander Graf <agraf@csgraf.de>; Peng Fan <peng.fan@nxp.com>
> >Subject: Re: [PATCH v3 03/10] lib: Makefile: build crc7.c when
> >CONFIG_MMC_SPI
> >
> >On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel <pragnesh.patel@sifive.com>
> >wrote:
> >>
> >> When build U-boot SPL, meet an issue of undefined reference to 'crc7'
> >> for drivers/mmc/mmc_spi.c, so let's compile crc7.c when CONFIG_MMC_SPI
> >> selected.
> >>
> >> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> >> Reviewed-by: Anup Patel <anup.patel@wdc.com>
> >> ---
> >> lib/Makefile | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/lib/Makefile b/lib/Makefile index 51eba80b89..d21e0a6b3a
> >> 100644
> >> --- a/lib/Makefile
> >> +++ b/lib/Makefile
> >> @@ -78,6 +78,7 @@ endif
> >>
> >> ifdef CONFIG_SPL_BUILD
> >> obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
> >> +obj-$(CONFIG_MMC_SPI) += crc7.o
> >
> >It is invalid to mark crc7 to MMC_SPI, try to add Kconfig option for CRC7. like
> >this.
> >https://paste.ubuntu.com/p/kSnkDWpTgS/
>
> Thanks for pointing me. How about if I will add like this:
>
> config SPL_CRC7_SUPPORT
> bool "Support CRC7 hashing drivers"
> default y if MMC_SPI
> help
> Enable CRC7 hashing for drivers which are using in SPL.
>
> Any comments?
Make sense.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 01/10] misc: add driver for the Sifive otp controller
2020-01-24 6:41 ` Jagan Teki
@ 2020-01-27 10:18 ` Pragnesh Patel
2020-02-10 12:44 ` Pragnesh Patel
0 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-27 10:18 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 24 January 2020 12:12
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
>Kadam <sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Simon
>Glass <sjg@chromium.org>; Heiko Stuebner <heiko.stuebner@theobroma-
>systems.com>; Michal Simek <michal.simek@xilinx.com>; Marcel Ziswiler
><marcel.ziswiler@toradex.com>; Finley Xiao <finley.xiao@rock-chips.com>;
>Peng Fan <peng.fan@nxp.com>; Tero Kristo <t-kristo@ti.com>; Eugen Hristev
><eugen.hristev@microchip.com>
>Subject: Re: [PATCH v3 01/10] misc: add driver for the Sifive otp controller
>
>On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> Added a misc driver to handle OTP memory in FU540.
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> Reviewed-by: Anup Patel <anup.patel@wdc.com>
>> ---
>> arch/riscv/dts/fu540-c000-u-boot.dtsi | 13 ++
>> .../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
>> board/sifive/fu540/fu540.c | 113 ++++------
>> configs/sifive_fu540_defconfig | 2 +
>> drivers/misc/Kconfig | 7 +
>> drivers/misc/Makefile | 1 +
>> drivers/misc/ememory-otp.c | 207 ++++++++++++++++++
>
>This patch need to break into
>1. add sifive otp driver
>2. enable the otp driver - board, dts, defconfig changes.
Will split in v4.
>
>> 7 files changed, 276 insertions(+), 73 deletions(-) create mode
>> 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
>> create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> create mode 100644 drivers/misc/ememory-otp.c
>>
>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..615a68c0e9
>> --- /dev/null
>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * (C) Copyright 2019 SiFive, Inc
>> + */
>> +
>> +/ {
>> + soc {
>> + otp: otp at 10070000 {
>> + compatible = "sifive,fu540-otp";
>> + reg = <0x0 0x10070000 0x0 0x0FFF>;
>> + };
>> + };
>> +};
>> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..bec0d19134
>> --- /dev/null
>> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> @@ -0,0 +1,6 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc
>> + */
>> +
>> +#include "fu540-c000-u-boot.dtsi"
>> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
>> index 47a2090251..3a5e74f1fb 100644
>> --- a/board/sifive/fu540/fu540.c
>> +++ b/board/sifive/fu540/fu540.c
>> @@ -10,94 +10,61 @@
>> #include <dm.h>
>> #include <linux/delay.h>
>> #include <linux/io.h>
>> +#include <misc.h>
>>
>> -#ifdef CONFIG_MISC_INIT_R
>> -
>> -#define FU540_OTP_BASE_ADDR 0x10070000
>> -
>> -struct fu540_otp_regs {
>> - u32 pa; /* Address input */
>> - u32 paio; /* Program address input */
>> - u32 pas; /* Program redundancy cell selection input */
>> - u32 pce; /* OTP Macro enable input */
>> - u32 pclk; /* Clock input */
>> - u32 pdin; /* Write data input */
>> - u32 pdout; /* Read data output */
>> - u32 pdstb; /* Deep standby mode enable input (active low) */
>> - u32 pprog; /* Program mode enable input */
>> - u32 ptc; /* Test column enable input */
>> - u32 ptm; /* Test mode enable input */
>> - u32 ptm_rep;/* Repair function test mode enable input */
>> - u32 ptr; /* Test row enable input */
>> - u32 ptrim; /* Repair function enable input */
>> - u32 pwe; /* Write enable input (defines program cycle) */
>> -} __packed;
>> -
>> -#define BYTES_PER_FUSE 4
>> -#define NUM_FUSES 0x1000
>> -
>> -static int fu540_otp_read(int offset, void *buf, int size) -{
>> - struct fu540_otp_regs *regs = (void __iomem
>*)FU540_OTP_BASE_ADDR;
>> - unsigned int i;
>> - int fuseidx = offset / BYTES_PER_FUSE;
>> - int fusecount = size / BYTES_PER_FUSE;
>> - u32 fusebuf[fusecount];
>> -
>> - /* check bounds */
>> - if (offset < 0 || size < 0)
>> - return -EINVAL;
>> - if (fuseidx >= NUM_FUSES)
>> - return -EINVAL;
>> - if ((fuseidx + fusecount) > NUM_FUSES)
>> - return -EINVAL;
>> -
>> - /* init OTP */
>> - writel(0x01, ®s->pdstb); /* wake up from stand-by */
>> - writel(0x01, ®s->ptrim); /* enable repair function */
>> - writel(0x01, ®s->pce); /* enable input */
>> -
>> - /* read all requested fuses */
>> - for (i = 0; i < fusecount; i++, fuseidx++) {
>> - writel(fuseidx, ®s->pa);
>> -
>> - /* cycle clock to read */
>> - writel(0x01, ®s->pclk);
>> - mdelay(1);
>> - writel(0x00, ®s->pclk);
>> - mdelay(1);
>> -
>> - /* read the value */
>> - fusebuf[i] = readl(®s->pdout);
>> - }
>> -
>> - /* shut down */
>> - writel(0, ®s->pce);
>> - writel(0, ®s->ptrim);
>> - writel(0, ®s->pdstb);
>> -
>> - /* copy out */
>> - memcpy(buf, fusebuf, size);
>> +/*
>> + * This define is a value used for error/unknown serial.
>> + * If we really care about distinguishing errors and 0 is
>> + * valid, we'll need a different one.
>> + */
>> +#define ERROR_READING_SERIAL_NUMBER 0
>>
>> - return 0;
>> -}
>> +#ifdef CONFIG_MISC_INIT_R
>>
>> -static u32 fu540_read_serialnum(void)
>> +#if CONFIG_IS_ENABLED(EMEMORY_OTP)
>> +static u32 otp_read_serialnum(struct udevice *dev)
>> {
>> int ret;
>> u32 serial[2] = {0};
>>
>> for (int i = 0xfe * 4; i > 0; i -= 8) {
>> - ret = fu540_otp_read(i, serial, sizeof(serial));
>> + ret = misc_read(dev, i, serial, sizeof(serial));
>> +
>> if (ret) {
>> - printf("%s: error reading from OTP\n", __func__);
>> + printf("%s: error reading serial from OTP\n",
>> + __func__);
>> break;
>> }
>> +
>> if (serial[0] == ~serial[1])
>> return serial[0];
>> }
>>
>> - return 0;
>> + return ERROR_READING_SERIAL_NUMBER; } #endif
>> +
>> +static u32 fu540_read_serialnum(void) {
>> + u32 serial = ERROR_READING_SERIAL_NUMBER;
>> +
>> +#if CONFIG_IS_ENABLED(EMEMORY_OTP)
>> + struct udevice *dev;
>> + int ret;
>> +
>> + // init OTP
>> + ret = uclass_get_device_by_driver(UCLASS_MISC,
>> + DM_GET_DRIVER(hifive_otp),
>> + &dev);
>> +
>> + if (ret) {
>> + debug("%s: could not find otp device\n", __func__);
>> + return serial;
>> + }
>> +
>> + // read serial from OTP and set env var
>> + serial = otp_read_serialnum(dev); #endif
>> +
>> + return serial;
>> }
>>
>> static void fu540_setup_macaddr(u32 serialnum) diff --git
>> a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
>> index 6d61e6c960..40e78f12a2 100644
>> --- a/configs/sifive_fu540_defconfig
>> +++ b/configs/sifive_fu540_defconfig
>> @@ -6,6 +6,8 @@ CONFIG_ARCH_RV64I=y
>> CONFIG_RISCV_SMODE=y
>> CONFIG_DISTRO_DEFAULTS=y
>> CONFIG_FIT=y
>> +CONFIG_MISC=y
>> +CONFIG_EMEMORY_OTP=y
>
>Look like this opt is needed global to SiFive, If so select MISC in arch Kconfig.
Will update the "board/Sifive/fu540/Kconfig" in v4.
>
>> CONFIG_MISC_INIT_R=y
>> CONFIG_DISPLAY_CPUINFO=y
>> CONFIG_DISPLAY_BOARDINFO=y
>> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
>> f18aa8f7ba..cbda0deb14 100644
>> --- a/drivers/misc/Kconfig
>> +++ b/drivers/misc/Kconfig
>> @@ -68,6 +68,13 @@ config ROCKCHIP_OTP
>> addressing and a length or through child-nodes that are generated
>> based on the e-fuse map retrieved from the DTS.
>>
>> +config EMEMORY_OTP
>
>What about SIFIVE_OTP or SIFIVE_EMEM_OTP or similar?
Will change it to SIFIVE_OTP in v4.
>
>> + bool "Sifive Ememory OTP driver"
>> + depends on RISCV && MISC
>> + help
>> + Enable support for reading the Ememory OTP on the HiFive Unleashed
>> + OTP storage.
>> +
>> config VEXPRESS_CONFIG
>> bool "Enable support for Arm Versatile Express config bus"
>> depends on MISC
>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
>> 2b843de93c..dcf9b628c8 100644
>> --- a/drivers/misc/Makefile
>> +++ b/drivers/misc/Makefile
>> @@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
>> obj-$(CONFIG_QFW) += qfw.o
>> obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
>> obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
>> +obj-$(CONFIG_EMEMORY_OTP) += ememory-otp.o
>> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
>> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
>> obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o diff --git
>> a/drivers/misc/ememory-otp.c b/drivers/misc/ememory-otp.c new file
>> mode 100644 index 0000000000..73e7af496a
>> --- /dev/null
>> +++ b/drivers/misc/ememory-otp.c
>
>Again file name, would have platform or soc naming convention.
Agreed, will change in v4. Thanks for pointing me.
>
>> @@ -0,0 +1,207 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
>> + * One-Time-Programmable (OTP) memory used within the SiFive FU540.
>> + * It is documented in the FU540 manual here:
>> + *
>> +https://www.sifive.com/documentation/chips/freedom-u540-c000-
>manual/
>> + *
>> + * Copyright (C) 2018 Philipp Hug <philipp@hug.cx>
>> + * Copyright (C) 2018 Joey Hewitt <joey@joeyhewitt.com>
>> + *
>> + * Copyright (C) 2020 SiFive, Inc
>> + */
>> +
>> +/*
>> + * The FU540 stores 4096x32 bit (16KiB) values.
>> + * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
>> +*/
>
>Sorry, I didn't understand this comments. If it is memory map detail that
>occupy otp, try to elaborate more by giving full details. Would helpful to
>understand anyone in future.
Right now, OTP is used only for serial number. First 1 KB is reserved for Sifive
Internal use, serial number is one of them.
>
>> +
>> +#include <common.h>
>> +#include <dm/device.h>
>> +#include <dm/read.h>
>> +#include <linux/io.h>
>> +#include <misc.h>
>> +
>> +struct hifive_otp_regs {
>> + u32 pa; /* Address input */
>> + u32 paio; /* Program address input */
>> + u32 pas; /* Program redundancy cell selection input */
>> + u32 pce; /* OTP Macro enable input */
>> + u32 pclk; /* Clock input */
>> + u32 pdin; /* Write data input */
>> + u32 pdout; /* Read data output */
>> + u32 pdstb; /* Deep standby mode enable input (active low) */
>> + u32 pprog; /* Program mode enable input */
>> + u32 ptc; /* Test column enable input */
>> + u32 ptm; /* Test mode enable input */
>> + u32 ptm_rep;/* Repair function test mode enable input */
>> + u32 ptr; /* Test row enable input */
>> + u32 ptrim; /* Repair function enable input */
>> + u32 pwe; /* Write enable input (defines program cycle) */
>> +} __packed;
>> +
>> +struct hifive_otp_platdata {
>
>hifive here represent the board name, butter use soc name that has this otp.
Will update in v4.
>
>> + struct hifive_otp_regs __iomem *regs; };
>> +
>> +typedef u32 fuse_value_t;
>
>No typdef please.
>No global variables(unless it really need)
Will update in v4, thanks.
>
>> +#define BYTES_PER_FUSE 4
>> +
>> +#define NUM_FUSES 0x1000
>
>May be use dt properties.
Will check this.
>
>> +
>> +/*
>> + * offset and size are assumed aligned to the size of the fuses (32bit).
>> + */
>> +static int hifive_otp_read(struct udevice *dev, int offset,
>> + void *buf, int size) {
>> + struct hifive_otp_platdata *plat = dev_get_platdata(dev);
>> + struct hifive_otp_regs *regs = (struct hifive_otp_regs
>> +*)plat->regs;
>> +
>> + int fuseidx = offset / BYTES_PER_FUSE;
>> + int fusecount = size / BYTES_PER_FUSE;
>> + fuse_value_t fusebuf[fusecount];
>> +
>> + // check bounds
>
>use proper comment style.
Will update in v4.
>
>> + if (offset < 0 || size < 0)
>> + return -EINVAL;
>> + if (fuseidx >= NUM_FUSES)
>> + return -EINVAL;
>> + if ((fuseidx + fusecount) > NUM_FUSES)
>> + return -EINVAL;
>> +
>> + // init OTP
>> + iowrite32(0x01, ®s->pdstb); // wake up from stand-by
>> + iowrite32(0x01, ®s->ptrim); // enable repair function
>> + iowrite32(0x01, ®s->pce); // enable input
>
>use macros with proper bit names, like 0x01 would have proper macro.
Will update in v4.
>
>> +
>> + // read all requested fuses
>> + for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
>> + iowrite32(fuseidx, ®s->pa);
>> +
>> + // cycle clock to read
>> + iowrite32(0x01, ®s->pclk);
>> + mdelay(1);
>> + iowrite32(0x00, ®s->pclk);
>> + mdelay(1);
>> +
>> + // read the value
>> + fusebuf[i] = ioread32(®s->pdout);
>> + }
>> +
>> + // shut down
>> + iowrite32(0, ®s->pce);
>> + iowrite32(0, ®s->ptrim);
>> + iowrite32(0, ®s->pdstb);
>> +
>> + // copy out
>> + memcpy(buf, fusebuf, size);
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Caution:
>> + * OTP can be write only once, so use carefully.
>
>can be written
Thanks, will update in v4.
>
>> + *
>> + * offset and size are assumed aligned to the size of the fuses (32bit).
>> + */
>> +static int hifive_otp_write(struct udevice *dev, int offset,
>> + const void *buf, int size) {
>> + struct hifive_otp_platdata *plat = dev_get_platdata(dev);
>> + struct hifive_otp_regs *regs = (struct hifive_otp_regs
>> +*)plat->regs;
>> +
>> + int fuseidx = offset / BYTES_PER_FUSE;
>> + int fusecount = size / BYTES_PER_FUSE;
>> + u32 *write_buf = (u32 *)buf;
>> + u32 write_data;
>> + int i, pas, bit;
>> +
>> + // check bounds
>> + if (offset < 0 || size < 0)
>> + return -EINVAL;
>> + if (fuseidx >= NUM_FUSES)
>> + return -EINVAL;
>> + if ((fuseidx + fusecount) > NUM_FUSES)
>> + return -EINVAL;
>
>We have lib functions to do this bound, would you please try to use that.
Will check and update in v4, thanks for the review.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
2020-01-27 7:49 ` Pragnesh Patel
@ 2020-01-27 12:45 ` Anup Patel
0 siblings, 0 replies; 32+ messages in thread
From: Anup Patel @ 2020-01-27 12:45 UTC (permalink / raw)
To: u-boot
On Mon, Jan 27, 2020 at 1:19 PM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
>
> >-----Original Message-----
> >From: Anup Patel <anup@brainfault.org>
> >Sent: 25 January 2020 14:12
> >To: Jagan Teki <jagan@amarulasolutions.com>
> >Cc: Pragnesh Patel <pragnesh.patel@sifive.com>; Atish Patra
> ><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; U-
> >Boot-Denx <u-boot@lists.denx.de>
> >Subject: Re: [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
> >
> >On Fri, Jan 24, 2020 at 12:21 PM Jagan Teki <jagan@amarulasolutions.com>
> >wrote:
> >>
> >> On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
> >> <pragnesh.patel@sifive.com> wrote:
> >> >
> >> > With sifive_fu540_spl_defconfig:
> >> >
> >> > U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin
> >> > with
> >> > u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
> >> > image u-boot.itb from 1st partition of SD card (replace
> >> > fw_payload.bin with u-boot.itb) into RAM.
> >> >
> >> > U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD
> >> > card irrespective of GUID
> >> >
> >> > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> >> > ---
> >>
> >> I'm thinking we don't need any separate config for SPL. Say if we have
> >> single config that creates both SPL and U-Boot proper and give
> >> feasibility to the user to use
> >> 1) SPL + U-Boot proper
> >> 2) SiFive SPL + U-Boot proper
> >>
> >> We are using a similar approach for other platforms, I guess the same
> >> will valid here, any comments?
> >
> >I agree with Jagan.
> >
> >We can augment all required SPL related config options directly in
> >sifive_fu540_defconfig but we have to ensure that u-boot.bin created with
> >updated sifive_fu540_defconfig works fine with OpenSBI FW_PAYLOAD.
>
> If SPL related configs will be included in sifive_fu540_defconfig then the generated
> u-boot.bin works fine with OpenSBI FW_PAYLOAD.
>
> There are 2 cases:
> 1) Without U-boot SPL -
> FSBL + OpenSBI fw_payload + U-boot proper works.
>
> 2) With U-boot SPL -
> SPL + FW_DYNAMIC + U-boot proper works.
>
> Will include SPL related configs in sifive_fu540_defconfig in v4.
> Any comments?
You will have to update your last documentation patch accordingly.
Regards,
Anup
>
> >
> >Regards,
> >Anup
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info
2020-01-27 7:51 ` Jagan Teki
@ 2020-01-28 6:41 ` Pragnesh Patel
2020-02-04 15:19 ` Bin Meng
0 siblings, 1 reply; 32+ messages in thread
From: Pragnesh Patel @ 2020-01-28 6:41 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 27 January 2020 13:22
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
>Kadam <sagar.kadam@sifive.com>
>Subject: Re: [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info
>
>On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
><pragnesh.patel@sifive.com> wrote:
>>
>> Add ddr4 controller and phy related files
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> ---
>> board/sifive/fu540/Makefile | 4 +
>> board/sifive/fu540/ddr.c | 868 ++++++++++++++++++++
>> board/sifive/fu540/regconfig-ctl.h | 270 ++++++
>> board/sifive/fu540/regconfig-phy.h | 1220
>++++++++++++++++++++++++++++
>> board/sifive/fu540/ux00ddr.h | 45 +
>> 5 files changed, 2407 insertions(+)
>> create mode 100644 board/sifive/fu540/ddr.c
>> create mode 100644 board/sifive/fu540/regconfig-ctl.h
>> create mode 100644 board/sifive/fu540/regconfig-phy.h
>> create mode 100644 board/sifive/fu540/ux00ddr.h
>>
>> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
>> index 6e1862c475..e4e76e1de3 100644
>> --- a/board/sifive/fu540/Makefile
>> +++ b/board/sifive/fu540/Makefile
>> @@ -3,3 +3,7 @@
>> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>>
>> obj-y += fu540.o
>> +
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y += ddr.o
>> +endif
>> diff --git a/board/sifive/fu540/ddr.c b/board/sifive/fu540/ddr.c
>> new file mode 100644
>> index 0000000000..a4a86b1173
>> --- /dev/null
>> +++ b/board/sifive/fu540/ddr.c
>> @@ -0,0 +1,868 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + */
>> +
>> +#include <common.h>
>> +
>> +#include "regconfig-ctl.h"
>> +#include "regconfig-phy.h"
>> +
>> +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
>> +
>> +#define DRAM_CLASS_OFFSET 8
>> +#define OPTIMAL_RMODW_EN_OFFSET 0
>> +#define DISABLE_RD_INTERLEAVE_OFFSET 16
>> +#define OUT_OF_RANGE_OFFSET 1
>> +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
>> +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
>> +#define MC_INIT_COMPLETE_OFFSET 8
>> +#define LEVELING_OPERATION_COMPLETED_OFFSET 22
>> +#define DFI_PHY_WRLELV_MODE_OFFSET 24
>> +#define DFI_PHY_RDLVL_MODE_OFFSET 24
>> +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
>> +#define VREF_EN_OFFSET 24
>> +#define PORT_ADDR_PROTECTION_EN_OFFSET 0
>> +#define AXI0_ADDRESS_RANGE_ENABLE 8
>> +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
>> +#define RDLVL_EN_OFFSET 16
>> +#define RDLVL_GATE_EN_OFFSET 24
>> +#define WRLVL_EN_OFFSET 0
>> +
>> +#define PHY_RX_CAL_DQ0_0_OFFSET 0
>> +#define PHY_RX_CAL_DQ1_0_OFFSET 16
>> +
>> +static void phy_reset(u32 *ddrphyreg, const
>> + u32 *physettings)
>> +{
>> + unsigned int i;
>> +
>> + for (i = 1152; i <= 1214; i++) {
>> + u32 physet = physettings[i];
>> + /*if (physet!=0)*/ ddrphyreg[i] = physet;
>> + }
>> +
>> + for (i = 0; i <= 1151; i++) {
>> + u32 physet = physettings[i];
>> + /*if (physet!=0)*/ ddrphyreg[i] = physet;
>> + }
>> +}
>> +
>> +void ux00ddr_writeregmap(size_t ahbregaddr, const
>> + u32 *ctlsettings, const u32 *physettings)
>> +{
>> + u32 *ddrctlreg = (u32 *)ahbregaddr;
>> + u32 *ddrphyreg = ((u32 *)ahbregaddr) +
>> + (0x2000 / sizeof(u32));
>> +
>> + unsigned int i;
>> +
>> + for (i = 0; i <= 264; i++) {
>> + u32 ctlset = ctlsettings[i];
>> + /*if (ctlset!=0)*/ ddrctlreg[i] = ctlset;
>> + }
>> +
>> + phy_reset(ddrphyreg, physettings);
>> +}
>> +
>> +void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend)
>> +{
>> + // START register at ddrctl register base offset 0
>> + u32 regdata = _REG32(0 << 2, ahbregaddr);
>> +
>> + regdata |= 0x1;
>> + _REG32(0 << 2, ahbregaddr) = regdata;
>> +
>> + /*
>> + * WAIT for initialization complete : bit 8 of INT_STATUS
>> + * (DENALI_CTL_132) 0x210
>> + */
>> + while ((_REG32(132 << 2, ahbregaddr) & (1 <<
>> + MC_INIT_COMPLETE_OFFSET)) == 0) {
>> + }
>> +
>> + // Disable the BusBlocker in front of the controller AXI slave ports
>> + u64 *filterreg = (u64 *)filteraddr;
>> +
>> + filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
>> +}
>> +
>> +void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr)
>> +{
>> + /*
>> + * Mask off Bit 8 of Interrupt Status
>> + * Bit [8] The MC initialization has been completed
>> + */
>> +
>> + _REG32(136 << 2, ahbregaddr) |= (1 << MC_INIT_COMPLETE_OFFSET);
>> +}
>> +
>> +void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr)
>> +{
>> + /*
>> + * Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status
>> + * Bit [2] Multiple accesses outside the defined PHYSICAL memory
>> + * space have occurred
>> + * Bit [1] A memory access outside the defined PHYSICAL memory
>> + * space has occurred
>> + */
>> +
>> + _REG32(136 << 2, ahbregaddr) |= ((1 << OUT_OF_RANGE_OFFSET) | (1
><<
>> + MULTIPLE_OUT_OF_RANGE_OFFSET));
>> +}
>> +
>> +void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr)
>> +{
>> + /*
>> + * Mask off Bit 7 of Interrupt Status
>> + * Bit [7] An error occurred on the port command channel
>> + */
>> +
>> + _REG32(136 << 2, ahbregaddr) |= (1 <<
>> + PORT_COMMAND_CHANNEL_ERROR_OFFSET);
>> +}
>> +
>> +void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr)
>> +{
>> + /*
>> + * Mask off Bit 22 of Interrupt Status
>> + * Bit [22] The leveling operation has completed
>> + */
>> +
>> + _REG32(136 << 2, ahbregaddr) |= (1 <<
>> + LEVELING_OPERATION_COMPLETED_OFFSET);
>> +}
>> +
>> +void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr)
>> +{
>> + _REG32(209 << 2, ahbregaddr) = 0x0;
>> + size_t end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
>> +
>> + _REG32(210 << 2, ahbregaddr) = ((u32)end_addr_16kblocks);
>> + _REG32(212 << 2, ahbregaddr) = 0x0;
>> + _REG32(214 << 2, ahbregaddr) = 0x0;
>> + _REG32(216 << 2, ahbregaddr) = 0x0;
>> + _REG32(224 << 2, ahbregaddr) |= (0x3 <<
>AXI0_RANGE_PROT_BITS_0_OFFSET);
>> + _REG32(225 << 2, ahbregaddr) = 0xFFFFFFFF;
>> + _REG32(208 << 2, ahbregaddr) |= (1 <<
>AXI0_ADDRESS_RANGE_ENABLE);
>> + _REG32(208 << 2, ahbregaddr) |= (1 <<
>PORT_ADDR_PROTECTION_EN_OFFSET);
>> +}
>> +
>> +void ux00ddr_disableaxireadinterleave(size_t ahbregaddr)
>> +{
>> + _REG32(120 << 2, ahbregaddr) |= (1 <<
>DISABLE_RD_INTERLEAVE_OFFSET);
>> +}
>> +
>> +void ux00ddr_disableoptimalrmodw(size_t ahbregaddr)
>> +{
>> + _REG32(21 << 2, ahbregaddr) &= (~(1 <<
>OPTIMAL_RMODW_EN_OFFSET));
>> +}
>> +
>> +void ux00ddr_enablewriteleveling(size_t ahbregaddr)
>> +{
>> + _REG32(170 << 2, ahbregaddr) |= ((1 << WRLVL_EN_OFFSET) | (1 <<
>> + DFI_PHY_WRLELV_MODE_OFFSET));
>> +}
>> +
>> +void ux00ddr_enablereadleveling(size_t ahbregaddr)
>> +{
>> + _REG32(181 << 2, ahbregaddr) |= (1 <<
>DFI_PHY_RDLVL_MODE_OFFSET);
>> + _REG32(260 << 2, ahbregaddr) |= (1 << RDLVL_EN_OFFSET);
>> +}
>> +
>> +void ux00ddr_enablereadlevelinggate(size_t ahbregaddr)
>> +{
>> + _REG32(260 << 2, ahbregaddr) |= (1 << RDLVL_GATE_EN_OFFSET);
>> + _REG32(182 << 2, ahbregaddr) |= (1 <<
>DFI_PHY_RDLVL_GATE_MODE_OFFSET);
>> +}
>> +
>> +void ux00ddr_enablevreftraining(size_t ahbregaddr)
>> +{
>> + _REG32(184 << 2, ahbregaddr) |= (1 << VREF_EN_OFFSET);
>> +}
>> +
>> +u32 ux00ddr_getdramclass(size_t ahbregaddr)
>> +{
>> + return((_REG32(0, ahbregaddr) >> DRAM_CLASS_OFFSET) & 0xF);
>> +}
>> +
>> +u64 ux00ddr_phy_fixup(size_t ahbregaddr)
>> +{
>> + // return bitmask of failed lanes
>> +
>> + size_t ddrphyreg = ahbregaddr + 0x2000;
>> +
>> + u64 fails = 0;
>> + u32 slicebase = 0;
>> + u32 dq = 0;
>> +
>> + // check errata condition
>> + for (u32 slice = 0; slice < 8; slice++) {
>> + u32 regbase = slicebase + 34;
>> +
>> + for (u32 reg = 0; reg < 4; reg++) {
>> + u32 updownreg = _REG32((regbase + reg) << 2,
>> + ddrphyreg);
>> +
>> + for (u32 bit = 0; bit < 2; bit++) {
>> + u32 phy_rx_cal_dqn_0_offset;
>> +
>> + if (bit == 0) {
>> + phy_rx_cal_dqn_0_offset =
>> + PHY_RX_CAL_DQ0_0_OFFSET;
>> + } else {
>> + phy_rx_cal_dqn_0_offset =
>> + PHY_RX_CAL_DQ1_0_OFFSET;
>> + }
>> +
>> + u32 down = (updownreg >>
>> + phy_rx_cal_dqn_0_offset) & 0x3F;
>> + u32 up = (updownreg >>
>> + (phy_rx_cal_dqn_0_offset + 6)) &
>> + 0x3F;
>> +
>> + u8 failc0 = ((down == 0) && (up == 0x3F));
>> + u8 failc1 = ((up == 0) && (down == 0x3F));
>> +
>> + // print error message on failure
>> + if (failc0 || failc1) {
>> + if (fails == 0)
>> + printf("DDR error in fixing up\n");
>> +
>> + fails |= (1 << dq);
>> +
>> + char slicelsc = '0';
>> + char slicemsc = '0';
>> +
>> + slicelsc += (dq % 10);
>> + slicemsc += (dq / 10);
>> + printf("S ");
>> + printf("%c", slicemsc);
>> + printf("%c", slicelsc);
>> +
>> + if (failc0)
>> + printf("U");
>> + else
>> + printf("D");
>> +
>> + printf("\n");
>> + }
>> + dq++;
>> + }
>> + }
>> + slicebase += 128;
>> + }
>> + return(0);
>> +}
>> +
>> +u32 ddr_phy_settings[1215] = {
>> + DENALI_PHY_00_DATA, DENALI_PHY_01_DATA,
>DENALI_PHY_02_DATA,
>> + DENALI_PHY_03_DATA, DENALI_PHY_04_DATA,
>DENALI_PHY_05_DATA,
>> + DENALI_PHY_06_DATA, DENALI_PHY_07_DATA,
>DENALI_PHY_08_DATA,
>> + DENALI_PHY_09_DATA,
>> + DENALI_PHY_10_DATA, DENALI_PHY_11_DATA,
>DENALI_PHY_12_DATA,
>> + DENALI_PHY_13_DATA, DENALI_PHY_14_DATA,
>DENALI_PHY_15_DATA,
>> + DENALI_PHY_16_DATA, DENALI_PHY_17_DATA,
>DENALI_PHY_18_DATA,
>> + DENALI_PHY_19_DATA,
>> + DENALI_PHY_20_DATA, DENALI_PHY_21_DATA,
>DENALI_PHY_22_DATA,
>> + DENALI_PHY_23_DATA, DENALI_PHY_24_DATA,
>DENALI_PHY_25_DATA,
>> + DENALI_PHY_26_DATA, DENALI_PHY_27_DATA,
>DENALI_PHY_28_DATA,
>> + DENALI_PHY_29_DATA,
>> + DENALI_PHY_30_DATA, DENALI_PHY_31_DATA,
>DENALI_PHY_32_DATA,
>> + DENALI_PHY_33_DATA, DENALI_PHY_34_DATA,
>DENALI_PHY_35_DATA,
>> + DENALI_PHY_36_DATA, DENALI_PHY_37_DATA,
>DENALI_PHY_38_DATA,
>> + DENALI_PHY_39_DATA,
>> + DENALI_PHY_40_DATA, DENALI_PHY_41_DATA,
>DENALI_PHY_42_DATA,
>> + DENALI_PHY_43_DATA, DENALI_PHY_44_DATA,
>DENALI_PHY_45_DATA,
>> + DENALI_PHY_46_DATA, DENALI_PHY_47_DATA,
>DENALI_PHY_48_DATA,
>> + DENALI_PHY_49_DATA,
>> + DENALI_PHY_50_DATA, DENALI_PHY_51_DATA,
>DENALI_PHY_52_DATA,
>> + DENALI_PHY_53_DATA, DENALI_PHY_54_DATA,
>DENALI_PHY_55_DATA,
>> + DENALI_PHY_56_DATA, DENALI_PHY_57_DATA,
>DENALI_PHY_58_DATA,
>> + DENALI_PHY_59_DATA,
>> + DENALI_PHY_60_DATA, DENALI_PHY_61_DATA,
>DENALI_PHY_62_DATA,
>> + DENALI_PHY_63_DATA, DENALI_PHY_64_DATA,
>DENALI_PHY_65_DATA,
>> + DENALI_PHY_66_DATA, DENALI_PHY_67_DATA,
>DENALI_PHY_68_DATA,
>> + DENALI_PHY_69_DATA,
>> + DENALI_PHY_70_DATA, DENALI_PHY_71_DATA,
>DENALI_PHY_72_DATA,
>> + DENALI_PHY_73_DATA, DENALI_PHY_74_DATA,
>DENALI_PHY_75_DATA,
>> + DENALI_PHY_76_DATA, DENALI_PHY_77_DATA,
>DENALI_PHY_78_DATA,
>> + DENALI_PHY_79_DATA,
>> + DENALI_PHY_80_DATA, DENALI_PHY_81_DATA,
>DENALI_PHY_82_DATA,
>> + DENALI_PHY_83_DATA, DENALI_PHY_84_DATA,
>DENALI_PHY_85_DATA,
>> + DENALI_PHY_86_DATA, DENALI_PHY_87_DATA,
>DENALI_PHY_88_DATA,
>> + DENALI_PHY_89_DATA,
>> + DENALI_PHY_90_DATA, DENALI_PHY_91_DATA,
>DENALI_PHY_92_DATA,
>> + DENALI_PHY_93_DATA, DENALI_PHY_94_DATA,
>DENALI_PHY_95_DATA,
>> + DENALI_PHY_96_DATA, DENALI_PHY_97_DATA,
>DENALI_PHY_98_DATA,
>> + DENALI_PHY_99_DATA,
>> +
>> + DENALI_PHY_100_DATA, DENALI_PHY_101_DATA,
>DENALI_PHY_102_DATA,
>> + DENALI_PHY_103_DATA, DENALI_PHY_104_DATA,
>DENALI_PHY_105_DATA,
>> + DENALI_PHY_106_DATA, DENALI_PHY_107_DATA,
>DENALI_PHY_108_DATA,
>> + DENALI_PHY_109_DATA,
>> + DENALI_PHY_110_DATA, DENALI_PHY_111_DATA,
>DENALI_PHY_112_DATA,
>> + DENALI_PHY_113_DATA, DENALI_PHY_114_DATA,
>DENALI_PHY_115_DATA,
>> + DENALI_PHY_116_DATA, DENALI_PHY_117_DATA,
>DENALI_PHY_118_DATA,
>> + DENALI_PHY_119_DATA,
>> + DENALI_PHY_120_DATA, DENALI_PHY_121_DATA,
>DENALI_PHY_122_DATA,
>> + DENALI_PHY_123_DATA, DENALI_PHY_124_DATA,
>DENALI_PHY_125_DATA,
>> + DENALI_PHY_126_DATA, DENALI_PHY_127_DATA,
>DENALI_PHY_128_DATA,
>> + DENALI_PHY_129_DATA,
>> + DENALI_PHY_130_DATA, DENALI_PHY_131_DATA,
>DENALI_PHY_132_DATA,
>> + DENALI_PHY_133_DATA, DENALI_PHY_134_DATA,
>DENALI_PHY_135_DATA,
>> + DENALI_PHY_136_DATA, DENALI_PHY_137_DATA,
>DENALI_PHY_138_DATA,
>> + DENALI_PHY_139_DATA,
>> + DENALI_PHY_140_DATA, DENALI_PHY_141_DATA,
>DENALI_PHY_142_DATA,
>> + DENALI_PHY_143_DATA, DENALI_PHY_144_DATA,
>DENALI_PHY_145_DATA,
>> + DENALI_PHY_146_DATA, DENALI_PHY_147_DATA,
>DENALI_PHY_148_DATA,
>> + DENALI_PHY_149_DATA,
>> + DENALI_PHY_150_DATA, DENALI_PHY_151_DATA,
>DENALI_PHY_152_DATA,
>> + DENALI_PHY_153_DATA, DENALI_PHY_154_DATA,
>DENALI_PHY_155_DATA,
>> + DENALI_PHY_156_DATA, DENALI_PHY_157_DATA,
>DENALI_PHY_158_DATA,
>> + DENALI_PHY_159_DATA,
>> + DENALI_PHY_160_DATA, DENALI_PHY_161_DATA,
>DENALI_PHY_162_DATA,
>> + DENALI_PHY_163_DATA, DENALI_PHY_164_DATA,
>DENALI_PHY_165_DATA,
>> + DENALI_PHY_166_DATA, DENALI_PHY_167_DATA,
>DENALI_PHY_168_DATA,
>> + DENALI_PHY_169_DATA,
>> + DENALI_PHY_170_DATA, DENALI_PHY_171_DATA,
>DENALI_PHY_172_DATA,
>> + DENALI_PHY_173_DATA, DENALI_PHY_174_DATA,
>DENALI_PHY_175_DATA,
>> + DENALI_PHY_176_DATA, DENALI_PHY_177_DATA,
>DENALI_PHY_178_DATA,
>> + DENALI_PHY_179_DATA,
>> + DENALI_PHY_180_DATA, DENALI_PHY_181_DATA,
>DENALI_PHY_182_DATA,
>> + DENALI_PHY_183_DATA, DENALI_PHY_184_DATA,
>DENALI_PHY_185_DATA,
>> + DENALI_PHY_186_DATA, DENALI_PHY_187_DATA,
>DENALI_PHY_188_DATA,
>> + DENALI_PHY_189_DATA,
>> + DENALI_PHY_190_DATA, DENALI_PHY_191_DATA,
>DENALI_PHY_192_DATA,
>> + DENALI_PHY_193_DATA, DENALI_PHY_194_DATA,
>DENALI_PHY_195_DATA,
>> + DENALI_PHY_196_DATA, DENALI_PHY_197_DATA,
>DENALI_PHY_198_DATA,
>> + DENALI_PHY_199_DATA,
>> +
>> + DENALI_PHY_200_DATA, DENALI_PHY_201_DATA,
>DENALI_PHY_202_DATA,
>> + DENALI_PHY_203_DATA, DENALI_PHY_204_DATA,
>DENALI_PHY_205_DATA,
>> + DENALI_PHY_206_DATA, DENALI_PHY_207_DATA,
>DENALI_PHY_208_DATA,
>> + DENALI_PHY_209_DATA,
>> + DENALI_PHY_210_DATA, DENALI_PHY_211_DATA,
>DENALI_PHY_212_DATA,
>> + DENALI_PHY_213_DATA, DENALI_PHY_214_DATA,
>DENALI_PHY_215_DATA,
>> + DENALI_PHY_216_DATA, DENALI_PHY_217_DATA,
>DENALI_PHY_218_DATA,
>> + DENALI_PHY_219_DATA,
>> + DENALI_PHY_220_DATA, DENALI_PHY_221_DATA,
>DENALI_PHY_222_DATA,
>> + DENALI_PHY_223_DATA, DENALI_PHY_224_DATA,
>DENALI_PHY_225_DATA,
>> + DENALI_PHY_226_DATA, DENALI_PHY_227_DATA,
>DENALI_PHY_228_DATA,
>> + DENALI_PHY_229_DATA,
>> + DENALI_PHY_230_DATA, DENALI_PHY_231_DATA,
>DENALI_PHY_232_DATA,
>> + DENALI_PHY_233_DATA, DENALI_PHY_234_DATA,
>DENALI_PHY_235_DATA,
>> + DENALI_PHY_236_DATA, DENALI_PHY_237_DATA,
>DENALI_PHY_238_DATA,
>> + DENALI_PHY_239_DATA,
>> + DENALI_PHY_240_DATA, DENALI_PHY_241_DATA,
>DENALI_PHY_242_DATA,
>> + DENALI_PHY_243_DATA, DENALI_PHY_244_DATA,
>DENALI_PHY_245_DATA,
>> + DENALI_PHY_246_DATA, DENALI_PHY_247_DATA,
>DENALI_PHY_248_DATA,
>> + DENALI_PHY_249_DATA,
>> + DENALI_PHY_250_DATA, DENALI_PHY_251_DATA,
>DENALI_PHY_252_DATA,
>> + DENALI_PHY_253_DATA, DENALI_PHY_254_DATA,
>DENALI_PHY_255_DATA,
>> + DENALI_PHY_256_DATA, DENALI_PHY_257_DATA,
>DENALI_PHY_258_DATA,
>> + DENALI_PHY_259_DATA,
>> + DENALI_PHY_260_DATA, DENALI_PHY_261_DATA,
>DENALI_PHY_262_DATA,
>> + DENALI_PHY_263_DATA, DENALI_PHY_264_DATA,
>DENALI_PHY_265_DATA,
>> + DENALI_PHY_266_DATA, DENALI_PHY_267_DATA,
>DENALI_PHY_268_DATA,
>> + DENALI_PHY_269_DATA,
>> + DENALI_PHY_270_DATA, DENALI_PHY_271_DATA,
>DENALI_PHY_272_DATA,
>> + DENALI_PHY_273_DATA, DENALI_PHY_274_DATA,
>DENALI_PHY_275_DATA,
>> + DENALI_PHY_276_DATA, DENALI_PHY_277_DATA,
>DENALI_PHY_278_DATA,
>> + DENALI_PHY_279_DATA,
>> + DENALI_PHY_280_DATA, DENALI_PHY_281_DATA,
>DENALI_PHY_282_DATA,
>> + DENALI_PHY_283_DATA, DENALI_PHY_284_DATA,
>DENALI_PHY_285_DATA,
>> + DENALI_PHY_286_DATA, DENALI_PHY_287_DATA,
>DENALI_PHY_288_DATA,
>> + DENALI_PHY_289_DATA,
>> + DENALI_PHY_290_DATA, DENALI_PHY_291_DATA,
>DENALI_PHY_292_DATA,
>> + DENALI_PHY_293_DATA, DENALI_PHY_294_DATA,
>DENALI_PHY_295_DATA,
>> + DENALI_PHY_296_DATA, DENALI_PHY_297_DATA,
>DENALI_PHY_298_DATA,
>> + DENALI_PHY_299_DATA,
>> +
>> + DENALI_PHY_300_DATA, DENALI_PHY_301_DATA,
>DENALI_PHY_302_DATA,
>> + DENALI_PHY_303_DATA, DENALI_PHY_304_DATA,
>DENALI_PHY_305_DATA,
>> + DENALI_PHY_306_DATA, DENALI_PHY_307_DATA,
>DENALI_PHY_308_DATA,
>> + DENALI_PHY_309_DATA,
>> + DENALI_PHY_310_DATA, DENALI_PHY_311_DATA,
>DENALI_PHY_312_DATA,
>> + DENALI_PHY_313_DATA, DENALI_PHY_314_DATA,
>DENALI_PHY_315_DATA,
>> + DENALI_PHY_316_DATA, DENALI_PHY_317_DATA,
>DENALI_PHY_318_DATA,
>> + DENALI_PHY_319_DATA,
>> + DENALI_PHY_320_DATA, DENALI_PHY_321_DATA,
>DENALI_PHY_322_DATA,
>> + DENALI_PHY_323_DATA, DENALI_PHY_324_DATA,
>DENALI_PHY_325_DATA,
>> + DENALI_PHY_326_DATA, DENALI_PHY_327_DATA,
>DENALI_PHY_328_DATA,
>> + DENALI_PHY_329_DATA,
>> + DENALI_PHY_330_DATA, DENALI_PHY_331_DATA,
>DENALI_PHY_332_DATA,
>> + DENALI_PHY_333_DATA, DENALI_PHY_334_DATA,
>DENALI_PHY_335_DATA,
>> + DENALI_PHY_336_DATA, DENALI_PHY_337_DATA,
>DENALI_PHY_338_DATA,
>> + DENALI_PHY_339_DATA,
>> + DENALI_PHY_340_DATA, DENALI_PHY_341_DATA,
>DENALI_PHY_342_DATA,
>> + DENALI_PHY_343_DATA, DENALI_PHY_344_DATA,
>DENALI_PHY_345_DATA,
>> + DENALI_PHY_346_DATA, DENALI_PHY_347_DATA,
>DENALI_PHY_348_DATA,
>> + DENALI_PHY_349_DATA,
>> + DENALI_PHY_350_DATA, DENALI_PHY_351_DATA,
>DENALI_PHY_352_DATA,
>> + DENALI_PHY_353_DATA, DENALI_PHY_354_DATA,
>DENALI_PHY_355_DATA,
>> + DENALI_PHY_356_DATA, DENALI_PHY_357_DATA,
>DENALI_PHY_358_DATA,
>> + DENALI_PHY_359_DATA,
>> + DENALI_PHY_360_DATA, DENALI_PHY_361_DATA,
>DENALI_PHY_362_DATA,
>> + DENALI_PHY_363_DATA, DENALI_PHY_364_DATA,
>DENALI_PHY_365_DATA,
>> + DENALI_PHY_366_DATA, DENALI_PHY_367_DATA,
>DENALI_PHY_368_DATA,
>> + DENALI_PHY_369_DATA,
>> + DENALI_PHY_370_DATA, DENALI_PHY_371_DATA,
>DENALI_PHY_372_DATA,
>> + DENALI_PHY_373_DATA, DENALI_PHY_374_DATA,
>DENALI_PHY_375_DATA,
>> + DENALI_PHY_376_DATA, DENALI_PHY_377_DATA,
>DENALI_PHY_378_DATA,
>> + DENALI_PHY_379_DATA,
>> + DENALI_PHY_380_DATA, DENALI_PHY_381_DATA,
>DENALI_PHY_382_DATA,
>> + DENALI_PHY_383_DATA, DENALI_PHY_384_DATA,
>DENALI_PHY_385_DATA,
>> + DENALI_PHY_386_DATA, DENALI_PHY_387_DATA,
>DENALI_PHY_388_DATA,
>> + DENALI_PHY_389_DATA,
>> + DENALI_PHY_390_DATA, DENALI_PHY_391_DATA,
>DENALI_PHY_392_DATA,
>> + DENALI_PHY_393_DATA, DENALI_PHY_394_DATA,
>DENALI_PHY_395_DATA,
>> + DENALI_PHY_396_DATA, DENALI_PHY_397_DATA,
>DENALI_PHY_398_DATA,
>> + DENALI_PHY_399_DATA,
>> +
>> + DENALI_PHY_400_DATA, DENALI_PHY_401_DATA,
>DENALI_PHY_402_DATA,
>> + DENALI_PHY_403_DATA, DENALI_PHY_404_DATA,
>DENALI_PHY_405_DATA,
>> + DENALI_PHY_406_DATA, DENALI_PHY_407_DATA,
>DENALI_PHY_408_DATA,
>> + DENALI_PHY_409_DATA,
>> + DENALI_PHY_410_DATA, DENALI_PHY_411_DATA,
>DENALI_PHY_412_DATA,
>> + DENALI_PHY_413_DATA, DENALI_PHY_414_DATA,
>DENALI_PHY_415_DATA,
>> + DENALI_PHY_416_DATA, DENALI_PHY_417_DATA,
>DENALI_PHY_418_DATA,
>> + DENALI_PHY_419_DATA,
>> + DENALI_PHY_420_DATA, DENALI_PHY_421_DATA,
>DENALI_PHY_422_DATA,
>> + DENALI_PHY_423_DATA, DENALI_PHY_424_DATA,
>DENALI_PHY_425_DATA,
>> + DENALI_PHY_426_DATA, DENALI_PHY_427_DATA,
>DENALI_PHY_428_DATA,
>> + DENALI_PHY_429_DATA,
>> + DENALI_PHY_430_DATA, DENALI_PHY_431_DATA,
>DENALI_PHY_432_DATA,
>> + DENALI_PHY_433_DATA, DENALI_PHY_434_DATA,
>DENALI_PHY_435_DATA,
>> + DENALI_PHY_436_DATA, DENALI_PHY_437_DATA,
>DENALI_PHY_438_DATA,
>> + DENALI_PHY_439_DATA,
>> + DENALI_PHY_440_DATA, DENALI_PHY_441_DATA,
>DENALI_PHY_442_DATA,
>> + DENALI_PHY_443_DATA, DENALI_PHY_444_DATA,
>DENALI_PHY_445_DATA,
>> + DENALI_PHY_446_DATA, DENALI_PHY_447_DATA,
>DENALI_PHY_448_DATA,
>> + DENALI_PHY_449_DATA,
>> + DENALI_PHY_450_DATA, DENALI_PHY_451_DATA,
>DENALI_PHY_452_DATA,
>> + DENALI_PHY_453_DATA, DENALI_PHY_454_DATA,
>DENALI_PHY_455_DATA,
>> + DENALI_PHY_456_DATA, DENALI_PHY_457_DATA,
>DENALI_PHY_458_DATA,
>> + DENALI_PHY_459_DATA,
>> + DENALI_PHY_460_DATA, DENALI_PHY_461_DATA,
>DENALI_PHY_462_DATA,
>> + DENALI_PHY_463_DATA, DENALI_PHY_464_DATA,
>DENALI_PHY_465_DATA,
>> + DENALI_PHY_466_DATA, DENALI_PHY_467_DATA,
>DENALI_PHY_468_DATA,
>> + DENALI_PHY_469_DATA,
>> + DENALI_PHY_470_DATA, DENALI_PHY_471_DATA,
>DENALI_PHY_472_DATA,
>> + DENALI_PHY_473_DATA, DENALI_PHY_474_DATA,
>DENALI_PHY_475_DATA,
>> + DENALI_PHY_476_DATA, DENALI_PHY_477_DATA,
>DENALI_PHY_478_DATA,
>> + DENALI_PHY_479_DATA,
>> + DENALI_PHY_480_DATA, DENALI_PHY_481_DATA,
>DENALI_PHY_482_DATA,
>> + DENALI_PHY_483_DATA, DENALI_PHY_484_DATA,
>DENALI_PHY_485_DATA,
>> + DENALI_PHY_486_DATA, DENALI_PHY_487_DATA,
>DENALI_PHY_488_DATA,
>> + DENALI_PHY_489_DATA,
>> + DENALI_PHY_490_DATA, DENALI_PHY_491_DATA,
>DENALI_PHY_492_DATA,
>> + DENALI_PHY_493_DATA, DENALI_PHY_494_DATA,
>DENALI_PHY_495_DATA,
>> + DENALI_PHY_496_DATA, DENALI_PHY_497_DATA,
>DENALI_PHY_498_DATA,
>> + DENALI_PHY_499_DATA,
>> +
>> + DENALI_PHY_500_DATA, DENALI_PHY_501_DATA,
>DENALI_PHY_502_DATA,
>> + DENALI_PHY_503_DATA, DENALI_PHY_504_DATA,
>DENALI_PHY_505_DATA,
>> + DENALI_PHY_506_DATA, DENALI_PHY_507_DATA,
>DENALI_PHY_508_DATA,
>> + DENALI_PHY_509_DATA,
>> + DENALI_PHY_510_DATA, DENALI_PHY_511_DATA,
>DENALI_PHY_512_DATA,
>> + DENALI_PHY_513_DATA, DENALI_PHY_514_DATA,
>DENALI_PHY_515_DATA,
>> + DENALI_PHY_516_DATA, DENALI_PHY_517_DATA,
>DENALI_PHY_518_DATA,
>> + DENALI_PHY_519_DATA,
>> + DENALI_PHY_520_DATA, DENALI_PHY_521_DATA,
>DENALI_PHY_522_DATA,
>> + DENALI_PHY_523_DATA, DENALI_PHY_524_DATA,
>DENALI_PHY_525_DATA,
>> + DENALI_PHY_526_DATA, DENALI_PHY_527_DATA,
>DENALI_PHY_528_DATA,
>> + DENALI_PHY_529_DATA,
>> + DENALI_PHY_530_DATA, DENALI_PHY_531_DATA,
>DENALI_PHY_532_DATA,
>> + DENALI_PHY_533_DATA, DENALI_PHY_534_DATA,
>DENALI_PHY_535_DATA,
>> + DENALI_PHY_536_DATA, DENALI_PHY_537_DATA,
>DENALI_PHY_538_DATA,
>> + DENALI_PHY_539_DATA,
>> + DENALI_PHY_540_DATA, DENALI_PHY_541_DATA,
>DENALI_PHY_542_DATA,
>> + DENALI_PHY_543_DATA, DENALI_PHY_544_DATA,
>DENALI_PHY_545_DATA,
>> + DENALI_PHY_546_DATA, DENALI_PHY_547_DATA,
>DENALI_PHY_548_DATA,
>> + DENALI_PHY_549_DATA,
>> + DENALI_PHY_550_DATA, DENALI_PHY_551_DATA,
>DENALI_PHY_552_DATA,
>> + DENALI_PHY_553_DATA, DENALI_PHY_554_DATA,
>DENALI_PHY_555_DATA,
>> + DENALI_PHY_556_DATA, DENALI_PHY_557_DATA,
>DENALI_PHY_558_DATA,
>> + DENALI_PHY_559_DATA,
>> + DENALI_PHY_560_DATA, DENALI_PHY_561_DATA,
>DENALI_PHY_562_DATA,
>> + DENALI_PHY_563_DATA, DENALI_PHY_564_DATA,
>DENALI_PHY_565_DATA,
>> + DENALI_PHY_566_DATA, DENALI_PHY_567_DATA,
>DENALI_PHY_568_DATA,
>> + DENALI_PHY_569_DATA,
>> + DENALI_PHY_570_DATA, DENALI_PHY_571_DATA,
>DENALI_PHY_572_DATA,
>> + DENALI_PHY_573_DATA, DENALI_PHY_574_DATA,
>DENALI_PHY_575_DATA,
>> + DENALI_PHY_576_DATA, DENALI_PHY_577_DATA,
>DENALI_PHY_578_DATA,
>> + DENALI_PHY_579_DATA,
>> + DENALI_PHY_580_DATA, DENALI_PHY_581_DATA,
>DENALI_PHY_582_DATA,
>> + DENALI_PHY_583_DATA, DENALI_PHY_584_DATA,
>DENALI_PHY_585_DATA,
>> + DENALI_PHY_586_DATA, DENALI_PHY_587_DATA,
>DENALI_PHY_588_DATA,
>> + DENALI_PHY_589_DATA,
>> + DENALI_PHY_590_DATA, DENALI_PHY_591_DATA,
>DENALI_PHY_592_DATA,
>> + DENALI_PHY_593_DATA, DENALI_PHY_594_DATA,
>DENALI_PHY_595_DATA,
>> + DENALI_PHY_596_DATA, DENALI_PHY_597_DATA,
>DENALI_PHY_598_DATA,
>> + DENALI_PHY_599_DATA,
>> +
>> + DENALI_PHY_600_DATA, DENALI_PHY_601_DATA,
>DENALI_PHY_602_DATA,
>> + DENALI_PHY_603_DATA, DENALI_PHY_604_DATA,
>DENALI_PHY_605_DATA,
>> + DENALI_PHY_606_DATA, DENALI_PHY_607_DATA,
>DENALI_PHY_608_DATA,
>> + DENALI_PHY_609_DATA,
>> + DENALI_PHY_610_DATA, DENALI_PHY_611_DATA,
>DENALI_PHY_612_DATA,
>> + DENALI_PHY_613_DATA, DENALI_PHY_614_DATA,
>DENALI_PHY_615_DATA,
>> + DENALI_PHY_616_DATA, DENALI_PHY_617_DATA,
>DENALI_PHY_618_DATA,
>> + DENALI_PHY_619_DATA,
>> + DENALI_PHY_620_DATA, DENALI_PHY_621_DATA,
>DENALI_PHY_622_DATA,
>> + DENALI_PHY_623_DATA, DENALI_PHY_624_DATA,
>DENALI_PHY_625_DATA,
>> + DENALI_PHY_626_DATA, DENALI_PHY_627_DATA,
>DENALI_PHY_628_DATA,
>> + DENALI_PHY_629_DATA,
>> + DENALI_PHY_630_DATA, DENALI_PHY_631_DATA,
>DENALI_PHY_632_DATA,
>> + DENALI_PHY_633_DATA, DENALI_PHY_634_DATA,
>DENALI_PHY_635_DATA,
>> + DENALI_PHY_636_DATA, DENALI_PHY_637_DATA,
>DENALI_PHY_638_DATA,
>> + DENALI_PHY_639_DATA,
>> + DENALI_PHY_640_DATA, DENALI_PHY_641_DATA,
>DENALI_PHY_642_DATA,
>> + DENALI_PHY_643_DATA, DENALI_PHY_644_DATA,
>DENALI_PHY_645_DATA,
>> + DENALI_PHY_646_DATA, DENALI_PHY_647_DATA,
>DENALI_PHY_648_DATA,
>> + DENALI_PHY_649_DATA,
>> + DENALI_PHY_650_DATA, DENALI_PHY_651_DATA,
>DENALI_PHY_652_DATA,
>> + DENALI_PHY_653_DATA, DENALI_PHY_654_DATA,
>DENALI_PHY_655_DATA,
>> + DENALI_PHY_656_DATA, DENALI_PHY_657_DATA,
>DENALI_PHY_658_DATA,
>> + DENALI_PHY_659_DATA,
>> + DENALI_PHY_660_DATA, DENALI_PHY_661_DATA,
>DENALI_PHY_662_DATA,
>> + DENALI_PHY_663_DATA, DENALI_PHY_664_DATA,
>DENALI_PHY_665_DATA,
>> + DENALI_PHY_666_DATA, DENALI_PHY_667_DATA,
>DENALI_PHY_668_DATA,
>> + DENALI_PHY_669_DATA,
>> + DENALI_PHY_670_DATA, DENALI_PHY_671_DATA,
>DENALI_PHY_672_DATA,
>> + DENALI_PHY_673_DATA, DENALI_PHY_674_DATA,
>DENALI_PHY_675_DATA,
>> + DENALI_PHY_676_DATA, DENALI_PHY_677_DATA,
>DENALI_PHY_678_DATA,
>> + DENALI_PHY_679_DATA,
>> + DENALI_PHY_680_DATA, DENALI_PHY_681_DATA,
>DENALI_PHY_682_DATA,
>> + DENALI_PHY_683_DATA, DENALI_PHY_684_DATA,
>DENALI_PHY_685_DATA,
>> + DENALI_PHY_686_DATA, DENALI_PHY_687_DATA,
>DENALI_PHY_688_DATA,
>> + DENALI_PHY_689_DATA,
>> + DENALI_PHY_690_DATA, DENALI_PHY_691_DATA,
>DENALI_PHY_692_DATA,
>> + DENALI_PHY_693_DATA, DENALI_PHY_694_DATA,
>DENALI_PHY_695_DATA,
>> + DENALI_PHY_696_DATA, DENALI_PHY_697_DATA,
>DENALI_PHY_698_DATA,
>> + DENALI_PHY_699_DATA,
>> +
>> + DENALI_PHY_700_DATA, DENALI_PHY_701_DATA,
>DENALI_PHY_702_DATA,
>> + DENALI_PHY_703_DATA, DENALI_PHY_704_DATA,
>DENALI_PHY_705_DATA,
>> + DENALI_PHY_706_DATA, DENALI_PHY_707_DATA,
>DENALI_PHY_708_DATA,
>> + DENALI_PHY_709_DATA,
>> + DENALI_PHY_710_DATA, DENALI_PHY_711_DATA,
>DENALI_PHY_712_DATA,
>> + DENALI_PHY_713_DATA, DENALI_PHY_714_DATA,
>DENALI_PHY_715_DATA,
>> + DENALI_PHY_716_DATA, DENALI_PHY_717_DATA,
>DENALI_PHY_718_DATA,
>> + DENALI_PHY_719_DATA,
>> + DENALI_PHY_720_DATA, DENALI_PHY_721_DATA,
>DENALI_PHY_722_DATA,
>> + DENALI_PHY_723_DATA, DENALI_PHY_724_DATA,
>DENALI_PHY_725_DATA,
>> + DENALI_PHY_726_DATA, DENALI_PHY_727_DATA,
>DENALI_PHY_728_DATA,
>> + DENALI_PHY_729_DATA,
>> + DENALI_PHY_730_DATA, DENALI_PHY_731_DATA,
>DENALI_PHY_732_DATA,
>> + DENALI_PHY_733_DATA, DENALI_PHY_734_DATA,
>DENALI_PHY_735_DATA,
>> + DENALI_PHY_736_DATA, DENALI_PHY_737_DATA,
>DENALI_PHY_738_DATA,
>> + DENALI_PHY_739_DATA,
>> + DENALI_PHY_740_DATA, DENALI_PHY_741_DATA,
>DENALI_PHY_742_DATA,
>> + DENALI_PHY_743_DATA, DENALI_PHY_744_DATA,
>DENALI_PHY_745_DATA,
>> + DENALI_PHY_746_DATA, DENALI_PHY_747_DATA,
>DENALI_PHY_748_DATA,
>> + DENALI_PHY_749_DATA,
>> + DENALI_PHY_750_DATA, DENALI_PHY_751_DATA,
>DENALI_PHY_752_DATA,
>> + DENALI_PHY_753_DATA, DENALI_PHY_754_DATA,
>DENALI_PHY_755_DATA,
>> + DENALI_PHY_756_DATA, DENALI_PHY_757_DATA,
>DENALI_PHY_758_DATA,
>> + DENALI_PHY_759_DATA,
>> + DENALI_PHY_760_DATA, DENALI_PHY_761_DATA,
>DENALI_PHY_762_DATA,
>> + DENALI_PHY_763_DATA, DENALI_PHY_764_DATA,
>DENALI_PHY_765_DATA,
>> + DENALI_PHY_766_DATA, DENALI_PHY_767_DATA,
>DENALI_PHY_768_DATA,
>> + DENALI_PHY_769_DATA,
>> + DENALI_PHY_770_DATA, DENALI_PHY_771_DATA,
>DENALI_PHY_772_DATA,
>> + DENALI_PHY_773_DATA, DENALI_PHY_774_DATA,
>DENALI_PHY_775_DATA,
>> + DENALI_PHY_776_DATA, DENALI_PHY_777_DATA,
>DENALI_PHY_778_DATA,
>> + DENALI_PHY_779_DATA,
>> + DENALI_PHY_780_DATA, DENALI_PHY_781_DATA,
>DENALI_PHY_782_DATA,
>> + DENALI_PHY_783_DATA, DENALI_PHY_784_DATA,
>DENALI_PHY_785_DATA,
>> + DENALI_PHY_786_DATA, DENALI_PHY_787_DATA,
>DENALI_PHY_788_DATA,
>> + DENALI_PHY_789_DATA,
>> + DENALI_PHY_790_DATA, DENALI_PHY_791_DATA,
>DENALI_PHY_792_DATA,
>> + DENALI_PHY_793_DATA, DENALI_PHY_794_DATA,
>DENALI_PHY_795_DATA,
>> + DENALI_PHY_796_DATA, DENALI_PHY_797_DATA,
>DENALI_PHY_798_DATA,
>> + DENALI_PHY_799_DATA,
>> +
>> + DENALI_PHY_800_DATA, DENALI_PHY_801_DATA,
>DENALI_PHY_802_DATA,
>> + DENALI_PHY_803_DATA, DENALI_PHY_804_DATA,
>DENALI_PHY_805_DATA,
>> + DENALI_PHY_806_DATA, DENALI_PHY_807_DATA,
>DENALI_PHY_808_DATA,
>> + DENALI_PHY_809_DATA,
>> + DENALI_PHY_810_DATA, DENALI_PHY_811_DATA,
>DENALI_PHY_812_DATA,
>> + DENALI_PHY_813_DATA, DENALI_PHY_814_DATA,
>DENALI_PHY_815_DATA,
>> + DENALI_PHY_816_DATA, DENALI_PHY_817_DATA,
>DENALI_PHY_818_DATA,
>> + DENALI_PHY_819_DATA,
>> + DENALI_PHY_820_DATA, DENALI_PHY_821_DATA,
>DENALI_PHY_822_DATA,
>> + DENALI_PHY_823_DATA, DENALI_PHY_824_DATA,
>DENALI_PHY_825_DATA,
>> + DENALI_PHY_826_DATA, DENALI_PHY_827_DATA,
>DENALI_PHY_828_DATA,
>> + DENALI_PHY_829_DATA,
>> + DENALI_PHY_830_DATA, DENALI_PHY_831_DATA,
>DENALI_PHY_832_DATA,
>> + DENALI_PHY_833_DATA, DENALI_PHY_834_DATA,
>DENALI_PHY_835_DATA,
>> + DENALI_PHY_836_DATA, DENALI_PHY_837_DATA,
>DENALI_PHY_838_DATA,
>> + DENALI_PHY_839_DATA,
>> + DENALI_PHY_840_DATA, DENALI_PHY_841_DATA,
>DENALI_PHY_842_DATA,
>> + DENALI_PHY_843_DATA, DENALI_PHY_844_DATA,
>DENALI_PHY_845_DATA,
>> + DENALI_PHY_846_DATA, DENALI_PHY_847_DATA,
>DENALI_PHY_848_DATA,
>> + DENALI_PHY_849_DATA,
>> + DENALI_PHY_850_DATA, DENALI_PHY_851_DATA,
>DENALI_PHY_852_DATA,
>> + DENALI_PHY_853_DATA, DENALI_PHY_854_DATA,
>DENALI_PHY_855_DATA,
>> + DENALI_PHY_856_DATA, DENALI_PHY_857_DATA,
>DENALI_PHY_858_DATA,
>> + DENALI_PHY_859_DATA,
>> + DENALI_PHY_860_DATA, DENALI_PHY_861_DATA,
>DENALI_PHY_862_DATA,
>> + DENALI_PHY_863_DATA, DENALI_PHY_864_DATA,
>DENALI_PHY_865_DATA,
>> + DENALI_PHY_866_DATA, DENALI_PHY_867_DATA,
>DENALI_PHY_868_DATA,
>> + DENALI_PHY_869_DATA,
>> + DENALI_PHY_870_DATA, DENALI_PHY_871_DATA,
>DENALI_PHY_872_DATA,
>> + DENALI_PHY_873_DATA, DENALI_PHY_874_DATA,
>DENALI_PHY_875_DATA,
>> + DENALI_PHY_876_DATA, DENALI_PHY_877_DATA,
>DENALI_PHY_878_DATA,
>> + DENALI_PHY_879_DATA,
>> + DENALI_PHY_880_DATA, DENALI_PHY_881_DATA,
>DENALI_PHY_882_DATA,
>> + DENALI_PHY_883_DATA, DENALI_PHY_884_DATA,
>DENALI_PHY_885_DATA,
>> + DENALI_PHY_886_DATA, DENALI_PHY_887_DATA,
>DENALI_PHY_888_DATA,
>> + DENALI_PHY_889_DATA,
>> + DENALI_PHY_890_DATA, DENALI_PHY_891_DATA,
>DENALI_PHY_892_DATA,
>> + DENALI_PHY_893_DATA, DENALI_PHY_894_DATA,
>DENALI_PHY_895_DATA,
>> + DENALI_PHY_896_DATA, DENALI_PHY_897_DATA,
>DENALI_PHY_898_DATA,
>> + DENALI_PHY_899_DATA,
>> +
>> + DENALI_PHY_900_DATA, DENALI_PHY_901_DATA,
>DENALI_PHY_902_DATA,
>> + DENALI_PHY_903_DATA, DENALI_PHY_904_DATA,
>DENALI_PHY_905_DATA,
>> + DENALI_PHY_906_DATA, DENALI_PHY_907_DATA,
>DENALI_PHY_908_DATA,
>> + DENALI_PHY_909_DATA,
>> + DENALI_PHY_910_DATA, DENALI_PHY_911_DATA,
>DENALI_PHY_912_DATA,
>> + DENALI_PHY_913_DATA, DENALI_PHY_914_DATA,
>DENALI_PHY_915_DATA,
>> + DENALI_PHY_916_DATA, DENALI_PHY_917_DATA,
>DENALI_PHY_918_DATA,
>> + DENALI_PHY_919_DATA,
>> + DENALI_PHY_920_DATA, DENALI_PHY_921_DATA,
>DENALI_PHY_922_DATA,
>> + DENALI_PHY_923_DATA, DENALI_PHY_924_DATA,
>DENALI_PHY_925_DATA,
>> + DENALI_PHY_926_DATA, DENALI_PHY_927_DATA,
>DENALI_PHY_928_DATA,
>> + DENALI_PHY_929_DATA,
>> + DENALI_PHY_930_DATA, DENALI_PHY_931_DATA,
>DENALI_PHY_932_DATA,
>> + DENALI_PHY_933_DATA, DENALI_PHY_934_DATA,
>DENALI_PHY_935_DATA,
>> + DENALI_PHY_936_DATA, DENALI_PHY_937_DATA,
>DENALI_PHY_938_DATA,
>> + DENALI_PHY_939_DATA,
>> + DENALI_PHY_940_DATA, DENALI_PHY_941_DATA,
>DENALI_PHY_942_DATA,
>> + DENALI_PHY_943_DATA, DENALI_PHY_944_DATA,
>DENALI_PHY_945_DATA,
>> + DENALI_PHY_946_DATA, DENALI_PHY_947_DATA,
>DENALI_PHY_948_DATA,
>> + DENALI_PHY_949_DATA,
>> + DENALI_PHY_950_DATA, DENALI_PHY_951_DATA,
>DENALI_PHY_952_DATA,
>> + DENALI_PHY_953_DATA, DENALI_PHY_954_DATA,
>DENALI_PHY_955_DATA,
>> + DENALI_PHY_956_DATA, DENALI_PHY_957_DATA,
>DENALI_PHY_958_DATA,
>> + DENALI_PHY_959_DATA,
>> + DENALI_PHY_960_DATA, DENALI_PHY_961_DATA,
>DENALI_PHY_962_DATA,
>> + DENALI_PHY_963_DATA, DENALI_PHY_964_DATA,
>DENALI_PHY_965_DATA,
>> + DENALI_PHY_966_DATA, DENALI_PHY_967_DATA,
>DENALI_PHY_968_DATA,
>> + DENALI_PHY_969_DATA,
>> + DENALI_PHY_970_DATA, DENALI_PHY_971_DATA,
>DENALI_PHY_972_DATA,
>> + DENALI_PHY_973_DATA, DENALI_PHY_974_DATA,
>DENALI_PHY_975_DATA,
>> + DENALI_PHY_976_DATA, DENALI_PHY_977_DATA,
>DENALI_PHY_978_DATA,
>> + DENALI_PHY_979_DATA,
>> + DENALI_PHY_980_DATA, DENALI_PHY_981_DATA,
>DENALI_PHY_982_DATA,
>> + DENALI_PHY_983_DATA, DENALI_PHY_984_DATA,
>DENALI_PHY_985_DATA,
>> + DENALI_PHY_986_DATA, DENALI_PHY_987_DATA,
>DENALI_PHY_988_DATA,
>> + DENALI_PHY_989_DATA,
>> + DENALI_PHY_990_DATA, DENALI_PHY_991_DATA,
>DENALI_PHY_992_DATA,
>> + DENALI_PHY_993_DATA, DENALI_PHY_994_DATA,
>DENALI_PHY_995_DATA,
>> + DENALI_PHY_996_DATA, DENALI_PHY_997_DATA,
>DENALI_PHY_998_DATA,
>> + DENALI_PHY_999_DATA,
>> +
>> + DENALI_PHY_1000_DATA, DENALI_PHY_1001_DATA,
>DENALI_PHY_1002_DATA,
>> + DENALI_PHY_1003_DATA, DENALI_PHY_1004_DATA,
>DENALI_PHY_1005_DATA,
>> + DENALI_PHY_1006_DATA, DENALI_PHY_1007_DATA,
>DENALI_PHY_1008_DATA,
>> + DENALI_PHY_1009_DATA,
>> + DENALI_PHY_1010_DATA, DENALI_PHY_1011_DATA,
>DENALI_PHY_1012_DATA,
>> + DENALI_PHY_1013_DATA, DENALI_PHY_1014_DATA,
>DENALI_PHY_1015_DATA,
>> + DENALI_PHY_1016_DATA, DENALI_PHY_1017_DATA,
>DENALI_PHY_1018_DATA,
>> + DENALI_PHY_1019_DATA,
>> + DENALI_PHY_1020_DATA, DENALI_PHY_1021_DATA,
>DENALI_PHY_1022_DATA,
>> + DENALI_PHY_1023_DATA, DENALI_PHY_1024_DATA,
>DENALI_PHY_1025_DATA,
>> + DENALI_PHY_1026_DATA, DENALI_PHY_1027_DATA,
>DENALI_PHY_1028_DATA,
>> + DENALI_PHY_1029_DATA,
>> + DENALI_PHY_1030_DATA, DENALI_PHY_1031_DATA,
>DENALI_PHY_1032_DATA,
>> + DENALI_PHY_1033_DATA, DENALI_PHY_1034_DATA,
>DENALI_PHY_1035_DATA,
>> + DENALI_PHY_1036_DATA, DENALI_PHY_1037_DATA,
>DENALI_PHY_1038_DATA,
>> + DENALI_PHY_1039_DATA,
>> + DENALI_PHY_1040_DATA, DENALI_PHY_1041_DATA,
>DENALI_PHY_1042_DATA,
>> + DENALI_PHY_1043_DATA, DENALI_PHY_1044_DATA,
>DENALI_PHY_1045_DATA,
>> + DENALI_PHY_1046_DATA, DENALI_PHY_1047_DATA,
>DENALI_PHY_1048_DATA,
>> + DENALI_PHY_1049_DATA,
>> + DENALI_PHY_1050_DATA, DENALI_PHY_1051_DATA,
>DENALI_PHY_1052_DATA,
>> + DENALI_PHY_1053_DATA, DENALI_PHY_1054_DATA,
>DENALI_PHY_1055_DATA,
>> + DENALI_PHY_1056_DATA, DENALI_PHY_1057_DATA,
>DENALI_PHY_1058_DATA,
>> + DENALI_PHY_1059_DATA,
>> + DENALI_PHY_1060_DATA, DENALI_PHY_1061_DATA,
>DENALI_PHY_1062_DATA,
>> + DENALI_PHY_1063_DATA, DENALI_PHY_1064_DATA,
>DENALI_PHY_1065_DATA,
>> + DENALI_PHY_1066_DATA, DENALI_PHY_1067_DATA,
>DENALI_PHY_1068_DATA,
>> + DENALI_PHY_1069_DATA,
>> + DENALI_PHY_1070_DATA, DENALI_PHY_1071_DATA,
>DENALI_PHY_1072_DATA,
>> + DENALI_PHY_1073_DATA, DENALI_PHY_1074_DATA,
>DENALI_PHY_1075_DATA,
>> + DENALI_PHY_1076_DATA, DENALI_PHY_1077_DATA,
>DENALI_PHY_1078_DATA,
>> + DENALI_PHY_1079_DATA,
>> + DENALI_PHY_1080_DATA, DENALI_PHY_1081_DATA,
>DENALI_PHY_1082_DATA,
>> + DENALI_PHY_1083_DATA, DENALI_PHY_1084_DATA,
>DENALI_PHY_1085_DATA,
>> + DENALI_PHY_1086_DATA, DENALI_PHY_1087_DATA,
>DENALI_PHY_1088_DATA,
>> + DENALI_PHY_1089_DATA,
>> + DENALI_PHY_1090_DATA, DENALI_PHY_1091_DATA,
>DENALI_PHY_1092_DATA,
>> + DENALI_PHY_1093_DATA, DENALI_PHY_1094_DATA,
>DENALI_PHY_1095_DATA,
>> + DENALI_PHY_1096_DATA, DENALI_PHY_1097_DATA,
>DENALI_PHY_1098_DATA,
>> + DENALI_PHY_1099_DATA,
>> +
>> + DENALI_PHY_1100_DATA, DENALI_PHY_1101_DATA,
>DENALI_PHY_1102_DATA,
>> + DENALI_PHY_1103_DATA, DENALI_PHY_1104_DATA,
>DENALI_PHY_1105_DATA,
>> + DENALI_PHY_1106_DATA, DENALI_PHY_1107_DATA,
>DENALI_PHY_1108_DATA,
>> + DENALI_PHY_1109_DATA,
>> + DENALI_PHY_1110_DATA, DENALI_PHY_1111_DATA,
>DENALI_PHY_1112_DATA,
>> + DENALI_PHY_1113_DATA, DENALI_PHY_1114_DATA,
>DENALI_PHY_1115_DATA,
>> + DENALI_PHY_1116_DATA, DENALI_PHY_1117_DATA,
>DENALI_PHY_1118_DATA,
>> + DENALI_PHY_1119_DATA,
>> + DENALI_PHY_1120_DATA, DENALI_PHY_1121_DATA,
>DENALI_PHY_1122_DATA,
>> + DENALI_PHY_1123_DATA, DENALI_PHY_1124_DATA,
>DENALI_PHY_1125_DATA,
>> + DENALI_PHY_1126_DATA, DENALI_PHY_1127_DATA,
>DENALI_PHY_1128_DATA,
>> + DENALI_PHY_1129_DATA,
>> + DENALI_PHY_1130_DATA, DENALI_PHY_1131_DATA,
>DENALI_PHY_1132_DATA,
>> + DENALI_PHY_1133_DATA, DENALI_PHY_1134_DATA,
>DENALI_PHY_1135_DATA,
>> + DENALI_PHY_1136_DATA, DENALI_PHY_1137_DATA,
>DENALI_PHY_1138_DATA,
>> + DENALI_PHY_1139_DATA,
>> + DENALI_PHY_1140_DATA, DENALI_PHY_1141_DATA,
>DENALI_PHY_1142_DATA,
>> + DENALI_PHY_1143_DATA, DENALI_PHY_1144_DATA,
>DENALI_PHY_1145_DATA,
>> + DENALI_PHY_1146_DATA, DENALI_PHY_1147_DATA,
>DENALI_PHY_1148_DATA,
>> + DENALI_PHY_1149_DATA,
>> + DENALI_PHY_1150_DATA, DENALI_PHY_1151_DATA,
>DENALI_PHY_1152_DATA,
>> + DENALI_PHY_1153_DATA, DENALI_PHY_1154_DATA,
>DENALI_PHY_1155_DATA,
>> + DENALI_PHY_1156_DATA, DENALI_PHY_1157_DATA,
>DENALI_PHY_1158_DATA,
>> + DENALI_PHY_1159_DATA,
>> + DENALI_PHY_1160_DATA, DENALI_PHY_1161_DATA,
>DENALI_PHY_1162_DATA,
>> + DENALI_PHY_1163_DATA, DENALI_PHY_1164_DATA,
>DENALI_PHY_1165_DATA,
>> + DENALI_PHY_1166_DATA, DENALI_PHY_1167_DATA,
>DENALI_PHY_1168_DATA,
>> + DENALI_PHY_1169_DATA,
>> + DENALI_PHY_1170_DATA, DENALI_PHY_1171_DATA,
>DENALI_PHY_1172_DATA,
>> + DENALI_PHY_1173_DATA, DENALI_PHY_1174_DATA,
>DENALI_PHY_1175_DATA,
>> + DENALI_PHY_1176_DATA, DENALI_PHY_1177_DATA,
>DENALI_PHY_1178_DATA,
>> + DENALI_PHY_1179_DATA,
>> + DENALI_PHY_1180_DATA, DENALI_PHY_1181_DATA,
>DENALI_PHY_1182_DATA,
>> + DENALI_PHY_1183_DATA, DENALI_PHY_1184_DATA,
>DENALI_PHY_1185_DATA,
>> + DENALI_PHY_1186_DATA, DENALI_PHY_1187_DATA,
>DENALI_PHY_1188_DATA,
>> + DENALI_PHY_1189_DATA,
>> + DENALI_PHY_1190_DATA, DENALI_PHY_1191_DATA,
>DENALI_PHY_1192_DATA,
>> + DENALI_PHY_1193_DATA, DENALI_PHY_1194_DATA,
>DENALI_PHY_1195_DATA,
>> + DENALI_PHY_1196_DATA, DENALI_PHY_1197_DATA,
>DENALI_PHY_1198_DATA,
>> + DENALI_PHY_1199_DATA,
>> +
>> + DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA,
>DENALI_PHY_1202_DATA,
>> + DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA,
>DENALI_PHY_1205_DATA,
>> + DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA,
>DENALI_PHY_1208_DATA,
>> + DENALI_PHY_1209_DATA,
>> + DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA,
>DENALI_PHY_1212_DATA,
>> + DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA
>> +};
>> +
>> +u32 ddr_ctl_settings[265] = {
>> + DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA,
>> + DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA,
>> + DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA,
>> + DENALI_CTL_09_DATA,
>> + DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA,
>> + DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA,
>> + DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA,
>> + DENALI_CTL_19_DATA,
>> + DENALI_CTL_20_DATA, DENALI_CTL_21_DATA, DENALI_CTL_22_DATA,
>> + DENALI_CTL_23_DATA, DENALI_CTL_24_DATA, DENALI_CTL_25_DATA,
>> + DENALI_CTL_26_DATA, DENALI_CTL_27_DATA, DENALI_CTL_28_DATA,
>> + DENALI_CTL_29_DATA,
>> + DENALI_CTL_30_DATA, DENALI_CTL_31_DATA, DENALI_CTL_32_DATA,
>> + DENALI_CTL_33_DATA, DENALI_CTL_34_DATA, DENALI_CTL_35_DATA,
>> + DENALI_CTL_36_DATA, DENALI_CTL_37_DATA, DENALI_CTL_38_DATA,
>> + DENALI_CTL_39_DATA,
>> + DENALI_CTL_40_DATA, DENALI_CTL_41_DATA, DENALI_CTL_42_DATA,
>> + DENALI_CTL_43_DATA, DENALI_CTL_44_DATA, DENALI_CTL_45_DATA,
>> + DENALI_CTL_46_DATA, DENALI_CTL_47_DATA, DENALI_CTL_48_DATA,
>> + DENALI_CTL_49_DATA,
>> + DENALI_CTL_50_DATA, DENALI_CTL_51_DATA, DENALI_CTL_52_DATA,
>> + DENALI_CTL_53_DATA, DENALI_CTL_54_DATA, DENALI_CTL_55_DATA,
>> + DENALI_CTL_56_DATA, DENALI_CTL_57_DATA, DENALI_CTL_58_DATA,
>> + DENALI_CTL_59_DATA,
>> + DENALI_CTL_60_DATA, DENALI_CTL_61_DATA, DENALI_CTL_62_DATA,
>> + DENALI_CTL_63_DATA, DENALI_CTL_64_DATA, DENALI_CTL_65_DATA,
>> + DENALI_CTL_66_DATA, DENALI_CTL_67_DATA, DENALI_CTL_68_DATA,
>> + DENALI_CTL_69_DATA,
>> + DENALI_CTL_70_DATA, DENALI_CTL_71_DATA, DENALI_CTL_72_DATA,
>> + DENALI_CTL_73_DATA, DENALI_CTL_74_DATA, DENALI_CTL_75_DATA,
>> + DENALI_CTL_76_DATA, DENALI_CTL_77_DATA, DENALI_CTL_78_DATA,
>> + DENALI_CTL_79_DATA,
>> + DENALI_CTL_80_DATA, DENALI_CTL_81_DATA, DENALI_CTL_82_DATA,
>> + DENALI_CTL_83_DATA, DENALI_CTL_84_DATA, DENALI_CTL_85_DATA,
>> + DENALI_CTL_86_DATA, DENALI_CTL_87_DATA, DENALI_CTL_88_DATA,
>> + DENALI_CTL_89_DATA,
>> + DENALI_CTL_90_DATA, DENALI_CTL_91_DATA, DENALI_CTL_92_DATA,
>> + DENALI_CTL_93_DATA, DENALI_CTL_94_DATA, DENALI_CTL_95_DATA,
>> + DENALI_CTL_96_DATA, DENALI_CTL_97_DATA, DENALI_CTL_98_DATA,
>> + DENALI_CTL_99_DATA,
>> +
>> + DENALI_CTL_100_DATA, DENALI_CTL_101_DATA,
>DENALI_CTL_102_DATA,
>> + DENALI_CTL_103_DATA, DENALI_CTL_104_DATA,
>DENALI_CTL_105_DATA,
>> + DENALI_CTL_106_DATA, DENALI_CTL_107_DATA,
>DENALI_CTL_108_DATA,
>> + DENALI_CTL_109_DATA,
>> + DENALI_CTL_110_DATA, DENALI_CTL_111_DATA,
>DENALI_CTL_112_DATA,
>> + DENALI_CTL_113_DATA, DENALI_CTL_114_DATA,
>DENALI_CTL_115_DATA,
>> + DENALI_CTL_116_DATA, DENALI_CTL_117_DATA,
>DENALI_CTL_118_DATA,
>> + DENALI_CTL_119_DATA,
>> + DENALI_CTL_120_DATA, DENALI_CTL_121_DATA,
>DENALI_CTL_122_DATA,
>> + DENALI_CTL_123_DATA, DENALI_CTL_124_DATA,
>DENALI_CTL_125_DATA,
>> + DENALI_CTL_126_DATA, DENALI_CTL_127_DATA,
>DENALI_CTL_128_DATA,
>> + DENALI_CTL_129_DATA,
>> + DENALI_CTL_130_DATA, DENALI_CTL_131_DATA,
>DENALI_CTL_132_DATA,
>> + DENALI_CTL_133_DATA, DENALI_CTL_134_DATA,
>DENALI_CTL_135_DATA,
>> + DENALI_CTL_136_DATA, DENALI_CTL_137_DATA,
>DENALI_CTL_138_DATA,
>> + DENALI_CTL_139_DATA,
>> + DENALI_CTL_140_DATA, DENALI_CTL_141_DATA,
>DENALI_CTL_142_DATA,
>> + DENALI_CTL_143_DATA, DENALI_CTL_144_DATA,
>DENALI_CTL_145_DATA,
>> + DENALI_CTL_146_DATA, DENALI_CTL_147_DATA,
>DENALI_CTL_148_DATA,
>> + DENALI_CTL_149_DATA,
>> + DENALI_CTL_150_DATA, DENALI_CTL_151_DATA,
>DENALI_CTL_152_DATA,
>> + DENALI_CTL_153_DATA, DENALI_CTL_154_DATA,
>DENALI_CTL_155_DATA,
>> + DENALI_CTL_156_DATA, DENALI_CTL_157_DATA,
>DENALI_CTL_158_DATA,
>> + DENALI_CTL_159_DATA,
>> + DENALI_CTL_160_DATA, DENALI_CTL_161_DATA,
>DENALI_CTL_162_DATA,
>> + DENALI_CTL_163_DATA, DENALI_CTL_164_DATA,
>DENALI_CTL_165_DATA,
>> + DENALI_CTL_166_DATA, DENALI_CTL_167_DATA,
>DENALI_CTL_168_DATA,
>> + DENALI_CTL_169_DATA,
>> + DENALI_CTL_170_DATA, DENALI_CTL_171_DATA,
>DENALI_CTL_172_DATA,
>> + DENALI_CTL_173_DATA, DENALI_CTL_174_DATA,
>DENALI_CTL_175_DATA,
>> + DENALI_CTL_176_DATA, DENALI_CTL_177_DATA,
>DENALI_CTL_178_DATA,
>> + DENALI_CTL_179_DATA,
>> + DENALI_CTL_180_DATA, DENALI_CTL_181_DATA,
>DENALI_CTL_182_DATA,
>> + DENALI_CTL_183_DATA, DENALI_CTL_184_DATA,
>DENALI_CTL_185_DATA,
>> + DENALI_CTL_186_DATA, DENALI_CTL_187_DATA,
>DENALI_CTL_188_DATA,
>> + DENALI_CTL_189_DATA,
>> + DENALI_CTL_190_DATA, DENALI_CTL_191_DATA,
>DENALI_CTL_192_DATA,
>> + DENALI_CTL_193_DATA, DENALI_CTL_194_DATA,
>DENALI_CTL_195_DATA,
>> + DENALI_CTL_196_DATA, DENALI_CTL_197_DATA,
>DENALI_CTL_198_DATA,
>> + DENALI_CTL_199_DATA,
>> +
>> + DENALI_CTL_200_DATA, DENALI_CTL_201_DATA,
>DENALI_CTL_202_DATA,
>> + DENALI_CTL_203_DATA, DENALI_CTL_204_DATA,
>DENALI_CTL_205_DATA,
>> + DENALI_CTL_206_DATA, DENALI_CTL_207_DATA,
>DENALI_CTL_208_DATA,
>> + DENALI_CTL_209_DATA,
>> + DENALI_CTL_210_DATA, DENALI_CTL_211_DATA,
>DENALI_CTL_212_DATA,
>> + DENALI_CTL_213_DATA, DENALI_CTL_214_DATA,
>DENALI_CTL_215_DATA,
>> + DENALI_CTL_216_DATA, DENALI_CTL_217_DATA,
>DENALI_CTL_218_DATA,
>> + DENALI_CTL_219_DATA,
>> + DENALI_CTL_220_DATA, DENALI_CTL_221_DATA,
>DENALI_CTL_222_DATA,
>> + DENALI_CTL_223_DATA, DENALI_CTL_224_DATA,
>DENALI_CTL_225_DATA,
>> + DENALI_CTL_226_DATA, DENALI_CTL_227_DATA,
>DENALI_CTL_228_DATA,
>> + DENALI_CTL_229_DATA,
>> + DENALI_CTL_230_DATA, DENALI_CTL_231_DATA,
>DENALI_CTL_232_DATA,
>> + DENALI_CTL_233_DATA, DENALI_CTL_234_DATA,
>DENALI_CTL_235_DATA,
>> + DENALI_CTL_236_DATA, DENALI_CTL_237_DATA,
>DENALI_CTL_238_DATA,
>> + DENALI_CTL_239_DATA,
>> + DENALI_CTL_240_DATA, DENALI_CTL_241_DATA,
>DENALI_CTL_242_DATA,
>> + DENALI_CTL_243_DATA, DENALI_CTL_244_DATA,
>DENALI_CTL_245_DATA,
>> + DENALI_CTL_246_DATA, DENALI_CTL_247_DATA,
>DENALI_CTL_248_DATA,
>> + DENALI_CTL_249_DATA,
>> + DENALI_CTL_250_DATA, DENALI_CTL_251_DATA,
>DENALI_CTL_252_DATA,
>> + DENALI_CTL_253_DATA, DENALI_CTL_254_DATA,
>DENALI_CTL_255_DATA,
>> + DENALI_CTL_256_DATA, DENALI_CTL_257_DATA,
>DENALI_CTL_258_DATA,
>> + DENALI_CTL_259_DATA,
>> + DENALI_CTL_260_DATA, DENALI_CTL_261_DATA,
>DENALI_CTL_262_DATA,
>> + DENALI_CTL_263_DATA, DENALI_CTL_264_DATA
>> +};
>> diff --git a/board/sifive/fu540/regconfig-ctl.h
>b/board/sifive/fu540/regconfig-ctl.h
>> new file mode 100644
>> index 0000000000..b8f50f5b35
>> --- /dev/null
>> +++ b/board/sifive/fu540/regconfig-ctl.h
>> @@ -0,0 +1,270 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + */
>> +
>> +#define DENALI_CTL_00_DATA 0x00000a00
>> +#define DENALI_CTL_01_DATA 0x00000000
>> +#define DENALI_CTL_02_DATA 0x00000000
>> +#define DENALI_CTL_03_DATA 0x00000000
>> +#define DENALI_CTL_04_DATA 0x00000000
>> +#define DENALI_CTL_05_DATA 0x00000000
>> +#define DENALI_CTL_06_DATA 0x0000000a
>> +#define DENALI_CTL_07_DATA 0x0002d362
>> +#define DENALI_CTL_08_DATA 0x00071073
>> +#define DENALI_CTL_09_DATA 0x0a1c0255
>> +#define DENALI_CTL_10_DATA 0x1c1c0400
>> +#define DENALI_CTL_11_DATA 0x0404990b
>> +#define DENALI_CTL_12_DATA 0x2b050405
>> +#define DENALI_CTL_13_DATA 0x0e0c081e
>> +#define DENALI_CTL_14_DATA 0x08090914
>> +#define DENALI_CTL_15_DATA 0x00fde718
>> +#define DENALI_CTL_16_DATA 0x00180a05
>> +#define DENALI_CTL_17_DATA 0x008b130e
>> +#define DENALI_CTL_18_DATA 0x01000118
>> +#define DENALI_CTL_19_DATA 0x0e032101
>> +#define DENALI_CTL_20_DATA 0x00000000
>> +#define DENALI_CTL_21_DATA 0x00000101
>> +#define DENALI_CTL_22_DATA 0x00000000
>> +#define DENALI_CTL_23_DATA 0x0a000000
>> +#define DENALI_CTL_24_DATA 0x00000000
>> +#define DENALI_CTL_25_DATA 0x01450100
>> +#define DENALI_CTL_26_DATA 0x00001c36
>> +#define DENALI_CTL_27_DATA 0x00000005
>> +#define DENALI_CTL_28_DATA 0x00170006
>> +#define DENALI_CTL_29_DATA 0x014e0300
>> +#define DENALI_CTL_30_DATA 0x03010000
>> +#define DENALI_CTL_31_DATA 0x000a0e00
>> +#define DENALI_CTL_32_DATA 0x04030200
>> +#define DENALI_CTL_33_DATA 0x0000031f
>> +#define DENALI_CTL_34_DATA 0x00070004
>> +#define DENALI_CTL_35_DATA 0x00000000
>> +#define DENALI_CTL_36_DATA 0x00000000
>> +#define DENALI_CTL_37_DATA 0x00000000
>> +#define DENALI_CTL_38_DATA 0x00000000
>> +#define DENALI_CTL_39_DATA 0x00000000
>> +#define DENALI_CTL_40_DATA 0x00000000
>> +#define DENALI_CTL_41_DATA 0x00000000
>> +#define DENALI_CTL_42_DATA 0x00000000
>> +#define DENALI_CTL_43_DATA 0x00000000
>> +#define DENALI_CTL_44_DATA 0x00000000
>> +#define DENALI_CTL_45_DATA 0x00000000
>> +#define DENALI_CTL_46_DATA 0x00000000
>> +#define DENALI_CTL_47_DATA 0x00000000
>> +#define DENALI_CTL_48_DATA 0x00000000
>> +#define DENALI_CTL_49_DATA 0x00000000
>> +#define DENALI_CTL_50_DATA 0x00000000
>> +#define DENALI_CTL_51_DATA 0x00000000
>> +#define DENALI_CTL_52_DATA 0x00000000
>> +#define DENALI_CTL_53_DATA 0x00000000
>> +#define DENALI_CTL_54_DATA 0x00000000
>> +#define DENALI_CTL_55_DATA 0x00000000
>> +#define DENALI_CTL_56_DATA 0x00000000
>> +#define DENALI_CTL_57_DATA 0x00000000
>> +#define DENALI_CTL_58_DATA 0x00000000
>> +#define DENALI_CTL_59_DATA 0x00000000
>> +#define DENALI_CTL_60_DATA 0x00000424
>> +#define DENALI_CTL_61_DATA 0x00000201
>> +#define DENALI_CTL_62_DATA 0x00001008
>> +#define DENALI_CTL_63_DATA 0x00000000
>> +#define DENALI_CTL_64_DATA 0x00000200
>> +#define DENALI_CTL_65_DATA 0x00000000
>> +#define DENALI_CTL_66_DATA 0x00000481
>> +#define DENALI_CTL_67_DATA 0x00000400
>> +#define DENALI_CTL_68_DATA 0x00000424
>> +#define DENALI_CTL_69_DATA 0x00000201
>> +#define DENALI_CTL_70_DATA 0x00001008
>> +#define DENALI_CTL_71_DATA 0x00000000
>> +#define DENALI_CTL_72_DATA 0x00000200
>> +#define DENALI_CTL_73_DATA 0x00000000
>> +#define DENALI_CTL_74_DATA 0x00000481
>> +#define DENALI_CTL_75_DATA 0x00000400
>> +#define DENALI_CTL_76_DATA 0x01010000
>> +#define DENALI_CTL_77_DATA 0x00000000
>> +#define DENALI_CTL_78_DATA 0x00000000
>> +#define DENALI_CTL_79_DATA 0x00000000
>> +#define DENALI_CTL_80_DATA 0x00000000
>> +#define DENALI_CTL_81_DATA 0x00000000
>> +#define DENALI_CTL_82_DATA 0x00000000
>> +#define DENALI_CTL_83_DATA 0x00000000
>> +#define DENALI_CTL_84_DATA 0x00000000
>> +#define DENALI_CTL_85_DATA 0x00000000
>> +#define DENALI_CTL_86_DATA 0x00000000
>> +#define DENALI_CTL_87_DATA 0x00000000
>> +#define DENALI_CTL_88_DATA 0x00000000
>> +#define DENALI_CTL_89_DATA 0x00000000
>> +#define DENALI_CTL_90_DATA 0x00000000
>> +#define DENALI_CTL_91_DATA 0x00000000
>> +#define DENALI_CTL_92_DATA 0x00000000
>> +#define DENALI_CTL_93_DATA 0x00000000
>> +#define DENALI_CTL_94_DATA 0x00000000
>> +#define DENALI_CTL_95_DATA 0x00000000
>> +#define DENALI_CTL_96_DATA 0x00000000
>> +#define DENALI_CTL_97_DATA 0x00000000
>> +#define DENALI_CTL_98_DATA 0x00000000
>> +#define DENALI_CTL_99_DATA 0x00000000
>> +#define DENALI_CTL_100_DATA 0x00000000
>> +#define DENALI_CTL_101_DATA 0x00000000
>> +#define DENALI_CTL_102_DATA 0x00000000
>> +#define DENALI_CTL_103_DATA 0x00000000
>> +#define DENALI_CTL_104_DATA 0x00000000
>> +#define DENALI_CTL_105_DATA 0x00000003
>> +#define DENALI_CTL_106_DATA 0x00000000
>> +#define DENALI_CTL_107_DATA 0x00000000
>> +#define DENALI_CTL_108_DATA 0x00000000
>> +#define DENALI_CTL_109_DATA 0x00000000
>> +#define DENALI_CTL_110_DATA 0x01000000
>> +#define DENALI_CTL_111_DATA 0x00040000
>> +#define DENALI_CTL_112_DATA 0x00800200
>> +#define DENALI_CTL_113_DATA 0x00000200
>> +#define DENALI_CTL_114_DATA 0x00000040
>> +#define DENALI_CTL_115_DATA 0x01000100
>> +#define DENALI_CTL_116_DATA 0x0a000002
>> +#define DENALI_CTL_117_DATA 0x0101ffff
>> +#define DENALI_CTL_118_DATA 0x01010101
>> +#define DENALI_CTL_119_DATA 0x01010101
>> +#define DENALI_CTL_120_DATA 0x0000010b
>> +#define DENALI_CTL_121_DATA 0x00000c01
>> +#define DENALI_CTL_122_DATA 0x00000000
>> +#define DENALI_CTL_123_DATA 0x00000000
>> +#define DENALI_CTL_124_DATA 0x00000000
>> +#define DENALI_CTL_125_DATA 0x00000000
>> +#define DENALI_CTL_126_DATA 0x00030300
>> +#define DENALI_CTL_127_DATA 0x00000000
>> +#define DENALI_CTL_128_DATA 0x00010001
>> +#define DENALI_CTL_129_DATA 0x00000000
>> +#define DENALI_CTL_130_DATA 0x00000000
>> +#define DENALI_CTL_131_DATA 0x00000000
>> +#define DENALI_CTL_132_DATA 0x00000000
>> +#define DENALI_CTL_133_DATA 0x00000000
>> +#define DENALI_CTL_134_DATA 0x00000000
>> +#define DENALI_CTL_135_DATA 0x00000000
>> +#define DENALI_CTL_136_DATA 0x00000000
>> +#define DENALI_CTL_137_DATA 0x00000000
>> +#define DENALI_CTL_138_DATA 0x00000000
>> +#define DENALI_CTL_139_DATA 0x00000000
>> +#define DENALI_CTL_140_DATA 0x00000000
>> +#define DENALI_CTL_141_DATA 0x00000000
>> +#define DENALI_CTL_142_DATA 0x00000000
>> +#define DENALI_CTL_143_DATA 0x00000000
>> +#define DENALI_CTL_144_DATA 0x00000000
>> +#define DENALI_CTL_145_DATA 0x00000000
>> +#define DENALI_CTL_146_DATA 0x00000000
>> +#define DENALI_CTL_147_DATA 0x00000000
>> +#define DENALI_CTL_148_DATA 0x00000000
>> +#define DENALI_CTL_149_DATA 0x00000000
>> +#define DENALI_CTL_150_DATA 0x00000000
>> +#define DENALI_CTL_151_DATA 0x00000000
>> +#define DENALI_CTL_152_DATA 0x00000000
>> +#define DENALI_CTL_153_DATA 0x00000000
>> +#define DENALI_CTL_154_DATA 0x00000000
>> +#define DENALI_CTL_155_DATA 0x00000000
>> +#define DENALI_CTL_156_DATA 0x00000000
>> +#define DENALI_CTL_157_DATA 0x00000000
>> +#define DENALI_CTL_158_DATA 0x00000000
>> +#define DENALI_CTL_159_DATA 0x00000000
>> +#define DENALI_CTL_160_DATA 0x00000000
>> +#define DENALI_CTL_161_DATA 0x02010102
>> +#define DENALI_CTL_162_DATA 0x0107070d
>> +#define DENALI_CTL_163_DATA 0x04040400
>> +#define DENALI_CTL_164_DATA 0x03000503
>> +#define DENALI_CTL_165_DATA 0x00000000
>> +#define DENALI_CTL_166_DATA 0x00000000
>> +#define DENALI_CTL_167_DATA 0x00000000
>> +#define DENALI_CTL_168_DATA 0x00000000
>> +#define DENALI_CTL_169_DATA 0x280d0000
>> +#define DENALI_CTL_170_DATA 0x01000000
>> +#define DENALI_CTL_171_DATA 0x00000000
>> +#define DENALI_CTL_172_DATA 0x00010001
>> +#define DENALI_CTL_173_DATA 0x00000000
>> +#define DENALI_CTL_174_DATA 0x00000000
>> +#define DENALI_CTL_175_DATA 0x00000000
>> +#define DENALI_CTL_176_DATA 0x00000000
>> +#define DENALI_CTL_177_DATA 0x00000000
>> +#define DENALI_CTL_178_DATA 0x00000000
>> +#define DENALI_CTL_179_DATA 0x00000000
>> +#define DENALI_CTL_180_DATA 0x00000000
>> +#define DENALI_CTL_181_DATA 0x01000000
>> +#define DENALI_CTL_182_DATA 0x00000001
>> +#define DENALI_CTL_183_DATA 0x00000100
>> +#define DENALI_CTL_184_DATA 0x00000101
>> +#define DENALI_CTL_185_DATA 0x67676701
>> +#define DENALI_CTL_186_DATA 0x67676767
>> +#define DENALI_CTL_187_DATA 0x67676767
>> +#define DENALI_CTL_188_DATA 0x67676767
>> +#define DENALI_CTL_189_DATA 0x67676767
>> +#define DENALI_CTL_190_DATA 0x67676767
>> +#define DENALI_CTL_191_DATA 0x67676767
>> +#define DENALI_CTL_192_DATA 0x67676767
>> +#define DENALI_CTL_193_DATA 0x67676767
>> +#define DENALI_CTL_194_DATA 0x01000067
>> +#define DENALI_CTL_195_DATA 0x00000001
>> +#define DENALI_CTL_196_DATA 0x00000101
>> +#define DENALI_CTL_197_DATA 0x00000000
>> +#define DENALI_CTL_198_DATA 0x00000000
>> +#define DENALI_CTL_199_DATA 0x00000000
>> +#define DENALI_CTL_200_DATA 0x00000000
>> +#define DENALI_CTL_201_DATA 0x00000000
>> +#define DENALI_CTL_202_DATA 0x00000000
>> +#define DENALI_CTL_203_DATA 0x00000000
>> +#define DENALI_CTL_204_DATA 0x00000000
>> +#define DENALI_CTL_205_DATA 0x00000000
>> +#define DENALI_CTL_206_DATA 0x00000000
>> +#define DENALI_CTL_207_DATA 0x00000000
>> +#define DENALI_CTL_208_DATA 0x00000001
>> +#define DENALI_CTL_209_DATA 0x00000000
>> +#define DENALI_CTL_210_DATA 0x007fffff
>> +#define DENALI_CTL_211_DATA 0x00000000
>> +#define DENALI_CTL_212_DATA 0x007fffff
>> +#define DENALI_CTL_213_DATA 0x00000000
>> +#define DENALI_CTL_214_DATA 0x007fffff
>> +#define DENALI_CTL_215_DATA 0x00000000
>> +#define DENALI_CTL_216_DATA 0x007fffff
>> +#define DENALI_CTL_217_DATA 0x00000000
>> +#define DENALI_CTL_218_DATA 0x007fffff
>> +#define DENALI_CTL_219_DATA 0x00000000
>> +#define DENALI_CTL_220_DATA 0x007fffff
>> +#define DENALI_CTL_221_DATA 0x00000000
>> +#define DENALI_CTL_222_DATA 0x007fffff
>> +#define DENALI_CTL_223_DATA 0x00000000
>> +#define DENALI_CTL_224_DATA 0x037fffff
>> +#define DENALI_CTL_225_DATA 0xffffffff
>> +#define DENALI_CTL_226_DATA 0x000f000f
>> +#define DENALI_CTL_227_DATA 0x00ffff03
>> +#define DENALI_CTL_228_DATA 0x000fffff
>> +#define DENALI_CTL_229_DATA 0x0003000f
>> +#define DENALI_CTL_230_DATA 0xffffffff
>> +#define DENALI_CTL_231_DATA 0x000f000f
>> +#define DENALI_CTL_232_DATA 0x00ffff03
>> +#define DENALI_CTL_233_DATA 0x000fffff
>> +#define DENALI_CTL_234_DATA 0x0003000f
>> +#define DENALI_CTL_235_DATA 0xffffffff
>> +#define DENALI_CTL_236_DATA 0x000f000f
>> +#define DENALI_CTL_237_DATA 0x00ffff03
>> +#define DENALI_CTL_238_DATA 0x000fffff
>> +#define DENALI_CTL_239_DATA 0x0003000f
>> +#define DENALI_CTL_240_DATA 0xffffffff
>> +#define DENALI_CTL_241_DATA 0x000f000f
>> +#define DENALI_CTL_242_DATA 0x00ffff03
>> +#define DENALI_CTL_243_DATA 0x000fffff
>> +#define DENALI_CTL_244_DATA 0x6407000f
>> +#define DENALI_CTL_245_DATA 0x01640001
>> +#define DENALI_CTL_246_DATA 0x00000000
>> +#define DENALI_CTL_247_DATA 0x00000000
>> +#define DENALI_CTL_248_DATA 0x00001700
>> +#define DENALI_CTL_249_DATA 0x00386c05
>> +#define DENALI_CTL_250_DATA 0x02000200
>> +#define DENALI_CTL_251_DATA 0x02000200
>> +#define DENALI_CTL_252_DATA 0x0000386c
>> +#define DENALI_CTL_253_DATA 0x00023438
>> +#define DENALI_CTL_254_DATA 0x02020d10
>> +#define DENALI_CTL_255_DATA 0x00140303
>> +#define DENALI_CTL_256_DATA 0x00000000
>> +#define DENALI_CTL_257_DATA 0x00000000
>> +#define DENALI_CTL_258_DATA 0x00001403
>> +#define DENALI_CTL_259_DATA 0x00000000
>> +#define DENALI_CTL_260_DATA 0x00000000
>> +#define DENALI_CTL_261_DATA 0x00000000
>> +#define DENALI_CTL_262_DATA 0x00000000
>> +#define DENALI_CTL_263_DATA 0x0d010000
>> +#define DENALI_CTL_264_DATA 0x00000008
>> diff --git a/board/sifive/fu540/regconfig-phy.h
>b/board/sifive/fu540/regconfig-phy.h
>> new file mode 100644
>> index 0000000000..62163290b9
>> --- /dev/null
>> +++ b/board/sifive/fu540/regconfig-phy.h
>> @@ -0,0 +1,1220 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright (c) 2019 SiFive, Inc
>> + */
>> +
>> +#define DENALI_PHY_00_DATA 0x31706542
>> +#define DENALI_PHY_01_DATA 0x0004c008
>> +#define DENALI_PHY_02_DATA 0x000000da
>> +#define DENALI_PHY_03_DATA 0x00000000
>> +#define DENALI_PHY_04_DATA 0x00000000
>> +#define DENALI_PHY_05_DATA 0x00010000
>> +#define DENALI_PHY_06_DATA 0x01DDDD90
>> +#define DENALI_PHY_07_DATA 0x01DDDD90
>> +#define DENALI_PHY_08_DATA 0x01030000
>> +#define DENALI_PHY_09_DATA 0x01000000
>> +#define DENALI_PHY_10_DATA 0x00c00000
>> +#define DENALI_PHY_11_DATA 0x00000007
>> +#define DENALI_PHY_12_DATA 0x00000000
>> +#define DENALI_PHY_13_DATA 0x00000000
>> +#define DENALI_PHY_14_DATA 0x04000408
>> +#define DENALI_PHY_15_DATA 0x00000408
>> +#define DENALI_PHY_16_DATA 0x00e4e400
>> +#define DENALI_PHY_17_DATA 0x00000000
>> +#define DENALI_PHY_18_DATA 0x00000000
>> +#define DENALI_PHY_19_DATA 0x00000000
>> +#define DENALI_PHY_20_DATA 0x00000000
>> +#define DENALI_PHY_21_DATA 0x00000000
>> +#define DENALI_PHY_22_DATA 0x00000000
>> +#define DENALI_PHY_23_DATA 0x00000000
>> +#define DENALI_PHY_24_DATA 0x00000000
>> +#define DENALI_PHY_25_DATA 0x00000000
>> +#define DENALI_PHY_26_DATA 0x00000000
>> +#define DENALI_PHY_27_DATA 0x00000000
>> +#define DENALI_PHY_28_DATA 0x00000000
>> +#define DENALI_PHY_29_DATA 0x00000000
>> +#define DENALI_PHY_30_DATA 0x00000000
>> +#define DENALI_PHY_31_DATA 0x00000000
>> +#define DENALI_PHY_32_DATA 0x00000000
>> +#define DENALI_PHY_33_DATA 0x00200000
>> +#define DENALI_PHY_34_DATA 0x00000000
>> +#define DENALI_PHY_35_DATA 0x00000000
>> +#define DENALI_PHY_36_DATA 0x00000000
>> +#define DENALI_PHY_37_DATA 0x00000000
>> +#define DENALI_PHY_38_DATA 0x00000000
>> +#define DENALI_PHY_39_DATA 0x00000000
>> +#define DENALI_PHY_40_DATA 0x02800280
>> +#define DENALI_PHY_41_DATA 0x02800280
>> +#define DENALI_PHY_42_DATA 0x02800280
>> +#define DENALI_PHY_43_DATA 0x02800280
>> +#define DENALI_PHY_44_DATA 0x00000280
>> +#define DENALI_PHY_45_DATA 0x00000000
>> +#define DENALI_PHY_46_DATA 0x00000000
>> +#define DENALI_PHY_47_DATA 0x00000000
>> +#define DENALI_PHY_48_DATA 0x00000000
>> +#define DENALI_PHY_49_DATA 0x00000000
>> +#define DENALI_PHY_50_DATA 0x00800080
>> +#define DENALI_PHY_51_DATA 0x00800080
>> +#define DENALI_PHY_52_DATA 0x00800080
>> +#define DENALI_PHY_53_DATA 0x00800080
>> +#define DENALI_PHY_54_DATA 0x00800080
>> +#define DENALI_PHY_55_DATA 0x00800080
>> +#define DENALI_PHY_56_DATA 0x00800080
>> +#define DENALI_PHY_57_DATA 0x00800080
>> +#define DENALI_PHY_58_DATA 0x00800080
>> +#define DENALI_PHY_59_DATA 0x000100da
>> +#define DENALI_PHY_60_DATA 0x01000200
>> +#define DENALI_PHY_61_DATA 0x00000000
>> +#define DENALI_PHY_62_DATA 0x00000000
>> +#define DENALI_PHY_63_DATA 0x00000002
>> +#define DENALI_PHY_64_DATA 0x51313152
>> +#define DENALI_PHY_65_DATA 0x80013130
>> +#define DENALI_PHY_66_DATA 0x02000080
>> +#define DENALI_PHY_67_DATA 0x00100001
>> +#define DENALI_PHY_68_DATA 0x0c064208
>> +#define DENALI_PHY_69_DATA 0x000f0c0f
>> +#define DENALI_PHY_70_DATA 0x01000140
>> +#define DENALI_PHY_71_DATA 0x0000000c
>> +#define DENALI_PHY_72_DATA 0x00000000
>> +#define DENALI_PHY_73_DATA 0x00000000
>> +#define DENALI_PHY_74_DATA 0x00000000
>> +#define DENALI_PHY_75_DATA 0x00000000
>> +#define DENALI_PHY_76_DATA 0x00000000
>> +#define DENALI_PHY_77_DATA 0x00000000
>> +#define DENALI_PHY_78_DATA 0x00000000
>> +#define DENALI_PHY_79_DATA 0x00000000
>> +#define DENALI_PHY_80_DATA 0x00000000
>> +#define DENALI_PHY_81_DATA 0x00000000
>> +#define DENALI_PHY_82_DATA 0x00000000
>> +#define DENALI_PHY_83_DATA 0x00000000
>> +#define DENALI_PHY_84_DATA 0x00000000
>> +#define DENALI_PHY_85_DATA 0x00000000
>> +#define DENALI_PHY_86_DATA 0x00000000
>> +#define DENALI_PHY_87_DATA 0x00000000
>> +#define DENALI_PHY_88_DATA 0x00000000
>> +#define DENALI_PHY_89_DATA 0x00000000
>> +#define DENALI_PHY_90_DATA 0x00000000
>> +#define DENALI_PHY_91_DATA 0x00000000
>> +#define DENALI_PHY_92_DATA 0x00000000
>> +#define DENALI_PHY_93_DATA 0x00000000
>> +#define DENALI_PHY_94_DATA 0x00000000
>> +#define DENALI_PHY_95_DATA 0x00000000
>> +#define DENALI_PHY_96_DATA 0x00000000
>> +#define DENALI_PHY_97_DATA 0x00000000
>> +#define DENALI_PHY_98_DATA 0x00000000
>> +#define DENALI_PHY_99_DATA 0x00000000
>> +#define DENALI_PHY_100_DATA 0x00000000
>> +#define DENALI_PHY_101_DATA 0x00000000
>> +#define DENALI_PHY_102_DATA 0x00000000
>> +#define DENALI_PHY_103_DATA 0x00000000
>> +#define DENALI_PHY_104_DATA 0x00000000
>> +#define DENALI_PHY_105_DATA 0x00000000
>> +#define DENALI_PHY_106_DATA 0x00000000
>> +#define DENALI_PHY_107_DATA 0x00000000
>> +#define DENALI_PHY_108_DATA 0x00000000
>> +#define DENALI_PHY_109_DATA 0x00000000
>> +#define DENALI_PHY_110_DATA 0x00000000
>> +#define DENALI_PHY_111_DATA 0x00000000
>> +#define DENALI_PHY_112_DATA 0x00000000
>> +#define DENALI_PHY_113_DATA 0x00000000
>> +#define DENALI_PHY_114_DATA 0x00000000
>> +#define DENALI_PHY_115_DATA 0x00000000
>> +#define DENALI_PHY_116_DATA 0x00000000
>> +#define DENALI_PHY_117_DATA 0x00000000
>> +#define DENALI_PHY_118_DATA 0x00000000
>> +#define DENALI_PHY_119_DATA 0x00000000
>> +#define DENALI_PHY_120_DATA 0x00000000
>> +#define DENALI_PHY_121_DATA 0x00000000
>> +#define DENALI_PHY_122_DATA 0x00000000
>> +#define DENALI_PHY_123_DATA 0x00000000
>> +#define DENALI_PHY_124_DATA 0x00000000
>> +#define DENALI_PHY_125_DATA 0x00000000
>> +#define DENALI_PHY_126_DATA 0x00000000
>> +#define DENALI_PHY_127_DATA 0x00000000
>> +#define DENALI_PHY_128_DATA 0x40263571
>> +#define DENALI_PHY_129_DATA 0x0004c008
>> +#define DENALI_PHY_130_DATA 0x000000da
>> +#define DENALI_PHY_131_DATA 0x00000000
>> +#define DENALI_PHY_132_DATA 0x00000000
>> +#define DENALI_PHY_133_DATA 0x00010000
>> +#define DENALI_PHY_134_DATA 0x01DDDD90
>> +#define DENALI_PHY_135_DATA 0x01DDDD90
>> +#define DENALI_PHY_136_DATA 0x01030000
>> +#define DENALI_PHY_137_DATA 0x01000000
>> +#define DENALI_PHY_138_DATA 0x00c00000
>> +#define DENALI_PHY_139_DATA 0x00000007
>> +#define DENALI_PHY_140_DATA 0x00000000
>> +#define DENALI_PHY_141_DATA 0x00000000
>> +#define DENALI_PHY_142_DATA 0x04000408
>> +#define DENALI_PHY_143_DATA 0x00000408
>> +#define DENALI_PHY_144_DATA 0x00e4e400
>> +#define DENALI_PHY_145_DATA 0x00000000
>> +#define DENALI_PHY_146_DATA 0x00000000
>> +#define DENALI_PHY_147_DATA 0x00000000
>> +#define DENALI_PHY_148_DATA 0x00000000
>> +#define DENALI_PHY_149_DATA 0x00000000
>> +#define DENALI_PHY_150_DATA 0x00000000
>> +#define DENALI_PHY_151_DATA 0x00000000
>> +#define DENALI_PHY_152_DATA 0x00000000
>> +#define DENALI_PHY_153_DATA 0x00000000
>> +#define DENALI_PHY_154_DATA 0x00000000
>> +#define DENALI_PHY_155_DATA 0x00000000
>> +#define DENALI_PHY_156_DATA 0x00000000
>> +#define DENALI_PHY_157_DATA 0x00000000
>> +#define DENALI_PHY_158_DATA 0x00000000
>> +#define DENALI_PHY_159_DATA 0x00000000
>> +#define DENALI_PHY_160_DATA 0x00000000
>> +#define DENALI_PHY_161_DATA 0x00200000
>> +#define DENALI_PHY_162_DATA 0x00000000
>> +#define DENALI_PHY_163_DATA 0x00000000
>> +#define DENALI_PHY_164_DATA 0x00000000
>> +#define DENALI_PHY_165_DATA 0x00000000
>> +#define DENALI_PHY_166_DATA 0x00000000
>> +#define DENALI_PHY_167_DATA 0x00000000
>> +#define DENALI_PHY_168_DATA 0x02800280
>> +#define DENALI_PHY_169_DATA 0x02800280
>> +#define DENALI_PHY_170_DATA 0x02800280
>> +#define DENALI_PHY_171_DATA 0x02800280
>> +#define DENALI_PHY_172_DATA 0x00000280
>> +#define DENALI_PHY_173_DATA 0x00000000
>> +#define DENALI_PHY_174_DATA 0x00000000
>> +#define DENALI_PHY_175_DATA 0x00000000
>> +#define DENALI_PHY_176_DATA 0x00000000
>> +#define DENALI_PHY_177_DATA 0x00000000
>> +#define DENALI_PHY_178_DATA 0x00800080
>> +#define DENALI_PHY_179_DATA 0x00800080
>> +#define DENALI_PHY_180_DATA 0x00800080
>> +#define DENALI_PHY_181_DATA 0x00800080
>> +#define DENALI_PHY_182_DATA 0x00800080
>> +#define DENALI_PHY_183_DATA 0x00800080
>> +#define DENALI_PHY_184_DATA 0x00800080
>> +#define DENALI_PHY_185_DATA 0x00800080
>> +#define DENALI_PHY_186_DATA 0x00800080
>> +#define DENALI_PHY_187_DATA 0x000100da
>> +#define DENALI_PHY_188_DATA 0x01000200
>> +#define DENALI_PHY_189_DATA 0x00000000
>> +#define DENALI_PHY_190_DATA 0x00000000
>> +#define DENALI_PHY_191_DATA 0x00000002
>> +#define DENALI_PHY_192_DATA 0x51313152
>> +#define DENALI_PHY_193_DATA 0x80013130
>> +#define DENALI_PHY_194_DATA 0x02000080
>> +#define DENALI_PHY_195_DATA 0x00100001
>> +#define DENALI_PHY_196_DATA 0x0c064208
>> +#define DENALI_PHY_197_DATA 0x000f0c0f
>> +#define DENALI_PHY_198_DATA 0x01000140
>> +#define DENALI_PHY_199_DATA 0x0000000c
>> +#define DENALI_PHY_200_DATA 0x00000000
>> +#define DENALI_PHY_201_DATA 0x00000000
>> +#define DENALI_PHY_202_DATA 0x00000000
>> +#define DENALI_PHY_203_DATA 0x00000000
>> +#define DENALI_PHY_204_DATA 0x00000000
>> +#define DENALI_PHY_205_DATA 0x00000000
>> +#define DENALI_PHY_206_DATA 0x00000000
>> +#define DENALI_PHY_207_DATA 0x00000000
>> +#define DENALI_PHY_208_DATA 0x00000000
>> +#define DENALI_PHY_209_DATA 0x00000000
>> +#define DENALI_PHY_210_DATA 0x00000000
>> +#define DENALI_PHY_211_DATA 0x00000000
>> +#define DENALI_PHY_212_DATA 0x00000000
>> +#define DENALI_PHY_213_DATA 0x00000000
>> +#define DENALI_PHY_214_DATA 0x00000000
>> +#define DENALI_PHY_215_DATA 0x00000000
>> +#define DENALI_PHY_216_DATA 0x00000000
>> +#define DENALI_PHY_217_DATA 0x00000000
>> +#define DENALI_PHY_218_DATA 0x00000000
>> +#define DENALI_PHY_219_DATA 0x00000000
>> +#define DENALI_PHY_220_DATA 0x00000000
>> +#define DENALI_PHY_221_DATA 0x00000000
>> +#define DENALI_PHY_222_DATA 0x00000000
>> +#define DENALI_PHY_223_DATA 0x00000000
>> +#define DENALI_PHY_224_DATA 0x00000000
>> +#define DENALI_PHY_225_DATA 0x00000000
>> +#define DENALI_PHY_226_DATA 0x00000000
>> +#define DENALI_PHY_227_DATA 0x00000000
>> +#define DENALI_PHY_228_DATA 0x00000000
>> +#define DENALI_PHY_229_DATA 0x00000000
>> +#define DENALI_PHY_230_DATA 0x00000000
>> +#define DENALI_PHY_231_DATA 0x00000000
>> +#define DENALI_PHY_232_DATA 0x00000000
>> +#define DENALI_PHY_233_DATA 0x00000000
>> +#define DENALI_PHY_234_DATA 0x00000000
>> +#define DENALI_PHY_235_DATA 0x00000000
>> +#define DENALI_PHY_236_DATA 0x00000000
>> +#define DENALI_PHY_237_DATA 0x00000000
>> +#define DENALI_PHY_238_DATA 0x00000000
>> +#define DENALI_PHY_239_DATA 0x00000000
>> +#define DENALI_PHY_240_DATA 0x00000000
>> +#define DENALI_PHY_241_DATA 0x00000000
>> +#define DENALI_PHY_242_DATA 0x00000000
>> +#define DENALI_PHY_243_DATA 0x00000000
>> +#define DENALI_PHY_244_DATA 0x00000000
>> +#define DENALI_PHY_245_DATA 0x00000000
>> +#define DENALI_PHY_246_DATA 0x00000000
>> +#define DENALI_PHY_247_DATA 0x00000000
>> +#define DENALI_PHY_248_DATA 0x00000000
>> +#define DENALI_PHY_249_DATA 0x00000000
>> +#define DENALI_PHY_250_DATA 0x00000000
>> +#define DENALI_PHY_251_DATA 0x00000000
>> +#define DENALI_PHY_252_DATA 0x00000000
>> +#define DENALI_PHY_253_DATA 0x00000000
>> +#define DENALI_PHY_254_DATA 0x00000000
>> +#define DENALI_PHY_255_DATA 0x00000000
>> +#define DENALI_PHY_256_DATA 0x46052371
>> +#define DENALI_PHY_257_DATA 0x0004c008
>> +#define DENALI_PHY_258_DATA 0x000000da
>> +#define DENALI_PHY_259_DATA 0x00000000
>> +#define DENALI_PHY_260_DATA 0x00000000
>> +#define DENALI_PHY_261_DATA 0x00010000
>> +#define DENALI_PHY_262_DATA 0x01DDDD90
>> +#define DENALI_PHY_263_DATA 0x01DDDD90
>> +#define DENALI_PHY_264_DATA 0x01030000
>> +#define DENALI_PHY_265_DATA 0x01000000
>> +#define DENALI_PHY_266_DATA 0x00c00000
>> +#define DENALI_PHY_267_DATA 0x00000007
>> +#define DENALI_PHY_268_DATA 0x00000000
>> +#define DENALI_PHY_269_DATA 0x00000000
>> +#define DENALI_PHY_270_DATA 0x04000408
>> +#define DENALI_PHY_271_DATA 0x00000408
>> +#define DENALI_PHY_272_DATA 0x00e4e400
>> +#define DENALI_PHY_273_DATA 0x00000000
>> +#define DENALI_PHY_274_DATA 0x00000000
>> +#define DENALI_PHY_275_DATA 0x00000000
>> +#define DENALI_PHY_276_DATA 0x00000000
>> +#define DENALI_PHY_277_DATA 0x00000000
>> +#define DENALI_PHY_278_DATA 0x00000000
>> +#define DENALI_PHY_279_DATA 0x00000000
>> +#define DENALI_PHY_280_DATA 0x00000000
>> +#define DENALI_PHY_281_DATA 0x00000000
>> +#define DENALI_PHY_282_DATA 0x00000000
>> +#define DENALI_PHY_283_DATA 0x00000000
>> +#define DENALI_PHY_284_DATA 0x00000000
>> +#define DENALI_PHY_285_DATA 0x00000000
>> +#define DENALI_PHY_286_DATA 0x00000000
>> +#define DENALI_PHY_287_DATA 0x00000000
>> +#define DENALI_PHY_288_DATA 0x00000000
>> +#define DENALI_PHY_289_DATA 0x00200000
>> +#define DENALI_PHY_290_DATA 0x00000000
>> +#define DENALI_PHY_291_DATA 0x00000000
>> +#define DENALI_PHY_292_DATA 0x00000000
>> +#define DENALI_PHY_293_DATA 0x00000000
>> +#define DENALI_PHY_294_DATA 0x00000000
>> +#define DENALI_PHY_295_DATA 0x00000000
>> +#define DENALI_PHY_296_DATA 0x02800280
>> +#define DENALI_PHY_297_DATA 0x02800280
>> +#define DENALI_PHY_298_DATA 0x02800280
>> +#define DENALI_PHY_299_DATA 0x02800280
>> +#define DENALI_PHY_300_DATA 0x00000280
>> +#define DENALI_PHY_301_DATA 0x00000000
>> +#define DENALI_PHY_302_DATA 0x00000000
>> +#define DENALI_PHY_303_DATA 0x00000000
>> +#define DENALI_PHY_304_DATA 0x00000000
>> +#define DENALI_PHY_305_DATA 0x00000000
>> +#define DENALI_PHY_306_DATA 0x00800080
>> +#define DENALI_PHY_307_DATA 0x00800080
>> +#define DENALI_PHY_308_DATA 0x00800080
>> +#define DENALI_PHY_309_DATA 0x00800080
>> +#define DENALI_PHY_310_DATA 0x00800080
>> +#define DENALI_PHY_311_DATA 0x00800080
>> +#define DENALI_PHY_312_DATA 0x00800080
>> +#define DENALI_PHY_313_DATA 0x00800080
>> +#define DENALI_PHY_314_DATA 0x00800080
>> +#define DENALI_PHY_315_DATA 0x000100da
>> +#define DENALI_PHY_316_DATA 0x00000200
>> +#define DENALI_PHY_317_DATA 0x00000000
>> +#define DENALI_PHY_318_DATA 0x00000000
>> +#define DENALI_PHY_319_DATA 0x00000002
>> +#define DENALI_PHY_320_DATA 0x51313152
>> +#define DENALI_PHY_321_DATA 0x80013130
>> +#define DENALI_PHY_322_DATA 0x02000080
>> +#define DENALI_PHY_323_DATA 0x00100001
>> +#define DENALI_PHY_324_DATA 0x0c064208
>> +#define DENALI_PHY_325_DATA 0x000f0c0f
>> +#define DENALI_PHY_326_DATA 0x01000140
>> +#define DENALI_PHY_327_DATA 0x0000000c
>> +#define DENALI_PHY_328_DATA 0x00000000
>> +#define DENALI_PHY_329_DATA 0x00000000
>> +#define DENALI_PHY_330_DATA 0x00000000
>> +#define DENALI_PHY_331_DATA 0x00000000
>> +#define DENALI_PHY_332_DATA 0x00000000
>> +#define DENALI_PHY_333_DATA 0x00000000
>> +#define DENALI_PHY_334_DATA 0x00000000
>> +#define DENALI_PHY_335_DATA 0x00000000
>> +#define DENALI_PHY_336_DATA 0x00000000
>> +#define DENALI_PHY_337_DATA 0x00000000
>> +#define DENALI_PHY_338_DATA 0x00000000
>> +#define DENALI_PHY_339_DATA 0x00000000
>> +#define DENALI_PHY_340_DATA 0x00000000
>> +#define DENALI_PHY_341_DATA 0x00000000
>> +#define DENALI_PHY_342_DATA 0x00000000
>> +#define DENALI_PHY_343_DATA 0x00000000
>> +#define DENALI_PHY_344_DATA 0x00000000
>> +#define DENALI_PHY_345_DATA 0x00000000
>> +#define DENALI_PHY_346_DATA 0x00000000
>> +#define DENALI_PHY_347_DATA 0x00000000
>> +#define DENALI_PHY_348_DATA 0x00000000
>> +#define DENALI_PHY_349_DATA 0x00000000
>> +#define DENALI_PHY_350_DATA 0x00000000
>> +#define DENALI_PHY_351_DATA 0x00000000
>> +#define DENALI_PHY_352_DATA 0x00000000
>> +#define DENALI_PHY_353_DATA 0x00000000
>> +#define DENALI_PHY_354_DATA 0x00000000
>> +#define DENALI_PHY_355_DATA 0x00000000
>> +#define DENALI_PHY_356_DATA 0x00000000
>> +#define DENALI_PHY_357_DATA 0x00000000
>> +#define DENALI_PHY_358_DATA 0x00000000
>> +#define DENALI_PHY_359_DATA 0x00000000
>> +#define DENALI_PHY_360_DATA 0x00000000
>> +#define DENALI_PHY_361_DATA 0x00000000
>> +#define DENALI_PHY_362_DATA 0x00000000
>> +#define DENALI_PHY_363_DATA 0x00000000
>> +#define DENALI_PHY_364_DATA 0x00000000
>> +#define DENALI_PHY_365_DATA 0x00000000
>> +#define DENALI_PHY_366_DATA 0x00000000
>> +#define DENALI_PHY_367_DATA 0x00000000
>> +#define DENALI_PHY_368_DATA 0x00000000
>> +#define DENALI_PHY_369_DATA 0x00000000
>> +#define DENALI_PHY_370_DATA 0x00000000
>> +#define DENALI_PHY_371_DATA 0x00000000
>> +#define DENALI_PHY_372_DATA 0x00000000
>> +#define DENALI_PHY_373_DATA 0x00000000
>> +#define DENALI_PHY_374_DATA 0x00000000
>> +#define DENALI_PHY_375_DATA 0x00000000
>> +#define DENALI_PHY_376_DATA 0x00000000
>> +#define DENALI_PHY_377_DATA 0x00000000
>> +#define DENALI_PHY_378_DATA 0x00000000
>> +#define DENALI_PHY_379_DATA 0x00000000
>> +#define DENALI_PHY_380_DATA 0x00000000
>> +#define DENALI_PHY_381_DATA 0x00000000
>> +#define DENALI_PHY_382_DATA 0x00000000
>> +#define DENALI_PHY_383_DATA 0x00000000
>> +#define DENALI_PHY_384_DATA 0x37654120
>> +#define DENALI_PHY_385_DATA 0x0004c008
>> +#define DENALI_PHY_386_DATA 0x000000da
>> +#define DENALI_PHY_387_DATA 0x00000000
>> +#define DENALI_PHY_388_DATA 0x00000000
>> +#define DENALI_PHY_389_DATA 0x00010000
>> +#define DENALI_PHY_390_DATA 0x01DDDD90
>> +#define DENALI_PHY_391_DATA 0x01DDDD90
>> +#define DENALI_PHY_392_DATA 0x01030000
>> +#define DENALI_PHY_393_DATA 0x01000000
>> +#define DENALI_PHY_394_DATA 0x00c00000
>> +#define DENALI_PHY_395_DATA 0x00000007
>> +#define DENALI_PHY_396_DATA 0x00000000
>> +#define DENALI_PHY_397_DATA 0x00000000
>> +#define DENALI_PHY_398_DATA 0x04000408
>> +#define DENALI_PHY_399_DATA 0x00000408
>> +#define DENALI_PHY_400_DATA 0x00e4e400
>> +#define DENALI_PHY_401_DATA 0x00000000
>> +#define DENALI_PHY_402_DATA 0x00000000
>> +#define DENALI_PHY_403_DATA 0x00000000
>> +#define DENALI_PHY_404_DATA 0x00000000
>> +#define DENALI_PHY_405_DATA 0x00000000
>> +#define DENALI_PHY_406_DATA 0x00000000
>> +#define DENALI_PHY_407_DATA 0x00000000
>> +#define DENALI_PHY_408_DATA 0x00000000
>> +#define DENALI_PHY_409_DATA 0x00000000
>> +#define DENALI_PHY_410_DATA 0x00000000
>> +#define DENALI_PHY_411_DATA 0x00000000
>> +#define DENALI_PHY_412_DATA 0x00000000
>> +#define DENALI_PHY_413_DATA 0x00000000
>> +#define DENALI_PHY_414_DATA 0x00000000
>> +#define DENALI_PHY_415_DATA 0x00000000
>> +#define DENALI_PHY_416_DATA 0x00000000
>> +#define DENALI_PHY_417_DATA 0x00200000
>> +#define DENALI_PHY_418_DATA 0x00000000
>> +#define DENALI_PHY_419_DATA 0x00000000
>> +#define DENALI_PHY_420_DATA 0x00000000
>> +#define DENALI_PHY_421_DATA 0x00000000
>> +#define DENALI_PHY_422_DATA 0x00000000
>> +#define DENALI_PHY_423_DATA 0x00000000
>> +#define DENALI_PHY_424_DATA 0x02800280
>> +#define DENALI_PHY_425_DATA 0x02800280
>> +#define DENALI_PHY_426_DATA 0x02800280
>> +#define DENALI_PHY_427_DATA 0x02800280
>> +#define DENALI_PHY_428_DATA 0x00000280
>> +#define DENALI_PHY_429_DATA 0x00000000
>> +#define DENALI_PHY_430_DATA 0x00000000
>> +#define DENALI_PHY_431_DATA 0x00000000
>> +#define DENALI_PHY_432_DATA 0x00000000
>> +#define DENALI_PHY_433_DATA 0x00000000
>> +#define DENALI_PHY_434_DATA 0x00800080
>> +#define DENALI_PHY_435_DATA 0x00800080
>> +#define DENALI_PHY_436_DATA 0x00800080
>> +#define DENALI_PHY_437_DATA 0x00800080
>> +#define DENALI_PHY_438_DATA 0x00800080
>> +#define DENALI_PHY_439_DATA 0x00800080
>> +#define DENALI_PHY_440_DATA 0x00800080
>> +#define DENALI_PHY_441_DATA 0x00800080
>> +#define DENALI_PHY_442_DATA 0x00800080
>> +#define DENALI_PHY_443_DATA 0x000100da
>> +#define DENALI_PHY_444_DATA 0x00000200
>> +#define DENALI_PHY_445_DATA 0x00000000
>> +#define DENALI_PHY_446_DATA 0x00000000
>> +#define DENALI_PHY_447_DATA 0x00000002
>> +#define DENALI_PHY_448_DATA 0x51313152
>> +#define DENALI_PHY_449_DATA 0x80013130
>> +#define DENALI_PHY_450_DATA 0x02000080
>> +#define DENALI_PHY_451_DATA 0x00100001
>> +#define DENALI_PHY_452_DATA 0x0c064208
>> +#define DENALI_PHY_453_DATA 0x000f0c0f
>> +#define DENALI_PHY_454_DATA 0x01000140
>> +#define DENALI_PHY_455_DATA 0x0000000c
>> +#define DENALI_PHY_456_DATA 0x00000000
>> +#define DENALI_PHY_457_DATA 0x00000000
>> +#define DENALI_PHY_458_DATA 0x00000000
>> +#define DENALI_PHY_459_DATA 0x00000000
>> +#define DENALI_PHY_460_DATA 0x00000000
>> +#define DENALI_PHY_461_DATA 0x00000000
>> +#define DENALI_PHY_462_DATA 0x00000000
>> +#define DENALI_PHY_463_DATA 0x00000000
>> +#define DENALI_PHY_464_DATA 0x00000000
>> +#define DENALI_PHY_465_DATA 0x00000000
>> +#define DENALI_PHY_466_DATA 0x00000000
>> +#define DENALI_PHY_467_DATA 0x00000000
>> +#define DENALI_PHY_468_DATA 0x00000000
>> +#define DENALI_PHY_469_DATA 0x00000000
>> +#define DENALI_PHY_470_DATA 0x00000000
>> +#define DENALI_PHY_471_DATA 0x00000000
>> +#define DENALI_PHY_472_DATA 0x00000000
>> +#define DENALI_PHY_473_DATA 0x00000000
>> +#define DENALI_PHY_474_DATA 0x00000000
>> +#define DENALI_PHY_475_DATA 0x00000000
>> +#define DENALI_PHY_476_DATA 0x00000000
>> +#define DENALI_PHY_477_DATA 0x00000000
>> +#define DENALI_PHY_478_DATA 0x00000000
>> +#define DENALI_PHY_479_DATA 0x00000000
>> +#define DENALI_PHY_480_DATA 0x00000000
>> +#define DENALI_PHY_481_DATA 0x00000000
>> +#define DENALI_PHY_482_DATA 0x00000000
>> +#define DENALI_PHY_483_DATA 0x00000000
>> +#define DENALI_PHY_484_DATA 0x00000000
>> +#define DENALI_PHY_485_DATA 0x00000000
>> +#define DENALI_PHY_486_DATA 0x00000000
>> +#define DENALI_PHY_487_DATA 0x00000000
>> +#define DENALI_PHY_488_DATA 0x00000000
>> +#define DENALI_PHY_489_DATA 0x00000000
>> +#define DENALI_PHY_490_DATA 0x00000000
>> +#define DENALI_PHY_491_DATA 0x00000000
>> +#define DENALI_PHY_492_DATA 0x00000000
>> +#define DENALI_PHY_493_DATA 0x00000000
>> +#define DENALI_PHY_494_DATA 0x00000000
>> +#define DENALI_PHY_495_DATA 0x00000000
>> +#define DENALI_PHY_496_DATA 0x00000000
>> +#define DENALI_PHY_497_DATA 0x00000000
>> +#define DENALI_PHY_498_DATA 0x00000000
>> +#define DENALI_PHY_499_DATA 0x00000000
>> +#define DENALI_PHY_500_DATA 0x00000000
>> +#define DENALI_PHY_501_DATA 0x00000000
>> +#define DENALI_PHY_502_DATA 0x00000000
>> +#define DENALI_PHY_503_DATA 0x00000000
>> +#define DENALI_PHY_504_DATA 0x00000000
>> +#define DENALI_PHY_505_DATA 0x00000000
>> +#define DENALI_PHY_506_DATA 0x00000000
>> +#define DENALI_PHY_507_DATA 0x00000000
>> +#define DENALI_PHY_508_DATA 0x00000000
>> +#define DENALI_PHY_509_DATA 0x00000000
>> +#define DENALI_PHY_510_DATA 0x00000000
>> +#define DENALI_PHY_511_DATA 0x00000000
>> +#define DENALI_PHY_512_DATA 0x24316750
>> +#define DENALI_PHY_513_DATA 0x0004c008
>> +#define DENALI_PHY_514_DATA 0x000000da
>> +#define DENALI_PHY_515_DATA 0x00000000
>> +#define DENALI_PHY_516_DATA 0x00000000
>> +#define DENALI_PHY_517_DATA 0x00010000
>> +#define DENALI_PHY_518_DATA 0x01DDDD90
>> +#define DENALI_PHY_519_DATA 0x01DDDD90
>> +#define DENALI_PHY_520_DATA 0x01030000
>> +#define DENALI_PHY_521_DATA 0x01000000
>> +#define DENALI_PHY_522_DATA 0x00c00000
>> +#define DENALI_PHY_523_DATA 0x00000007
>> +#define DENALI_PHY_524_DATA 0x00000000
>> +#define DENALI_PHY_525_DATA 0x00000000
>> +#define DENALI_PHY_526_DATA 0x04000408
>> +#define DENALI_PHY_527_DATA 0x00000408
>> +#define DENALI_PHY_528_DATA 0x00e4e400
>> +#define DENALI_PHY_529_DATA 0x00000000
>> +#define DENALI_PHY_530_DATA 0x00000000
>> +#define DENALI_PHY_531_DATA 0x00000000
>> +#define DENALI_PHY_532_DATA 0x00000000
>> +#define DENALI_PHY_533_DATA 0x00000000
>> +#define DENALI_PHY_534_DATA 0x00000000
>> +#define DENALI_PHY_535_DATA 0x00000000
>> +#define DENALI_PHY_536_DATA 0x00000000
>> +#define DENALI_PHY_537_DATA 0x00000000
>> +#define DENALI_PHY_538_DATA 0x00000000
>> +#define DENALI_PHY_539_DATA 0x00000000
>> +#define DENALI_PHY_540_DATA 0x00000000
>> +#define DENALI_PHY_541_DATA 0x00000000
>> +#define DENALI_PHY_542_DATA 0x00000000
>> +#define DENALI_PHY_543_DATA 0x00000000
>> +#define DENALI_PHY_544_DATA 0x00000000
>> +#define DENALI_PHY_545_DATA 0x00200000
>> +#define DENALI_PHY_546_DATA 0x00000000
>> +#define DENALI_PHY_547_DATA 0x00000000
>> +#define DENALI_PHY_548_DATA 0x00000000
>> +#define DENALI_PHY_549_DATA 0x00000000
>> +#define DENALI_PHY_550_DATA 0x00000000
>> +#define DENALI_PHY_551_DATA 0x00000000
>> +#define DENALI_PHY_552_DATA 0x02800280
>> +#define DENALI_PHY_553_DATA 0x02800280
>> +#define DENALI_PHY_554_DATA 0x02800280
>> +#define DENALI_PHY_555_DATA 0x02800280
>> +#define DENALI_PHY_556_DATA 0x00000280
>> +#define DENALI_PHY_557_DATA 0x00000000
>> +#define DENALI_PHY_558_DATA 0x00000000
>> +#define DENALI_PHY_559_DATA 0x00000000
>> +#define DENALI_PHY_560_DATA 0x00000000
>> +#define DENALI_PHY_561_DATA 0x00000000
>> +#define DENALI_PHY_562_DATA 0x00800080
>> +#define DENALI_PHY_563_DATA 0x00800080
>> +#define DENALI_PHY_564_DATA 0x00800080
>> +#define DENALI_PHY_565_DATA 0x00800080
>> +#define DENALI_PHY_566_DATA 0x00800080
>> +#define DENALI_PHY_567_DATA 0x00800080
>> +#define DENALI_PHY_568_DATA 0x00800080
>> +#define DENALI_PHY_569_DATA 0x00800080
>> +#define DENALI_PHY_570_DATA 0x00800080
>> +#define DENALI_PHY_571_DATA 0x000100da
>> +#define DENALI_PHY_572_DATA 0x00000200
>> +#define DENALI_PHY_573_DATA 0x00000000
>> +#define DENALI_PHY_574_DATA 0x00000000
>> +#define DENALI_PHY_575_DATA 0x00000002
>> +#define DENALI_PHY_576_DATA 0x51313152
>> +#define DENALI_PHY_577_DATA 0x80013130
>> +#define DENALI_PHY_578_DATA 0x02000080
>> +#define DENALI_PHY_579_DATA 0x00100001
>> +#define DENALI_PHY_580_DATA 0x0c064208
>> +#define DENALI_PHY_581_DATA 0x000f0c0f
>> +#define DENALI_PHY_582_DATA 0x01000140
>> +#define DENALI_PHY_583_DATA 0x0000000c
>> +#define DENALI_PHY_584_DATA 0x00000000
>> +#define DENALI_PHY_585_DATA 0x00000000
>> +#define DENALI_PHY_586_DATA 0x00000000
>> +#define DENALI_PHY_587_DATA 0x00000000
>> +#define DENALI_PHY_588_DATA 0x00000000
>> +#define DENALI_PHY_589_DATA 0x00000000
>> +#define DENALI_PHY_590_DATA 0x00000000
>> +#define DENALI_PHY_591_DATA 0x00000000
>> +#define DENALI_PHY_592_DATA 0x00000000
>> +#define DENALI_PHY_593_DATA 0x00000000
>> +#define DENALI_PHY_594_DATA 0x00000000
>> +#define DENALI_PHY_595_DATA 0x00000000
>> +#define DENALI_PHY_596_DATA 0x00000000
>> +#define DENALI_PHY_597_DATA 0x00000000
>> +#define DENALI_PHY_598_DATA 0x00000000
>> +#define DENALI_PHY_599_DATA 0x00000000
>> +#define DENALI_PHY_600_DATA 0x00000000
>> +#define DENALI_PHY_601_DATA 0x00000000
>> +#define DENALI_PHY_602_DATA 0x00000000
>> +#define DENALI_PHY_603_DATA 0x00000000
>> +#define DENALI_PHY_604_DATA 0x00000000
>> +#define DENALI_PHY_605_DATA 0x00000000
>> +#define DENALI_PHY_606_DATA 0x00000000
>> +#define DENALI_PHY_607_DATA 0x00000000
>> +#define DENALI_PHY_608_DATA 0x00000000
>> +#define DENALI_PHY_609_DATA 0x00000000
>> +#define DENALI_PHY_610_DATA 0x00000000
>> +#define DENALI_PHY_611_DATA 0x00000000
>> +#define DENALI_PHY_612_DATA 0x00000000
>> +#define DENALI_PHY_613_DATA 0x00000000
>> +#define DENALI_PHY_614_DATA 0x00000000
>> +#define DENALI_PHY_615_DATA 0x00000000
>> +#define DENALI_PHY_616_DATA 0x00000000
>> +#define DENALI_PHY_617_DATA 0x00000000
>> +#define DENALI_PHY_618_DATA 0x00000000
>> +#define DENALI_PHY_619_DATA 0x00000000
>> +#define DENALI_PHY_620_DATA 0x00000000
>> +#define DENALI_PHY_621_DATA 0x00000000
>> +#define DENALI_PHY_622_DATA 0x00000000
>> +#define DENALI_PHY_623_DATA 0x00000000
>> +#define DENALI_PHY_624_DATA 0x00000000
>> +#define DENALI_PHY_625_DATA 0x00000000
>> +#define DENALI_PHY_626_DATA 0x00000000
>> +#define DENALI_PHY_627_DATA 0x00000000
>> +#define DENALI_PHY_628_DATA 0x00000000
>> +#define DENALI_PHY_629_DATA 0x00000000
>> +#define DENALI_PHY_630_DATA 0x00000000
>> +#define DENALI_PHY_631_DATA 0x00000000
>> +#define DENALI_PHY_632_DATA 0x00000000
>> +#define DENALI_PHY_633_DATA 0x00000000
>> +#define DENALI_PHY_634_DATA 0x00000000
>> +#define DENALI_PHY_635_DATA 0x00000000
>> +#define DENALI_PHY_636_DATA 0x00000000
>> +#define DENALI_PHY_637_DATA 0x00000000
>> +#define DENALI_PHY_638_DATA 0x00000000
>> +#define DENALI_PHY_639_DATA 0x00000000
>> +#define DENALI_PHY_640_DATA 0x35174620
>> +#define DENALI_PHY_641_DATA 0x0004c008
>> +#define DENALI_PHY_642_DATA 0x000000da
>> +#define DENALI_PHY_643_DATA 0x00000000
>> +#define DENALI_PHY_644_DATA 0x00000000
>> +#define DENALI_PHY_645_DATA 0x00010000
>> +#define DENALI_PHY_646_DATA 0x01DDDD90
>> +#define DENALI_PHY_647_DATA 0x01DDDD90
>> +#define DENALI_PHY_648_DATA 0x01030000
>> +#define DENALI_PHY_649_DATA 0x01000000
>> +#define DENALI_PHY_650_DATA 0x00c00000
>> +#define DENALI_PHY_651_DATA 0x00000007
>> +#define DENALI_PHY_652_DATA 0x00000000
>> +#define DENALI_PHY_653_DATA 0x00000000
>> +#define DENALI_PHY_654_DATA 0x04000408
>> +#define DENALI_PHY_655_DATA 0x00000408
>> +#define DENALI_PHY_656_DATA 0x00e4e400
>> +#define DENALI_PHY_657_DATA 0x00000000
>> +#define DENALI_PHY_658_DATA 0x00000000
>> +#define DENALI_PHY_659_DATA 0x00000000
>> +#define DENALI_PHY_660_DATA 0x00000000
>> +#define DENALI_PHY_661_DATA 0x00000000
>> +#define DENALI_PHY_662_DATA 0x00000000
>> +#define DENALI_PHY_663_DATA 0x00000000
>> +#define DENALI_PHY_664_DATA 0x00000000
>> +#define DENALI_PHY_665_DATA 0x00000000
>> +#define DENALI_PHY_666_DATA 0x00000000
>> +#define DENALI_PHY_667_DATA 0x00000000
>> +#define DENALI_PHY_668_DATA 0x00000000
>> +#define DENALI_PHY_669_DATA 0x00000000
>> +#define DENALI_PHY_670_DATA 0x00000000
>> +#define DENALI_PHY_671_DATA 0x00000000
>> +#define DENALI_PHY_672_DATA 0x00000000
>> +#define DENALI_PHY_673_DATA 0x00200000
>> +#define DENALI_PHY_674_DATA 0x00000000
>> +#define DENALI_PHY_675_DATA 0x00000000
>> +#define DENALI_PHY_676_DATA 0x00000000
>> +#define DENALI_PHY_677_DATA 0x00000000
>> +#define DENALI_PHY_678_DATA 0x00000000
>> +#define DENALI_PHY_679_DATA 0x00000000
>> +#define DENALI_PHY_680_DATA 0x02800280
>> +#define DENALI_PHY_681_DATA 0x02800280
>> +#define DENALI_PHY_682_DATA 0x02800280
>> +#define DENALI_PHY_683_DATA 0x02800280
>> +#define DENALI_PHY_684_DATA 0x00000280
>> +#define DENALI_PHY_685_DATA 0x00000000
>> +#define DENALI_PHY_686_DATA 0x00000000
>> +#define DENALI_PHY_687_DATA 0x00000000
>> +#define DENALI_PHY_688_DATA 0x00000000
>> +#define DENALI_PHY_689_DATA 0x00000000
>> +#define DENALI_PHY_690_DATA 0x00800080
>> +#define DENALI_PHY_691_DATA 0x00800080
>> +#define DENALI_PHY_692_DATA 0x00800080
>> +#define DENALI_PHY_693_DATA 0x00800080
>> +#define DENALI_PHY_694_DATA 0x00800080
>> +#define DENALI_PHY_695_DATA 0x00800080
>> +#define DENALI_PHY_696_DATA 0x00800080
>> +#define DENALI_PHY_697_DATA 0x00800080
>> +#define DENALI_PHY_698_DATA 0x00800080
>> +#define DENALI_PHY_699_DATA 0x000100da
>> +#define DENALI_PHY_700_DATA 0x00000200
>> +#define DENALI_PHY_701_DATA 0x00000000
>> +#define DENALI_PHY_702_DATA 0x00000000
>> +#define DENALI_PHY_703_DATA 0x00000002
>> +#define DENALI_PHY_704_DATA 0x51313152
>> +#define DENALI_PHY_705_DATA 0x80013130
>> +#define DENALI_PHY_706_DATA 0x02000080
>> +#define DENALI_PHY_707_DATA 0x00100001
>> +#define DENALI_PHY_708_DATA 0x0c064208
>> +#define DENALI_PHY_709_DATA 0x000f0c0f
>> +#define DENALI_PHY_710_DATA 0x01000140
>> +#define DENALI_PHY_711_DATA 0x0000000c
>> +#define DENALI_PHY_712_DATA 0x00000000
>> +#define DENALI_PHY_713_DATA 0x00000000
>> +#define DENALI_PHY_714_DATA 0x00000000
>> +#define DENALI_PHY_715_DATA 0x00000000
>> +#define DENALI_PHY_716_DATA 0x00000000
>> +#define DENALI_PHY_717_DATA 0x00000000
>> +#define DENALI_PHY_718_DATA 0x00000000
>> +#define DENALI_PHY_719_DATA 0x00000000
>> +#define DENALI_PHY_720_DATA 0x00000000
>> +#define DENALI_PHY_721_DATA 0x00000000
>> +#define DENALI_PHY_722_DATA 0x00000000
>> +#define DENALI_PHY_723_DATA 0x00000000
>> +#define DENALI_PHY_724_DATA 0x00000000
>> +#define DENALI_PHY_725_DATA 0x00000000
>> +#define DENALI_PHY_726_DATA 0x00000000
>> +#define DENALI_PHY_727_DATA 0x00000000
>> +#define DENALI_PHY_728_DATA 0x00000000
>> +#define DENALI_PHY_729_DATA 0x00000000
>> +#define DENALI_PHY_730_DATA 0x00000000
>> +#define DENALI_PHY_731_DATA 0x00000000
>> +#define DENALI_PHY_732_DATA 0x00000000
>> +#define DENALI_PHY_733_DATA 0x00000000
>> +#define DENALI_PHY_734_DATA 0x00000000
>> +#define DENALI_PHY_735_DATA 0x00000000
>> +#define DENALI_PHY_736_DATA 0x00000000
>> +#define DENALI_PHY_737_DATA 0x00000000
>> +#define DENALI_PHY_738_DATA 0x00000000
>> +#define DENALI_PHY_739_DATA 0x00000000
>> +#define DENALI_PHY_740_DATA 0x00000000
>> +#define DENALI_PHY_741_DATA 0x00000000
>> +#define DENALI_PHY_742_DATA 0x00000000
>> +#define DENALI_PHY_743_DATA 0x00000000
>> +#define DENALI_PHY_744_DATA 0x00000000
>> +#define DENALI_PHY_745_DATA 0x00000000
>> +#define DENALI_PHY_746_DATA 0x00000000
>> +#define DENALI_PHY_747_DATA 0x00000000
>> +#define DENALI_PHY_748_DATA 0x00000000
>> +#define DENALI_PHY_749_DATA 0x00000000
>> +#define DENALI_PHY_750_DATA 0x00000000
>> +#define DENALI_PHY_751_DATA 0x00000000
>> +#define DENALI_PHY_752_DATA 0x00000000
>> +#define DENALI_PHY_753_DATA 0x00000000
>> +#define DENALI_PHY_754_DATA 0x00000000
>> +#define DENALI_PHY_755_DATA 0x00000000
>> +#define DENALI_PHY_756_DATA 0x00000000
>> +#define DENALI_PHY_757_DATA 0x00000000
>> +#define DENALI_PHY_758_DATA 0x00000000
>> +#define DENALI_PHY_759_DATA 0x00000000
>> +#define DENALI_PHY_760_DATA 0x00000000
>> +#define DENALI_PHY_761_DATA 0x00000000
>> +#define DENALI_PHY_762_DATA 0x00000000
>> +#define DENALI_PHY_763_DATA 0x00000000
>> +#define DENALI_PHY_764_DATA 0x00000000
>> +#define DENALI_PHY_765_DATA 0x00000000
>> +#define DENALI_PHY_766_DATA 0x00000000
>> +#define DENALI_PHY_767_DATA 0x00000000
>> +#define DENALI_PHY_768_DATA 0x15203476
>> +#define DENALI_PHY_769_DATA 0x0004c008
>> +#define DENALI_PHY_770_DATA 0x000000da
>> +#define DENALI_PHY_771_DATA 0x00000000
>> +#define DENALI_PHY_772_DATA 0x00000000
>> +#define DENALI_PHY_773_DATA 0x00010000
>> +#define DENALI_PHY_774_DATA 0x01DDDD90
>> +#define DENALI_PHY_775_DATA 0x01DDDD90
>> +#define DENALI_PHY_776_DATA 0x01030000
>> +#define DENALI_PHY_777_DATA 0x01000000
>> +#define DENALI_PHY_778_DATA 0x00c00000
>> +#define DENALI_PHY_779_DATA 0x00000007
>> +#define DENALI_PHY_780_DATA 0x00000000
>> +#define DENALI_PHY_781_DATA 0x00000000
>> +#define DENALI_PHY_782_DATA 0x04000408
>> +#define DENALI_PHY_783_DATA 0x00000408
>> +#define DENALI_PHY_784_DATA 0x00e4e400
>> +#define DENALI_PHY_785_DATA 0x00000000
>> +#define DENALI_PHY_786_DATA 0x00000000
>> +#define DENALI_PHY_787_DATA 0x00000000
>> +#define DENALI_PHY_788_DATA 0x00000000
>> +#define DENALI_PHY_789_DATA 0x00000000
>> +#define DENALI_PHY_790_DATA 0x00000000
>> +#define DENALI_PHY_791_DATA 0x00000000
>> +#define DENALI_PHY_792_DATA 0x00000000
>> +#define DENALI_PHY_793_DATA 0x00000000
>> +#define DENALI_PHY_794_DATA 0x00000000
>> +#define DENALI_PHY_795_DATA 0x00000000
>> +#define DENALI_PHY_796_DATA 0x00000000
>> +#define DENALI_PHY_797_DATA 0x00000000
>> +#define DENALI_PHY_798_DATA 0x00000000
>> +#define DENALI_PHY_799_DATA 0x00000000
>> +#define DENALI_PHY_800_DATA 0x00000000
>> +#define DENALI_PHY_801_DATA 0x00200000
>> +#define DENALI_PHY_802_DATA 0x00000000
>> +#define DENALI_PHY_803_DATA 0x00000000
>> +#define DENALI_PHY_804_DATA 0x00000000
>> +#define DENALI_PHY_805_DATA 0x00000000
>> +#define DENALI_PHY_806_DATA 0x00000000
>> +#define DENALI_PHY_807_DATA 0x00000000
>> +#define DENALI_PHY_808_DATA 0x02800280
>> +#define DENALI_PHY_809_DATA 0x02800280
>> +#define DENALI_PHY_810_DATA 0x02800280
>> +#define DENALI_PHY_811_DATA 0x02800280
>> +#define DENALI_PHY_812_DATA 0x00000280
>> +#define DENALI_PHY_813_DATA 0x00000000
>> +#define DENALI_PHY_814_DATA 0x00000000
>> +#define DENALI_PHY_815_DATA 0x00000000
>> +#define DENALI_PHY_816_DATA 0x00000000
>> +#define DENALI_PHY_817_DATA 0x00000000
>> +#define DENALI_PHY_818_DATA 0x00800080
>> +#define DENALI_PHY_819_DATA 0x00800080
>> +#define DENALI_PHY_820_DATA 0x00800080
>> +#define DENALI_PHY_821_DATA 0x00800080
>> +#define DENALI_PHY_822_DATA 0x00800080
>> +#define DENALI_PHY_823_DATA 0x00800080
>> +#define DENALI_PHY_824_DATA 0x00800080
>> +#define DENALI_PHY_825_DATA 0x00800080
>> +#define DENALI_PHY_826_DATA 0x00800080
>> +#define DENALI_PHY_827_DATA 0x000100da
>> +#define DENALI_PHY_828_DATA 0x00000200
>> +#define DENALI_PHY_829_DATA 0x00000000
>> +#define DENALI_PHY_830_DATA 0x00000000
>> +#define DENALI_PHY_831_DATA 0x00000002
>> +#define DENALI_PHY_832_DATA 0x51313152
>> +#define DENALI_PHY_833_DATA 0x80013130
>> +#define DENALI_PHY_834_DATA 0x02000080
>> +#define DENALI_PHY_835_DATA 0x00100001
>> +#define DENALI_PHY_836_DATA 0x0c064208
>> +#define DENALI_PHY_837_DATA 0x000f0c0f
>> +#define DENALI_PHY_838_DATA 0x01000140
>> +#define DENALI_PHY_839_DATA 0x0000000c
>> +#define DENALI_PHY_840_DATA 0x00000000
>> +#define DENALI_PHY_841_DATA 0x00000000
>> +#define DENALI_PHY_842_DATA 0x00000000
>> +#define DENALI_PHY_843_DATA 0x00000000
>> +#define DENALI_PHY_844_DATA 0x00000000
>> +#define DENALI_PHY_845_DATA 0x00000000
>> +#define DENALI_PHY_846_DATA 0x00000000
>> +#define DENALI_PHY_847_DATA 0x00000000
>> +#define DENALI_PHY_848_DATA 0x00000000
>> +#define DENALI_PHY_849_DATA 0x00000000
>> +#define DENALI_PHY_850_DATA 0x00000000
>> +#define DENALI_PHY_851_DATA 0x00000000
>> +#define DENALI_PHY_852_DATA 0x00000000
>> +#define DENALI_PHY_853_DATA 0x00000000
>> +#define DENALI_PHY_854_DATA 0x00000000
>> +#define DENALI_PHY_855_DATA 0x00000000
>> +#define DENALI_PHY_856_DATA 0x00000000
>> +#define DENALI_PHY_857_DATA 0x00000000
>> +#define DENALI_PHY_858_DATA 0x00000000
>> +#define DENALI_PHY_859_DATA 0x00000000
>> +#define DENALI_PHY_860_DATA 0x00000000
>> +#define DENALI_PHY_861_DATA 0x00000000
>> +#define DENALI_PHY_862_DATA 0x00000000
>> +#define DENALI_PHY_863_DATA 0x00000000
>> +#define DENALI_PHY_864_DATA 0x00000000
>> +#define DENALI_PHY_865_DATA 0x00000000
>> +#define DENALI_PHY_866_DATA 0x00000000
>> +#define DENALI_PHY_867_DATA 0x00000000
>> +#define DENALI_PHY_868_DATA 0x00000000
>> +#define DENALI_PHY_869_DATA 0x00000000
>> +#define DENALI_PHY_870_DATA 0x00000000
>> +#define DENALI_PHY_871_DATA 0x00000000
>> +#define DENALI_PHY_872_DATA 0x00000000
>> +#define DENALI_PHY_873_DATA 0x00000000
>> +#define DENALI_PHY_874_DATA 0x00000000
>> +#define DENALI_PHY_875_DATA 0x00000000
>> +#define DENALI_PHY_876_DATA 0x00000000
>> +#define DENALI_PHY_877_DATA 0x00000000
>> +#define DENALI_PHY_878_DATA 0x00000000
>> +#define DENALI_PHY_879_DATA 0x00000000
>> +#define DENALI_PHY_880_DATA 0x00000000
>> +#define DENALI_PHY_881_DATA 0x00000000
>> +#define DENALI_PHY_882_DATA 0x00000000
>> +#define DENALI_PHY_883_DATA 0x00000000
>> +#define DENALI_PHY_884_DATA 0x00000000
>> +#define DENALI_PHY_885_DATA 0x00000000
>> +#define DENALI_PHY_886_DATA 0x00000000
>> +#define DENALI_PHY_887_DATA 0x00000000
>> +#define DENALI_PHY_888_DATA 0x00000000
>> +#define DENALI_PHY_889_DATA 0x00000000
>> +#define DENALI_PHY_890_DATA 0x00000000
>> +#define DENALI_PHY_891_DATA 0x00000000
>> +#define DENALI_PHY_892_DATA 0x00000000
>> +#define DENALI_PHY_893_DATA 0x00000000
>> +#define DENALI_PHY_894_DATA 0x00000000
>> +#define DENALI_PHY_895_DATA 0x00000000
>> +#define DENALI_PHY_896_DATA 0x41753206
>> +#define DENALI_PHY_897_DATA 0x0004c008
>> +#define DENALI_PHY_898_DATA 0x000000da
>> +#define DENALI_PHY_899_DATA 0x00000000
>> +#define DENALI_PHY_900_DATA 0x00000000
>> +#define DENALI_PHY_901_DATA 0x00010000
>> +#define DENALI_PHY_902_DATA 0x01DDDD90
>> +#define DENALI_PHY_903_DATA 0x01DDDD90
>> +#define DENALI_PHY_904_DATA 0x01030000
>> +#define DENALI_PHY_905_DATA 0x01000000
>> +#define DENALI_PHY_906_DATA 0x00c00000
>> +#define DENALI_PHY_907_DATA 0x00000007
>> +#define DENALI_PHY_908_DATA 0x00000000
>> +#define DENALI_PHY_909_DATA 0x00000000
>> +#define DENALI_PHY_910_DATA 0x04000408
>> +#define DENALI_PHY_911_DATA 0x00000408
>> +#define DENALI_PHY_912_DATA 0x00e4e400
>> +#define DENALI_PHY_913_DATA 0x00000000
>> +#define DENALI_PHY_914_DATA 0x00000000
>> +#define DENALI_PHY_915_DATA 0x00000000
>> +#define DENALI_PHY_916_DATA 0x00000000
>> +#define DENALI_PHY_917_DATA 0x00000000
>> +#define DENALI_PHY_918_DATA 0x00000000
>> +#define DENALI_PHY_919_DATA 0x00000000
>> +#define DENALI_PHY_920_DATA 0x00000000
>> +#define DENALI_PHY_921_DATA 0x00000000
>> +#define DENALI_PHY_922_DATA 0x00000000
>> +#define DENALI_PHY_923_DATA 0x00000000
>> +#define DENALI_PHY_924_DATA 0x00000000
>> +#define DENALI_PHY_925_DATA 0x00000000
>> +#define DENALI_PHY_926_DATA 0x00000000
>> +#define DENALI_PHY_927_DATA 0x00000000
>> +#define DENALI_PHY_928_DATA 0x00000000
>> +#define DENALI_PHY_929_DATA 0x00200000
>> +#define DENALI_PHY_930_DATA 0x00000000
>> +#define DENALI_PHY_931_DATA 0x00000000
>> +#define DENALI_PHY_932_DATA 0x00000000
>> +#define DENALI_PHY_933_DATA 0x00000000
>> +#define DENALI_PHY_934_DATA 0x00000000
>> +#define DENALI_PHY_935_DATA 0x00000000
>> +#define DENALI_PHY_936_DATA 0x02800280
>> +#define DENALI_PHY_937_DATA 0x02800280
>> +#define DENALI_PHY_938_DATA 0x02800280
>> +#define DENALI_PHY_939_DATA 0x02800280
>> +#define DENALI_PHY_940_DATA 0x00000280
>> +#define DENALI_PHY_941_DATA 0x00000000
>> +#define DENALI_PHY_942_DATA 0x00000000
>> +#define DENALI_PHY_943_DATA 0x00000000
>> +#define DENALI_PHY_944_DATA 0x00000000
>> +#define DENALI_PHY_945_DATA 0x00000000
>> +#define DENALI_PHY_946_DATA 0x00800080
>> +#define DENALI_PHY_947_DATA 0x00800080
>> +#define DENALI_PHY_948_DATA 0x00800080
>> +#define DENALI_PHY_949_DATA 0x00800080
>> +#define DENALI_PHY_950_DATA 0x00800080
>> +#define DENALI_PHY_951_DATA 0x00800080
>> +#define DENALI_PHY_952_DATA 0x00800080
>> +#define DENALI_PHY_953_DATA 0x00800080
>> +#define DENALI_PHY_954_DATA 0x00800080
>> +#define DENALI_PHY_955_DATA 0x000100da
>> +#define DENALI_PHY_956_DATA 0x00000200
>> +#define DENALI_PHY_957_DATA 0x00000000
>> +#define DENALI_PHY_958_DATA 0x00000000
>> +#define DENALI_PHY_959_DATA 0x00000002
>> +#define DENALI_PHY_960_DATA 0x51313152
>> +#define DENALI_PHY_961_DATA 0x80013130
>> +#define DENALI_PHY_962_DATA 0x02000080
>> +#define DENALI_PHY_963_DATA 0x00100001
>> +#define DENALI_PHY_964_DATA 0x0c064208
>> +#define DENALI_PHY_965_DATA 0x000f0c0f
>> +#define DENALI_PHY_966_DATA 0x01000140
>> +#define DENALI_PHY_967_DATA 0x0000000c
>> +#define DENALI_PHY_968_DATA 0x00000000
>> +#define DENALI_PHY_969_DATA 0x00000000
>> +#define DENALI_PHY_970_DATA 0x00000000
>> +#define DENALI_PHY_971_DATA 0x00000000
>> +#define DENALI_PHY_972_DATA 0x00000000
>> +#define DENALI_PHY_973_DATA 0x00000000
>> +#define DENALI_PHY_974_DATA 0x00000000
>> +#define DENALI_PHY_975_DATA 0x00000000
>> +#define DENALI_PHY_976_DATA 0x00000000
>> +#define DENALI_PHY_977_DATA 0x00000000
>> +#define DENALI_PHY_978_DATA 0x00000000
>> +#define DENALI_PHY_979_DATA 0x00000000
>> +#define DENALI_PHY_980_DATA 0x00000000
>> +#define DENALI_PHY_981_DATA 0x00000000
>> +#define DENALI_PHY_982_DATA 0x00000000
>> +#define DENALI_PHY_983_DATA 0x00000000
>> +#define DENALI_PHY_984_DATA 0x00000000
>> +#define DENALI_PHY_985_DATA 0x00000000
>> +#define DENALI_PHY_986_DATA 0x00000000
>> +#define DENALI_PHY_987_DATA 0x00000000
>> +#define DENALI_PHY_988_DATA 0x00000000
>> +#define DENALI_PHY_989_DATA 0x00000000
>> +#define DENALI_PHY_990_DATA 0x00000000
>> +#define DENALI_PHY_991_DATA 0x00000000
>> +#define DENALI_PHY_992_DATA 0x00000000
>> +#define DENALI_PHY_993_DATA 0x00000000
>> +#define DENALI_PHY_994_DATA 0x00000000
>> +#define DENALI_PHY_995_DATA 0x00000000
>> +#define DENALI_PHY_996_DATA 0x00000000
>> +#define DENALI_PHY_997_DATA 0x00000000
>> +#define DENALI_PHY_998_DATA 0x00000000
>> +#define DENALI_PHY_999_DATA 0x00000000
>> +#define DENALI_PHY_1000_DATA 0x00000000
>> +#define DENALI_PHY_1001_DATA 0x00000000
>> +#define DENALI_PHY_1002_DATA 0x00000000
>> +#define DENALI_PHY_1003_DATA 0x00000000
>> +#define DENALI_PHY_1004_DATA 0x00000000
>> +#define DENALI_PHY_1005_DATA 0x00000000
>> +#define DENALI_PHY_1006_DATA 0x00000000
>> +#define DENALI_PHY_1007_DATA 0x00000000
>> +#define DENALI_PHY_1008_DATA 0x00000000
>> +#define DENALI_PHY_1009_DATA 0x00000000
>> +#define DENALI_PHY_1010_DATA 0x00000000
>> +#define DENALI_PHY_1011_DATA 0x00000000
>> +#define DENALI_PHY_1012_DATA 0x00000000
>> +#define DENALI_PHY_1013_DATA 0x00000000
>> +#define DENALI_PHY_1014_DATA 0x00000000
>> +#define DENALI_PHY_1015_DATA 0x00000000
>> +#define DENALI_PHY_1016_DATA 0x00000000
>> +#define DENALI_PHY_1017_DATA 0x00000000
>> +#define DENALI_PHY_1018_DATA 0x00000000
>> +#define DENALI_PHY_1019_DATA 0x00000000
>> +#define DENALI_PHY_1020_DATA 0x00000000
>> +#define DENALI_PHY_1021_DATA 0x00000000
>> +#define DENALI_PHY_1022_DATA 0x00000000
>> +#define DENALI_PHY_1023_DATA 0x00000000
>> +#define DENALI_PHY_1024_DATA 0x36025174
>> +#define DENALI_PHY_1025_DATA 0x0004c008
>> +#define DENALI_PHY_1026_DATA 0x000000da
>> +#define DENALI_PHY_1027_DATA 0x00000000
>> +#define DENALI_PHY_1028_DATA 0x00000000
>> +#define DENALI_PHY_1029_DATA 0x00010000
>> +#define DENALI_PHY_1030_DATA 0x01DDDD90
>> +#define DENALI_PHY_1031_DATA 0x01DDDD90
>> +#define DENALI_PHY_1032_DATA 0x01030000
>> +#define DENALI_PHY_1033_DATA 0x01000000
>> +#define DENALI_PHY_1034_DATA 0x00c00000
>> +#define DENALI_PHY_1035_DATA 0x00000007
>> +#define DENALI_PHY_1036_DATA 0x00000000
>> +#define DENALI_PHY_1037_DATA 0x00000000
>> +#define DENALI_PHY_1038_DATA 0x04000408
>> +#define DENALI_PHY_1039_DATA 0x00000408
>> +#define DENALI_PHY_1040_DATA 0x00e4e400
>> +#define DENALI_PHY_1041_DATA 0x00000000
>> +#define DENALI_PHY_1042_DATA 0x00000000
>> +#define DENALI_PHY_1043_DATA 0x00000000
>> +#define DENALI_PHY_1044_DATA 0x00000000
>> +#define DENALI_PHY_1045_DATA 0x00000000
>> +#define DENALI_PHY_1046_DATA 0x00000000
>> +#define DENALI_PHY_1047_DATA 0x00000000
>> +#define DENALI_PHY_1048_DATA 0x00000000
>> +#define DENALI_PHY_1049_DATA 0x00000000
>> +#define DENALI_PHY_1050_DATA 0x00000000
>> +#define DENALI_PHY_1051_DATA 0x00000000
>> +#define DENALI_PHY_1052_DATA 0x00000000
>> +#define DENALI_PHY_1053_DATA 0x00000000
>> +#define DENALI_PHY_1054_DATA 0x00000000
>> +#define DENALI_PHY_1055_DATA 0x00000000
>> +#define DENALI_PHY_1056_DATA 0x00000000
>> +#define DENALI_PHY_1057_DATA 0x00200000
>> +#define DENALI_PHY_1058_DATA 0x00000000
>> +#define DENALI_PHY_1059_DATA 0x00000000
>> +#define DENALI_PHY_1060_DATA 0x00000000
>> +#define DENALI_PHY_1061_DATA 0x00000000
>> +#define DENALI_PHY_1062_DATA 0x00000000
>> +#define DENALI_PHY_1063_DATA 0x00000000
>> +#define DENALI_PHY_1064_DATA 0x02800280
>> +#define DENALI_PHY_1065_DATA 0x02800280
>> +#define DENALI_PHY_1066_DATA 0x02800280
>> +#define DENALI_PHY_1067_DATA 0x02800280
>> +#define DENALI_PHY_1068_DATA 0x00000280
>> +#define DENALI_PHY_1069_DATA 0x00000000
>> +#define DENALI_PHY_1070_DATA 0x00000000
>> +#define DENALI_PHY_1071_DATA 0x00000000
>> +#define DENALI_PHY_1072_DATA 0x00000000
>> +#define DENALI_PHY_1073_DATA 0x00000000
>> +#define DENALI_PHY_1074_DATA 0x00800080
>> +#define DENALI_PHY_1075_DATA 0x00800080
>> +#define DENALI_PHY_1076_DATA 0x00800080
>> +#define DENALI_PHY_1077_DATA 0x00800080
>> +#define DENALI_PHY_1078_DATA 0x00800080
>> +#define DENALI_PHY_1079_DATA 0x00800080
>> +#define DENALI_PHY_1080_DATA 0x00800080
>> +#define DENALI_PHY_1081_DATA 0x00800080
>> +#define DENALI_PHY_1082_DATA 0x00800080
>> +#define DENALI_PHY_1083_DATA 0x000100da
>> +#define DENALI_PHY_1084_DATA 0x00000200
>> +#define DENALI_PHY_1085_DATA 0x00000000
>> +#define DENALI_PHY_1086_DATA 0x00000000
>> +#define DENALI_PHY_1087_DATA 0x00000002
>> +#define DENALI_PHY_1088_DATA 0x51313152
>> +#define DENALI_PHY_1089_DATA 0x80013130
>> +#define DENALI_PHY_1090_DATA 0x02000080
>> +#define DENALI_PHY_1091_DATA 0x00100001
>> +#define DENALI_PHY_1092_DATA 0x0c064208
>> +#define DENALI_PHY_1093_DATA 0x000f0c0f
>> +#define DENALI_PHY_1094_DATA 0x01000140
>> +#define DENALI_PHY_1095_DATA 0x0000000c
>> +#define DENALI_PHY_1096_DATA 0x00000000
>> +#define DENALI_PHY_1097_DATA 0x00000000
>> +#define DENALI_PHY_1098_DATA 0x00000000
>> +#define DENALI_PHY_1099_DATA 0x00000000
>> +#define DENALI_PHY_1100_DATA 0x00000000
>> +#define DENALI_PHY_1101_DATA 0x00000000
>> +#define DENALI_PHY_1102_DATA 0x00000000
>> +#define DENALI_PHY_1103_DATA 0x00000000
>> +#define DENALI_PHY_1104_DATA 0x00000000
>> +#define DENALI_PHY_1105_DATA 0x00000000
>> +#define DENALI_PHY_1106_DATA 0x00000000
>> +#define DENALI_PHY_1107_DATA 0x00000000
>> +#define DENALI_PHY_1108_DATA 0x00000000
>> +#define DENALI_PHY_1109_DATA 0x00000000
>> +#define DENALI_PHY_1110_DATA 0x00000000
>> +#define DENALI_PHY_1111_DATA 0x00000000
>> +#define DENALI_PHY_1112_DATA 0x00000000
>> +#define DENALI_PHY_1113_DATA 0x00000000
>> +#define DENALI_PHY_1114_DATA 0x00000000
>> +#define DENALI_PHY_1115_DATA 0x00000000
>> +#define DENALI_PHY_1116_DATA 0x00000000
>> +#define DENALI_PHY_1117_DATA 0x00000000
>> +#define DENALI_PHY_1118_DATA 0x00000000
>> +#define DENALI_PHY_1119_DATA 0x00000000
>> +#define DENALI_PHY_1120_DATA 0x00000000
>> +#define DENALI_PHY_1121_DATA 0x00000000
>> +#define DENALI_PHY_1122_DATA 0x00000000
>> +#define DENALI_PHY_1123_DATA 0x00000000
>> +#define DENALI_PHY_1124_DATA 0x00000000
>> +#define DENALI_PHY_1125_DATA 0x00000000
>> +#define DENALI_PHY_1126_DATA 0x00000000
>> +#define DENALI_PHY_1127_DATA 0x00000000
>> +#define DENALI_PHY_1128_DATA 0x00000000
>> +#define DENALI_PHY_1129_DATA 0x00000000
>> +#define DENALI_PHY_1130_DATA 0x00000000
>> +#define DENALI_PHY_1131_DATA 0x00000000
>> +#define DENALI_PHY_1132_DATA 0x00000000
>> +#define DENALI_PHY_1133_DATA 0x00000000
>> +#define DENALI_PHY_1134_DATA 0x00000000
>> +#define DENALI_PHY_1135_DATA 0x00000000
>> +#define DENALI_PHY_1136_DATA 0x00000000
>> +#define DENALI_PHY_1137_DATA 0x00000000
>> +#define DENALI_PHY_1138_DATA 0x00000000
>> +#define DENALI_PHY_1139_DATA 0x00000000
>> +#define DENALI_PHY_1140_DATA 0x00000000
>> +#define DENALI_PHY_1141_DATA 0x00000000
>> +#define DENALI_PHY_1142_DATA 0x00000000
>> +#define DENALI_PHY_1143_DATA 0x00000000
>> +#define DENALI_PHY_1144_DATA 0x00000000
>> +#define DENALI_PHY_1145_DATA 0x00000000
>> +#define DENALI_PHY_1146_DATA 0x00000000
>> +#define DENALI_PHY_1147_DATA 0x00000000
>> +#define DENALI_PHY_1148_DATA 0x00000000
>> +#define DENALI_PHY_1149_DATA 0x00000000
>> +#define DENALI_PHY_1150_DATA 0x00000000
>> +#define DENALI_PHY_1151_DATA 0x00000000
>> +#define DENALI_PHY_1152_DATA 0x00000000
>> +#define DENALI_PHY_1153_DATA 0x00000000
>> +#define DENALI_PHY_1154_DATA 0x00050000
>> +#define DENALI_PHY_1155_DATA 0x00000000
>> +#define DENALI_PHY_1156_DATA 0x00000000
>> +#define DENALI_PHY_1157_DATA 0x00000000
>> +#define DENALI_PHY_1158_DATA 0x00000100
>> +#define DENALI_PHY_1159_DATA 0x00000000
>> +#define DENALI_PHY_1160_DATA 0x00000000
>> +#define DENALI_PHY_1161_DATA 0x00506401
>> +#define DENALI_PHY_1162_DATA 0x01221102
>> +#define DENALI_PHY_1163_DATA 0x00000122
>> +#define DENALI_PHY_1164_DATA 0x00000000
>> +#define DENALI_PHY_1165_DATA 0x000B1F00
>> +#define DENALI_PHY_1166_DATA 0x0B1F0B1F
>> +#define DENALI_PHY_1167_DATA 0x0B1F0B1B
>> +#define DENALI_PHY_1168_DATA 0x0B1F0B1F
>> +#define DENALI_PHY_1169_DATA 0x0B1F0B1F
>> +#define DENALI_PHY_1170_DATA 0x00000B00
>> +#define DENALI_PHY_1171_DATA 0x42080010
>> +#define DENALI_PHY_1172_DATA 0x01000100
>> +#define DENALI_PHY_1173_DATA 0x01000100
>> +#define DENALI_PHY_1174_DATA 0x01000100
>> +#define DENALI_PHY_1175_DATA 0x01000100
>> +#define DENALI_PHY_1176_DATA 0x00000000
>> +#define DENALI_PHY_1177_DATA 0x00000000
>> +#define DENALI_PHY_1178_DATA 0x00000000
>> +#define DENALI_PHY_1179_DATA 0x00000000
>> +#define DENALI_PHY_1180_DATA 0x00000000
>> +#define DENALI_PHY_1181_DATA 0x00000803
>> +#define DENALI_PHY_1182_DATA 0x223FFF00
>> +#define DENALI_PHY_1183_DATA 0x000008FF
>> +#define DENALI_PHY_1184_DATA 0x0000057F
>> +#define DENALI_PHY_1185_DATA 0x0000057F
>> +#define DENALI_PHY_1186_DATA 0x00037FFF
>> +#define DENALI_PHY_1187_DATA 0x00037FFF
>> +#define DENALI_PHY_1188_DATA 0x00004410
>> +#define DENALI_PHY_1189_DATA 0x00004410
>> +#define DENALI_PHY_1190_DATA 0x00004410
>> +#define DENALI_PHY_1191_DATA 0x00004410
>> +#define DENALI_PHY_1192_DATA 0x00004410
>> +#define DENALI_PHY_1193_DATA 0x00037FFF
>> +#define DENALI_PHY_1194_DATA 0x00037FFF
>> +#define DENALI_PHY_1195_DATA 0x00000000
>> +#define DENALI_PHY_1196_DATA 0x00000000
>> +#define DENALI_PHY_1197_DATA 0x00000000
>> +#define DENALI_PHY_1198_DATA 0x04000000
>> +#define DENALI_PHY_1199_DATA 0x00000000
>> +#define DENALI_PHY_1200_DATA 0x00000000
>> +#define DENALI_PHY_1201_DATA 0x00000108
>> +#define DENALI_PHY_1202_DATA 0x00000000
>> +#define DENALI_PHY_1203_DATA 0x00000000
>> +#define DENALI_PHY_1204_DATA 0x00000000
>> +#define DENALI_PHY_1205_DATA 0x00000001
>> +#define DENALI_PHY_1206_DATA 0x00000000
>> +#define DENALI_PHY_1207_DATA 0x00000000
>> +#define DENALI_PHY_1208_DATA 0x00000000
>> +#define DENALI_PHY_1209_DATA 0x00000000
>> +#define DENALI_PHY_1210_DATA 0x00000000
>> +#define DENALI_PHY_1211_DATA 0x00000000
>> +#define DENALI_PHY_1212_DATA 0x00020100
>> +#define DENALI_PHY_1213_DATA 0x00000000
>> +#define DENALI_PHY_1214_DATA 0x00000000
>
>Sorry, this entire ddr code look very difficult to undestand or
>review. I understand it is driven from the vendor blog or so but it is
>not in proper shape to mege it on mainline, IMHO. But I'm sure if we
>have a close attenetion then it would definetly a ready peice for
>mainline and readable for future proof.
>
>Suggestions would be try to differentiate the code into driver and
>timings, so we can write drivers/ram and the timings would be some
>sort of dtsi or script or platdata would centainly ddr chip depenent.
>
>I can help here, based on my experince with rockchip ddr, if you need any?
@Anup Patel do you have any comment on this?
>
>Jagan.
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info
2020-01-28 6:41 ` Pragnesh Patel
@ 2020-02-04 15:19 ` Bin Meng
0 siblings, 0 replies; 32+ messages in thread
From: Bin Meng @ 2020-02-04 15:19 UTC (permalink / raw)
To: u-boot
On Tue, Jan 28, 2020 at 2:41 PM Pragnesh Patel
<pragnesh.patel@sifive.com> wrote:
>
>
> >-----Original Message-----
> >From: Jagan Teki <jagan@amarulasolutions.com>
> >Sent: 27 January 2020 13:22
> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
> ><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
> ><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
> ><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
> ><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
> >Kadam <sagar.kadam@sifive.com>
> >Subject: Re: [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info
> >
> >On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
> ><pragnesh.patel@sifive.com> wrote:
> >>
> >> Add ddr4 controller and phy related files
> >>
> >> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> >> ---
> >> board/sifive/fu540/Makefile | 4 +
> >> board/sifive/fu540/ddr.c | 868 ++++++++++++++++++++
> >> board/sifive/fu540/regconfig-ctl.h | 270 ++++++
> >> board/sifive/fu540/regconfig-phy.h | 1220
> >++++++++++++++++++++++++++++
> >> board/sifive/fu540/ux00ddr.h | 45 +
> >> 5 files changed, 2407 insertions(+)
> >> create mode 100644 board/sifive/fu540/ddr.c
> >> create mode 100644 board/sifive/fu540/regconfig-ctl.h
> >> create mode 100644 board/sifive/fu540/regconfig-phy.h
> >> create mode 100644 board/sifive/fu540/ux00ddr.h
> >>
[snip]
> >
> >Sorry, this entire ddr code look very difficult to undestand or
> >review. I understand it is driven from the vendor blog or so but it is
> >not in proper shape to mege it on mainline, IMHO. But I'm sure if we
> >have a close attenetion then it would definetly a ready peice for
> >mainline and readable for future proof.
> >
> >Suggestions would be try to differentiate the code into driver and
> >timings, so we can write drivers/ram and the timings would be some
> >sort of dtsi or script or platdata would centainly ddr chip depenent.
> >
I agree with Jagan. And if we don't write RAM drivers, perhaps we need
put these codes into arch/riscv/cpu/sifive for the memory controller
is SoC specific stuff.
> >I can help here, based on my experince with rockchip ddr, if you need any?
>
> @Anup Patel do you have any comment on this?
Regards,
Bin
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 01/10] misc: add driver for the Sifive otp controller
2020-01-27 10:18 ` Pragnesh Patel
@ 2020-02-10 12:44 ` Pragnesh Patel
0 siblings, 0 replies; 32+ messages in thread
From: Pragnesh Patel @ 2020-02-10 12:44 UTC (permalink / raw)
To: u-boot
Hi Jagan,
>-----Original Message-----
>From: Pragnesh Patel
>Sent: 27 January 2020 15:48
>To: Jagan Teki <jagan@amarulasolutions.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
>Kadam <sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Simon
>Glass <sjg@chromium.org>; Heiko Stuebner <heiko.stuebner@theobroma-
>systems.com>; Michal Simek <michal.simek@xilinx.com>; Marcel Ziswiler
><marcel.ziswiler@toradex.com>; Finley Xiao <finley.xiao@rock-chips.com>;
>Peng Fan <peng.fan@nxp.com>; Tero Kristo <t-kristo@ti.com>; Eugen Hristev
><eugen.hristev@microchip.com>
>Subject: RE: [PATCH v3 01/10] misc: add driver for the Sifive otp controller
>
>
>>-----Original Message-----
>>From: Jagan Teki <jagan@amarulasolutions.com>
>>Sent: 24 January 2020 12:12
>>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
>><atish.patra@wdc.com>; palmerdabbelt at google.com; Bin Meng
>><bmeng.cn@gmail.com>; Paul Walmsley ( Sifive)
>><paul.walmsley@sifive.com>; Troy Benjegerdes ( Sifive)
>><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
>>Kadam <sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Simon
>>Glass <sjg@chromium.org>; Heiko Stuebner <heiko.stuebner@theobroma-
>>systems.com>; Michal Simek <michal.simek@xilinx.com>; Marcel Ziswiler
>><marcel.ziswiler@toradex.com>; Finley Xiao
>><finley.xiao@rock-chips.com>; Peng Fan <peng.fan@nxp.com>; Tero Kristo
>><t-kristo@ti.com>; Eugen Hristev <eugen.hristev@microchip.com>
>>Subject: Re: [PATCH v3 01/10] misc: add driver for the Sifive otp
>>controller
>>
>>On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
>><pragnesh.patel@sifive.com>
>>wrote:
>>>
>>> Added a misc driver to handle OTP memory in FU540.
>>>
>>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>>> Reviewed-by: Anup Patel <anup.patel@wdc.com>
>>> ---
>>> arch/riscv/dts/fu540-c000-u-boot.dtsi | 13 ++
>>> .../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
>>> board/sifive/fu540/fu540.c | 113 ++++------
>>> configs/sifive_fu540_defconfig | 2 +
>>> drivers/misc/Kconfig | 7 +
>>> drivers/misc/Makefile | 1 +
>>> drivers/misc/ememory-otp.c | 207 ++++++++++++++++++
>>
>>This patch need to break into
>>1. add sifive otp driver
>>2. enable the otp driver - board, dts, defconfig changes.
>
>Will split in v4.
>
>>
>>> 7 files changed, 276 insertions(+), 73 deletions(-) create mode
>>> 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
>>> create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>>> create mode 100644 drivers/misc/ememory-otp.c
>>>
>>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>> b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>> new file mode 100644
>>> index 0000000000..615a68c0e9
>>> --- /dev/null
>>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>>> @@ -0,0 +1,13 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * (C) Copyright 2019 SiFive, Inc
>>> + */
>>> +
>>> +/ {
>>> + soc {
>>> + otp: otp at 10070000 {
>>> + compatible = "sifive,fu540-otp";
>>> + reg = <0x0 0x10070000 0x0 0x0FFF>;
>>> + };
>>> + };
>>> +};
>>> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>>> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>>> new file mode 100644
>>> index 0000000000..bec0d19134
>>> --- /dev/null
>>> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>>> @@ -0,0 +1,6 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright (C) 2019 SiFive, Inc
>>> + */
>>> +
>>> +#include "fu540-c000-u-boot.dtsi"
>>> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
>>> index 47a2090251..3a5e74f1fb 100644
>>> --- a/board/sifive/fu540/fu540.c
>>> +++ b/board/sifive/fu540/fu540.c
>>> @@ -10,94 +10,61 @@
>>> #include <dm.h>
>>> #include <linux/delay.h>
>>> #include <linux/io.h>
>>> +#include <misc.h>
>>>
>>> -#ifdef CONFIG_MISC_INIT_R
>>> -
>>> -#define FU540_OTP_BASE_ADDR 0x10070000
>>> -
>>> -struct fu540_otp_regs {
>>> - u32 pa; /* Address input */
>>> - u32 paio; /* Program address input */
>>> - u32 pas; /* Program redundancy cell selection input */
>>> - u32 pce; /* OTP Macro enable input */
>>> - u32 pclk; /* Clock input */
>>> - u32 pdin; /* Write data input */
>>> - u32 pdout; /* Read data output */
>>> - u32 pdstb; /* Deep standby mode enable input (active low) */
>>> - u32 pprog; /* Program mode enable input */
>>> - u32 ptc; /* Test column enable input */
>>> - u32 ptm; /* Test mode enable input */
>>> - u32 ptm_rep;/* Repair function test mode enable input */
>>> - u32 ptr; /* Test row enable input */
>>> - u32 ptrim; /* Repair function enable input */
>>> - u32 pwe; /* Write enable input (defines program cycle) */
>>> -} __packed;
>>> -
>>> -#define BYTES_PER_FUSE 4
>>> -#define NUM_FUSES 0x1000
>>> -
>>> -static int fu540_otp_read(int offset, void *buf, int size) -{
>>> - struct fu540_otp_regs *regs = (void __iomem
>>*)FU540_OTP_BASE_ADDR;
>>> - unsigned int i;
>>> - int fuseidx = offset / BYTES_PER_FUSE;
>>> - int fusecount = size / BYTES_PER_FUSE;
>>> - u32 fusebuf[fusecount];
>>> -
>>> - /* check bounds */
>>> - if (offset < 0 || size < 0)
>>> - return -EINVAL;
>>> - if (fuseidx >= NUM_FUSES)
>>> - return -EINVAL;
>>> - if ((fuseidx + fusecount) > NUM_FUSES)
>>> - return -EINVAL;
>>> -
>>> - /* init OTP */
>>> - writel(0x01, ®s->pdstb); /* wake up from stand-by */
>>> - writel(0x01, ®s->ptrim); /* enable repair function */
>>> - writel(0x01, ®s->pce); /* enable input */
>>> -
>>> - /* read all requested fuses */
>>> - for (i = 0; i < fusecount; i++, fuseidx++) {
>>> - writel(fuseidx, ®s->pa);
>>> -
>>> - /* cycle clock to read */
>>> - writel(0x01, ®s->pclk);
>>> - mdelay(1);
>>> - writel(0x00, ®s->pclk);
>>> - mdelay(1);
>>> -
>>> - /* read the value */
>>> - fusebuf[i] = readl(®s->pdout);
>>> - }
>>> -
>>> - /* shut down */
>>> - writel(0, ®s->pce);
>>> - writel(0, ®s->ptrim);
>>> - writel(0, ®s->pdstb);
>>> -
>>> - /* copy out */
>>> - memcpy(buf, fusebuf, size);
>>> +/*
>>> + * This define is a value used for error/unknown serial.
>>> + * If we really care about distinguishing errors and 0 is
>>> + * valid, we'll need a different one.
>>> + */
>>> +#define ERROR_READING_SERIAL_NUMBER 0
>>>
>>> - return 0;
>>> -}
>>> +#ifdef CONFIG_MISC_INIT_R
>>>
>>> -static u32 fu540_read_serialnum(void)
>>> +#if CONFIG_IS_ENABLED(EMEMORY_OTP)
>>> +static u32 otp_read_serialnum(struct udevice *dev)
>>> {
>>> int ret;
>>> u32 serial[2] = {0};
>>>
>>> for (int i = 0xfe * 4; i > 0; i -= 8) {
>>> - ret = fu540_otp_read(i, serial, sizeof(serial));
>>> + ret = misc_read(dev, i, serial, sizeof(serial));
>>> +
>>> if (ret) {
>>> - printf("%s: error reading from OTP\n", __func__);
>>> + printf("%s: error reading serial from OTP\n",
>>> + __func__);
>>> break;
>>> }
>>> +
>>> if (serial[0] == ~serial[1])
>>> return serial[0];
>>> }
>>>
>>> - return 0;
>>> + return ERROR_READING_SERIAL_NUMBER; } #endif
>>> +
>>> +static u32 fu540_read_serialnum(void) {
>>> + u32 serial = ERROR_READING_SERIAL_NUMBER;
>>> +
>>> +#if CONFIG_IS_ENABLED(EMEMORY_OTP)
>>> + struct udevice *dev;
>>> + int ret;
>>> +
>>> + // init OTP
>>> + ret = uclass_get_device_by_driver(UCLASS_MISC,
>>> + DM_GET_DRIVER(hifive_otp),
>>> + &dev);
>>> +
>>> + if (ret) {
>>> + debug("%s: could not find otp device\n", __func__);
>>> + return serial;
>>> + }
>>> +
>>> + // read serial from OTP and set env var
>>> + serial = otp_read_serialnum(dev); #endif
>>> +
>>> + return serial;
>>> }
>>>
>>> static void fu540_setup_macaddr(u32 serialnum) diff --git
>>> a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
>>> index 6d61e6c960..40e78f12a2 100644
>>> --- a/configs/sifive_fu540_defconfig
>>> +++ b/configs/sifive_fu540_defconfig
>>> @@ -6,6 +6,8 @@ CONFIG_ARCH_RV64I=y
>>> CONFIG_RISCV_SMODE=y
>>> CONFIG_DISTRO_DEFAULTS=y
>>> CONFIG_FIT=y
>>> +CONFIG_MISC=y
>>> +CONFIG_EMEMORY_OTP=y
>>
>>Look like this opt is needed global to SiFive, If so select MISC in arch Kconfig.
>
>Will update the "board/Sifive/fu540/Kconfig" in v4.
>
>>
>>> CONFIG_MISC_INIT_R=y
>>> CONFIG_DISPLAY_CPUINFO=y
>>> CONFIG_DISPLAY_BOARDINFO=y
>>> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
>>> f18aa8f7ba..cbda0deb14 100644
>>> --- a/drivers/misc/Kconfig
>>> +++ b/drivers/misc/Kconfig
>>> @@ -68,6 +68,13 @@ config ROCKCHIP_OTP
>>> addressing and a length or through child-nodes that are generated
>>> based on the e-fuse map retrieved from the DTS.
>>>
>>> +config EMEMORY_OTP
>>
>>What about SIFIVE_OTP or SIFIVE_EMEM_OTP or similar?
>
>Will change it to SIFIVE_OTP in v4.
>
>>
>>> + bool "Sifive Ememory OTP driver"
>>> + depends on RISCV && MISC
>>> + help
>>> + Enable support for reading the Ememory OTP on the HiFive
>Unleashed
>>> + OTP storage.
>>> +
>>> config VEXPRESS_CONFIG
>>> bool "Enable support for Arm Versatile Express config bus"
>>> depends on MISC
>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
>>> 2b843de93c..dcf9b628c8 100644
>>> --- a/drivers/misc/Makefile
>>> +++ b/drivers/misc/Makefile
>>> @@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
>>> obj-$(CONFIG_QFW) += qfw.o
>>> obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
>>> obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
>>> +obj-$(CONFIG_EMEMORY_OTP) += ememory-otp.o
>>> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
>>> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
>>> obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o diff --git
>>> a/drivers/misc/ememory-otp.c b/drivers/misc/ememory-otp.c new file
>>> mode 100644 index 0000000000..73e7af496a
>>> --- /dev/null
>>> +++ b/drivers/misc/ememory-otp.c
>>
>>Again file name, would have platform or soc naming convention.
>
>Agreed, will change in v4. Thanks for pointing me.
>
>>
>>> @@ -0,0 +1,207 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
>>> + * One-Time-Programmable (OTP) memory used within the SiFive FU540.
>>> + * It is documented in the FU540 manual here:
>>> + *
>>> +https://www.sifive.com/documentation/chips/freedom-u540-c000-
>>manual/
>>> + *
>>> + * Copyright (C) 2018 Philipp Hug <philipp@hug.cx>
>>> + * Copyright (C) 2018 Joey Hewitt <joey@joeyhewitt.com>
>>> + *
>>> + * Copyright (C) 2020 SiFive, Inc
>>> + */
>>> +
>>> +/*
>>> + * The FU540 stores 4096x32 bit (16KiB) values.
>>> + * Index 0x00-0xff are reserved for SiFive internal use. (first
>>> +1KiB) */
>>
>>Sorry, I didn't understand this comments. If it is memory map detail
>>that occupy otp, try to elaborate more by giving full details. Would
>>helpful to understand anyone in future.
>
>Right now, OTP is used only for serial number. First 1 KB is reserved for Sifive
>Internal use, serial number is one of them.
>
>>
>>> +
>>> +#include <common.h>
>>> +#include <dm/device.h>
>>> +#include <dm/read.h>
>>> +#include <linux/io.h>
>>> +#include <misc.h>
>>> +
>>> +struct hifive_otp_regs {
>>> + u32 pa; /* Address input */
>>> + u32 paio; /* Program address input */
>>> + u32 pas; /* Program redundancy cell selection input */
>>> + u32 pce; /* OTP Macro enable input */
>>> + u32 pclk; /* Clock input */
>>> + u32 pdin; /* Write data input */
>>> + u32 pdout; /* Read data output */
>>> + u32 pdstb; /* Deep standby mode enable input (active low) */
>>> + u32 pprog; /* Program mode enable input */
>>> + u32 ptc; /* Test column enable input */
>>> + u32 ptm; /* Test mode enable input */
>>> + u32 ptm_rep;/* Repair function test mode enable input */
>>> + u32 ptr; /* Test row enable input */
>>> + u32 ptrim; /* Repair function enable input */
>>> + u32 pwe; /* Write enable input (defines program cycle) */
>>> +} __packed;
>>> +
>>> +struct hifive_otp_platdata {
>>
>>hifive here represent the board name, butter use soc name that has this otp.
>
>Will update in v4.
>
>>
>>> + struct hifive_otp_regs __iomem *regs; };
>>> +
>>> +typedef u32 fuse_value_t;
>>
>>No typdef please.
>>No global variables(unless it really need)
>
>Will update in v4, thanks.
>
>>
>>> +#define BYTES_PER_FUSE 4
>>> +
>>> +#define NUM_FUSES 0x1000
>>
>>May be use dt properties.
>
>Will check this.
>
>>
>>> +
>>> +/*
>>> + * offset and size are assumed aligned to the size of the fuses (32bit).
>>> + */
>>> +static int hifive_otp_read(struct udevice *dev, int offset,
>>> + void *buf, int size) {
>>> + struct hifive_otp_platdata *plat = dev_get_platdata(dev);
>>> + struct hifive_otp_regs *regs = (struct hifive_otp_regs
>>> +*)plat->regs;
>>> +
>>> + int fuseidx = offset / BYTES_PER_FUSE;
>>> + int fusecount = size / BYTES_PER_FUSE;
>>> + fuse_value_t fusebuf[fusecount];
>>> +
>>> + // check bounds
>>
>>use proper comment style.
>
>Will update in v4.
>
>>
>>> + if (offset < 0 || size < 0)
>>> + return -EINVAL;
>>> + if (fuseidx >= NUM_FUSES)
>>> + return -EINVAL;
>>> + if ((fuseidx + fusecount) > NUM_FUSES)
>>> + return -EINVAL;
>>> +
>>> + // init OTP
>>> + iowrite32(0x01, ®s->pdstb); // wake up from stand-by
>>> + iowrite32(0x01, ®s->ptrim); // enable repair function
>>> + iowrite32(0x01, ®s->pce); // enable input
>>
>>use macros with proper bit names, like 0x01 would have proper macro.
>
>Will update in v4.
>
>>
>>> +
>>> + // read all requested fuses
>>> + for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
>>> + iowrite32(fuseidx, ®s->pa);
>>> +
>>> + // cycle clock to read
>>> + iowrite32(0x01, ®s->pclk);
>>> + mdelay(1);
>>> + iowrite32(0x00, ®s->pclk);
>>> + mdelay(1);
>>> +
>>> + // read the value
>>> + fusebuf[i] = ioread32(®s->pdout);
>>> + }
>>> +
>>> + // shut down
>>> + iowrite32(0, ®s->pce);
>>> + iowrite32(0, ®s->ptrim);
>>> + iowrite32(0, ®s->pdstb);
>>> +
>>> + // copy out
>>> + memcpy(buf, fusebuf, size);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +/*
>>> + * Caution:
>>> + * OTP can be write only once, so use carefully.
>>
>>can be written
>
>Thanks, will update in v4.
>
>>
>>> + *
>>> + * offset and size are assumed aligned to the size of the fuses (32bit).
>>> + */
>>> +static int hifive_otp_write(struct udevice *dev, int offset,
>>> + const void *buf, int size) {
>>> + struct hifive_otp_platdata *plat = dev_get_platdata(dev);
>>> + struct hifive_otp_regs *regs = (struct hifive_otp_regs
>>> +*)plat->regs;
>>> +
>>> + int fuseidx = offset / BYTES_PER_FUSE;
>>> + int fusecount = size / BYTES_PER_FUSE;
>>> + u32 *write_buf = (u32 *)buf;
>>> + u32 write_data;
>>> + int i, pas, bit;
>>> +
>>> + // check bounds
>>> + if (offset < 0 || size < 0)
>>> + return -EINVAL;
>>> + if (fuseidx >= NUM_FUSES)
>>> + return -EINVAL;
>>> + if ((fuseidx + fusecount) > NUM_FUSES)
>>> + return -EINVAL;
>>
>>We have lib functions to do this bound, would you please try to use that.
Which lib functions you want me to use here ?
>
>Will check and update in v4, thanks for the review.
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2020-02-10 12:44 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-24 5:50 [PATCH v3 00/10] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 01/10] misc: add driver for the Sifive otp controller Pragnesh Patel
2020-01-24 6:41 ` Jagan Teki
2020-01-27 10:18 ` Pragnesh Patel
2020-02-10 12:44 ` Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 02/10] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-01-24 6:44 ` Jagan Teki
2020-01-24 5:50 ` [PATCH v3 03/10] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-01-24 6:27 ` Jagan Teki
2020-01-24 8:06 ` Pragnesh Patel
2020-01-27 7:58 ` Jagan Teki
2020-01-24 5:50 ` [PATCH v3 04/10] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 05/10] riscv: sifive: fu540: add DDR4 info Pragnesh Patel
2020-01-25 8:31 ` Anup Patel
2020-01-27 7:51 ` Jagan Teki
2020-01-28 6:41 ` Pragnesh Patel
2020-02-04 15:19 ` Bin Meng
2020-01-24 5:50 ` [PATCH v3 06/10] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-01-25 8:35 ` Anup Patel
2020-01-24 5:50 ` [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL Pragnesh Patel
2020-01-24 6:50 ` Jagan Teki
2020-01-25 8:41 ` Anup Patel
2020-01-27 7:49 ` Pragnesh Patel
2020-01-27 12:45 ` Anup Patel
2020-01-27 6:50 ` Pragnesh Patel
2020-01-27 7:38 ` Anup Patel
2020-01-27 7:41 ` Pragnesh Patel
2020-01-24 5:50 ` [PATCH v3 08/10] riscv: sifive: fu540: enable all cache ways from u-boot proper Pragnesh Patel
2020-01-25 8:36 ` Anup Patel
2020-01-24 5:50 ` [PATCH v3 09/10] sifive: fix palmer's email address and add sifive_fu540_spl_defconfig Pragnesh Patel
2020-01-25 8:37 ` Anup Patel
2020-01-24 5:50 ` [PATCH v3 10/10] doc: update FU540 RISC-V documentation Pragnesh Patel
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