From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <alistair.francis@wdc.com> Cc: Palmer Dabbelt <palmer@dabbelt.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Alistair Francis <alistair23@gmail.com> Subject: Re: [PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU Date: Fri, 15 May 2020 12:57:27 +0800 [thread overview] Message-ID: <CAEUhbmWJ0TsPnCUtawfpXm=N=qX+X=Fby0r9WeufN8TD31=3_Q@mail.gmail.com> (raw) In-Reply-To: <698e2a1723bbf04ffa941450f7a351397bcec789.1588878756.git.alistair.francis@wdc.com> On Fri, May 8, 2020 at 3:23 AM Alistair Francis <alistair.francis@wdc.com> wrote: > Please include some commit message to have a brief introduction of this new CPU. > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8f837edf8d..235101f685 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -160,6 +160,15 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) > set_feature(env, RISCV_FEATURE_PMP); > } > > +static void rv32imcu_nommu_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVC | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > + set_resetvec(env, 0x8088); > + set_feature(env, RISCV_FEATURE_PMP); > +} > + > static void rv32imacu_nommu_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -620,6 +629,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), > #if defined(TARGET_RISCV32) > DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index d0e7f5b9c5..8733d7467f 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -35,6 +35,7 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > -- Otherwise, looks good to me. Reviewed-by: Bin Meng <bin.meng@windriver.com> Regards, Bin
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <alistair.francis@wdc.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair23@gmail.com> Subject: Re: [PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU Date: Fri, 15 May 2020 12:57:27 +0800 [thread overview] Message-ID: <CAEUhbmWJ0TsPnCUtawfpXm=N=qX+X=Fby0r9WeufN8TD31=3_Q@mail.gmail.com> (raw) In-Reply-To: <698e2a1723bbf04ffa941450f7a351397bcec789.1588878756.git.alistair.francis@wdc.com> On Fri, May 8, 2020 at 3:23 AM Alistair Francis <alistair.francis@wdc.com> wrote: > Please include some commit message to have a brief introduction of this new CPU. > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8f837edf8d..235101f685 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -160,6 +160,15 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) > set_feature(env, RISCV_FEATURE_PMP); > } > > +static void rv32imcu_nommu_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVC | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > + set_resetvec(env, 0x8088); > + set_feature(env, RISCV_FEATURE_PMP); > +} > + > static void rv32imacu_nommu_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -620,6 +629,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), > #if defined(TARGET_RISCV32) > DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index d0e7f5b9c5..8733d7467f 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -35,6 +35,7 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > -- Otherwise, looks good to me. Reviewed-by: Bin Meng <bin.meng@windriver.com> Regards, Bin
next prev parent reply other threads:[~2020-05-15 4:58 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-07 19:12 [PATCH v2 0/9] RISC-V Add the OpenTitan Machine Alistair Francis 2020-05-07 19:12 ` Alistair Francis 2020-05-07 19:13 ` [PATCH v2 1/9] riscv/boot: Add a missing header include Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-14 15:33 ` Bin Meng 2020-05-14 15:33 ` Bin Meng 2020-05-14 15:30 ` Alistair Francis 2020-05-14 15:30 ` Alistair Francis 2020-05-14 15:46 ` Bin Meng 2020-05-14 15:46 ` Bin Meng 2020-05-14 17:51 ` Philippe Mathieu-Daudé 2020-05-14 17:51 ` Philippe Mathieu-Daudé 2020-05-15 5:00 ` Bin Meng 2020-05-15 5:00 ` Bin Meng 2020-05-07 19:13 ` [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-14 17:54 ` Philippe Mathieu-Daudé 2020-05-14 17:54 ` Philippe Mathieu-Daudé 2020-05-14 21:42 ` Alistair Francis 2020-05-14 21:42 ` Alistair Francis 2020-05-15 4:54 ` Bin Meng 2020-05-15 4:54 ` Bin Meng 2020-05-15 19:43 ` Alistair Francis 2020-05-15 19:43 ` Alistair Francis 2020-05-16 9:03 ` Bin Meng 2020-05-16 9:03 ` Bin Meng 2020-05-19 18:03 ` Alistair Francis 2020-05-19 18:03 ` Alistair Francis 2020-05-07 19:13 ` [PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-15 4:57 ` Bin Meng [this message] 2020-05-15 4:57 ` Bin Meng 2020-05-07 19:13 ` [PATCH v2 4/9] riscv: Initial commit of OpenTitan machine Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-15 5:14 ` Bin Meng 2020-05-15 5:14 ` Bin Meng 2020-05-07 19:13 ` [PATCH v2 5/9] hw/char: Initial commit of Ibex UART Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-14 17:59 ` Philippe Mathieu-Daudé 2020-05-14 17:59 ` Philippe Mathieu-Daudé 2020-05-14 21:59 ` Alistair Francis 2020-05-14 21:59 ` Alistair Francis 2020-05-15 7:25 ` Philippe Mathieu-Daudé 2020-05-15 7:25 ` Philippe Mathieu-Daudé 2020-05-15 7:28 ` Philippe Mathieu-Daudé 2020-05-15 7:28 ` Philippe Mathieu-Daudé 2020-05-15 19:46 ` Alistair Francis 2020-05-15 19:46 ` Alistair Francis 2020-05-07 19:13 ` [PATCH v2 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-14 18:40 ` Philippe Mathieu-Daudé 2020-05-14 18:40 ` Philippe Mathieu-Daudé 2020-05-14 21:53 ` Alistair Francis 2020-05-14 21:53 ` Alistair Francis 2020-05-07 19:13 ` [PATCH v2 7/9] riscv/opentitan: Connect the PLIC device Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-15 6:29 ` Bin Meng 2020-05-15 6:29 ` Bin Meng 2020-05-07 19:13 ` [PATCH v2 8/9] riscv/opentitan: Connect the UART device Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-15 6:29 ` Bin Meng 2020-05-15 6:29 ` Bin Meng 2020-05-07 19:13 ` [PATCH v2 9/9] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis 2020-05-07 19:13 ` Alistair Francis 2020-05-15 6:28 ` Bin Meng 2020-05-15 6:28 ` Bin Meng 2020-05-13 18:18 ` [PATCH v2 0/9] RISC-V Add the OpenTitan Machine Alistair Francis 2020-05-13 18:18 ` Alistair Francis
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