From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v2 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
Date: Fri, 15 May 2020 14:28:59 +0800 [thread overview]
Message-ID: <CAEUhbmXnAcXPsa90JuHaqCu0HHot+dScx+mH8rR=SetxJx-ajA@mail.gmail.com> (raw)
In-Reply-To: <246b1d1fa8d1ad334152ace0cad21e8f40d53e7f.1588878756.git.alistair.francis@wdc.com>
On Fri, May 8, 2020 at 3:29 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/pmp.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 0e6b640fbd..5aba4d13ea 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -233,12 +233,21 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> return true;
> }
>
> - /*
> - * if size is unknown (0), assume that all bytes
> - * from addr to the end of the page will be accessed.
> - */
> if (size == 0) {
> - pmp_size = -(addr | TARGET_PAGE_MASK);
> + if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
> + /*
> + * if size is unknown (0), assume that all bytes
> + * from addr to the end of the page will be accessed.
> + */
> + pmp_size = -(addr | TARGET_PAGE_MASK);
> + } else {
> + /*
> + * If size is unknown (0) and we don't have an MMU,
> + * just guess the size as the xlen as we don't want to
> + * access an entire page worth.
> + */
It looks the comment does not match the code logic. This else branch
is the MMU branch.
> + pmp_size = sizeof(target_ulong);
> + }
> } else {
> pmp_size = size;
> }
> --
Regards,
Bin
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v2 9/9] target/riscv: Use a smaller guess size for no-MMU PMP
Date: Fri, 15 May 2020 14:28:59 +0800 [thread overview]
Message-ID: <CAEUhbmXnAcXPsa90JuHaqCu0HHot+dScx+mH8rR=SetxJx-ajA@mail.gmail.com> (raw)
In-Reply-To: <246b1d1fa8d1ad334152ace0cad21e8f40d53e7f.1588878756.git.alistair.francis@wdc.com>
On Fri, May 8, 2020 at 3:29 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/pmp.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 0e6b640fbd..5aba4d13ea 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -233,12 +233,21 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> return true;
> }
>
> - /*
> - * if size is unknown (0), assume that all bytes
> - * from addr to the end of the page will be accessed.
> - */
> if (size == 0) {
> - pmp_size = -(addr | TARGET_PAGE_MASK);
> + if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
> + /*
> + * if size is unknown (0), assume that all bytes
> + * from addr to the end of the page will be accessed.
> + */
> + pmp_size = -(addr | TARGET_PAGE_MASK);
> + } else {
> + /*
> + * If size is unknown (0) and we don't have an MMU,
> + * just guess the size as the xlen as we don't want to
> + * access an entire page worth.
> + */
It looks the comment does not match the code logic. This else branch
is the MMU branch.
> + pmp_size = sizeof(target_ulong);
> + }
> } else {
> pmp_size = size;
> }
> --
Regards,
Bin
next prev parent reply other threads:[~2020-05-15 6:30 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-07 19:12 [PATCH v2 0/9] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-07 19:12 ` Alistair Francis
2020-05-07 19:13 ` [PATCH v2 1/9] riscv/boot: Add a missing header include Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-14 15:33 ` Bin Meng
2020-05-14 15:33 ` Bin Meng
2020-05-14 15:30 ` Alistair Francis
2020-05-14 15:30 ` Alistair Francis
2020-05-14 15:46 ` Bin Meng
2020-05-14 15:46 ` Bin Meng
2020-05-14 17:51 ` Philippe Mathieu-Daudé
2020-05-14 17:51 ` Philippe Mathieu-Daudé
2020-05-15 5:00 ` Bin Meng
2020-05-15 5:00 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 2/9] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-14 17:54 ` Philippe Mathieu-Daudé
2020-05-14 17:54 ` Philippe Mathieu-Daudé
2020-05-14 21:42 ` Alistair Francis
2020-05-14 21:42 ` Alistair Francis
2020-05-15 4:54 ` Bin Meng
2020-05-15 4:54 ` Bin Meng
2020-05-15 19:43 ` Alistair Francis
2020-05-15 19:43 ` Alistair Francis
2020-05-16 9:03 ` Bin Meng
2020-05-16 9:03 ` Bin Meng
2020-05-19 18:03 ` Alistair Francis
2020-05-19 18:03 ` Alistair Francis
2020-05-07 19:13 ` [PATCH v2 3/9] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-15 4:57 ` Bin Meng
2020-05-15 4:57 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 4/9] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-15 5:14 ` Bin Meng
2020-05-15 5:14 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 5/9] hw/char: Initial commit of Ibex UART Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-14 17:59 ` Philippe Mathieu-Daudé
2020-05-14 17:59 ` Philippe Mathieu-Daudé
2020-05-14 21:59 ` Alistair Francis
2020-05-14 21:59 ` Alistair Francis
2020-05-15 7:25 ` Philippe Mathieu-Daudé
2020-05-15 7:25 ` Philippe Mathieu-Daudé
2020-05-15 7:28 ` Philippe Mathieu-Daudé
2020-05-15 7:28 ` Philippe Mathieu-Daudé
2020-05-15 19:46 ` Alistair Francis
2020-05-15 19:46 ` Alistair Francis
2020-05-07 19:13 ` [PATCH v2 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-14 18:40 ` Philippe Mathieu-Daudé
2020-05-14 18:40 ` Philippe Mathieu-Daudé
2020-05-14 21:53 ` Alistair Francis
2020-05-14 21:53 ` Alistair Francis
2020-05-07 19:13 ` [PATCH v2 7/9] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-15 6:29 ` Bin Meng
2020-05-15 6:29 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 8/9] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-15 6:29 ` Bin Meng
2020-05-15 6:29 ` Bin Meng
2020-05-07 19:13 ` [PATCH v2 9/9] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-05-07 19:13 ` Alistair Francis
2020-05-15 6:28 ` Bin Meng [this message]
2020-05-15 6:28 ` Bin Meng
2020-05-13 18:18 ` [PATCH v2 0/9] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-13 18:18 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAEUhbmXnAcXPsa90JuHaqCu0HHot+dScx+mH8rR=SetxJx-ajA@mail.gmail.com' \
--to=bmeng.cn@gmail.com \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.