Re: [PATCH v2 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC

[Alistair Francis <alistair23@gmail.com>]

On Thu, May 14, 2020 at 11:40 AM Philippe Mathieu-Daudé
<philmd@redhat.com> wrote:
>
> On 5/7/20 9:13 PM, Alistair Francis wrote:
> > The Ibex core contains a PLIC that although similar to the RISC-V spec
> > is not RISC-V spec compliant.
> >
> > This patch implements a Ibex PLIC in a somewhat generic way.
> >
> > As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex
> > PLIC move towards spec compliance this PLIC implementation can be
> > updated until it can replace the current PLIC.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >   MAINTAINERS                 |   2 +
> >   hw/intc/Makefile.objs       |   1 +
> >   hw/intc/ibex_plic.c         | 261 ++++++++++++++++++++++++++++++++++++
> >   include/hw/intc/ibex_plic.h |  63 +++++++++
> >   4 files changed, 327 insertions(+)
> >   create mode 100644 hw/intc/ibex_plic.c
> >   create mode 100644 include/hw/intc/ibex_plic.h
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index d3d47564ce..f8c3cf6182 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1237,8 +1237,10 @@ L: qemu-riscv@nongnu.org
> >   S: Supported
> >   F: hw/riscv/opentitan.c
> >   F: hw/char/ibex_uart.c
> > +F: hw/intc/ibex_plic.c
> >   F: include/hw/riscv/opentitan.h
> >   F: include/hw/char/ibex_uart.h
> > +F: include/hw/intc/ibex_plic.h
> >
> >
> >   SH4 Machines
> > diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> > index f726d87532..a61e6728fe 100644
> > --- a/hw/intc/Makefile.objs
> > +++ b/hw/intc/Makefile.objs
> > @@ -49,3 +49,4 @@ obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o
> >   obj-$(CONFIG_MIPS_CPS) += mips_gic.o
> >   obj-$(CONFIG_NIOS2) += nios2_iic.o
> >   obj-$(CONFIG_OMPIC) += ompic.o
> > +obj-$(CONFIG_IBEX) += ibex_plic.o
> > diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> > new file mode 100644
> > index 0000000000..35c52d9d16
> > --- /dev/null
> > +++ b/hw/intc/ibex_plic.c
> > @@ -0,0 +1,261 @@
> > +/*
> > + * QEMU RISC-V lowRISC Ibex PLIC
> > + *
> > + * Copyright (c) 2020 Western Digital
> > + *
> > + * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2 or later, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along with
> > + * this program.  If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/core/cpu.h"
> > +#include "hw/boards.h"
> > +#include "hw/pci/msi.h"
> > +#include "target/riscv/cpu_bits.h"
> > +#include "target/riscv/cpu.h"
> > +#include "hw/intc/ibex_plic.h"
> > +
> > +static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
> > +{
> > +    uint32_t end = base + (num * 0x04);
> > +
> > +    if (addr >= base && addr < end) {
> > +        return true;
> > +    }
> > +
> > +    return false;
> > +}
> > +
> > +static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
> > +{
> > +    int pending_num = irq / 32;
> > +
> > +    s->pending[pending_num] |= level << (irq % 32);
> > +}
> > +
> > +static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
> > +{
> > +    int i;
> > +
> > +    for (i = 0; i < s->pending_num; i++) {
> > +        uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
> > +
> > +        if (!(s->pending[i] & s->enable[i])) {
> > +            /* No pending and enabled IRQ */
> > +            continue;
> > +        }
> > +
> > +        if (s->priority[irq_num] > s->threshold) {
> > +            if (!s->claim) {
> > +                s->claim = irq_num;
> > +            }
> > +            return true;
> > +        }
> > +    }
> > +
> > +    return 0;
>
> return 'false'.

Fixed.

>
> > +}
> > +
> > +static void ibex_plic_update(IbexPlicState *s)
> > +{
> > +    CPUState *cpu;
> > +    int level, i;
> > +
> > +    for (i = 0; i < s->num_cpus; i++) {
> > +        cpu = qemu_get_cpu(i);
> > +
> > +        if (!cpu) {
> > +            continue;
> > +        }
> > +
> > +        level = ibex_plic_irqs_pending(s, 0);
> > +
> > +        riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
> > +    }
> > +}
> > +
> > +static void ibex_plic_reset(DeviceState *dev)
> > +{
> > +    IbexPlicState *s = IBEX_PLIC(dev);
> > +
> > +    s->threshold = 0x00000000;
> > +    s->claim = 0x00000000;
>
> I haven't check the datasheet reset values, for the rest:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Thanks for reviewing these :)

Alistair