* [PATCH] riscv: dts: microchip: Define hart clocks
@ 2021-06-16 6:27 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2021-06-16 6:27 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Declare that each hart in the DT is clocked by <&clkcfg 0>.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/,
this adds the same <clock> property to PolarFire SoC CPU nodes so that we can
calculate the running frequency of the hart.
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index a00d9dc560d3..0659068b62f7 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -24,6 +24,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg 0>;
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -50,6 +51,7 @@ cpu@1 {
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu1_intc: interrupt-controller {
@@ -76,6 +78,7 @@ cpu@2 {
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu2_intc: interrupt-controller {
@@ -102,6 +105,7 @@ cpu@3 {
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu3_intc: interrupt-controller {
@@ -128,6 +132,7 @@ cpu@4 {
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH] riscv: dts: microchip: Define hart clocks
@ 2021-06-16 6:27 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2021-06-16 6:27 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Declare that each hart in the DT is clocked by <&clkcfg 0>.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/,
this adds the same <clock> property to PolarFire SoC CPU nodes so that we can
calculate the running frequency of the hart.
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index a00d9dc560d3..0659068b62f7 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -24,6 +24,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg 0>;
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -50,6 +51,7 @@ cpu@1 {
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu1_intc: interrupt-controller {
@@ -76,6 +78,7 @@ cpu@2 {
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu2_intc: interrupt-controller {
@@ -102,6 +105,7 @@ cpu@3 {
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu3_intc: interrupt-controller {
@@ -128,6 +132,7 @@ cpu@4 {
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&clkcfg 0>;
status = "okay";
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] riscv: dts: microchip: Define hart clocks
2021-06-16 6:27 ` Bin Meng
@ 2021-07-08 13:39 ` Bin Meng
-1 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2021-07-08 13:39 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Atish Patra, linux-kernel, linux-riscv
Cc: Bin Meng
On Wed, Jun 16, 2021 at 2:27 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Declare that each hart in the DT is clocked by <&clkcfg 0>.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
>
> ---
> Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/,
> this adds the same <clock> property to PolarFire SoC CPU nodes so that we can
> calculate the running frequency of the hart.
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
Ping?
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: dts: microchip: Define hart clocks
2021-06-16 6:27 ` Bin Meng
@ 2021-07-13 15:31 ` Conor.Dooley
-1 siblings, 0 replies; 6+ messages in thread
From: Conor.Dooley @ 2021-07-13 15:31 UTC (permalink / raw)
To: bmeng.cn, palmer, paul.walmsley, atish.patra, linux-kernel, linux-riscv
Cc: bin.meng
On 16/06/2021 07:27, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Declare that each hart in the DT is clocked by <&clkcfg 0>.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
>
> ---
> Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/,
> this adds the same <clock> property to PolarFire SoC CPU nodes so that we can
> calculate the running frequency of the hart.
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index a00d9dc560d3..0659068b62f7 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -24,6 +24,7 @@ cpu@0 {
> i-cache-size = <16384>;
> reg = <0>;
> riscv,isa = "rv64imac";
> + clocks = <&clkcfg 0>;
> status = "disabled";
>
> cpu0_intc: interrupt-controller {
> @@ -50,6 +51,7 @@ cpu@1 {
> reg = <1>;
> riscv,isa = "rv64imafdc";
> tlb-split;
> + clocks = <&clkcfg 0>;
> status = "okay";
>
> cpu1_intc: interrupt-controller {
> @@ -76,6 +78,7 @@ cpu@2 {
> reg = <2>;
> riscv,isa = "rv64imafdc";
> tlb-split;
> + clocks = <&clkcfg 0>;
> status = "okay";
>
> cpu2_intc: interrupt-controller {
> @@ -102,6 +105,7 @@ cpu@3 {
> reg = <3>;
> riscv,isa = "rv64imafdc";
> tlb-split;
> + clocks = <&clkcfg 0>;
> status = "okay";
>
> cpu3_intc: interrupt-controller {
> @@ -128,6 +132,7 @@ cpu@4 {
> reg = <4>;
> riscv,isa = "rv64imafdc";
> tlb-split;
> + clocks = <&clkcfg 0>;
> status = "okay";
> cpu4_intc: interrupt-controller {
> #interrupt-cells = <1>;
> --
> 2.25.1
>
Reviewed-by: conor dooley<conor.dooley@microchip.com>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] riscv: dts: microchip: Define hart clocks
@ 2021-07-13 15:31 ` Conor.Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor.Dooley @ 2021-07-13 15:31 UTC (permalink / raw)
To: bmeng.cn, palmer, paul.walmsley, atish.patra, linux-kernel, linux-riscv
Cc: bin.meng
On 16/06/2021 07:27, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Declare that each hart in the DT is clocked by <&clkcfg 0>.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
>
> ---
> Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/,
> this adds the same <clock> property to PolarFire SoC CPU nodes so that we can
> calculate the running frequency of the hart.
>
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index a00d9dc560d3..0659068b62f7 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -24,6 +24,7 @@ cpu@0 {
> i-cache-size = <16384>;
> reg = <0>;
> riscv,isa = "rv64imac";
> + clocks = <&clkcfg 0>;
> status = "disabled";
>
> cpu0_intc: interrupt-controller {
> @@ -50,6 +51,7 @@ cpu@1 {
> reg = <1>;
> riscv,isa = "rv64imafdc";
> tlb-split;
> + clocks = <&clkcfg 0>;
> status = "okay";
>
> cpu1_intc: interrupt-controller {
> @@ -76,6 +78,7 @@ cpu@2 {
> reg = <2>;
> riscv,isa = "rv64imafdc";
> tlb-split;
> + clocks = <&clkcfg 0>;
> status = "okay";
>
> cpu2_intc: interrupt-controller {
> @@ -102,6 +105,7 @@ cpu@3 {
> reg = <3>;
> riscv,isa = "rv64imafdc";
> tlb-split;
> + clocks = <&clkcfg 0>;
> status = "okay";
>
> cpu3_intc: interrupt-controller {
> @@ -128,6 +132,7 @@ cpu@4 {
> reg = <4>;
> riscv,isa = "rv64imafdc";
> tlb-split;
> + clocks = <&clkcfg 0>;
> status = "okay";
> cpu4_intc: interrupt-controller {
> #interrupt-cells = <1>;
> --
> 2.25.1
>
Reviewed-by: conor dooley<conor.dooley@microchip.com>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-07-13 15:31 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-16 6:27 [PATCH] riscv: dts: microchip: Define hart clocks Bin Meng
2021-06-16 6:27 ` Bin Meng
2021-07-08 13:39 ` Bin Meng
2021-07-08 13:39 ` Bin Meng
2021-07-13 15:31 ` Conor.Dooley
2021-07-13 15:31 ` Conor.Dooley
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