[U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL

[U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL

[Simon Glass]

At present SPL is used on 64-bit platforms, to allow SPL to be built as
a 32-bit program and U-Boot proper to be built as 64-bit.

However it is useful to be able to use SPL on any x86 platform, where
U-Boot needs to be updated in the field. Then SPL can select which U-Boot
to run (A or B) and most of the code can be updated. Similarly, using TPL
allows both SPL and U-Boot to be updated. This is the best approach, since
it means that all of U-Boot proper as well as SPL (in particular SDRAM
init) can be updated in the field. This provides for the smallest possible
amount of read-only (non-updateable) code: just the TPL code.

This series contains a number of changes to allow x86 boards to use TPL,
SPL and U-Boot proper. As a test, it is enabled for samus with a new
chromebook_samus_tpl board.

Changes in v3:
- Rebase to x86/master
- Use acpi_s3.h header for constants (and tidy up header order)
- Fix multi-line comment format
- Remove unneeded pch-reset node
- Drop unnecessary change to chromebook_link_defconfig

Changes in v2:
- Update the commit message to explain the implications on aliases
- Add new patch to separate out the EFI code in sysreset
- Add new patch to implement power-off if available
- Add a comment about the hard-coded text base
- Add new patch to enable the RTC in Kconfig
- Add a new patch to update PCH to work in TPL
- Add a new patch allowing jumping from TPL to SPL
- Sort defconfig and adjust it to build after rebase on maste

Simon Glass (18):
  cros_ec: Use a hyphen in the uclass name
  x86: Add a simple TPL implementation
  x86: sysreset: Separate out the EFI code
  x86: sysreset: Implement power-off if available
  x86: sysreset: Implement the get_last() method
  x86: Add documention on the samus flashmap
  x86: samus: Update device tree for SPL
  x86: samus: Update device tree for verified boot
  x86: Update device tree for TPL
  x86: Update device tree for Chromium OS verified boot
  x86: Fix device-tree indentation
  x86: samus: Increase the pre-reloc memory again
  Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
  x86: Enable the RTC on all boards
  x86: Update the memory map a little
  x86: broadwell: Update PCH to work in TPL
  x86: Add a way to jump from TPL to SPL
  x86: samus: Add a target to boot through TPL

 arch/Kconfig                              |   1 +
 arch/x86/cpu/broadwell/pch.c              |  12 +-
 arch/x86/cpu/start.S                      |  13 ++
 arch/x86/dts/chromebook_samus.dts         |  55 +++++++-
 arch/x86/dts/u-boot.dtsi                  | 162 ++++++++++++++--------
 arch/x86/include/asm/spl.h                |  17 ++-
 arch/x86/lib/Makefile                     |   9 +-
 arch/x86/lib/spl.c                        |  44 +++++-
 arch/x86/lib/tpl.c                        | 118 ++++++++++++++++
 board/google/Kconfig                      |   8 ++
 board/google/chromebook_samus/Kconfig     |  14 +-
 board/google/chromebook_samus/MAINTAINERS |   7 +
 configs/chromebook_samus_defconfig        |   2 +-
 configs/chromebook_samus_tpl_defconfig    |  82 +++++++++++
 doc/README.x86                            |  16 +++
 drivers/misc/cros_ec.c                    |   2 +-
 drivers/sysreset/sysreset_x86.c           | 101 +++++++++++++-
 include/configs/chromebook_link.h         |   3 -
 include/configs/chromebook_samus.h        |   2 +
 include/configs/qemu-x86.h                |   5 -
 include/configs/x86-common.h              |   1 -
 include/pci.h                             |   6 +-
 22 files changed, 583 insertions(+), 97 deletions(-)
 create mode 100644 arch/x86/lib/tpl.c
 create mode 100644 configs/chromebook_samus_tpl_defconfig

-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 01/18] cros_ec: Use a hyphen in the uclass name

[Simon Glass]

Device-tree rules require that aliases use a hyphen rather than a
underscore. Update the uclass name to fit with this.

This allows device-tree aliases to be used to refer to cros-ec devices,
for example:

	aliases {
	    cros-ec0 = &ec;
	    cros-ec1 = &pd;
	};

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2:
- Update the commit message to explain the implications on aliases

 drivers/misc/cros_ec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 565de040fe9..382f8262863 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1482,7 +1482,7 @@ int cros_ec_set_lid_shutdown_mask(struct udevice *dev, int enable)
 
 UCLASS_DRIVER(cros_ec) = {
 	.id		= UCLASS_CROS_EC,
-	.name		= "cros_ec",
+	.name		= "cros-ec",
 	.per_device_auto_alloc_size = sizeof(struct cros_ec_dev),
 	.post_bind	= dm_scan_fdt_dev,
 	.flags		= DM_UC_FLAG_ALLOC_PRIV_DMA,
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 02/18] x86: Add a simple TPL implementation

[Simon Glass]

Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Rebase to x86/master

Changes in v2: None

 arch/x86/include/asm/spl.h        |  17 ++++-
 arch/x86/lib/Makefile             |   9 ++-
 arch/x86/lib/spl.c                |  44 ++++++++++-
 arch/x86/lib/tpl.c                | 118 ++++++++++++++++++++++++++++++
 include/configs/chromebook_link.h |   3 -
 include/configs/qemu-x86.h        |   5 --
 6 files changed, 183 insertions(+), 13 deletions(-)
 create mode 100644 arch/x86/lib/tpl.c

diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h
index 8cf59d14e7c..27432b28979 100644
--- a/arch/x86/include/asm/spl.h
+++ b/arch/x86/include/asm/spl.h
@@ -2,6 +2,19 @@
 /*
  * Copyright (C) 2017 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
- *
- * This file is required for SPL to build, but is empty.
  */
+
+#ifndef __asm_spl_h
+#define __asm_spl_h
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
+enum {
+	BOOT_DEVICE_SPI		= 10,
+	BOOT_DEVICE_BOARD,
+	BOOT_DEVICE_CROS_VBOOT,
+};
+
+void jump_to_spl(ulong entry);
+
+#endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 56fd680033b..436252dd831 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -43,7 +43,14 @@ ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_ZBOOT)	+= zimage.o
 endif
 obj-$(CONFIG_HAVE_FSP) += fsp/
-obj-$(CONFIG_SPL_BUILD) += spl.o
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_TPL_BUILD
+obj-y += tpl.o
+else
+obj-y += spl.o
+endif
+endif
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += div64.o
 
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 7d290740bfa..5d5d1a9ca74 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -5,8 +5,10 @@
 
 #include <common.h>
 #include <debug_uart.h>
+#include <malloc.h>
 #include <spl.h>
 #include <asm/cpu.h>
+#include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm-generic/sections.h>
@@ -20,6 +22,7 @@ __weak int arch_cpu_init_dm(void)
 
 static int x86_spl_init(void)
 {
+#ifndef CONFIG_TPL
 	/*
 	 * TODO(sjg at chromium.org): We use this area of RAM for the stack
 	 * and global_data in SPL. Once U-Boot starts up and releocates it
@@ -27,6 +30,7 @@ static int x86_spl_init(void)
 	 * place it immediately below CONFIG_SYS_TEXT_BASE.
 	 */
 	char *ptr = (char *)0x110000;
+#endif
 	int ret;
 
 	debug("%s starting\n", __func__);
@@ -35,27 +39,44 @@ static int x86_spl_init(void)
 		debug("%s: spl_init() failed\n", __func__);
 		return ret;
 	}
+#ifdef CONFIG_TPL
+	/* Do a mini-init if TPL has already done the full init */
+	ret = x86_cpu_reinit_f();
+#else
 	ret = arch_cpu_init();
+#endif
 	if (ret) {
 		debug("%s: arch_cpu_init() failed\n", __func__);
 		return ret;
 	}
+#ifndef CONFIG_TPL
 	ret = arch_cpu_init_dm();
 	if (ret) {
 		debug("%s: arch_cpu_init_dm() failed\n", __func__);
 		return ret;
 	}
+#endif
 	preloader_console_init();
+#ifndef CONFIG_TPL
 	ret = print_cpuinfo();
 	if (ret) {
 		debug("%s: print_cpuinfo() failed\n", __func__);
 		return ret;
 	}
+#endif
 	ret = dram_init();
 	if (ret) {
 		debug("%s: dram_init() failed\n", __func__);
 		return ret;
 	}
+	if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
+		ret = mrccache_spl_save();
+		if (ret)
+			debug("%s: Failed to write to mrccache (err=%d)\n",
+			      __func__, ret);
+	}
+
+#ifndef CONFIG_TPL
 	memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
 
 	/* TODO(sjg at chromium.org): Consider calling cpu_init_r() here */
@@ -80,9 +101,11 @@ static int x86_spl_init(void)
 			       (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
 			       CONFIG_XIP_ROM_SIZE);
 	if (ret) {
-		debug("%s: SPI cache setup failed\n", __func__);
+		debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
 		return ret;
 	}
+	mtrr_commit(true);
+#endif
 
 	return 0;
 }
@@ -96,9 +119,17 @@ void board_init_f(ulong flags)
 		debug("Error %d\n", ret);
 		hang();
 	}
-
+#ifdef CONFIG_TPL
+	gd->bd = malloc(sizeof(*gd->bd));
+	if (!gd->bd) {
+		printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
+		hang();
+	}
+	board_init_r(gd, 0);
+#else
 	/* Uninit CAR and jump to board_init_f_r() */
 	board_init_f_r_trampoline(gd->start_addr_sp);
+#endif
 }
 
 void board_init_f_r(void)
@@ -144,6 +175,7 @@ int spl_spi_load_image(void)
 	return -EPERM;
 }
 
+#ifdef CONFIG_X86_RUN_64BIT
 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
 	int ret;
@@ -154,3 +186,11 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	while (1)
 		;
 }
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_TPL
+	preloader_console_init();
+#endif
+}
diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c
new file mode 100644
index 00000000000..492a2d65216
--- /dev/null
+++ b/arch/x86/lib/tpl.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 Google, Inc
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+#include <asm/cpu.h>
+#include <asm/mtrr.h>
+#include <asm/processor.h>
+#include <asm-generic/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int arch_cpu_init_dm(void)
+{
+	return 0;
+}
+
+static int x86_tpl_init(void)
+{
+	int ret;
+
+	debug("%s starting\n", __func__);
+	ret = spl_init();
+	if (ret) {
+		debug("%s: spl_init() failed\n", __func__);
+		return ret;
+	}
+	ret = arch_cpu_init();
+	if (ret) {
+		debug("%s: arch_cpu_init() failed\n", __func__);
+		return ret;
+	}
+	ret = arch_cpu_init_dm();
+	if (ret) {
+		debug("%s: arch_cpu_init_dm() failed\n", __func__);
+		return ret;
+	}
+	preloader_console_init();
+	ret = print_cpuinfo();
+	if (ret) {
+		debug("%s: print_cpuinfo() failed\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+void board_init_f(ulong flags)
+{
+	int ret;
+
+	ret = x86_tpl_init();
+	if (ret) {
+		debug("Error %d\n", ret);
+		hang();
+	}
+
+	/* Uninit CAR and jump to board_init_f_r() */
+	board_init_r(gd, 0);
+}
+
+void board_init_f_r(void)
+{
+	/* Not used since we never call board_init_f_r_trampoline() */
+	while (1);
+}
+
+u32 spl_boot_device(void)
+{
+	return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
+		BOOT_DEVICE_BOARD;
+}
+
+int spl_start_uboot(void)
+{
+	return 0;
+}
+
+void spl_board_announce_boot_device(void)
+{
+	printf("SPI flash");
+}
+
+static int spl_board_load_image(struct spl_image_info *spl_image,
+				struct spl_boot_device *bootdev)
+{
+	spl_image->size = CONFIG_SYS_MONITOR_LEN;  /* We don't know SPL size */
+	spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
+	spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
+	spl_image->os = IH_OS_U_BOOT;
+	spl_image->name = "U-Boot";
+
+	debug("Loading to %lx\n", spl_image->load_addr);
+
+	return 0;
+}
+SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+
+int spl_spi_load_image(void)
+{
+	return -EPERM;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	printf("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
+	jump_to_spl(spl_image->entry_point);
+	while (1)
+		;
+}
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index ca592768925..f26e463fe53 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -18,9 +18,6 @@
 #define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_ENV_OFFSET		0x003f8000
 
-#define BOOT_DEVICE_SPI			10
-
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
-#define BOOT_DEVICE_BOARD		11
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 4cd1cac3bd2..64e7a60b8a0 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -33,11 +33,6 @@
 #define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
 #define CONFIG_ATAPI
 
-/* SPI is not supported */
-
-#define BOOT_DEVICE_SPI			10
-
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
-#define BOOT_DEVICE_BOARD		11
 
 #endif	/* __CONFIG_H */
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 03/18] x86: sysreset: Separate out the EFI code

[Simon Glass]

The EFI implementation of reset sits inside the driver and is called
directly from outside the driver, breaking the normal driver-model
conventions. Worse, it passed NULL as the device pointer, hoping that
the called function won't use it, which breaks as soon as code is added
to use it.

Separate out the implementation to improve the situation enough to allow
a future patch to add new sysreset features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Add new patch to separate out the EFI code in sysreset

 drivers/sysreset/sysreset_x86.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index 009f3766027..d484ec5de49 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -12,8 +12,7 @@
 #include <asm/processor.h>
 #include <efi_loader.h>
 
-static __efi_runtime int x86_sysreset_request(struct udevice *dev,
-					      enum sysreset_t type)
+static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	int value;
 
@@ -39,11 +38,18 @@ void __efi_runtime EFIAPI efi_reset_system(
 			efi_status_t reset_status,
 			unsigned long data_size, void *reset_data)
 {
+	int value;
+
+	/*
+	 * inline this code since we are not caused in the context of a
+	 * udevice and passing NULL to x86_sysreset_request() is too horrible.
+	 */
 	if (reset_type == EFI_RESET_COLD ||
 		 reset_type == EFI_RESET_PLATFORM_SPECIFIC)
-		x86_sysreset_request(NULL, SYSRESET_COLD);
-	else if (reset_type == EFI_RESET_WARM)
-		x86_sysreset_request(NULL, SYSRESET_WARM);
+		value = SYS_RST | RST_CPU | FULL_RST;
+	else /* assume EFI_RESET_WARM since we cannot return an error */
+		value = SYS_RST | RST_CPU;
+	outb(value, IO_PORT_RESET);
 
 	/* TODO EFI_RESET_SHUTDOWN */
 
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 04/18] x86: sysreset: Implement power-off if available

[Simon Glass]

On modern x86 devices we can power the system off using the power-
management features of the PCH. Add an implementation for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- Use acpi_s3.h header for constants (and tidy up header order)
- Fix multi-line comment format

Changes in v2:
- Add new patch to implement power-off if available

 drivers/sysreset/sysreset_x86.c | 79 ++++++++++++++++++++++++++++++++-
 1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index d484ec5de49..ca892b305e2 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -7,14 +7,75 @@
 
 #include <common.h>
 #include <dm.h>
+#include <efi_loader.h>
+#include <pch.h>
 #include <sysreset.h>
+#include <asm/acpi_s3.h>
 #include <asm/io.h>
 #include <asm/processor.h>
-#include <efi_loader.h>
+
+struct x86_sysreset_platdata {
+	struct udevice *pch;
+};
+
+/*
+ * Power down the machine by using the power management sleep control
+ * of the chipset. This will currently only work on Intel chipsets.
+ * However, adapting it to new chipsets is fairly simple. You will
+ * have to find the IO address of the power management register block
+ * in your southbridge, and look up the appropriate SLP_TYP_S5 value
+ * from your southbridge's data sheet.
+ *
+ * This function never returns.
+ */
+int pch_sysreset_power_off(struct udevice *dev)
+{
+	struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
+	struct pch_pmbase_info pm;
+	u32 reg32;
+	int ret;
+
+	if (!plat->pch)
+		return -ENOENT;
+	ret = pch_ioctl(plat->pch, PCH_REQ_PMBASE_INFO, &pm, sizeof(pm));
+	if (ret)
+		return ret;
+
+	/*
+	 * Mask interrupts or system might stay in a coma, not executing code
+	 * anymore, but not powered off either.
+	 */
+	asm("cli");
+
+	/*
+	 * Avoid any GPI waking the system from S5* or the system might stay in
+	 * a coma
+	 */
+	outl(0x00000000, pm.base + pm.gpio0_en_ofs);
+
+	/* Clear Power Button Status */
+	outw(PWRBTN_STS, pm.base + pm.pm1_sts_ofs);
+
+	/* PMBASE + 4, Bit 10-12, Sleeping Type, * set to 111 -> S5, soft_off */
+	reg32 = inl(pm.base + pm.pm1_cnt_ofs);
+
+	/* Set Sleeping Type to S5 (poweroff) */
+	reg32 &= ~(SLP_EN | SLP_TYP);
+	reg32 |= SLP_TYP_S5;
+	outl(reg32, pm.base + pm.pm1_cnt_ofs);
+
+	/* Now set the Sleep Enable bit */
+	reg32 |= SLP_EN;
+	outl(reg32, pm.base + pm.pm1_cnt_ofs);
+
+	for (;;)
+		asm("hlt");
+}
 
 static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	int value;
+	int ret;
 
 	switch (type) {
 	case SYSRESET_WARM:
@@ -23,6 +84,11 @@ static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
 	case SYSRESET_COLD:
 		value = SYS_RST | RST_CPU | FULL_RST;
 		break;
+	case SYSRESET_POWER_OFF:
+		ret = pch_sysreset_power_off(dev);
+		if (ret)
+			return ret;
+		return -EINPROGRESS;
 	default:
 		return -ENOSYS;
 	}
@@ -57,6 +123,15 @@ void __efi_runtime EFIAPI efi_reset_system(
 }
 #endif
 
+static int x86_sysreset_probe(struct udevice *dev)
+{
+	struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
+
+	/* Locate the PCH if there is one. It isn't essential */
+	uclass_first_device(UCLASS_PCH, &plat->pch);
+
+	return 0;
+}
 
 static const struct udevice_id x86_sysreset_ids[] = {
 	{ .compatible = "x86,reset" },
@@ -72,4 +147,6 @@ U_BOOT_DRIVER(x86_sysreset) = {
 	.id = UCLASS_SYSRESET,
 	.of_match = x86_sysreset_ids,
 	.ops = &x86_sysreset_ops,
+	.probe = x86_sysreset_probe,
+	.platdata_auto_alloc_size	= sizeof(struct x86_sysreset_platdata),
 };
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 05/18] x86: sysreset: Implement the get_last() method

[Simon Glass]

Add a default implementation of this method which always indicates that
the last reset was a power-on reset. This is the most likely type of reset
and without a PCH-specific driver we cannot determine any other type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 drivers/sysreset/sysreset_x86.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index ca892b305e2..072f7948efa 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -98,6 +98,11 @@ static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
 	return -EINPROGRESS;
 }
 
+static int x86_sysreset_get_last(struct udevice *dev)
+{
+	return SYSRESET_POWER;
+}
+
 #ifdef CONFIG_EFI_LOADER
 void __efi_runtime EFIAPI efi_reset_system(
 			enum efi_reset_type reset_type,
@@ -140,6 +145,7 @@ static const struct udevice_id x86_sysreset_ids[] = {
 
 static struct sysreset_ops x86_sysreset_ops = {
 	.request = x86_sysreset_request,
+	.get_last = x86_sysreset_get_last,
 };
 
 U_BOOT_DRIVER(x86_sysreset) = {
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 06/18] x86: Add documention on the samus flashmap

[Simon Glass]

There are quite a few variables which control where things appear in the
final ROM image. Add a flashmap in the documentation to make this easier
to figure out.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 doc/README.x86 | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/doc/README.x86 b/doc/README.x86
index fa49cb8b8a2..d5224b75367 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -185,6 +185,20 @@ If you are using em100, then this command will flash write -Boot:
 
    em100 -s -d filename.rom -c W25Q64CV -r
 
+Flash map for samus / broadwell:
+
+   fffff800	SYS_X86_START16
+   ffff0000	RESET_SEG_START
+   fffd8000	TPL_TEXT_BASE
+   fffa0000	X86_MRC_ADDR
+   fff90000	VGA_BIOS_ADDR
+   ffed0000	SYS_TEXT_BASE
+   ffea0000	X86_REFCODE_ADDR
+   ffe70000	SPL_TEXT_BASE
+   ffa00000	<spare>
+   ff801000	intel-me (address set by descriptor.bin)
+   ff800000	intel-descriptor
+
 ---
 
 Intel Crown Bay specific instructions for bare mode:
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 07/18] x86: samus: Update device tree for SPL

[Simon Glass]

Add tags to allow required nodes to be present in SPL / TPL. Also enable
the sysreset driver.

Signed-off-by: Simon Glass <sjg@chromium.org>

---

Changes in v3:
- Remove unneeded pch-reset node

Changes in v2: None

 arch/x86/dts/chromebook_samus.dts | 33 +++++++++++++++++++++++++++----
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 35211ed81b1..33df0e1f718 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -17,6 +17,7 @@
 		spi0 = &spi;
 		usb0 = &usb_0;
 		usb1 = &usb_1;
+		cros-ec0 = &cros_ec;
 	};
 
 	config {
@@ -73,6 +74,7 @@
 
 		/* Put this first: it is the default */
 		gpio_unused: gpio-unused {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -80,6 +82,7 @@
 		};
 
 		gpio_acpi_sci: acpi-sci {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			invert;
@@ -87,6 +90,7 @@
 		};
 
 		gpio_acpi_smi: acpi-smi {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			invert;
@@ -94,12 +98,14 @@
 		};
 
 		gpio_input: gpio-input {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
 		};
 
 		gpio_input_invert: gpio-input-invert {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -107,9 +113,11 @@
 		};
 
 		gpio_native: gpio-native {
+			u-boot,dm-pre-reloc;
 		};
 
 		gpio_out_high: gpio-out-high {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_OUTPUT>;
 			output-value = <1>;
@@ -118,6 +126,7 @@
 		};
 
 		gpio_out_low: gpio-out-low {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_OUTPUT>;
 			output-value = <0>;
@@ -126,6 +135,7 @@
 		};
 
 		gpio_pirq: gpio-pirq {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -133,6 +143,7 @@
 		};
 
 		soc_gpio at 0 {
+			u-boot,dm-pre-reloc;
 			config =
 				<0 &gpio_unused 0>,	/* unused */
 				<1 &gpio_unused 0>,	/* unused */
@@ -250,8 +261,10 @@
 			spd {
 				#address-cells = <1>;
 				#size-cells = <0>;
+				u-boot,dm-pre-reloc;
 				samsung_4 {
 					reg = <6>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 04 11 05 0b
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -291,6 +304,7 @@
 					 * columns 10, density 4096 mb, x32
 					 */
 					reg = <8>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 04 11 05 0b
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -326,6 +340,7 @@
 					};
 				samsung_8 {
 					reg = <10>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 04 12 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -365,6 +380,7 @@
 					 * columns 11, density 4096 mb, x16
 					 */
 					reg = <12>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 04 12 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -404,6 +420,7 @@
 					 * columns 11, density 8192 mb, x16
 					 */
 					reg = <13>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 05 1a 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -443,6 +460,7 @@
 					 * columns 11, density 8192 mb, x16
 					 */
 					reg = <15>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 05 1a 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -540,7 +558,7 @@
 			compatible = "ehci-pci";
 		};
 
-		pch at 1f,0 {
+		pch: pch at 1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,broadwell-pch";
 			u-boot,dm-pre-reloc;
@@ -559,17 +577,20 @@
 			power-enable-gpio = <&gpio_a 23 0>;
 
 			spi: spi {
+				u-boot,dm-pre-reloc;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
 				spi-flash at 0 {
+					u-boot,dm-pre-reloc;
 					#size-cells = <1>;
 					#address-cells = <1>;
 					reg = <0>;
 					compatible = "winbond,w25q64",
 							"jedec,spi-nor";
-					memory-map = <0xff800000 0x00800000>;
+					memory-map = <0 0xff800000 0 0x00800000>;
 					rw-mrc-cache {
+						u-boot,dm-pre-reloc;
 						label = "rw-mrc-cache";
 						reg = <0x003e0000 0x00010000>;
 					};
@@ -609,7 +630,8 @@
 				#size-cells = <0>;
 				u-boot,dm-pre-reloc;
 				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
-				cros-ec at 200 {
+				cros_ec: cros-ec {
+					u-boot,dm-pre-reloc;
 					compatible = "google,cros-ec-lpc";
 					reg = <0x204 1 0x200 1 0x880 0x80>;
 
@@ -630,7 +652,7 @@
 		sata at 1f,2 {
 			compatible = "intel,wildcatpoint-ahci";
 			reg = <0x0000fa00 0 0 0 0>;
-			u-boot,dm-pre-reloc;
+			u-boot,dm-pre-proper;
 			intel,sata-mode = "ahci";
 			intel,sata-port-map = <1>;
 			intel,sata-port0-gen3-tx = <0x72>;
@@ -645,12 +667,15 @@
 	};
 
 	tpm {
+		u-boot,dm-pre-reloc;
 		reg = <0xfed40000 0x5000>;
 		compatible = "infineon,slb9635lpc";
 	};
 
 	microcode {
+		u-boot,dm-pre-reloc;
 		update at 0 {
+			u-boot,dm-pre-reloc;
 #include "microcode/mc0306d4_00000018.dtsi"
 		};
 	};
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 08/18] x86: samus: Update device tree for verified boot

[Simon Glass]

Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/dts/chromebook_samus.dts | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 33df0e1f718..d6a1df63ece 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -9,6 +9,12 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#ifdef CONFIG_CHROMEOS
+#include "chromeos-x86.dtsi"
+#include "flashmap-x86-ro.dtsi"
+#include "flashmap-8mb-rw.dtsi"
+#endif
+
 / {
 	model = "Google Samus";
 	compatible = "google,samus", "intel,broadwell";
@@ -581,7 +587,7 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
-				spi-flash at 0 {
+				fwstore_spi: spi-flash at 0 {
 					u-boot,dm-pre-reloc;
 					#size-cells = <1>;
 					#address-cells = <1>;
@@ -670,6 +676,10 @@
 		u-boot,dm-pre-reloc;
 		reg = <0xfed40000 0x5000>;
 		compatible = "infineon,slb9635lpc";
+		secdata {
+			u-boot,dm-pre-reloc;
+			compatible = "google,tpm-secdata";
+		};
 	};
 
 	microcode {
@@ -693,3 +703,13 @@
 	};
 
 };
+
+&rtc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nvdata {
+		u-boot,dm-pre-reloc;
+		compatible = "google,cmos-nvdata";
+		reg = <0x26>;
+	};
+};
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 09/18] x86: Update device tree for TPL

[Simon Glass]

Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2:
- Add a comment about the hard-coded text base

 arch/x86/dts/u-boot.dtsi | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1050236330a..9cf733806a5 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -22,7 +22,21 @@
 			filename = CONFIG_INTEL_ME_FILE;
 		};
 #endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+		u-boot-tpl-with-ucode-ptr {
+			offset = <CONFIG_TPL_TEXT_BASE>;
+		};
+		u-boot-tpl-dtb {
+		};
+		u-boot-spl {
+			offset = <CONFIG_SPL_TEXT_BASE>;
+		};
+		u-boot-spl-dtb {
+		};
+		u-boot {
+			offset = <CONFIG_SYS_TEXT_BASE>;
+		};
+#elif defined(CONFIG_SPL)
 		u-boot-spl-with-ucode-ptr {
 			offset = <CONFIG_SPL_TEXT_BASE>;
 		};
@@ -31,7 +45,19 @@
 			type = "u-boot-dtb-with-ucode";
 		};
 		u-boot {
+		/*
+		 * TODO(sjg at chromium.org):
+		 * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
+		 * for boards with textbase in SDRAM we cannot do this. Just use
+		 * an assumed-valid value (1MB before the end of flash) here so
+		 * that we can actually build an image for coreboot, etc.
+		 * We need a better solution, perhaps a separate Kconfig.
+		 */
+#if CONFIG_SYS_TEXT_BASE == 0x1110000
 			offset = <0xfff00000>;
+#else
+			offset = <CONFIG_SYS_TEXT_BASE>;
+#endif
 		};
 #else
 		u-boot-with-ucode-ptr {
@@ -77,7 +103,11 @@
 			offset = <CONFIG_X86_REFCODE_ADDR>;
 		};
 #endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+		x86-start16-tpl {
+			offset = <CONFIG_SYS_X86_START16>;
+		};
+#elif defined(CONFIG_SPL)
 		x86-start16-spl {
 			offset = <CONFIG_SYS_X86_START16>;
 		};
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 10/18] x86: Update device tree for Chromium OS verified boot

[Simon Glass]

The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/dts/u-boot.dtsi | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 9cf733806a5..6b176339aed 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -6,9 +6,23 @@
 
 #include <config.h>
 
-#ifdef CONFIG_ROM_SIZE
+#ifdef CONFIG_CHROMEOS
 / {
 	binman {
+		multiple-images;
+		rom: rom {
+		};
+	};
+};
+#else
+/ {
+	rom: binman {
+	};
+};
+#endif
+
+#ifdef CONFIG_ROM_SIZE
+&rom {
 		filename = "u-boot.rom";
 		end-at-4gb;
 		sort-by-offset;
@@ -116,6 +130,5 @@
 			offset = <CONFIG_SYS_X86_START16>;
 		};
 #endif
-	};
 };
 #endif
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 11/18] x86: Fix device-tree indentation

[Simon Glass]

With the use of a phandle we can outdent the device tree nodes a little.
Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/dts/u-boot.dtsi | 147 +++++++++++++++++++--------------------
 1 file changed, 73 insertions(+), 74 deletions(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 6b176339aed..daeb168b65f 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -23,42 +23,41 @@
 
 #ifdef CONFIG_ROM_SIZE
 &rom {
-		filename = "u-boot.rom";
-		end-at-4gb;
-		sort-by-offset;
-		pad-byte = <0xff>;
-		size = <CONFIG_ROM_SIZE>;
+	filename = "u-boot.rom";
+	end-at-4gb;
+	sort-by-offset;
+	pad-byte = <0xff>;
+	size = <CONFIG_ROM_SIZE>;
 #ifdef CONFIG_HAVE_INTEL_ME
-		intel-descriptor {
-			filename = CONFIG_FLASH_DESCRIPTOR_FILE;
-		};
-		intel-me {
-			filename = CONFIG_INTEL_ME_FILE;
-		};
+	intel-descriptor {
+		filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+	};
+	intel-me {
+		filename = CONFIG_INTEL_ME_FILE;
+	};
 #endif
 #ifdef CONFIG_TPL
-		u-boot-tpl-with-ucode-ptr {
-			offset = <CONFIG_TPL_TEXT_BASE>;
-		};
-		u-boot-tpl-dtb {
-		};
-		u-boot-spl {
-			offset = <CONFIG_SPL_TEXT_BASE>;
-		};
-		u-boot-spl-dtb {
-		};
-		u-boot {
-			offset = <CONFIG_SYS_TEXT_BASE>;
-		};
+	u-boot-tpl-with-ucode-ptr {
+		offset = <CONFIG_TPL_TEXT_BASE>;
+	};
+	u-boot-tpl-dtb {
+	};
+	u-boot-spl {
+		offset = <CONFIG_SPL_TEXT_BASE>;
+	};
+	u-boot-spl-dtb {
+	};
+	u-boot {
+		offset = <CONFIG_SYS_TEXT_BASE>;
+	};
 #elif defined(CONFIG_SPL)
-		u-boot-spl-with-ucode-ptr {
-			offset = <CONFIG_SPL_TEXT_BASE>;
-		};
-
-		u-boot-dtb-with-ucode2 {
-			type = "u-boot-dtb-with-ucode";
-		};
-		u-boot {
+	u-boot-spl-with-ucode-ptr {
+		offset = <CONFIG_SPL_TEXT_BASE>;
+	};
+	u-boot-dtb-with-ucode2 {
+		type = "u-boot-dtb-with-ucode";
+	};
+	u-boot {
 		/*
 		 * TODO(sjg at chromium.org):
 		 * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
@@ -68,67 +67,67 @@
 		 * We need a better solution, perhaps a separate Kconfig.
 		 */
 #if CONFIG_SYS_TEXT_BASE == 0x1110000
-			offset = <0xfff00000>;
+		offset = <0xfff00000>;
 #else
-			offset = <CONFIG_SYS_TEXT_BASE>;
+		offset = <CONFIG_SYS_TEXT_BASE>;
 #endif
-		};
+	};
 #else
-		u-boot-with-ucode-ptr {
-			offset = <CONFIG_SYS_TEXT_BASE>;
-		};
+	u-boot-with-ucode-ptr {
+		offset = <CONFIG_SYS_TEXT_BASE>;
+	};
 #endif
-		u-boot-dtb-with-ucode {
-		};
-		u-boot-ucode {
-			align = <16>;
-		};
+	u-boot-dtb-with-ucode {
+	};
+	u-boot-ucode {
+		align = <16>;
+	};
 #ifdef CONFIG_HAVE_MRC
-		intel-mrc {
-			offset = <CONFIG_X86_MRC_ADDR>;
-		};
+	intel-mrc {
+		offset = <CONFIG_X86_MRC_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_FSP
-		intel-fsp {
-			filename = CONFIG_FSP_FILE;
-			offset = <CONFIG_FSP_ADDR>;
-		};
+	intel-fsp {
+		filename = CONFIG_FSP_FILE;
+		offset = <CONFIG_FSP_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_CMC
-		intel-cmc {
-			filename = CONFIG_CMC_FILE;
-			offset = <CONFIG_CMC_ADDR>;
-		};
+	intel-cmc {
+		filename = CONFIG_CMC_FILE;
+		offset = <CONFIG_CMC_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_VGA_BIOS
-		intel-vga {
-			filename = CONFIG_VGA_BIOS_FILE;
-			offset = <CONFIG_VGA_BIOS_ADDR>;
-		};
+	intel-vga {
+		filename = CONFIG_VGA_BIOS_FILE;
+		offset = <CONFIG_VGA_BIOS_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_VBT
-		intel-vbt {
-			filename = CONFIG_VBT_FILE;
-			offset = <CONFIG_VBT_ADDR>;
-		};
+	intel-vbt {
+		filename = CONFIG_VBT_FILE;
+		offset = <CONFIG_VBT_ADDR>;
+	};
 #endif
 #ifdef CONFIG_HAVE_REFCODE
-		intel-refcode {
-			offset = <CONFIG_X86_REFCODE_ADDR>;
-		};
+	intel-refcode {
+		offset = <CONFIG_X86_REFCODE_ADDR>;
+	};
 #endif
 #ifdef CONFIG_TPL
-		x86-start16-tpl {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16-tpl {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #elif defined(CONFIG_SPL)
-		x86-start16-spl {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16-spl {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #else
-		x86-start16 {
-			offset = <CONFIG_SYS_X86_START16>;
-		};
+	x86-start16 {
+		offset = <CONFIG_SYS_X86_START16>;
+	};
 #endif
 };
 #endif
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 12/18] x86: samus: Increase the pre-reloc memory again

[Simon Glass]

This is again too small, so increase it slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 configs/chromebook_samus_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index d0749f14fc9..91d9fdf9615 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -1,6 +1,6 @@
 CONFIG_X86=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
-CONFIG_SYS_MALLOC_F_LEN=0x1c00
+CONFIG_SYS_MALLOC_F_LEN=0x1d00
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x3f8
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 13/18] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"

[Simon Glass]

This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d.

Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.

The offending line is in UCLASS_DRIVER(pci):

	.per_device_auto_alloc_size = sizeof(struct pci_controller),

This means that all PCI devices have the controller struct associated
with them. The solution is to move the regions[] member out of the array,
makes its size dynamic, or split UCLASS_PCI into controllers and
non-controllers, as the comment suggests.

For now, revert the commit to get things running again.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 include/pci.h | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/include/pci.h b/include/pci.h
index 066238a9c3c..508f7bca81c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -546,11 +546,7 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
 				      struct pci_config_table *);
 
-#ifdef CONFIG_NR_DRAM_BANKS
-#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
-#else
-#define MAX_PCI_REGIONS 7
-#endif
+#define MAX_PCI_REGIONS		7
 
 #define INDIRECT_TYPE_NO_PCIE_LINK	1
 
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 14/18] x86: Enable the RTC on all boards

[Simon Glass]

With the move to Kconfig this option should be set in Kconfig, not in the
config header file. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Drop unnecessary change to chromebook_link_defconfig

Changes in v2:
- Add new patch to enable the RTC in Kconfig

 arch/Kconfig                 | 1 +
 include/configs/x86-common.h | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index a1d1ac301d6..2a93b72dbc4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -165,6 +165,7 @@ config X86
 	imply USB_ETHER_SMSC95XX
 	imply USB_HOST_ETHER
 	imply PCH
+	imply RTC_MC146818
 
 	# Thing to enable for when SPL/TPL are enabled: SPL
 	imply SPL_DM
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 4180b25f977..7fcf76a6bf2 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -36,7 +36,6 @@
 /*-----------------------------------------------------------------------
  * Real Time Clock Configuration
  */
-#define CONFIG_RTC_MC146818
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
 #define CONFIG_SYS_ISA_IO      CONFIG_SYS_ISA_IO_BASE_ADDRESS
 
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 15/18] x86: Update the memory map a little

[Simon Glass]

The memory map currently omits the environment and the MRC region. Add
these in for completeness.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 doc/README.x86 | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/doc/README.x86 b/doc/README.x86
index d5224b75367..8e0a3f36edf 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -195,6 +195,8 @@ Flash map for samus / broadwell:
    ffed0000	SYS_TEXT_BASE
    ffea0000	X86_REFCODE_ADDR
    ffe70000	SPL_TEXT_BASE
+   ffbf8000	CONFIG_ENV_OFFSET (environemnt offset)
+   ffbe0000	rw-mrc-cache (Memory-reference-code cache)
    ffa00000	<spare>
    ff801000	intel-me (address set by descriptor.bin)
    ff800000	intel-descriptor
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 16/18] x86: broadwell: Update PCH to work in TPL

[Simon Glass]

The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Add a new patch to update PCH to work in TPL

 arch/x86/cpu/broadwell/pch.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
index e61efa7b16c..a48945adf11 100644
--- a/arch/x86/cpu/broadwell/pch.c
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -599,10 +599,16 @@ static int broadwell_pch_init(struct udevice *dev)
 
 static int broadwell_pch_probe(struct udevice *dev)
 {
-	if (!(gd->flags & GD_FLG_RELOC))
-		return broadwell_pch_early_init(dev);
-	else
+	if (CONFIG_IS_ENABLED(X86_32BIT_INIT)) {
+		if (!(gd->flags & GD_FLG_RELOC))
+			return broadwell_pch_early_init(dev);
+		else
+			return broadwell_pch_init(dev);
+	} else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
 		return broadwell_pch_init(dev);
+	} else {
+		return 0;
+	}
 }
 
 static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 17/18] x86: Add a way to jump from TPL to SPL

[Simon Glass]

When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Add a new patch allowing jumping from TPL to SPL

 arch/x86/cpu/start.S | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 30fa7def464..4a82add76b7 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -190,6 +190,19 @@ board_init_f_r_trampoline:
 	/* Re-enter U-Boot by calling board_init_f_r() */
 	call	board_init_f_r
 
+#ifdef CONFIG_TPL
+.globl jump_to_spl
+.type jump_to_spl, @function
+jump_to_spl:
+	/* Reset stack to the top of CAR space */
+	movl	$(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
+#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
+	subl	$CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
+#endif
+
+	jmp	*%eax
+#endif
+
 die:
 	hlt
 	jmp	die
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 18/18] x86: samus: Add a target to boot through TPL

[Simon Glass]

Add a version of samus which supports booting from TPL to SPL and then
to U-Boot. This allows TPL to select from an A or B SPL to support
verified boot with field upgrade.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Sort defconfig and adjust it to build after rebase on maste

 board/google/Kconfig                      |  8 +++
 board/google/chromebook_samus/Kconfig     | 14 +++-
 board/google/chromebook_samus/MAINTAINERS |  7 ++
 configs/chromebook_samus_tpl_defconfig    | 82 +++++++++++++++++++++++
 include/configs/chromebook_samus.h        |  2 +
 5 files changed, 111 insertions(+), 2 deletions(-)
 create mode 100644 configs/chromebook_samus_tpl_defconfig

diff --git a/board/google/Kconfig b/board/google/Kconfig
index d98a5e818fc..679a0f10239 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -52,6 +52,14 @@ config TARGET_CHROMEBOOK_SAMUS
 	  Chrome OS EC connected on LPC, and it provides a 2560x1700 high
 	  resolution touch-enabled LCD display.
 
+config TARGET_CHROMEBOOK_SAMUS_TPL
+	bool "Chromebook samus booting from TPL"
+	help
+	  This is a version of Samus which boots into TPL, then to SPL and
+	  U-Boot proper. This is useful where verified boot must select
+	  between different A/B versions of SPL/U-Boot, to allow upgrading of
+	  almost all U-Boot code in the field.
+
 endchoice
 
 source "board/google/chromebook_link/Kconfig"
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
index afbfe53deb4..90c23cba1be 100644
--- a/board/google/chromebook_samus/Kconfig
+++ b/board/google/chromebook_samus/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_CHROMEBOOK_SAMUS
+if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL
 
 config SYS_BOARD
 	default "chromebook_samus"
@@ -10,7 +10,8 @@ config SYS_SOC
 	default "broadwell"
 
 config SYS_CONFIG_NAME
-	default "chromebook_samus"
+	default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS
+	default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL
 
 config SYS_TEXT_BASE
 	default 0xffe00000
@@ -39,3 +40,12 @@ config SYS_CAR_SIZE
 	default 0x40000
 
 endif
+
+if TARGET_CHROMEBOOK_SAMUS_TPL
+
+config BOARD_SPECIFIC_OPTIONS_TPL # dummy
+	def_bool y
+	select SPL
+	select TPL
+
+endif
diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS
index 5500e46b408..ca4b16500af 100644
--- a/board/google/chromebook_samus/MAINTAINERS
+++ b/board/google/chromebook_samus/MAINTAINERS
@@ -4,3 +4,10 @@ S:	Maintained
 F:	board/google/chromebook_samus/
 F:	include/configs/chromebook_samus.h
 F:	configs/chromebook_samus_defconfig
+
+CHROMEBOOK SAMUS TPL BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_samus/
+F:	include/configs/chromebook_samus.h
+F:	configs/chromebook_samus_tpl_defconfig
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
new file mode 100644
index 00000000000..6ebfaa83a19
--- /dev/null
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -0,0 +1,82 @@
+CONFIG_X86=y
+CONFIG_SYS_TEXT_BASE=0xffed0000
+CONFIG_SYS_MALLOC_F_LEN=0x1a00
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_TARGET_CHROMEBOOK_SAMUS_TPL=y
+CONFIG_DEBUG_UART=y
+CONFIG_HAVE_MRC=y
+CONFIG_HAVE_REFCODE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_MISC_INIT_R=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_SIZE=0x1000
+CONFIG_BLOBLIST_ADDR=0xff7c0000
+CONFIG_HANDOFF=y
+CONFIG_SPL_TEXT_BASE=0xffe70000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_PCI=y
+CONFIG_SPL_PCH_SUPPORT=y
+CONFIG_TPL_PCI=y
+CONFIG_TPL_PCH_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_SPL_MAC_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
+# CONFIG_NET is not set
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_TPL_MISC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SYS_NS16550=y
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_SOUND_RT5677=y
+CONFIG_SPI=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_TPM=y
diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h
index ccb2fe8caad..2f7dd69fb82 100644
--- a/include/configs/chromebook_samus.h
+++ b/include/configs/chromebook_samus.h
@@ -23,4 +23,6 @@
 #define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_ENV_OFFSET		0x003f8000
 
+#define CONFIG_TPL_TEXT_BASE		0xfffd8000
+
 #endif	/* __CONFIG_H */
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v3 01/18] cros_ec: Use a hyphen in the uclass name

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> Device-tree rules require that aliases use a hyphen rather than a
> underscore. Update the uclass name to fit with this.
>
> This allows device-tree aliases to be used to refer to cros-ec devices,
> for example:
>
>         aliases {
>             cros-ec0 = &ec;
>             cros-ec1 = &pd;
>         };
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Update the commit message to explain the implications on aliases
>
>  drivers/misc/cros_ec.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 07/18] x86: samus: Update device tree for SPL

[Bin Meng]

Hi Simon,

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add tags to allow required nodes to be present in SPL / TPL. Also enable
> the sysreset driver.

I don't see the sysreset dtsi file is included. Maybe we should remove
this from the commit message.

>
> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v3:
> - Remove unneeded pch-reset node
>
> Changes in v2: None
>
>  arch/x86/dts/chromebook_samus.dts | 33 +++++++++++++++++++++++++++----
>  1 file changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
> index 35211ed81b1..33df0e1f718 100644
> --- a/arch/x86/dts/chromebook_samus.dts
> +++ b/arch/x86/dts/chromebook_samus.dts
> @@ -17,6 +17,7 @@
>                 spi0 = &spi;
>                 usb0 = &usb_0;
>                 usb1 = &usb_1;
> +               cros-ec0 = &cros_ec;
>         };
>
>         config {
> @@ -73,6 +74,7 @@
>
>                 /* Put this first: it is the default */
>                 gpio_unused: gpio-unused {
> +                       u-boot,dm-pre-reloc;
>                         mode-gpio;
>                         direction = <PIN_INPUT>;
>                         owner = <OWNER_GPIO>;
> @@ -80,6 +82,7 @@
>                 };
>
>                 gpio_acpi_sci: acpi-sci {
> +                       u-boot,dm-pre-reloc;
>                         mode-gpio;
>                         direction = <PIN_INPUT>;
>                         invert;
> @@ -87,6 +90,7 @@
>                 };
>
>                 gpio_acpi_smi: acpi-smi {
> +                       u-boot,dm-pre-reloc;
>                         mode-gpio;
>                         direction = <PIN_INPUT>;
>                         invert;
> @@ -94,12 +98,14 @@
>                 };
>
>                 gpio_input: gpio-input {
> +                       u-boot,dm-pre-reloc;
>                         mode-gpio;
>                         direction = <PIN_INPUT>;
>                         owner = <OWNER_GPIO>;
>                 };
>
>                 gpio_input_invert: gpio-input-invert {
> +                       u-boot,dm-pre-reloc;
>                         mode-gpio;
>                         direction = <PIN_INPUT>;
>                         owner = <OWNER_GPIO>;
> @@ -107,9 +113,11 @@
>                 };
>
>                 gpio_native: gpio-native {
> +                       u-boot,dm-pre-reloc;
>                 };
>
>                 gpio_out_high: gpio-out-high {
> +                       u-boot,dm-pre-reloc;
>                         mode-gpio;
>                         direction = <PIN_OUTPUT>;
>                         output-value = <1>;
> @@ -118,6 +126,7 @@
>                 };
>
>                 gpio_out_low: gpio-out-low {
> +                       u-boot,dm-pre-reloc;
>                         mode-gpio;
>                         direction = <PIN_OUTPUT>;
>                         output-value = <0>;
> @@ -126,6 +135,7 @@
>                 };
>
>                 gpio_pirq: gpio-pirq {
> +                       u-boot,dm-pre-reloc;
>                         mode-gpio;
>                         direction = <PIN_INPUT>;
>                         owner = <OWNER_GPIO>;
> @@ -133,6 +143,7 @@
>                 };
>
>                 soc_gpio at 0 {
> +                       u-boot,dm-pre-reloc;
>                         config =
>                                 <0 &gpio_unused 0>,     /* unused */
>                                 <1 &gpio_unused 0>,     /* unused */
> @@ -250,8 +261,10 @@
>                         spd {
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> +                               u-boot,dm-pre-reloc;
>                                 samsung_4 {
>                                         reg = <6>;
> +                                       u-boot,dm-pre-reloc;
>                                         data = [91 20 f1 03 04 11 05 0b
>                                                 03 11 01 08 0a 00 50 01
>                                                 78 78 90 50 90 11 50 e0
> @@ -291,6 +304,7 @@
>                                          * columns 10, density 4096 mb, x32
>                                          */
>                                         reg = <8>;
> +                                       u-boot,dm-pre-reloc;
>                                         data = [91 20 f1 03 04 11 05 0b
>                                                 03 11 01 08 0a 00 50 01
>                                                 78 78 90 50 90 11 50 e0
> @@ -326,6 +340,7 @@
>                                         };
>                                 samsung_8 {
>                                         reg = <10>;
> +                                       u-boot,dm-pre-reloc;
>                                         data = [91 20 f1 03 04 12 05 0a
>                                                 03 11 01 08 0a 00 50 01
>                                                 78 78 90 50 90 11 50 e0
> @@ -365,6 +380,7 @@
>                                          * columns 11, density 4096 mb, x16
>                                          */
>                                         reg = <12>;
> +                                       u-boot,dm-pre-reloc;
>                                         data = [91 20 f1 03 04 12 05 0a
>                                                 03 11 01 08 0a 00 50 01
>                                                 78 78 90 50 90 11 50 e0
> @@ -404,6 +420,7 @@
>                                          * columns 11, density 8192 mb, x16
>                                          */
>                                         reg = <13>;
> +                                       u-boot,dm-pre-reloc;
>                                         data = [91 20 f1 03 05 1a 05 0a
>                                                 03 11 01 08 0a 00 50 01
>                                                 78 78 90 50 90 11 50 e0
> @@ -443,6 +460,7 @@
>                                          * columns 11, density 8192 mb, x16
>                                          */
>                                         reg = <15>;
> +                                       u-boot,dm-pre-reloc;
>                                         data = [91 20 f1 03 05 1a 05 0a
>                                                 03 11 01 08 0a 00 50 01
>                                                 78 78 90 50 90 11 50 e0
> @@ -540,7 +558,7 @@
>                         compatible = "ehci-pci";
>                 };
>
> -               pch at 1f,0 {
> +               pch: pch at 1f,0 {
>                         reg = <0x0000f800 0 0 0 0>;
>                         compatible = "intel,broadwell-pch";
>                         u-boot,dm-pre-reloc;
> @@ -559,17 +577,20 @@
>                         power-enable-gpio = <&gpio_a 23 0>;
>
>                         spi: spi {
> +                               u-boot,dm-pre-reloc;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
>                                 compatible = "intel,ich9-spi";
>                                 spi-flash at 0 {
> +                                       u-boot,dm-pre-reloc;
>                                         #size-cells = <1>;
>                                         #address-cells = <1>;
>                                         reg = <0>;
>                                         compatible = "winbond,w25q64",
>                                                         "jedec,spi-nor";
> -                                       memory-map = <0xff800000 0x00800000>;
> +                                       memory-map = <0 0xff800000 0 0x00800000>;

Looks this change is irrelevant to the "u-boot,dm-pre-reloc" tag
changes. Is this the fix to the broken spi-nor support?

>                                         rw-mrc-cache {
> +                                               u-boot,dm-pre-reloc;
>                                                 label = "rw-mrc-cache";
>                                                 reg = <0x003e0000 0x00010000>;
>                                         };
> @@ -609,7 +630,8 @@
>                                 #size-cells = <0>;
>                                 u-boot,dm-pre-reloc;
>                                 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
> -                               cros-ec at 200 {
> +                               cros_ec: cros-ec {
> +                                       u-boot,dm-pre-reloc;
>                                         compatible = "google,cros-ec-lpc";
>                                         reg = <0x204 1 0x200 1 0x880 0x80>;
>
> @@ -630,7 +652,7 @@
>                 sata at 1f,2 {
>                         compatible = "intel,wildcatpoint-ahci";
>                         reg = <0x0000fa00 0 0 0 0>;
> -                       u-boot,dm-pre-reloc;
> +                       u-boot,dm-pre-proper;
>                         intel,sata-mode = "ahci";
>                         intel,sata-port-map = <1>;
>                         intel,sata-port0-gen3-tx = <0x72>;
> @@ -645,12 +667,15 @@
>         };
>
>         tpm {
> +               u-boot,dm-pre-reloc;
>                 reg = <0xfed40000 0x5000>;
>                 compatible = "infineon,slb9635lpc";
>         };
>
>         microcode {
> +               u-boot,dm-pre-reloc;
>                 update at 0 {
> +                       u-boot,dm-pre-reloc;
>  #include "microcode/mc0306d4_00000018.dtsi"
>                 };
>         };
> --

Regards,
Bin

[U-Boot] [PATCH v3 09/18] x86: Update device tree for TPL

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add TPL binaries to the device x86 binman desciption. When enabled, TPL
> will start first, doing the 16-bit init, then jump to SPL and finally
> U-Boot proper.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Add a comment about the hard-coded text base
>
>  arch/x86/dts/u-boot.dtsi | 34 ++++++++++++++++++++++++++++++++--
>  1 file changed, 32 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 14/18] x86: Enable the RTC on all boards

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> With the move to Kconfig this option should be set in Kconfig, not in the
> config header file. Move it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Drop unnecessary change to chromebook_link_defconfig
>
> Changes in v2:
> - Add new patch to enable the RTC in Kconfig
>
>  arch/Kconfig                 | 1 +
>  include/configs/x86-common.h | 1 -
>  2 files changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 01/18] cros_ec: Use a hyphen in the uclass name

[Bin Meng]

On Tue, May 7, 2019 at 5:10 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Device-tree rules require that aliases use a hyphen rather than a
> > underscore. Update the uclass name to fit with this.
> >
> > This allows device-tree aliases to be used to refer to cros-ec devices,
> > for example:
> >
> >         aliases {
> >             cros-ec0 = &ec;
> >             cros-ec1 = &pd;
> >         };
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v3: None
> > Changes in v2:
> > - Update the commit message to explain the implications on aliases
> >
> >  drivers/misc/cros_ec.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 02/18] x86: Add a simple TPL implementation

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add the required CPU code so that TPL builds correctly. Also update the
> SPL code to deal with being booted from TPL.
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Rebase to x86/master
>
> Changes in v2: None
>
>  arch/x86/include/asm/spl.h        |  17 ++++-
>  arch/x86/lib/Makefile             |   9 ++-
>  arch/x86/lib/spl.c                |  44 ++++++++++-
>  arch/x86/lib/tpl.c                | 118 ++++++++++++++++++++++++++++++
>  include/configs/chromebook_link.h |   3 -
>  include/configs/qemu-x86.h        |   5 --
>  6 files changed, 183 insertions(+), 13 deletions(-)
>  create mode 100644 arch/x86/lib/tpl.c
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 03/18] x86: sysreset: Separate out the EFI code

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> The EFI implementation of reset sits inside the driver and is called
> directly from outside the driver, breaking the normal driver-model
> conventions. Worse, it passed NULL as the device pointer, hoping that
> the called function won't use it, which breaks as soon as code is added
> to use it.
>
> Separate out the implementation to improve the situation enough to allow
> a future patch to add new sysreset features.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Add new patch to separate out the EFI code in sysreset
>
>  drivers/sysreset/sysreset_x86.c | 16 +++++++++++-----
>  1 file changed, 11 insertions(+), 5 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 04/18] x86: sysreset: Implement power-off if available

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> On modern x86 devices we can power the system off using the power-
> management features of the PCH. Add an implementation for this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - Use acpi_s3.h header for constants (and tidy up header order)
> - Fix multi-line comment format
>
> Changes in v2:
> - Add new patch to implement power-off if available
>
>  drivers/sysreset/sysreset_x86.c | 79 ++++++++++++++++++++++++++++++++-
>  1 file changed, 78 insertions(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 05/18] x86: sysreset: Implement the get_last() method

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add a default implementation of this method which always indicates that
> the last reset was a power-on reset. This is the most likely type of reset
> and without a PCH-specific driver we cannot determine any other type.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  drivers/sysreset/sysreset_x86.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 06/18] x86: Add documention on the samus flashmap

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> There are quite a few variables which control where things appear in the
> final ROM image. Add a flashmap in the documentation to make this easier
> to figure out.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  doc/README.x86 | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 09/18] x86: Update device tree for TPL

[Bin Meng]

On Tue, May 7, 2019 at 5:10 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Add TPL binaries to the device x86 binman desciption. When enabled, TPL
> > will start first, doing the 16-bit init, then jump to SPL and finally
> > U-Boot proper.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v3: None
> > Changes in v2:
> > - Add a comment about the hard-coded text base
> >
> >  arch/x86/dts/u-boot.dtsi | 34 ++++++++++++++++++++++++++++++++--
> >  1 file changed, 32 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 10/18] x86: Update device tree for Chromium OS verified boot

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> The standard image generated by U-Boot on x86 is u-boot.rom. Add a
> separate image called image.bin for verified boot. This supports
> verification in TPL of which SPL/U-Boot to start, then jumping to the
> correct one, with SPL setting up the SDRAM and U-Boot proper providing
> the user interface if needed.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/dts/u-boot.dtsi | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 11/18] x86: Fix device-tree indentation

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> With the use of a phandle we can outdent the device tree nodes a little.
> Fix this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/dts/u-boot.dtsi | 147 +++++++++++++++++++--------------------
>  1 file changed, 73 insertions(+), 74 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 12/18] x86: samus: Increase the pre-reloc memory again

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> This is again too small, so increase it slightly.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  configs/chromebook_samus_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 14/18] x86: Enable the RTC on all boards

[Bin Meng]

On Tue, May 7, 2019 at 5:10 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > With the move to Kconfig this option should be set in Kconfig, not in the
> > config header file. Move it.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v3:
> > - Drop unnecessary change to chromebook_link_defconfig
> >
> > Changes in v2:
> > - Add new patch to enable the RTC in Kconfig
> >
> >  arch/Kconfig                 | 1 +
> >  include/configs/x86-common.h | 1 -
> >  2 files changed, 1 insertion(+), 1 deletion(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 15/18] x86: Update the memory map a little

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> The memory map currently omits the environment and the MRC region. Add
> these in for completeness.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  doc/README.x86 | 2 ++
>  1 file changed, 2 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 16/18] x86: broadwell: Update PCH to work in TPL

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> The early init should only happen once. Update the probe method to
> deal with TPL, SPL and U-Boot proper.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Add a new patch to update PCH to work in TPL
>
>  arch/x86/cpu/broadwell/pch.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 17/18] x86: Add a way to jump from TPL to SPL

[Bin Meng]

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> When TPL finishes it needs to jump to SPL with the stack set up correctly.
> Add a function to handle this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Add a new patch allowing jumping from TPL to SPL
>
>  arch/x86/cpu/start.S | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 15/18] x86: Update the memory map a little

[Bin Meng]

On Tue, May 7, 2019 at 5:31 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > The memory map currently omits the environment and the MRC region. Add
> > these in for completeness.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> > Changes in v3: None
> > Changes in v2: None
> >
> >  doc/README.x86 | 2 ++
> >  1 file changed, 2 insertions(+)
> >
>
> applied to u-boot-x86, thanks!

For the record, I squashed this commit to "x86: Add documention on the
samus flashmap" since they are updating the same section in the same
series.

Regards,
Bin

[U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL

[Bin Meng]

Hi Simon,

On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present SPL is used on 64-bit platforms, to allow SPL to be built as
> a 32-bit program and U-Boot proper to be built as 64-bit.
>
> However it is useful to be able to use SPL on any x86 platform, where
> U-Boot needs to be updated in the field. Then SPL can select which U-Boot
> to run (A or B) and most of the code can be updated. Similarly, using TPL
> allows both SPL and U-Boot to be updated. This is the best approach, since
> it means that all of U-Boot proper as well as SPL (in particular SDRAM
> init) can be updated in the field. This provides for the smallest possible
> amount of read-only (non-updateable) code: just the TPL code.
>
> This series contains a number of changes to allow x86 boards to use TPL,
> SPL and U-Boot proper. As a test, it is enabled for samus with a new
> chromebook_samus_tpl board.
>
> Changes in v3:
> - Rebase to x86/master
> - Use acpi_s3.h header for constants (and tidy up header order)
> - Fix multi-line comment format
> - Remove unneeded pch-reset node
> - Drop unnecessary change to chromebook_link_defconfig
>

I applied 14 patches and left 4 below that have open questions:
http://patchwork.ozlabs.org/project/uboot/list/?series=105795

In the meantime, it looks that travis-ci complained some failures in
my last run for the applied patches. I will redo the travis-ci and let
you know the results.

Regards,
Bin

[U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL

[Bin Meng]

Hi Simon,

On Tue, May 7, 2019 at 6:07 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present SPL is used on 64-bit platforms, to allow SPL to be built as
> > a 32-bit program and U-Boot proper to be built as 64-bit.
> >
> > However it is useful to be able to use SPL on any x86 platform, where
> > U-Boot needs to be updated in the field. Then SPL can select which U-Boot
> > to run (A or B) and most of the code can be updated. Similarly, using TPL
> > allows both SPL and U-Boot to be updated. This is the best approach, since
> > it means that all of U-Boot proper as well as SPL (in particular SDRAM
> > init) can be updated in the field. This provides for the smallest possible
> > amount of read-only (non-updateable) code: just the TPL code.
> >
> > This series contains a number of changes to allow x86 boards to use TPL,
> > SPL and U-Boot proper. As a test, it is enabled for samus with a new
> > chromebook_samus_tpl board.
> >
> > Changes in v3:
> > - Rebase to x86/master
> > - Use acpi_s3.h header for constants (and tidy up header order)
> > - Fix multi-line comment format
> > - Remove unneeded pch-reset node
> > - Drop unnecessary change to chromebook_link_defconfig
> >
>
> I applied 14 patches and left 4 below that have open questions:
> http://patchwork.ozlabs.org/project/uboot/list/?series=105795
>
> In the meantime, it looks that travis-ci complained some failures in
> my last run for the applied patches. I will redo the travis-ci and let
> you know the results.

Travis-ci reported qemu-x86 is broken. I figured out the issue was due
to the sysreset-x86 driver added platdata_auto_alloc_size that
requires more memory. I will send a patch soon.

Regards,
Bin

[U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL

[Simon Glass]

Hi Bin,

On Tue, 7 May 2019 at 21:33, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Tue, May 7, 2019 at 6:07 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
> > >
> > > At present SPL is used on 64-bit platforms, to allow SPL to be built as
> > > a 32-bit program and U-Boot proper to be built as 64-bit.
> > >
> > > However it is useful to be able to use SPL on any x86 platform, where
> > > U-Boot needs to be updated in the field. Then SPL can select which U-Boot
> > > to run (A or B) and most of the code can be updated. Similarly, using TPL
> > > allows both SPL and U-Boot to be updated. This is the best approach, since
> > > it means that all of U-Boot proper as well as SPL (in particular SDRAM
> > > init) can be updated in the field. This provides for the smallest possible
> > > amount of read-only (non-updateable) code: just the TPL code.
> > >
> > > This series contains a number of changes to allow x86 boards to use TPL,
> > > SPL and U-Boot proper. As a test, it is enabled for samus with a new
> > > chromebook_samus_tpl board.
> > >
> > > Changes in v3:
> > > - Rebase to x86/master
> > > - Use acpi_s3.h header for constants (and tidy up header order)
> > > - Fix multi-line comment format
> > > - Remove unneeded pch-reset node
> > > - Drop unnecessary change to chromebook_link_defconfig
> > >
> >
> > I applied 14 patches and left 4 below that have open questions:
> > http://patchwork.ozlabs.org/project/uboot/list/?series=105795
> >
> > In the meantime, it looks that travis-ci complained some failures in
> > my last run for the applied patches. I will redo the travis-ci and let
> > you know the results.
>
> Travis-ci reported qemu-x86 is broken. I figured out the issue was due
> to the sysreset-x86 driver added platdata_auto_alloc_size that
> requires more memory. I will send a patch soon.

OK thank you. I have sent v4 now.

Regards,
Simon

[U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL

[Bin Meng]

Hi Simon,

On Wed, May 8, 2019 at 11:41 AM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Tue, 7 May 2019 at 21:33, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Simon,
> >
> > On Tue, May 7, 2019 at 6:07 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Simon,
> > >
> > > On Fri, May 3, 2019 at 12:52 AM Simon Glass <sjg@chromium.org> wrote:
> > > >
> > > > At present SPL is used on 64-bit platforms, to allow SPL to be built as
> > > > a 32-bit program and U-Boot proper to be built as 64-bit.
> > > >
> > > > However it is useful to be able to use SPL on any x86 platform, where
> > > > U-Boot needs to be updated in the field. Then SPL can select which U-Boot
> > > > to run (A or B) and most of the code can be updated. Similarly, using TPL
> > > > allows both SPL and U-Boot to be updated. This is the best approach, since
> > > > it means that all of U-Boot proper as well as SPL (in particular SDRAM
> > > > init) can be updated in the field. This provides for the smallest possible
> > > > amount of read-only (non-updateable) code: just the TPL code.
> > > >
> > > > This series contains a number of changes to allow x86 boards to use TPL,
> > > > SPL and U-Boot proper. As a test, it is enabled for samus with a new
> > > > chromebook_samus_tpl board.
> > > >
> > > > Changes in v3:
> > > > - Rebase to x86/master
> > > > - Use acpi_s3.h header for constants (and tidy up header order)
> > > > - Fix multi-line comment format
> > > > - Remove unneeded pch-reset node
> > > > - Drop unnecessary change to chromebook_link_defconfig
> > > >
> > >
> > > I applied 14 patches and left 4 below that have open questions:
> > > http://patchwork.ozlabs.org/project/uboot/list/?series=105795
> > >
> > > In the meantime, it looks that travis-ci complained some failures in
> > > my last run for the applied patches. I will redo the travis-ci and let
> > > you know the results.
> >
> > Travis-ci reported qemu-x86 is broken. I figured out the issue was due
> > to the sysreset-x86 driver added platdata_auto_alloc_size that
> > requires more memory. I will send a patch soon.
>
> OK thank you. I have sent v4 now.

After applying "Revert "pci: Scale MAX_PCI_REGIONS based on
CONFIG_NR_DRAM_BANKS"" patch, qemu-x86 boots again :)

So it looks that I don't need send the patch to increase the malloc
memory for QEMU, at least for now.

Regards,
Bin