* [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-03-06 21:36 ` Alistair Francis
0 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-03-06 21:36 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
v3:
- Improve machine function names
v2:
- Fix the serial setting so it correctly sets
Alistair Francis (2):
riscv/sifive_u: Fix up file ordering
riscv/sifive_u: Add a serial property to the sifive_u SoC
Bin Meng (1):
riscv/sifive_u: Add a serial property to the sifive_u machine
hw/riscv/sifive_u.c | 137 +++++++++++++++++++++---------------
include/hw/riscv/sifive_u.h | 3 +
2 files changed, 85 insertions(+), 55 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-03-06 21:36 ` Alistair Francis
0 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-03-06 21:36 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
v3:
- Improve machine function names
v2:
- Fix the serial setting so it correctly sets
Alistair Francis (2):
riscv/sifive_u: Fix up file ordering
riscv/sifive_u: Add a serial property to the sifive_u SoC
Bin Meng (1):
riscv/sifive_u: Add a serial property to the sifive_u machine
hw/riscv/sifive_u.c | 137 +++++++++++++++++++++---------------
include/hw/riscv/sifive_u.h | 3 +
2 files changed, 85 insertions(+), 55 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering
2020-03-06 21:36 ` Alistair Francis
@ 2020-03-06 21:36 ` Alistair Francis
-1 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-03-06 21:36 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
Split the file into clear machine and SoC sections.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 109 ++++++++++++++++++++++----------------------
1 file changed, 55 insertions(+), 54 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 156a003642..4688837216 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -308,7 +308,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
-static void riscv_sifive_u_init(MachineState *machine)
+static void sifive_u_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
SiFiveUState *s = RISCV_U_MACHINE(machine);
@@ -399,6 +399,60 @@ static void riscv_sifive_u_init(MachineState *machine)
&address_space_memory);
}
+static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ return s->start_in_flash;
+}
+
+static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = value;
+}
+
+static void sifive_u_machine_instance_init(Object *obj)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = false;
+ object_property_add_bool(obj, "start-in-flash", sifive_u_machine_get_start_in_flash,
+ sifive_u_machine_set_start_in_flash, NULL);
+ object_property_set_description(obj, "start-in-flash",
+ "Set on to tell QEMU's ROM to jump to " \
+ "flash. Otherwise QEMU will jump to DRAM",
+ NULL);
+}
+
+
+static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V Board compatible with SiFive U SDK";
+ mc->init = sifive_u_machine_init;
+ mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
+ mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
+ mc->default_cpus = mc->min_cpus;
+}
+
+static const TypeInfo sifive_u_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("sifive_u"),
+ .parent = TYPE_MACHINE,
+ .class_init = sifive_u_machine_class_init,
+ .instance_init = sifive_u_machine_instance_init,
+ .instance_size = sizeof(SiFiveUState),
+};
+
+static void sifive_u_machine_init_register_types(void)
+{
+ type_register_static(&sifive_u_machine_typeinfo);
+}
+
+type_init(sifive_u_machine_init_register_types)
+
static void riscv_sifive_u_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -439,33 +493,6 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM);
}
-static bool sifive_u_get_start_in_flash(Object *obj, Error **errp)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- return s->start_in_flash;
-}
-
-static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- s->start_in_flash = value;
-}
-
-static void riscv_sifive_u_machine_instance_init(Object *obj)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- s->start_in_flash = false;
- object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_flash,
- sifive_u_set_start_in_flash, NULL);
- object_property_set_description(obj, "start-in-flash",
- "Set on to tell QEMU's ROM to jump to " \
- "flash. Otherwise QEMU will jump to DRAM",
- NULL);
-}
-
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -603,29 +630,3 @@ static void riscv_sifive_u_soc_register_types(void)
}
type_init(riscv_sifive_u_soc_register_types)
-
-static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->desc = "RISC-V Board compatible with SiFive U SDK";
- mc->init = riscv_sifive_u_init;
- mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
- mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
- mc->default_cpus = mc->min_cpus;
-}
-
-static const TypeInfo riscv_sifive_u_machine_typeinfo = {
- .name = MACHINE_TYPE_NAME("sifive_u"),
- .parent = TYPE_MACHINE,
- .class_init = riscv_sifive_u_machine_class_init,
- .instance_init = riscv_sifive_u_machine_instance_init,
- .instance_size = sizeof(SiFiveUState),
-};
-
-static void riscv_sifive_u_machine_init_register_types(void)
-{
- type_register_static(&riscv_sifive_u_machine_typeinfo);
-}
-
-type_init(riscv_sifive_u_machine_init_register_types)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering
@ 2020-03-06 21:36 ` Alistair Francis
0 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-03-06 21:36 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
Split the file into clear machine and SoC sections.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 109 ++++++++++++++++++++++----------------------
1 file changed, 55 insertions(+), 54 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 156a003642..4688837216 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -308,7 +308,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
-static void riscv_sifive_u_init(MachineState *machine)
+static void sifive_u_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
SiFiveUState *s = RISCV_U_MACHINE(machine);
@@ -399,6 +399,60 @@ static void riscv_sifive_u_init(MachineState *machine)
&address_space_memory);
}
+static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ return s->start_in_flash;
+}
+
+static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = value;
+}
+
+static void sifive_u_machine_instance_init(Object *obj)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = false;
+ object_property_add_bool(obj, "start-in-flash", sifive_u_machine_get_start_in_flash,
+ sifive_u_machine_set_start_in_flash, NULL);
+ object_property_set_description(obj, "start-in-flash",
+ "Set on to tell QEMU's ROM to jump to " \
+ "flash. Otherwise QEMU will jump to DRAM",
+ NULL);
+}
+
+
+static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V Board compatible with SiFive U SDK";
+ mc->init = sifive_u_machine_init;
+ mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
+ mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
+ mc->default_cpus = mc->min_cpus;
+}
+
+static const TypeInfo sifive_u_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("sifive_u"),
+ .parent = TYPE_MACHINE,
+ .class_init = sifive_u_machine_class_init,
+ .instance_init = sifive_u_machine_instance_init,
+ .instance_size = sizeof(SiFiveUState),
+};
+
+static void sifive_u_machine_init_register_types(void)
+{
+ type_register_static(&sifive_u_machine_typeinfo);
+}
+
+type_init(sifive_u_machine_init_register_types)
+
static void riscv_sifive_u_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -439,33 +493,6 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM);
}
-static bool sifive_u_get_start_in_flash(Object *obj, Error **errp)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- return s->start_in_flash;
-}
-
-static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- s->start_in_flash = value;
-}
-
-static void riscv_sifive_u_machine_instance_init(Object *obj)
-{
- SiFiveUState *s = RISCV_U_MACHINE(obj);
-
- s->start_in_flash = false;
- object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_flash,
- sifive_u_set_start_in_flash, NULL);
- object_property_set_description(obj, "start-in-flash",
- "Set on to tell QEMU's ROM to jump to " \
- "flash. Otherwise QEMU will jump to DRAM",
- NULL);
-}
-
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -603,29 +630,3 @@ static void riscv_sifive_u_soc_register_types(void)
}
type_init(riscv_sifive_u_soc_register_types)
-
-static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->desc = "RISC-V Board compatible with SiFive U SDK";
- mc->init = riscv_sifive_u_init;
- mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
- mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
- mc->default_cpus = mc->min_cpus;
-}
-
-static const TypeInfo riscv_sifive_u_machine_typeinfo = {
- .name = MACHINE_TYPE_NAME("sifive_u"),
- .parent = TYPE_MACHINE,
- .class_init = riscv_sifive_u_machine_class_init,
- .instance_init = riscv_sifive_u_machine_instance_init,
- .instance_size = sizeof(SiFiveUState),
-};
-
-static void riscv_sifive_u_machine_init_register_types(void)
-{
- type_register_static(&riscv_sifive_u_machine_typeinfo);
-}
-
-type_init(riscv_sifive_u_machine_init_register_types)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
2020-03-06 21:36 ` Alistair Francis
@ 2020-03-06 21:36 ` Alistair Francis
-1 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-03-06 21:36 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to the sifive_u SoC to specify
the board serial number. When not given, the default serial number
1 is used.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/riscv/sifive_u.c | 8 +++++++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4688837216..dc572c761a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -488,7 +488,6 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_SIFIVE_U_PRCI);
sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
TYPE_SIFIVE_U_OTP);
- qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
@@ -581,6 +580,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
@@ -607,10 +607,16 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
}
+static Property riscv_sifive_u_soc_props[] = {
+ DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, riscv_sifive_u_soc_props);
dc->realize = riscv_sifive_u_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 82667b5746..a2baa1de5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState {
SiFiveUPRCIState prci;
SiFiveUOTPState otp;
CadenceGEMState gem;
+
+ uint32_t serial;
} SiFiveUSoCState;
#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
@ 2020-03-06 21:36 ` Alistair Francis
0 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-03-06 21:36 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to the sifive_u SoC to specify
the board serial number. When not given, the default serial number
1 is used.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/riscv/sifive_u.c | 8 +++++++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4688837216..dc572c761a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -488,7 +488,6 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_SIFIVE_U_PRCI);
sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
TYPE_SIFIVE_U_OTP);
- qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
@@ -581,6 +580,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
@@ -607,10 +607,16 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
}
+static Property riscv_sifive_u_soc_props[] = {
+ DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, riscv_sifive_u_soc_props);
dc->realize = riscv_sifive_u_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 82667b5746..a2baa1de5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState {
SiFiveUPRCIState prci;
SiFiveUOTPState otp;
CadenceGEMState gem;
+
+ uint32_t serial;
} SiFiveUSoCState;
#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine
2020-03-06 21:36 ` Alistair Francis
@ 2020-03-06 21:36 ` Alistair Francis
-1 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-03-06 21:36 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23
From: Bin Meng <bmeng.cn@gmail.com>
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com>
[ Changed by AF:
- Use the SoC's serial property to pass the info to the SoC
- Fixup commit title
- Rebase on file restructuring
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 20 ++++++++++++++++++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index dc572c761a..44cb72f09e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -34,6 +34,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
@@ -322,6 +323,8 @@ static void sifive_u_machine_init(MachineState *machine)
object_initialize_child(OBJECT(machine), "soc", &s->soc,
sizeof(s->soc), TYPE_RISCV_U_SOC,
&error_abort, NULL);
+ object_property_set_uint(OBJECT(&s->soc), s->serial, "serial",
+ &error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_abort);
@@ -413,6 +416,18 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
s->start_in_flash = value;
}
+static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
+static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
static void sifive_u_machine_instance_init(Object *obj)
{
SiFiveUState *s = RISCV_U_MACHINE(obj);
@@ -424,6 +439,11 @@ static void sifive_u_machine_instance_init(Object *obj)
"Set on to tell QEMU's ROM to jump to " \
"flash. Otherwise QEMU will jump to DRAM",
NULL);
+
+ s->serial = OTP_SERIAL;
+ object_property_add(obj, "serial", "uint32", sifive_u_machine_get_serial,
+ sifive_u_machine_set_serial, NULL, &s->serial, NULL);
+ object_property_set_description(obj, "serial", "Board serial number", NULL);
}
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index a2baa1de5f..16c297ec5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -61,6 +61,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+ uint32_t serial;
} SiFiveUState;
enum {
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v3 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine
@ 2020-03-06 21:36 ` Alistair Francis
0 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-03-06 21:36 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23
From: Bin Meng <bmeng.cn@gmail.com>
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com>
[ Changed by AF:
- Use the SoC's serial property to pass the info to the SoC
- Fixup commit title
- Rebase on file restructuring
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 20 ++++++++++++++++++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index dc572c761a..44cb72f09e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -34,6 +34,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
@@ -322,6 +323,8 @@ static void sifive_u_machine_init(MachineState *machine)
object_initialize_child(OBJECT(machine), "soc", &s->soc,
sizeof(s->soc), TYPE_RISCV_U_SOC,
&error_abort, NULL);
+ object_property_set_uint(OBJECT(&s->soc), s->serial, "serial",
+ &error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_abort);
@@ -413,6 +416,18 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
s->start_in_flash = value;
}
+static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
+static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
static void sifive_u_machine_instance_init(Object *obj)
{
SiFiveUState *s = RISCV_U_MACHINE(obj);
@@ -424,6 +439,11 @@ static void sifive_u_machine_instance_init(Object *obj)
"Set on to tell QEMU's ROM to jump to " \
"flash. Otherwise QEMU will jump to DRAM",
NULL);
+
+ s->serial = OTP_SERIAL;
+ object_property_add(obj, "serial", "uint32", sifive_u_machine_get_serial,
+ sifive_u_machine_set_serial, NULL, &s->serial, NULL);
+ object_property_set_description(obj, "serial", "Board serial number", NULL);
}
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index a2baa1de5f..16c297ec5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -61,6 +61,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+ uint32_t serial;
} SiFiveUState;
enum {
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering
2020-03-06 21:36 ` Alistair Francis
@ 2020-03-07 1:14 ` Bin Meng
-1 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2020-03-07 1:14 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Sat, Mar 7, 2020 at 5:44 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Split the file into clear machine and SoC sections.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 109 ++++++++++++++++++++++----------------------
> 1 file changed, 55 insertions(+), 54 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering
@ 2020-03-07 1:14 ` Bin Meng
0 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2020-03-07 1:14 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis
On Sat, Mar 7, 2020 at 5:44 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Split the file into clear machine and SoC sections.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 109 ++++++++++++++++++++++----------------------
> 1 file changed, 55 insertions(+), 54 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
2020-03-06 21:36 ` Alistair Francis
@ 2020-03-24 2:08 ` Bin Meng
-1 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2020-03-24 2:08 UTC (permalink / raw)
To: Alistair Francis, Palmer Dabbelt
Cc: Alistair Francis, open list:RISC-V, qemu-devel@nongnu.org Developers
Hi Palmer,
On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. When multiple QEMU 'sifive_u' instances are
> created and connected to the same subnet, they all have the same
> MAC address hence it creates a unusable network.
>
> A new "serial" property is introduced to specify the board serial
> number. When not given, the default serial number 1 is used.
>
Could you please take this for v5.0.0?
Regards,
Bin
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-03-24 2:08 ` Bin Meng
0 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2020-03-24 2:08 UTC (permalink / raw)
To: Alistair Francis, Palmer Dabbelt
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Alistair Francis
Hi Palmer,
On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. When multiple QEMU 'sifive_u' instances are
> created and connected to the same subnet, they all have the same
> MAC address hence it creates a unusable network.
>
> A new "serial" property is introduced to specify the board serial
> number. When not given, the default serial number 1 is used.
>
Could you please take this for v5.0.0?
Regards,
Bin
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
2020-03-24 2:08 ` Bin Meng
@ 2020-04-02 5:39 ` Bin Meng
-1 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2020-04-02 5:39 UTC (permalink / raw)
To: Alistair Francis, Palmer Dabbelt
Cc: Alistair Francis, open list:RISC-V, qemu-devel@nongnu.org Developers
On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Palmer,
>
> On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > At present the board serial number is hard-coded to 1, and passed
> > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > the serial number to generate a unique MAC address for the on-chip
> > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > created and connected to the same subnet, they all have the same
> > MAC address hence it creates a unusable network.
> >
> > A new "serial" property is introduced to specify the board serial
> > number. When not given, the default serial number 1 is used.
> >
>
> Could you please take this for v5.0.0?
Ping?
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-04-02 5:39 ` Bin Meng
0 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2020-04-02 5:39 UTC (permalink / raw)
To: Alistair Francis, Palmer Dabbelt
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Alistair Francis
On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Palmer,
>
> On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > At present the board serial number is hard-coded to 1, and passed
> > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > the serial number to generate a unique MAC address for the on-chip
> > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > created and connected to the same subnet, they all have the same
> > MAC address hence it creates a unusable network.
> >
> > A new "serial" property is introduced to specify the board serial
> > number. When not given, the default serial number 1 is used.
> >
>
> Could you please take this for v5.0.0?
Ping?
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
2020-03-24 2:08 ` Bin Meng
@ 2020-04-03 16:01 ` Palmer Dabbelt
-1 siblings, 0 replies; 24+ messages in thread
From: Palmer Dabbelt @ 2020-04-03 16:01 UTC (permalink / raw)
To: bmeng.cn; +Cc: qemu-riscv, Alistair Francis, qemu-devel, alistair23
On Mon, 23 Mar 2020 19:08:19 PDT (-0700), bmeng.cn@gmail.com wrote:
> Hi Palmer,
>
> On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
>>
>> At present the board serial number is hard-coded to 1, and passed
>> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
>> the serial number to generate a unique MAC address for the on-chip
>> ethernet controller. When multiple QEMU 'sifive_u' instances are
>> created and connected to the same subnet, they all have the same
>> MAC address hence it creates a unusable network.
>>
>> A new "serial" property is introduced to specify the board serial
>> number. When not given, the default serial number 1 is used.
>>
>
> Could you please take this for v5.0.0?
It's in the queue, sorry I missed them.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-04-03 16:01 ` Palmer Dabbelt
0 siblings, 0 replies; 24+ messages in thread
From: Palmer Dabbelt @ 2020-04-03 16:01 UTC (permalink / raw)
To: bmeng.cn; +Cc: Alistair Francis, qemu-devel, qemu-riscv, alistair23
On Mon, 23 Mar 2020 19:08:19 PDT (-0700), bmeng.cn@gmail.com wrote:
> Hi Palmer,
>
> On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
>>
>> At present the board serial number is hard-coded to 1, and passed
>> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
>> the serial number to generate a unique MAC address for the on-chip
>> ethernet controller. When multiple QEMU 'sifive_u' instances are
>> created and connected to the same subnet, they all have the same
>> MAC address hence it creates a unusable network.
>>
>> A new "serial" property is introduced to specify the board serial
>> number. When not given, the default serial number 1 is used.
>>
>
> Could you please take this for v5.0.0?
It's in the queue, sorry I missed them.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
2020-04-02 5:39 ` Bin Meng
@ 2020-04-20 19:17 ` Alistair Francis
-1 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-04-20 19:17 UTC (permalink / raw)
To: Bin Meng
Cc: Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Palmer,
> >
> > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > <alistair.francis@wdc.com> wrote:
> > >
> > > At present the board serial number is hard-coded to 1, and passed
> > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > the serial number to generate a unique MAC address for the on-chip
> > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > created and connected to the same subnet, they all have the same
> > > MAC address hence it creates a unusable network.
> > >
> > > A new "serial" property is introduced to specify the board serial
> > > number. When not given, the default serial number 1 is used.
> > >
> >
> > Could you please take this for v5.0.0?
Applied to the RISC-V tree for 5.1
Alistair
>
> Ping?
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-04-20 19:17 ` Alistair Francis
0 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-04-20 19:17 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Palmer Dabbelt,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Palmer,
> >
> > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > <alistair.francis@wdc.com> wrote:
> > >
> > > At present the board serial number is hard-coded to 1, and passed
> > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > the serial number to generate a unique MAC address for the on-chip
> > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > created and connected to the same subnet, they all have the same
> > > MAC address hence it creates a unusable network.
> > >
> > > A new "serial" property is introduced to specify the board serial
> > > number. When not given, the default serial number 1 is used.
> > >
> >
> > Could you please take this for v5.0.0?
Applied to the RISC-V tree for 5.1
Alistair
>
> Ping?
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
2020-04-20 19:17 ` Alistair Francis
@ 2020-04-21 2:17 ` Bin Meng
-1 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2020-04-21 2:17 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Palmer,
> > >
> > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > > <alistair.francis@wdc.com> wrote:
> > > >
> > > > At present the board serial number is hard-coded to 1, and passed
> > > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > > the serial number to generate a unique MAC address for the on-chip
> > > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > > created and connected to the same subnet, they all have the same
> > > > MAC address hence it creates a unusable network.
> > > >
> > > > A new "serial" property is introduced to specify the board serial
> > > > number. When not given, the default serial number 1 is used.
> > > >
> > >
> > > Could you please take this for v5.0.0?
>
> Applied to the RISC-V tree for 5.1
>
Sigh, this patch was submitted on Mar 7 and that is before soft freeze ...
Any chance to get this in 5.0?
Regards,
Bin
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-04-21 2:17 ` Bin Meng
0 siblings, 0 replies; 24+ messages in thread
From: Bin Meng @ 2020-04-21 2:17 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Palmer,
> > >
> > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > > <alistair.francis@wdc.com> wrote:
> > > >
> > > > At present the board serial number is hard-coded to 1, and passed
> > > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > > the serial number to generate a unique MAC address for the on-chip
> > > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > > created and connected to the same subnet, they all have the same
> > > > MAC address hence it creates a unusable network.
> > > >
> > > > A new "serial" property is introduced to specify the board serial
> > > > number. When not given, the default serial number 1 is used.
> > > >
> > >
> > > Could you please take this for v5.0.0?
>
> Applied to the RISC-V tree for 5.1
>
Sigh, this patch was submitted on Mar 7 and that is before soft freeze ...
Any chance to get this in 5.0?
Regards,
Bin
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
2020-04-21 2:17 ` Bin Meng
@ 2020-04-21 17:40 ` Alistair Francis
-1 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-04-21 17:40 UTC (permalink / raw)
To: Bin Meng
Cc: Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Mon, Apr 20, 2020 at 7:17 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >
> > > > Hi Palmer,
> > > >
> > > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > > > <alistair.francis@wdc.com> wrote:
> > > > >
> > > > > At present the board serial number is hard-coded to 1, and passed
> > > > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > > > the serial number to generate a unique MAC address for the on-chip
> > > > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > > > created and connected to the same subnet, they all have the same
> > > > > MAC address hence it creates a unusable network.
> > > > >
> > > > > A new "serial" property is introduced to specify the board serial
> > > > > number. When not given, the default serial number 1 is used.
> > > > >
> > > >
> > > > Could you please take this for v5.0.0?
> >
> > Applied to the RISC-V tree for 5.1
> >
>
> Sigh, this patch was submitted on Mar 7 and that is before soft freeze ...
>
> Any chance to get this in 5.0?
That is up to Palmer. I'm only taking over PRs after the 5.0 release.
Alistair
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-04-21 17:40 ` Alistair Francis
0 siblings, 0 replies; 24+ messages in thread
From: Alistair Francis @ 2020-04-21 17:40 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Palmer Dabbelt,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Mon, Apr 20, 2020 at 7:17 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >
> > > > Hi Palmer,
> > > >
> > > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
> > > > <alistair.francis@wdc.com> wrote:
> > > > >
> > > > > At present the board serial number is hard-coded to 1, and passed
> > > > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> > > > > the serial number to generate a unique MAC address for the on-chip
> > > > > ethernet controller. When multiple QEMU 'sifive_u' instances are
> > > > > created and connected to the same subnet, they all have the same
> > > > > MAC address hence it creates a unusable network.
> > > > >
> > > > > A new "serial" property is introduced to specify the board serial
> > > > > number. When not given, the default serial number 1 is used.
> > > > >
> > > >
> > > > Could you please take this for v5.0.0?
> >
> > Applied to the RISC-V tree for 5.1
> >
>
> Sigh, this patch was submitted on Mar 7 and that is before soft freeze ...
>
> Any chance to get this in 5.0?
That is up to Palmer. I'm only taking over PRs after the 5.0 release.
Alistair
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
2020-04-21 17:40 ` Alistair Francis
@ 2020-04-21 17:54 ` Palmer Dabbelt
-1 siblings, 0 replies; 24+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 17:54 UTC (permalink / raw)
To: alistair23; +Cc: qemu-riscv, bmeng.cn, Alistair Francis, qemu-devel
On Tue, 21 Apr 2020 10:40:05 PDT (-0700), alistair23@gmail.com wrote:
> On Mon, Apr 20, 2020 at 7:17 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis <alistair23@gmail.com> wrote:
>> >
>> > On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>> > >
>> > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>> > > >
>> > > > Hi Palmer,
>> > > >
>> > > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
>> > > > <alistair.francis@wdc.com> wrote:
>> > > > >
>> > > > > At present the board serial number is hard-coded to 1, and passed
>> > > > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
>> > > > > the serial number to generate a unique MAC address for the on-chip
>> > > > > ethernet controller. When multiple QEMU 'sifive_u' instances are
>> > > > > created and connected to the same subnet, they all have the same
>> > > > > MAC address hence it creates a unusable network.
>> > > > >
>> > > > > A new "serial" property is introduced to specify the board serial
>> > > > > number. When not given, the default serial number 1 is used.
>> > > > >
>> > > >
>> > > > Could you please take this for v5.0.0?
>> >
>> > Applied to the RISC-V tree for 5.1
>> >
>>
>> Sigh, this patch was submitted on Mar 7 and that is before soft freeze ...
>>
>> Any chance to get this in 5.0?
>
> That is up to Palmer. I'm only taking over PRs after the 5.0 release.
Oh, sorry, I just saw this. I though I'd sent out this in a PR weeks ago, but
it looks like I didn't actually send it out. I'm not sure if 5.0 is still
open, but I'll send a PR out now...
>
> Alistair
>
>>
>> Regards,
>> Bin
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
@ 2020-04-21 17:54 ` Palmer Dabbelt
0 siblings, 0 replies; 24+ messages in thread
From: Palmer Dabbelt @ 2020-04-21 17:54 UTC (permalink / raw)
To: alistair23; +Cc: bmeng.cn, Alistair Francis, qemu-devel, qemu-riscv
On Tue, 21 Apr 2020 10:40:05 PDT (-0700), alistair23@gmail.com wrote:
> On Mon, Apr 20, 2020 at 7:17 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis <alistair23@gmail.com> wrote:
>> >
>> > On Wed, Apr 1, 2020 at 10:39 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>> > >
>> > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>> > > >
>> > > > Hi Palmer,
>> > > >
>> > > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis
>> > > > <alistair.francis@wdc.com> wrote:
>> > > > >
>> > > > > At present the board serial number is hard-coded to 1, and passed
>> > > > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses
>> > > > > the serial number to generate a unique MAC address for the on-chip
>> > > > > ethernet controller. When multiple QEMU 'sifive_u' instances are
>> > > > > created and connected to the same subnet, they all have the same
>> > > > > MAC address hence it creates a unusable network.
>> > > > >
>> > > > > A new "serial" property is introduced to specify the board serial
>> > > > > number. When not given, the default serial number 1 is used.
>> > > > >
>> > > >
>> > > > Could you please take this for v5.0.0?
>> >
>> > Applied to the RISC-V tree for 5.1
>> >
>>
>> Sigh, this patch was submitted on Mar 7 and that is before soft freeze ...
>>
>> Any chance to get this in 5.0?
>
> That is up to Palmer. I'm only taking over PRs after the 5.0 release.
Oh, sorry, I just saw this. I though I'd sent out this in a PR weeks ago, but
it looks like I didn't actually send it out. I'm not sure if 5.0 is still
open, but I'll send a PR out now...
>
> Alistair
>
>>
>> Regards,
>> Bin
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2020-04-21 17:55 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-06 21:36 [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u Alistair Francis
2020-03-06 21:36 ` Alistair Francis
2020-03-06 21:36 ` [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering Alistair Francis
2020-03-06 21:36 ` Alistair Francis
2020-03-07 1:14 ` Bin Meng
2020-03-07 1:14 ` Bin Meng
2020-03-06 21:36 ` [PATCH v3 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC Alistair Francis
2020-03-06 21:36 ` Alistair Francis
2020-03-06 21:36 ` [PATCH v3 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine Alistair Francis
2020-03-06 21:36 ` Alistair Francis
2020-03-24 2:08 ` [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u Bin Meng
2020-03-24 2:08 ` Bin Meng
2020-04-02 5:39 ` Bin Meng
2020-04-02 5:39 ` Bin Meng
2020-04-20 19:17 ` Alistair Francis
2020-04-20 19:17 ` Alistair Francis
2020-04-21 2:17 ` Bin Meng
2020-04-21 2:17 ` Bin Meng
2020-04-21 17:40 ` Alistair Francis
2020-04-21 17:40 ` Alistair Francis
2020-04-21 17:54 ` Palmer Dabbelt
2020-04-21 17:54 ` Palmer Dabbelt
2020-04-03 16:01 ` Palmer Dabbelt
2020-04-03 16:01 ` Palmer Dabbelt
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