Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer

From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <anthony@codemonkey.ws>
Cc: "Liu Ping Fan" <pingfank@linux.vnet.ibm.com>,
	"Jan Kiszka" <jan.kiszka@web.de>,
	qemu-devel <qemu-devel@nongnu.org>,
	"Alexander Graf" <agraf@suse.de>,
	"Hervé Poussineau" <hpoussin@reactos.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Andreas Färber" <afaerber@suse.de>
Subject: Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer
Date: Sun, 14 Jul 2013 15:58:08 +0100	[thread overview]
Message-ID: <CAFEAcA-Tq-CfRBvUbBf7iBWJ42c-_Jd5rZM-KcnteCX3C2yfFQ@mail.gmail.com> (raw)
In-Reply-To: <874nbxqolf.fsf@codemonkey.ws>

On 14 July 2013 14:05, Anthony Liguori <anthony@codemonkey.ws> wrote:
>> Also, what devices exactly would have a non-native byte order?!?  I'm
>> confused...
>
> MMIO/PIO requests don't have a byte order.  It's literally 64 or 32 data
> pins that are numbered D0..D31 whereas D0 is the LSB.  It doesn't matter
> how the pins are arranged.

Devices themselves do have a byte order, though, right? Specifically,
if you do a 32 bit read of address 0 on a device and an 8 bit read,
then you can distinguish a BE device from an LE one.
(Most notably, RAM in QEMU is always host-endian...)
Devices which only allow 32 bit reads and abort any others wouldn't
have an endianness though.

(I need to sit down and think about this all and draw diagrams
and look at what we currently do, though. BE guests on LE hosts
with and without KVM look particularly thorny.)

-- PMM