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* [Qemu-devel] [PULL 00/33] target-arm queue
@ 2017-09-04 16:21 Peter Maydell
  2017-09-04 17:28 ` Peter Maydell
  0 siblings, 1 reply; 8+ messages in thread
From: Peter Maydell @ 2017-09-04 16:21 UTC (permalink / raw)
  To: qemu-devel

Third time's the charm...

-- PMM

The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-2

for you to fetch changes up to 7229ec5825df6b933f150b54a8a2bedd2de1864c:

  arm_gicv3_kvm: Fix compile warning (2017-09-04 17:13:53 +0100)

----------------------------------------------------------------
target-arm:
 * collection of M profile cleanups and minor bugfixes
 * loader: handle ELF files with overlapping zero-init data
 * virt: allow PMU instantiation with userspace irqchip
 * wdt_aspeed: Add support for the reset width register
 * cpu: Define new cpu_transaction_failed() hook
 * Mark some SoC devices as not user-creatable
 * arm: Fix aa64 ldp register writeback
 * arm_gicv3_kvm: Fix compile warning

----------------------------------------------------------------
Andrew Jeffery (2):
      watchdog: wdt_aspeed: Add support for the reset width register
      aspeed_soc: Propagate silicon-rev to watchdog

Andrew Jones (4):
      hw/arm/virt: add pmu interrupt state
      target/arm/kvm: pmu: split init and set-irq stages
      hw/arm/virt: allow pmu instantiation with userspace irqchip
      target/arm/kvm: pmu: improve error handling

Peter Maydell (22):
      target/arm: Use MMUAccessType enum rather than int
      target/arm: Don't trap WFI/WFE for M profile
      target/arm: Consolidate PMSA handling in get_phys_addr()
      target/arm: Tighten up Thumb decode where new v8M insns will be
      hw/intc/armv7m_nvic.c: Remove out of date comment
      target/arm: Remove incorrect comment about MPU_CTRL
      target/arm: Fix outdated comment about exception exit
      target/arm: Define and use XPSR bit masks
      target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
      target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
      target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
      target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
      target/arm: Create and use new function arm_v7m_is_handler_mode()
      armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
      nvic: Implement "user accesses BusFault" SCS region behaviour
      loader: Handle ELF files with overlapping zero-initialized data
      loader: Ignore zero-sized ELF segments
      memory.h: Move MemTxResult type to memattrs.h
      cpu: Define new cpu_transaction_failed() hook
      cputlb: Support generating CPU exceptions on memory transaction failures
      target/arm: Factor out fault delivery code
      target/arm: Allow deliver_fault() caller to specify EA bit

Philippe Mathieu-Daudé (1):
      hw/arm: use defined type name instead of hard-coded string

Pranith Kumar (1):
      arm_gicv3_kvm: Fix compile warning

Richard Henderson (1):
      target/arm: Fix aa64 ldp register writeback

Thomas Huth (2):
      hw/arm/aspeed_soc: Mark devices as user_creatable = false
      hw/arm/digic: Mark device with user_creatable = false

 include/exec/memattrs.h                |  10 +++
 include/exec/memory.h                  |  10 ---
 include/hw/arm/armv7m.h                |   2 +-
 include/hw/elf_ops.h                   |  72 +++++++++++++++++--
 include/hw/{arm => intc}/armv7m_nvic.h |   0
 include/hw/watchdog/wdt_aspeed.h       |   2 +
 include/qom/cpu.h                      |  22 ++++++
 softmmu_template.h                     |   4 +-
 target/arm/cpu.h                       |  56 +++++++++++----
 target/arm/internals.h                 |   5 +-
 target/arm/kvm_arm.h                   |   9 ++-
 accel/tcg/cputlb.c                     |  32 ++++++++-
 hw/arm/armv7m.c                        |   4 +-
 hw/arm/aspeed_soc.c                    |   4 ++
 hw/arm/digic.c                         |   2 +
 hw/arm/exynos4210.c                    |   4 +-
 hw/arm/highbank.c                      |  11 +--
 hw/arm/realview.c                      |   6 +-
 hw/arm/vexpress.c                      |   6 +-
 hw/arm/virt.c                          |  12 +++-
 hw/arm/xilinx_zynq.c                   |  14 ++--
 hw/intc/arm_gicv3_kvm.c                |   2 +-
 hw/intc/armv7m_nvic.c                  |  68 +++++++++++-------
 hw/watchdog/wdt_aspeed.c               |  93 ++++++++++++++++++++++---
 target/arm/cpu.c                       |   7 +-
 target/arm/helper.c                    | 124 ++++++++++++++++-----------------
 target/arm/kvm.c                       |   6 +-
 target/arm/kvm32.c                     |   8 ++-
 target/arm/kvm64.c                     |  63 ++++++++++-------
 target/arm/machine.c                   |  54 +++++++++++++-
 target/arm/op_helper.c                 | 121 +++++++++++++++++---------------
 target/arm/translate-a64.c             |  29 ++++----
 target/arm/translate.c                 | 106 +++++++++++++++++++++-------
 33 files changed, 677 insertions(+), 291 deletions(-)
 rename include/hw/{arm => intc}/armv7m_nvic.h (100%)

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [Qemu-devel] [PULL 00/33] target-arm queue
@ 2018-10-08 13:59 Peter Maydell
  2018-10-08 14:46 ` Peter Maydell
  0 siblings, 1 reply; 8+ messages in thread
From: Peter Maydell @ 2018-10-08 13:59 UTC (permalink / raw)
  To: qemu-devel

target-arm queue: the big things in here are SVE in system
emulation mode, and v8M stack limit checking; there are
also a handful of smaller fixes.

thanks
-- PMM

The following changes since commit 079911cb6e26898e16f5bb56ef4f9d33cf92d32d:

  Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20181005' into staging (2018-10-08 12:44:35 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181008

for you to fetch changes up to 74e2e59b8d0a68be0956310fc349179c89fd7be0:

  hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow (2018-10-08 14:55:05 +0100)

----------------------------------------------------------------
target-arm queue:
 * target/arm: fix error in a code comment
 * virt: Suppress external aborts on virt-2.10 and earlier
 * target/arm: Correct condition for v8M callee stack push
 * target/arm: Don't read r4 from v8M exception stackframe twice
 * target/arm: Support SVE in system emulation mode
 * target/arm: Implement v8M hardware stack limit checking
 * hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow

----------------------------------------------------------------
Dongjiu Geng (1):
      target/arm: fix code comments error

Peter Maydell (17):
      virt: Suppress external aborts on virt-2.10 and earlier
      target/arm: Correct condition for v8M callee stack push
      target/arm: Don't read r4 from v8M exception stackframe twice
      target/arm: Define new TBFLAG for v8M stack checking
      target/arm: Define new EXCP type for v8M stack overflows
      target/arm: Move v7m_using_psp() to internals.h
      target/arm: Add v8M stack checks on ADD/SUB/MOV of SP
      target/arm: Add some comments in Thumb decode
      target/arm: Add v8M stack checks on exception entry
      target/arm: Add v8M stack limit checks on NS function calls
      target/arm: Add v8M stack checks for LDRD/STRD (imm)
      target/arm: Add v8M stack checks for Thumb2 LDM/STM
      target/arm: Add v8M stack checks for T32 load/store single
      target/arm: Add v8M stack checks for Thumb push/pop
      target/arm: Add v8M stack checks for VLDM/VSTM
      target/arm: Add v8M stack checks for MSR to SP_NS
      hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow

Richard Henderson (15):
      target/arm: Define ID_AA64ZFR0_EL1
      target/arm: Adjust sve_exception_el
      target/arm: Pass in current_el to fp and sve_exception_el
      target/arm: Handle SVE vector length changes in system mode
      target/arm: Adjust aarch64_cpu_dump_state for system mode SVE
      target/arm: Clear unused predicate bits for LD1RQ
      target/arm: Rewrite helper_sve_ld1*_r using pages
      target/arm: Rewrite helper_sve_ld[234]*_r
      target/arm: Rewrite helper_sve_st[1234]*_r
      target/arm: Split contiguous loads for endianness
      target/arm: Split contiguous stores for endianness
      target/arm: Rewrite vector gather loads
      target/arm: Rewrite vector gather stores
      target/arm: Rewrite vector gather first-fault loads
      target/arm: Pass TCGMemOpIdx to sve memory helpers

 target/arm/cpu.h           |   17 +
 target/arm/helper-sve.h    |  385 ++++++---
 target/arm/helper.h        |    2 +
 target/arm/internals.h     |   44 +
 target/arm/kvm_arm.h       |    4 +-
 target/arm/translate.h     |    1 +
 hw/arm/virt.c              |    2 +
 hw/display/bcm2835_fb.c    |    2 +-
 target/arm/cpu64.c         |   42 -
 target/arm/helper.c        |  345 +++++---
 target/arm/kvm.c           |    2 +-
 target/arm/op_helper.c     |   24 +-
 target/arm/sve_helper.c    | 1961 ++++++++++++++++++++++++++++++--------------
 target/arm/translate-a64.c |    8 +-
 target/arm/translate-sve.c |  670 ++++++++++-----
 target/arm/translate.c     |  198 ++++-
 16 files changed, 2611 insertions(+), 1096 deletions(-)

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [Qemu-devel] [PULL 00/33] target-arm queue
@ 2014-12-11 12:19 Peter Maydell
  2014-12-11 18:26 ` Peter Maydell
  0 siblings, 1 reply; 8+ messages in thread
From: Peter Maydell @ 2014-12-11 12:19 UTC (permalink / raw)
  To: qemu-devel

First ARM pullreq for 2.3; the big thing here is all the TrustZone
support, though we still don't enable it for any CPUs yet, so in
theory no behavioural changes.

The following changes since commit a09f2d16f6b9f5bcdedb4d116bb54da86e9a3f6e:

  Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20141210' into staging (2014-12-11 11:41:11 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20141211

for you to fetch changes up to 25f2895e0e437a3548f9794846001fb5d5ab853d:

  target-arm: Check error conditions on kvm_arm_reset_vcpu (2014-12-11 12:07:53 +0000)

----------------------------------------------------------------
target-arm queue:
 * pass semihosting exit code out to system
 * more TrustZone support code (still not enabled yet)
 * allow user to direct semihosting to gdb or native explicitly
   rather than always auto-guessing the destination
 * fix memory leak in realview_init
 * fix coverity warning in hw/arm/boot
 * get state migration working for AArch64 CPUs
 * check errors in kvm_arm_reset_vcpu

----------------------------------------------------------------
Alex Bennée (1):
      target-arm/kvm: make reg sync code common between kvm32/64

Christoffer Dall (1):
      target-arm: Check error conditions on kvm_arm_reset_vcpu

Fabian Aggeler (18):
      target-arm: add banked register accessors
      target-arm: add CPREG secure state support
      target-arm: insert AArch32 cpregs twice into hashtable
      target-arm: move AArch32 SCR into security reglist
      target-arm: implement IRQ/FIQ routing to Monitor mode
      target-arm: add NSACR register
      target-arm: add MVBAR support
      target-arm: add SCTLR_EL3 and make SCTLR banked
      target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI
      target-arm: make CSSELR banked
      target-arm: make TTBR0/1 banked
      target-arm: make TTBCR banked
      target-arm: make DACR banked
      target-arm: make IFSR banked
      target-arm: make DFSR banked
      target-arm: make IFAR/DFAR banked
      target-arm: make PAR banked
      target-arm: make c13 cp regs banked (FCSEIDR, ...)

Greg Bellows (5):
      target-arm: extend async excp masking
      target-arm: add async excp target_el function
      target-arm: add SDER definition
      target-arm: make VBAR banked
      target-arm: make MAIR0/1 banked

Liviu Ionescu (2):
      Pass semihosting exit code back to system.
      Add the "-semihosting-config" option.

Nikita Belov (1):
      hw/arm/realview.c: Fix memory leak in realview_init()

Peter Maydell (3):
      target-arm: add secure state bit to CPREG hash
      arm_gic_kvm: Tell kernel about number of IRQs
      target-arm: Support save/load for 64 bit CPUs

Sergey Fedorov (1):
      target-arm: add non-secure Translation Block flag

zhanghailiang (1):
      hw/arm/boot: fix uninitialized scalar variable warning reported by coverity

 gdbstub.c                       |  15 +-
 hw/arm/boot.c                   |   4 +-
 hw/arm/pxa2xx.c                 |   6 +-
 hw/arm/realview.c               |   3 +-
 hw/intc/arm_gic_kvm.c           |  20 ++
 include/exec/gdbstub.h          |   6 +
 linux-user/aarch64/target_cpu.h |   2 +-
 linux-user/arm/target_cpu.h     |   2 +-
 linux-user/main.c               |   2 +-
 qemu-options.hx                 |  12 +-
 target-arm/arm-semi.c           |  11 +-
 target-arm/cpu.c                |  10 +-
 target-arm/cpu.h                | 364 ++++++++++++++++++---
 target-arm/helper.c             | 677 ++++++++++++++++++++++++++++++----------
 target-arm/internals.h          |   6 +-
 target-arm/kvm.c                | 107 +++++++
 target-arm/kvm32.c              | 100 +-----
 target-arm/kvm64.c              |  24 +-
 target-arm/kvm_arm.h            |  22 ++
 target-arm/machine.c            |  22 +-
 target-arm/op_helper.c          |   4 +-
 target-arm/translate.c          |  15 +-
 target-arm/translate.h          |   1 +
 vl.c                            |  48 +++
 24 files changed, 1141 insertions(+), 342 deletions(-)

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [Qemu-devel] [PULL 00/33] target-arm queue
@ 2012-06-20 12:26 Peter Maydell
  2012-06-24 12:27 ` Blue Swirl
  0 siblings, 1 reply; 8+ messages in thread
From: Peter Maydell @ 2012-06-20 12:26 UTC (permalink / raw)
  To: Blue Swirl; +Cc: qemu-devel, Anthony Liguori, Paul Brook

This is a pullreq for outstanding target-arm patches. In fact it
only has my cp15 rework series in it. (No changes in that since the
v2 series I sent out some weeks back except for a tiny trivial fix
for a textual rebase conflict.)

Please pull.

-- PMM


The following changes since commit 93bfef4c6e4b23caea9d51e1099d06433d8835a4:

  Allow machines to configure the QEMU_VERSION that's exposed via hardware (2012-06-19 13:36:56 -0500)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Peter Maydell (33):
      target-arm: Fix 11MPCore cache type register value
      target-arm: initial coprocessor register framework
      hw/pxa2xx: Convert cp14 perf registers to new scheme
      hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs
      hw/pxa2xx_pic: Convert coprocessor registers to new scheme
      target-arm: Remove old cpu_arm_set_cp_io infrastructure
      target-arm: Add register_cp_regs_for_features()
      target-arm: Convert debug registers to cp_reginfo
      target-arm: Convert TEECR, TEEHBR to new scheme
      target-arm: Convert WFI/barriers special cases to cp_reginfo
      target-arm: Convert TLS registers
      target-arm: Convert performance monitor registers
      target-arm: Convert generic timer cp15 regs
      target-arm: Convert cp15 c3 register
      target-arm: Convert MMU fault status cp15 registers
      target-arm: Convert cp15 crn=2 registers
      target-arm: Convert cp15 crn=13 registers
      target-arm: Convert cp15 crn=10 registers
      target-arm: Convert cp15 crn=15 registers
      target-arm: Convert cp15 MMU TLB control
      target-arm: Convert cp15 VA-PA translation registers
      target-arm: convert cp15 crn=7 registers
      target-arm: Convert cp15 crn=6 registers
      target-arm: Convert cp15 crn=9 registers
      target-arm: Convert cp15 crn=1 registers
      target-arm: Convert cp15 crn=0 crm={1,2} feature registers
      target-arm: Convert cp15 cache ID registers
      target-arm: Convert MPIDR
      target-arm: Convert final ID registers
      target-arm: Remove c0_cachetype CPUARMState field
      target-arm: Move block cache ops to new cp15 framework
      target-arm: Remove remaining old cp15 infrastructure
      target-arm: Remove ARM_CPUID_* macros

 hw/pxa2xx.c            |  285 +++----
 hw/pxa2xx_pic.c        |   53 +-
 linux-user/cpu-uname.c |    5 +-
 target-arm/cpu-qom.h   |    5 +
 target-arm/cpu.c       |  230 +++++--
 target-arm/cpu.h       |  248 +++++-
 target-arm/helper.c    | 2070 +++++++++++++++++++++++++++---------------------
 target-arm/helper.h    |   11 +-
 target-arm/machine.c   |    2 -
 target-arm/op_helper.c |   42 +-
 target-arm/translate.c |  474 ++++--------
 11 files changed, 1889 insertions(+), 1536 deletions(-)

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-10-08 14:46 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-04 16:21 [Qemu-devel] [PULL 00/33] target-arm queue Peter Maydell
2017-09-04 17:28 ` Peter Maydell
  -- strict thread matches above, loose matches on Subject: below --
2018-10-08 13:59 Peter Maydell
2018-10-08 14:46 ` Peter Maydell
2014-12-11 12:19 Peter Maydell
2014-12-11 18:26 ` Peter Maydell
2012-06-20 12:26 Peter Maydell
2012-06-24 12:27 ` Blue Swirl

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