[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Palmer Dabbelt]

The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:

  ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)

are available in the Git repository at:

  git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1

for you to fetch changes up to 82f014671cf057de51c4a577c9e2ad637dcec6f9:

  target/riscv: update mstatus.SD when FS is set dirty (2020-01-16 10:03:15 -0800)

----------------------------------------------------------------
RISC-V Patches for the 5.0 Soft Freeze, Part 1

This patch set contains a handful of collected fixes that I'd like to target
for the 5.0 soft freeze (I know that's a long way away, I just don't know what
else to call these):

* A fix for a memory leak initializing the sifive_u board.
* Fixes to privilege mode emulation related to interrupts and fstatus.

Notably absent is the H extension implementation.  That's pretty much reviewed,
but not quite ready to go yet and I didn't want to hold back these important
fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
and passes "make check".

----------------------------------------------------------------
Pan Nengyuan (1):
      riscv/sifive_u: fix a memory leak in soc_realize()

ShihPo Hung (3):
      target/riscv: Fix tb->flags FS status
      target/riscv: fsd/fsw doesn't dirty FP state
      target/riscv: update mstatus.SD when FS is set dirty

Yiting Wang (1):
      riscv: Set xPIE to 1 after xRET

 hw/riscv/sifive_u.c                     | 1 +
 target/riscv/cpu.h                      | 5 +----
 target/riscv/csr.c                      | 3 +--
 target/riscv/insn_trans/trans_rvd.inc.c | 1 -
 target/riscv/insn_trans/trans_rvf.inc.c | 1 -
 target/riscv/op_helper.c                | 4 ++--
 target/riscv/translate.c                | 2 +-
 7 files changed, 6 insertions(+), 11 deletions(-)

[PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize()

[Palmer Dabbelt]

From: Pan Nengyuan <pannengyuan@huawei.com>

Fix a minor memory leak in riscv_sifive_u_soc_realize()

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 hw/riscv/sifive_u.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95732..0e12b3ccef 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_U_PLIC_CONTEXT_BASE,
         SIFIVE_U_PLIC_CONTEXT_STRIDE,
         memmap[SIFIVE_U_PLIC].size);
+    g_free(plic_hart_config);
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
-- 
2.25.0.341.g760bfbb309-goog

[PULL 2/5] riscv: Set xPIE to 1 after xRET

[Palmer Dabbelt]

From: Yiting Wang <yiting.wang@windriver.com>

When executing an xRET instruction, supposing xPP holds the
value y, xIE is set to xPIE; the privilege mode is changed to y;
xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.

Signed-off-by: Yiting Wang <yiting.wang@windriver.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 target/riscv/op_helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 331cc36232..e87c9115bc 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -93,7 +93,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
         env->priv_ver >= PRIV_VERSION_1_10_0 ?
         MSTATUS_SIE : MSTATUS_UIE << prev_priv,
         get_field(mstatus, MSTATUS_SPIE));
-    mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
+    mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
     mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
     riscv_cpu_set_mode(env, prev_priv);
     env->mstatus = mstatus;
@@ -118,7 +118,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
         env->priv_ver >= PRIV_VERSION_1_10_0 ?
         MSTATUS_MIE : MSTATUS_UIE << prev_priv,
         get_field(mstatus, MSTATUS_MPIE));
-    mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
+    mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
     mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
     riscv_cpu_set_mode(env, prev_priv);
     env->mstatus = mstatus;
-- 
2.25.0.341.g760bfbb309-goog

[PULL 3/5] target/riscv: Fix tb->flags FS status

[Palmer Dabbelt]

From: ShihPo Hung <shihpo.hung@sifive.com>

It was found that running libquantum on riscv-linux qemu produced an
incorrect result. After investigation, FP registers are not saved
during context switch due to incorrect mstatus.FS.

In current implementation tb->flags merges all non-disabled state to
dirty. This means the code in mark_fs_dirty in translate.c that
handles initial and clean states is unreachable.

This patch fixes it and is successfully tested with:
  libquantum

Thanks to Richard for pointing out the actual bug.

v3: remove the redundant condition
v2: root cause FS problem

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 target/riscv/cpu.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e59343e13c..de0a8d893a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -293,10 +293,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 #ifdef CONFIG_USER_ONLY
     *flags = TB_FLAGS_MSTATUS_FS;
 #else
-    *flags = cpu_mmu_index(env, 0);
-    if (riscv_cpu_fp_enabled(env)) {
-        *flags |= TB_FLAGS_MSTATUS_FS;
-    }
+    *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
 #endif
 }
 
-- 
2.25.0.341.g760bfbb309-goog

[PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state

[Palmer Dabbelt]

From: ShihPo Hung <shihpo.hung@sifive.com>

Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 target/riscv/insn_trans/trans_rvd.inc.c | 1 -
 target/riscv/insn_trans/trans_rvf.inc.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index 393fa0248c..ea1044f13b 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -43,7 +43,6 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
 
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
 
-    mark_fs_dirty(ctx);
     tcg_temp_free(t0);
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 172dbfa919..e23cd639a6 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -52,7 +52,6 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
 
     tcg_temp_free(t0);
-    mark_fs_dirty(ctx);
     return true;
 }
 
-- 
2.25.0.341.g760bfbb309-goog

[PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty

[Palmer Dabbelt]

From: ShihPo Hung <shihpo.hung@sifive.com>

remove the check becuase SD bit should summarize FS and XS fields
unconditionally.

Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 target/riscv/csr.c       | 3 +--
 target/riscv/translate.c | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..0e34c292c5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -341,8 +341,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 
     mstatus = (mstatus & ~mask) | (val & mask);
 
-    dirty = (riscv_cpu_fp_enabled(env) &&
-             ((mstatus & MSTATUS_FS) == MSTATUS_FS)) |
+    dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
     env->mstatus = mstatus;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ab6a891dc3..8e40ed3ac4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -394,7 +394,7 @@ static void mark_fs_dirty(DisasContext *ctx)
 
     tmp = tcg_temp_new();
     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
     tcg_temp_free(tmp);
 }
-- 
2.25.0.341.g760bfbb309-goog

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Peter Maydell]

On Tue, 21 Jan 2020 at 23:41, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
>
>   ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)
>
> are available in the Git repository at:
>
>   git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1
>
> for you to fetch changes up to 82f014671cf057de51c4a577c9e2ad637dcec6f9:
>
>   target/riscv: update mstatus.SD when FS is set dirty (2020-01-16 10:03:15 -0800)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.0 Soft Freeze, Part 1
>
> This patch set contains a handful of collected fixes that I'd like to target
> for the 5.0 soft freeze (I know that's a long way away, I just don't know what
> else to call these):
>
> * A fix for a memory leak initializing the sifive_u board.
> * Fixes to privilege mode emulation related to interrupts and fstatus.
>
> Notably absent is the H extension implementation.  That's pretty much reviewed,
> but not quite ready to go yet and I didn't want to hold back these important
> fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
> and passes "make check".

Hi. This pull request doesn't seem to be signed with the GPG
key that I have on record for you...

thanks
-- PMM

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Peter Maydell]

On Tue, 21 Jan 2020 at 23:41, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
>
>   ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)
>
> are available in the Git repository at:
>
>   git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1
>
> for you to fetch changes up to 82f014671cf057de51c4a577c9e2ad637dcec6f9:
>
>   target/riscv: update mstatus.SD when FS is set dirty (2020-01-16 10:03:15 -0800)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.0 Soft Freeze, Part 1
>
> This patch set contains a handful of collected fixes that I'd like to target
> for the 5.0 soft freeze (I know that's a long way away, I just don't know what
> else to call these):
>
> * A fix for a memory leak initializing the sifive_u board.
> * Fixes to privilege mode emulation related to interrupts and fstatus.
>
> Notably absent is the H extension implementation.  That's pretty much reviewed,
> but not quite ready to go yet and I didn't want to hold back these important
> fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
> and passes "make check".

Hi. This pull request doesn't seem to be signed with the GPG
key that I have on record for you...

thanks
-- PMM

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Palmer Dabbelt]

On Thu, 23 Jan 2020 06:38:07 PST (-0800), Peter Maydell wrote:
> On Tue, 21 Jan 2020 at 23:41, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>>
>> The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
>>
>>   ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)
>>
>> are available in the Git repository at:
>>
>>   git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1
>>
>> for you to fetch changes up to 82f014671cf057de51c4a577c9e2ad637dcec6f9:
>>
>>   target/riscv: update mstatus.SD when FS is set dirty (2020-01-16 10:03:15 -0800)
>>
>> ----------------------------------------------------------------
>> RISC-V Patches for the 5.0 Soft Freeze, Part 1
>>
>> This patch set contains a handful of collected fixes that I'd like to target
>> for the 5.0 soft freeze (I know that's a long way away, I just don't know what
>> else to call these):
>>
>> * A fix for a memory leak initializing the sifive_u board.
>> * Fixes to privilege mode emulation related to interrupts and fstatus.
>>
>> Notably absent is the H extension implementation.  That's pretty much reviewed,
>> but not quite ready to go yet and I didn't want to hold back these important
>> fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
>> and passes "make check".
>
> Hi. This pull request doesn't seem to be signed with the GPG
> key that I have on record for you...

When I moved to Google I got a Yubikey and made new subkeys for it.  If I
understand correctly the new subkeys should be signed by my main key, but maybe
that didn't make it to your keyring?  I see

    $ gpg --list-keys palmer@dabbelt.com
    pub   rsa4096 2017-06-06 [SC] [expires: 2027-11-13]
          00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
    uid           [ultimate] Palmer Dabbelt <palmer@dabbelt.com>
    uid           [ultimate] Palmer Dabbelt <palmerdabbelt@google.com>
    sub   rsa4096 2017-06-06 [E]
    sub   rsa4096 2019-11-26 [S] [expires: 2024-11-24]
    sub   rsa4096 2019-11-26 [A] [expires: 2024-11-24]
    sub   rsa4096 2019-11-26 [E] [expires: 2024-11-24]

I have the master key at home, so if I didn't do this right I can re-spin
things tonight.

>
> thanks
> -- PMM

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Peter Maydell]

On Thu, 23 Jan 2020 at 18:43, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
> On Thu, 23 Jan 2020 06:38:07 PST (-0800), Peter Maydell wrote:
> > Hi. This pull request doesn't seem to be signed with the GPG
> > key that I have on record for you...
>
> When I moved to Google I got a Yubikey and made new subkeys for it.  If I
> understand correctly the new subkeys should be signed by my main key, but maybe
> that didn't make it to your keyring?  I see
>
>     $ gpg --list-keys palmer@dabbelt.com
>     pub   rsa4096 2017-06-06 [SC] [expires: 2027-11-13]
>           00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
>     uid           [ultimate] Palmer Dabbelt <palmer@dabbelt.com>
>     uid           [ultimate] Palmer Dabbelt <palmerdabbelt@google.com>
>     sub   rsa4096 2017-06-06 [E]
>     sub   rsa4096 2019-11-26 [S] [expires: 2024-11-24]
>     sub   rsa4096 2019-11-26 [A] [expires: 2024-11-24]
>     sub   rsa4096 2019-11-26 [E] [expires: 2024-11-24]

Yeah, I have those. I think I must have fumbled something
when I retried the pullreq after doing a refresh of your
gpg key, because I just did a retry now and it's fine.
(I'm just running the pull through my tests now.)

thanks
-- PMM

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Palmer Dabbelt]

On Fri, 24 Jan 2020 04:35:14 PST (-0800), Peter Maydell wrote:
> On Thu, 23 Jan 2020 at 18:43, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>> On Thu, 23 Jan 2020 06:38:07 PST (-0800), Peter Maydell wrote:
>> > Hi. This pull request doesn't seem to be signed with the GPG
>> > key that I have on record for you...
>>
>> When I moved to Google I got a Yubikey and made new subkeys for it.  If I
>> understand correctly the new subkeys should be signed by my main key, but maybe
>> that didn't make it to your keyring?  I see
>>
>>     $ gpg --list-keys palmer@dabbelt.com
>>     pub   rsa4096 2017-06-06 [SC] [expires: 2027-11-13]
>>           00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
>>     uid           [ultimate] Palmer Dabbelt <palmer@dabbelt.com>
>>     uid           [ultimate] Palmer Dabbelt <palmerdabbelt@google.com>
>>     sub   rsa4096 2017-06-06 [E]
>>     sub   rsa4096 2019-11-26 [S] [expires: 2024-11-24]
>>     sub   rsa4096 2019-11-26 [A] [expires: 2024-11-24]
>>     sub   rsa4096 2019-11-26 [E] [expires: 2024-11-24]
>
> Yeah, I have those. I think I must have fumbled something
> when I retried the pullreq after doing a refresh of your
> gpg key, because I just did a retry now and it's fine.
> (I'm just running the pull through my tests now.)

Thanks!

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Peter Maydell]

On Tue, 21 Jan 2020 at 23:41, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
>
>   ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)
>
> are available in the Git repository at:
>
>   git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1
>
> for you to fetch changes up to 82f014671cf057de51c4a577c9e2ad637dcec6f9:
>
>   target/riscv: update mstatus.SD when FS is set dirty (2020-01-16 10:03:15 -0800)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.0 Soft Freeze, Part 1
>
> This patch set contains a handful of collected fixes that I'd like to target
> for the 5.0 soft freeze (I know that's a long way away, I just don't know what
> else to call these):
>
> * A fix for a memory leak initializing the sifive_u board.
> * Fixes to privilege mode emulation related to interrupts and fstatus.
>
> Notably absent is the H extension implementation.  That's pretty much reviewed,
> but not quite ready to go yet and I didn't want to hold back these important
> fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
> and passes "make check".
>
> ----------------------------------------------------------------
> Pan Nengyuan (1):
>       riscv/sifive_u: fix a memory leak in soc_realize()
>
> ShihPo Hung (3):
>       target/riscv: Fix tb->flags FS status
>       target/riscv: fsd/fsw doesn't dirty FP state
>       target/riscv: update mstatus.SD when FS is set dirty
>
> Yiting Wang (1):
>       riscv: Set xPIE to 1 after xRET
>

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM

Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Peter Maydell]

On Tue, 21 Jan 2020 at 23:41, Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
>
>   ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)
>
> are available in the Git repository at:
>
>   git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1
>
> for you to fetch changes up to 82f014671cf057de51c4a577c9e2ad637dcec6f9:
>
>   target/riscv: update mstatus.SD when FS is set dirty (2020-01-16 10:03:15 -0800)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 5.0 Soft Freeze, Part 1
>
> This patch set contains a handful of collected fixes that I'd like to target
> for the 5.0 soft freeze (I know that's a long way away, I just don't know what
> else to call these):
>
> * A fix for a memory leak initializing the sifive_u board.
> * Fixes to privilege mode emulation related to interrupts and fstatus.
>
> Notably absent is the H extension implementation.  That's pretty much reviewed,
> but not quite ready to go yet and I didn't want to hold back these important
> fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
> and passes "make check".
>
> ----------------------------------------------------------------
> Pan Nengyuan (1):
>       riscv/sifive_u: fix a memory leak in soc_realize()
>
> ShihPo Hung (3):
>       target/riscv: Fix tb->flags FS status
>       target/riscv: fsd/fsw doesn't dirty FP state
>       target/riscv: update mstatus.SD when FS is set dirty
>
> Yiting Wang (1):
>       riscv: Set xPIE to 1 after xRET
>

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM