[PULL 0/5] target-arm queue

[PULL 0/5] target-arm queue

[Peter Maydell]

Hi; here's a collection of Arm bug fixes for rc2.

thanks
-- PMM

The following changes since commit a082fab9d259473a9d5d53307cf83b1223301181:

  Merge tag 'pull-ppc-20221117' of https://gitlab.com/danielhb/qemu into staging (2022-11-17 12:39:38 -0500)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221121

for you to fetch changes up to 312b71abce3005ca7294dc0db7d548dc7cc41fbf:

  target/arm: Limit LPA2 effective output address when TCR.DS == 0 (2022-11-21 11:46:46 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/sd: Fix sun4i allwinner-sdhost for U-Boot
 * hw/intc: add implementation of GICD_IIDR to Arm GIC
 * tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
 * target/arm: Limit LPA2 effective output address when TCR.DS == 0

----------------------------------------------------------------
Alex Bennée (2):
      hw/intc: clean-up access to GIC multi-byte registers
      hw/intc: add implementation of GICD_IIDR to Arm GIC

Ard Biesheuvel (1):
      target/arm: Limit LPA2 effective output address when TCR.DS == 0

Peter Maydell (1):
      tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s

Strahinja Jankovic (1):
      hw/sd: Fix sun4i allwinner-sdhost for U-Boot

 include/hw/sd/allwinner-sdhost.h |  1 +
 hw/intc/arm_gic.c                | 28 ++++++++++++-----
 hw/sd/allwinner-sdhost.c         | 67 +++++++++++++++++++++++++++-------------
 target/arm/ptw.c                 |  8 +++++
 tests/avocado/boot_linux.py      |  2 +-
 5 files changed, 77 insertions(+), 29 deletions(-)

[PULL 1/5] hw/sd: Fix sun4i allwinner-sdhost for U-Boot

[Peter Maydell]

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot
access SD card. The problem is that FIFO register in current
allwinner-sdhost implementation is at the address corresponding to
Allwinner H3, but not A10.
Linux kernel is not affected since Linux driver uses DMA access and does
not use FIFO register for reading/writing.

This patch adds new class parameter `is_sun4i` and based on that
parameter uses register at offset 0x100 either as FIFO register (if
sun4i) or as threshold register (if not sun4i; in this case register at
0x200 is FIFO register).

Tested with U-Boot and Linux kernel image built for Cubieboard and
OrangePi PC.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221112214900.24152-1-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/sd/allwinner-sdhost.h |  1 +
 hw/sd/allwinner-sdhost.c         | 67 ++++++++++++++++++++++----------
 2 files changed, 47 insertions(+), 21 deletions(-)

diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
index bfe08ff4ef2..30c1e604041 100644
--- a/include/hw/sd/allwinner-sdhost.h
+++ b/include/hw/sd/allwinner-sdhost.h
@@ -130,6 +130,7 @@ struct AwSdHostClass {
 
     /** Maximum buffer size in bytes per DMA descriptor */
     size_t max_desc_size;
+    bool   is_sun4i;
 
 };
 
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
index 455d6eabf64..51e5e908307 100644
--- a/hw/sd/allwinner-sdhost.c
+++ b/hw/sd/allwinner-sdhost.c
@@ -65,7 +65,7 @@ enum {
     REG_SD_DLBA       = 0x84,  /* Descriptor List Base Address */
     REG_SD_IDST       = 0x88,  /* Internal DMA Controller Status */
     REG_SD_IDIE       = 0x8C,  /* Internal DMA Controller IRQ Enable */
-    REG_SD_THLDC      = 0x100, /* Card Threshold Control */
+    REG_SD_THLDC      = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
     REG_SD_DSBD       = 0x10C, /* eMMC DDR Start Bit Detection Control */
     REG_SD_RES_CRC    = 0x110, /* Response CRC from card/eMMC */
     REG_SD_DATA7_CRC  = 0x114, /* CRC Data 7 from card/eMMC */
@@ -415,10 +415,29 @@ static void allwinner_sdhost_dma(AwSdHostState *s)
     }
 }
 
+static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
+{
+    uint32_t res = 0;
+
+    if (sdbus_data_ready(&s->sdbus)) {
+        sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
+        le32_to_cpus(&res);
+        allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
+        allwinner_sdhost_auto_stop(s);
+        allwinner_sdhost_update_irq(s);
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
+                      __func__);
+    }
+
+    return res;
+}
+
 static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
                                       unsigned size)
 {
     AwSdHostState *s = AW_SDHOST(opaque);
+    AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
     uint32_t res = 0;
 
     switch (offset) {
@@ -508,8 +527,12 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
     case REG_SD_IDIE:      /* Internal DMA Controller Interrupt Enable */
         res = s->dmac_irq;
         break;
-    case REG_SD_THLDC:     /* Card Threshold Control */
-        res = s->card_threshold;
+    case REG_SD_THLDC:     /* Card Threshold Control or FIFO register (sun4i) */
+        if (sc->is_sun4i) {
+            res = allwinner_sdhost_fifo_read(s);
+        } else {
+            res = s->card_threshold;
+        }
         break;
     case REG_SD_DSBD:      /* eMMC DDR Start Bit Detection Control */
         res = s->startbit_detect;
@@ -531,16 +554,7 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
         res = s->status_crc;
         break;
     case REG_SD_FIFO:      /* Read/Write FIFO */
-        if (sdbus_data_ready(&s->sdbus)) {
-            sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
-            le32_to_cpus(&res);
-            allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
-            allwinner_sdhost_auto_stop(s);
-            allwinner_sdhost_update_irq(s);
-        } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
-                          __func__);
-        }
+        res = allwinner_sdhost_fifo_read(s);
         break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
@@ -553,11 +567,20 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
     return res;
 }
 
+static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
+{
+    uint32_t u32 = cpu_to_le32(value);
+    sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
+    allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
+    allwinner_sdhost_auto_stop(s);
+    allwinner_sdhost_update_irq(s);
+}
+
 static void allwinner_sdhost_write(void *opaque, hwaddr offset,
                                    uint64_t value, unsigned size)
 {
     AwSdHostState *s = AW_SDHOST(opaque);
-    uint32_t u32;
+    AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
 
     trace_allwinner_sdhost_write(offset, value, size);
 
@@ -657,18 +680,18 @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
         s->dmac_irq = value;
         allwinner_sdhost_update_irq(s);
         break;
-    case REG_SD_THLDC:     /* Card Threshold Control */
-        s->card_threshold = value;
+    case REG_SD_THLDC:     /* Card Threshold Control or FIFO (sun4i) */
+        if (sc->is_sun4i) {
+            allwinner_sdhost_fifo_write(s, value);
+        } else {
+            s->card_threshold = value;
+        }
         break;
     case REG_SD_DSBD:      /* eMMC DDR Start Bit Detection Control */
         s->startbit_detect = value;
         break;
     case REG_SD_FIFO:      /* Read/Write FIFO */
-        u32 = cpu_to_le32(value);
-        sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
-        allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
-        allwinner_sdhost_auto_stop(s);
-        allwinner_sdhost_update_irq(s);
+        allwinner_sdhost_fifo_write(s, value);
         break;
     case REG_SD_RES_CRC:   /* Response CRC from card/eMMC */
     case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
@@ -834,12 +857,14 @@ static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
 {
     AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
     sc->max_desc_size = 8 * KiB;
+    sc->is_sun4i = true;
 }
 
 static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
 {
     AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
     sc->max_desc_size = 64 * KiB;
+    sc->is_sun4i = false;
 }
 
 static const TypeInfo allwinner_sdhost_info = {
-- 
2.25.1

[PULL 2/5] hw/intc: clean-up access to GIC multi-byte registers

[Peter Maydell]

From: Alex Bennée <alex.bennee@linaro.org>

gic_dist_readb was returning a word value which just happened to work
as a result of the way we OR the data together. Lets fix it so only
the explicit byte is returned for each part of GICD_TYPER. I've
changed the return type to uint8_t although the overflow is only
detected with an explicit -Wconversion.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 492b2421ab4..1a04144c38b 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -941,7 +941,7 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
     gic_update(s);
 }
 
-static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
+static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
 {
     GICState *s = (GICState *)opaque;
     uint32_t res;
@@ -955,6 +955,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
     cm = 1 << cpu;
     if (offset < 0x100) {
         if (offset == 0) {      /* GICD_CTLR */
+            /* We rely here on the only non-zero bits being in byte 0 */
             if (s->security_extn && !attrs.secure) {
                 /* The NS bank of this register is just an alias of the
                  * EnableGrp1 bit in the S bank version.
@@ -964,11 +965,14 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
                 return s->ctlr;
             }
         }
-        if (offset == 4)
-            /* Interrupt Controller Type Register */
-            return ((s->num_irq / 32) - 1)
-                    | ((s->num_cpu - 1) << 5)
-                    | (s->security_extn << 10);
+        if (offset == 4) {
+            /* GICD_TYPER byte 0 */
+            return ((s->num_irq / 32) - 1) | ((s->num_cpu - 1) << 5);
+        }
+        if (offset == 5) {
+            /* GICD_TYPER byte 1 */
+            return (s->security_extn << 2);
+        }
         if (offset < 0x08)
             return 0;
         if (offset >= 0x80) {
-- 
2.25.1

[PULL 3/5] hw/intc: add implementation of GICD_IIDR to Arm GIC

[Peter Maydell]

From: Alex Bennée <alex.bennee@linaro.org>

a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
this for the CPU interface register. The fact we don't implement it
shows up when running Xen with -d guest_error which is definitely
wrong because the guest is perfectly entitled to read it.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1a04144c38b..7a34bc0998a 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -973,8 +973,18 @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
             /* GICD_TYPER byte 1 */
             return (s->security_extn << 2);
         }
-        if (offset < 0x08)
+        if (offset == 8) {
+            /* GICD_IIDR byte 0 */
+            return 0x3b; /* Arm JEP106 identity */
+        }
+        if (offset == 9) {
+            /* GICD_IIDR byte 1 */
+            return 0x04; /* Arm JEP106 identity */
+        }
+        if (offset < 0x0c) {
+            /* All other bytes in this range are RAZ */
             return 0;
+        }
         if (offset >= 0x80) {
             /* Interrupt Group Registers: these RAZ/WI if this is an NS
              * access to a GIC with the security extensions, or if the GIC
-- 
2.25.1

[PULL 4/5] tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s

[Peter Maydell]

The two tests
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3

take quite a long time to run, and the current timeout of 240s
is not enough for the tests to complete on slow machines:
we've seen these tests time out in the gitlab CI in the
'avocado-system-alpine' CI job, for instance. The timeout
is also insufficient for running the test with a debug build
of QEMU: on my machine the tests take over 10 minutes to run
in that config.

Push the timeout up to 720s so that the test definitely has
enough time to complete.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 tests/avocado/boot_linux.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index 571d33882ae..32adae6ff6a 100644
--- a/tests/avocado/boot_linux.py
+++ b/tests/avocado/boot_linux.py
@@ -64,7 +64,7 @@ class BootLinuxAarch64(LinuxTest):
     :avocado: tags=machine:virt
     :avocado: tags=machine:gic-version=2
     """
-    timeout = 240
+    timeout = 720
 
     def add_common_args(self):
         self.vm.add_args('-bios',
-- 
2.25.1

[PULL 5/5] target/arm: Limit LPA2 effective output address when TCR.DS == 0

[Peter Maydell]

From: Ard Biesheuvel <ardb@kernel.org>

With LPA2, the effective output address size is at most 48 bits when
TCR.DS == 0. This case is currently unhandled in the page table walker,
where we happily assume LVA/64k granule when outputsize > 48 and
param.ds == 0, resulting in the wrong conversion to be used from a
page table descriptor to a physical address.

    if (outputsize > 48) {
        if (param.ds) {
            descaddr |= extract64(descriptor, 8, 2) << 50;
        } else {
            descaddr |= extract64(descriptor, 12, 4) << 48;
        }

So cap the outputsize to 48 when TCR.DS is cleared, as per the
architecture.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221116170316.259695-1-ardb@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3745ac97234..9a6277d862f 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1222,6 +1222,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
         ps = MIN(ps, param.ps);
         assert(ps < ARRAY_SIZE(pamax_map));
         outputsize = pamax_map[ps];
+
+        /*
+         * With LPA2, the effective output address (OA) size is at most 48 bits
+         * unless TCR.DS == 1
+         */
+        if (!param.ds && param.gran != Gran64K) {
+            outputsize = MIN(outputsize, 48);
+        }
     } else {
         param = aa32_va_parameters(env, address, mmu_idx);
         level = 1;
-- 
2.25.1

Re: [PULL 0/5] target-arm queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 115 bytes --]

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PULL 0/5] target-arm queue

[Peter Maydell]

On Mon, 21 Nov 2022 at 15:54, Stefan Hajnoczi <stefanha@redhat.com> wrote:
>
> Applied, thanks.

This doesn't seem to have reached https://gitlab.com/qemu-project/qemu.git:
did something go wrong?

thanks
-- PMM

Re: [PULL 0/5] target-arm queue

[Stefan Hajnoczi]

On Mon, 21 Nov 2022 at 16:11, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 21 Nov 2022 at 15:54, Stefan Hajnoczi <stefanha@redhat.com> wrote:
> >
> > Applied, thanks.
>
> This doesn't seem to have reached https://gitlab.com/qemu-project/qemu.git:
> did something go wrong?

I forgot to push staging to master. Thanks for letting me know!

Stefan

Re: [PULL 0/5] target-arm queue

[Peter Maydell]

On Tue, 2 Apr 2024 at 11:29, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Nothing exciting here: two minor bug fixes, some fixes for
> running on a 32-bit host, and a docs tweak.
>
> thanks
> -- PMM
>
> The following changes since commit 6af9d12c88b9720f209912f6e4b01fefe5906d59:
>
>   Merge tag 'migration-20240331-pull-request' of https://gitlab.com/peterx/qemu into staging (2024-04-01 13:12:40 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240402
>
> for you to fetch changes up to 393770d7a02135e7468018f52da610712f151ec0:
>
>   raspi4b: Reduce RAM to 1Gb on 32-bit hosts (2024-04-02 10:13:48 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * take HSTR traps of cp15 accesses to EL2, not EL1
>  * docs: sbsa: update specs, add dt note
>  * hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
>  * tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
>  * raspi4b: Reduce RAM to 1Gb on 32-bit hosts


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.

-- PMM

[PULL 0/5] target-arm queue

[Peter Maydell]

Nothing exciting here: two minor bug fixes, some fixes for
running on a 32-bit host, and a docs tweak.

thanks
-- PMM

The following changes since commit 6af9d12c88b9720f209912f6e4b01fefe5906d59:

  Merge tag 'migration-20240331-pull-request' of https://gitlab.com/peterx/qemu into staging (2024-04-01 13:12:40 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240402

for you to fetch changes up to 393770d7a02135e7468018f52da610712f151ec0:

  raspi4b: Reduce RAM to 1Gb on 32-bit hosts (2024-04-02 10:13:48 +0100)

----------------------------------------------------------------
target-arm queue:
 * take HSTR traps of cp15 accesses to EL2, not EL1
 * docs: sbsa: update specs, add dt note
 * hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
 * tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
 * raspi4b: Reduce RAM to 1Gb on 32-bit hosts

----------------------------------------------------------------
Cédric Le Goater (2):
      tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
      raspi4b: Reduce RAM to 1Gb on 32-bit hosts

Marcin Juszkiewicz (1):
      docs: sbsa: update specs, add dt note

Peter Maydell (2):
      target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
      hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled

 docs/system/arm/sbsa.rst          | 35 +++++++++++++++++------
 hw/arm/raspi4b.c                  |  4 +++
 hw/intc/arm_gicv3_cpuif.c         |  4 +--
 target/arm/tcg/translate.c        |  2 +-
 tests/qtest/stm32l4x5_gpio-test.c | 59 +++++++++++++++++++++++----------------
 5 files changed, 68 insertions(+), 36 deletions(-)

Re: [PULL 0/5] target-arm queue

[Peter Maydell]

On Tue, 25 Jul 2023 at 11:25, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> target-arm queue: just bugfixes, mostly mine.
>
> thanks
> -- PMM
>
> The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d:
>
>   Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725
>
> for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5:
>
>   tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * tests/decode: Suppress "error: " string for expected-failure tests
>  * ui/curses: For curses display, recognize a few more control keys
>  * target/arm: Special case M-profile in debug_helper.c code
>  * scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
>  * hw/arm/smmu: Handle big-endian hosts correctly
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.1
for any user-visible changes.

-- PMM

[PULL 0/5] target-arm queue

[Peter Maydell]

target-arm queue: just bugfixes, mostly mine.

thanks
-- PMM

The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d:

  Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725

for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5:

  tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100)

----------------------------------------------------------------
target-arm queue:
 * tests/decode: Suppress "error: " string for expected-failure tests
 * ui/curses: For curses display, recognize a few more control keys
 * target/arm: Special case M-profile in debug_helper.c code
 * scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
 * hw/arm/smmu: Handle big-endian hosts correctly

----------------------------------------------------------------
Peter Maydell (4):
      hw/arm/smmu: Handle big-endian hosts correctly
      scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
      target/arm: Special case M-profile in debug_helper.c code
      tests/decode: Suppress "error: " string for expected-failure tests

Sean Estabrooks (1):
      For curses display, recognize a few more control keys

 ui/curses_keys.h          |  6 ++++++
 hw/arm/smmu-common.c      |  3 +--
 hw/arm/smmuv3.c           | 39 +++++++++++++++++++++++++++++++--------
 target/arm/debug_helper.c | 18 ++++++++++++------
 scripts/decodetree.py     |  6 +++++-
 scripts/git-submodule.sh  |  2 +-
 6 files changed, 56 insertions(+), 18 deletions(-)

Re: [PULL 0/5] target-arm queue

[Richard Henderson]

On 8/12/22 04:45, Peter Maydell wrote:
> This pullreq has:
>   * two arm bug fixes which fix some "Linux fails to boot" bugs
>   * a docs typo-fixing patch
>   * a couple of compile failure/warning issues
> 
> I think they're all pretty safe and worth having in rc3.
> 
> thanks
> -- PMM
> 
> The following changes since commit a6b1c53e79d08a99a28cc3e67a3e1a7c34102d6b:
> 
>    Merge tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-08-10 10:26:57 -0700)
> 
> are available in the Git repository at:
> 
>    https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220812
> 
> for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65:
> 
>    cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100)
> 
> ----------------------------------------------------------------
> target-arm queue:
>   * Don't report Statistical Profiling Extension in ID registers
>   * virt ACPI tables: Present the GICR structure properly for GICv4
>   * Fix some typos in documentation
>   * tests/unit: fix a -Wformat-truncation warning
>   * cutils: Add missing dyld(3) include on macOS

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.


r~


> 
> ----------------------------------------------------------------
> Marc-André Lureau (1):
>        tests/unit: fix a -Wformat-truncation warning
> 
> Peter Maydell (1):
>        target/arm: Don't report Statistical Profiling Extension in ID registers
> 
> Philippe Mathieu-Daudé (1):
>        cutils: Add missing dyld(3) include on macOS
> 
> Stefan Weil (1):
>        Fix some typos in documentation (most of them found by codespell)
> 
> Zenghui Yu (1):
>        hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4
> 
>   docs/about/deprecated.rst               |  2 +-
>   docs/specs/acpi_erst.rst                |  4 ++--
>   docs/system/devices/canokey.rst         |  8 ++++----
>   docs/system/devices/cxl.rst             | 12 ++++++------
>   hw/arm/virt-acpi-build.c                |  4 ++--
>   target/arm/cpu.c                        | 11 +++++++++++
>   tests/unit/test-qobject-input-visitor.c |  3 +--
>   util/cutils.c                           |  4 ++++
>   util/oslib-posix.c                      |  4 ----
>   9 files changed, 31 insertions(+), 21 deletions(-)
> 

[PULL 0/5] target-arm queue

[Peter Maydell]

This pullreq has:
 * two arm bug fixes which fix some "Linux fails to boot" bugs
 * a docs typo-fixing patch
 * a couple of compile failure/warning issues

I think they're all pretty safe and worth having in rc3.

thanks
-- PMM

The following changes since commit a6b1c53e79d08a99a28cc3e67a3e1a7c34102d6b:

  Merge tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-08-10 10:26:57 -0700)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220812

for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65:

  cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100)

----------------------------------------------------------------
target-arm queue:
 * Don't report Statistical Profiling Extension in ID registers
 * virt ACPI tables: Present the GICR structure properly for GICv4
 * Fix some typos in documentation
 * tests/unit: fix a -Wformat-truncation warning
 * cutils: Add missing dyld(3) include on macOS

----------------------------------------------------------------
Marc-André Lureau (1):
      tests/unit: fix a -Wformat-truncation warning

Peter Maydell (1):
      target/arm: Don't report Statistical Profiling Extension in ID registers

Philippe Mathieu-Daudé (1):
      cutils: Add missing dyld(3) include on macOS

Stefan Weil (1):
      Fix some typos in documentation (most of them found by codespell)

Zenghui Yu (1):
      hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4

 docs/about/deprecated.rst               |  2 +-
 docs/specs/acpi_erst.rst                |  4 ++--
 docs/system/devices/canokey.rst         |  8 ++++----
 docs/system/devices/cxl.rst             | 12 ++++++------
 hw/arm/virt-acpi-build.c                |  4 ++--
 target/arm/cpu.c                        | 11 +++++++++++
 tests/unit/test-qobject-input-visitor.c |  3 +--
 util/cutils.c                           |  4 ++++
 util/oslib-posix.c                      |  4 ----
 9 files changed, 31 insertions(+), 21 deletions(-)

Re: [PULL 0/5] target-arm queue

[Richard Henderson]

On 11/29/21 11:39 AM, Peter Maydell wrote:
> Hi; this is a collection of mostly GIC related patches for rc3.
> The "Update cached state after LPI state changes" fix is important
> and fixes what would otherwise be a regression since we enable the
> ITS by default in the virt board now. The others are not regressions
> but I think are OK for rc3 as they're fairly self contained (and two
> of them are fixes to new-in-6.2 functionality).
> 
> thanks
> -- PMM
> 
> The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a:
> 
>    Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100)
> 
> are available in the Git repository at:
> 
>    https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211129
> 
> for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9:
> 
>    hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29 10:10:21 +0000)
> 
> ----------------------------------------------------------------
> target-arm queue:
>   * virt: Diagnose attempts to enable MTE or virt when using HVF accelerator
>   * GICv3 ITS: Allow clearing of ITS CTLR Enabled bit
>   * GICv3: Update cached state after LPI state changes
>   * GICv3: Fix handling of LPIs in list registers
> 
> ----------------------------------------------------------------
> Alexander Graf (1):
>        hw/arm/virt: Extend nested and mte checks to hvf
> 
> Peter Maydell (3):
>        hw/intc/arm_gicv3: Update cached state after LPI state changes
>        hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
>        hw/intc/arm_gicv3: fix handling of LPIs in list registers
> 
> Shashi Mallela (1):
>        hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
> 
>   hw/intc/gicv3_internal.h   | 30 ++++++++++++++++++++++++++++++
>   hw/arm/virt.c              | 15 +++++++++------
>   hw/intc/arm_gicv3.c        |  6 ++++--
>   hw/intc/arm_gicv3_cpuif.c  |  9 ++++-----
>   hw/intc/arm_gicv3_its.c    |  7 ++++---
>   hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
>   6 files changed, 61 insertions(+), 20 deletions(-)

Applied, thanks.


r~

[PULL 0/5] target-arm queue

[Peter Maydell]

Hi; this is a collection of mostly GIC related patches for rc3.
The "Update cached state after LPI state changes" fix is important
and fixes what would otherwise be a regression since we enable the
ITS by default in the virt board now. The others are not regressions
but I think are OK for rc3 as they're fairly self contained (and two
of them are fixes to new-in-6.2 functionality).

thanks
-- PMM

The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a:

  Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211129

for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9:

  hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29 10:10:21 +0000)

----------------------------------------------------------------
target-arm queue:
 * virt: Diagnose attempts to enable MTE or virt when using HVF accelerator
 * GICv3 ITS: Allow clearing of ITS CTLR Enabled bit
 * GICv3: Update cached state after LPI state changes
 * GICv3: Fix handling of LPIs in list registers

----------------------------------------------------------------
Alexander Graf (1):
      hw/arm/virt: Extend nested and mte checks to hvf

Peter Maydell (3):
      hw/intc/arm_gicv3: Update cached state after LPI state changes
      hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
      hw/intc/arm_gicv3: fix handling of LPIs in list registers

Shashi Mallela (1):
      hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit

 hw/intc/gicv3_internal.h   | 30 ++++++++++++++++++++++++++++++
 hw/arm/virt.c              | 15 +++++++++------
 hw/intc/arm_gicv3.c        |  6 ++++--
 hw/intc/arm_gicv3_cpuif.c  |  9 ++++-----
 hw/intc/arm_gicv3_its.c    |  7 ++++---
 hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
 6 files changed, 61 insertions(+), 20 deletions(-)

Re: [PULL 0/5] target-arm queue

[Peter Maydell]

On Mon, 12 Apr 2021 at 11:31, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Handful of arm fixes for the rc.
>
> The following changes since commit 555249a59e9cdd6b58da103aba5cf3a2d45c899f:
>
>   Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-04-10 16:58:56 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210412
>
> for you to fetch changes up to 52c01ada86611136e3122dd139788dbcbc292d86:
>
>   exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 (2021-04-12 11:06:24 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
>  * hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
>  * accel/tcg: Preserve PAGE_ANON when changing page permissions
>  * target/arm: Check PAGE_WRITE_ORG for MTE writeability
>  * exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

Re: [PULL 0/5] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/20210412103152.28433-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210412103152.28433-1-peter.maydell@linaro.org
Subject: [PULL 0/5] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20210412103152.28433-1-peter.maydell@linaro.org -> patchew/20210412103152.28433-1-peter.maydell@linaro.org
Switched to a new branch 'test'
b54ded2 exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
5f7d9e7 target/arm: Check PAGE_WRITE_ORG for MTE writeability
a3fb10e accel/tcg: Preserve PAGE_ANON when changing page permissions
435ceeb hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
21190f3 hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts

=== OUTPUT BEGIN ===
1/5 Checking commit 21190f31d420 (hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts)
2/5 Checking commit 435ceeb0c89a (hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs)
3/5 Checking commit a3fb10ec0d23 (accel/tcg: Preserve PAGE_ANON when changing page permissions)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#69: 
new file mode 100644

ERROR: "foo * bar" should be "foo *bar"
#126: FILE: tests/tcg/aarch64/mte.h:51:
+static void * alloc_mte_mem(size_t size) __attribute__((unused));

ERROR: "foo * bar" should be "foo *bar"
#127: FILE: tests/tcg/aarch64/mte.h:52:
+static void * alloc_mte_mem(size_t size)

total: 2 errors, 1 warnings, 84 lines checked

Patch 3/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/5 Checking commit 5f7d9e72dc1b (target/arm: Check PAGE_WRITE_ORG for MTE writeability)
WARNING: line over 80 characters
#30: FILE: target/arm/mte_helper.c:86:
+    if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) {

total: 0 errors, 1 warnings, 8 lines checked

Patch 4/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/5 Checking commit b54ded2ab9fb (exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210412103152.28433-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

[PULL 0/5] target-arm queue

[Peter Maydell]

Handful of arm fixes for the rc.

The following changes since commit 555249a59e9cdd6b58da103aba5cf3a2d45c899f:

  Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-04-10 16:58:56 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210412

for you to fetch changes up to 52c01ada86611136e3122dd139788dbcbc292d86:

  exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 (2021-04-12 11:06:24 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
 * hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
 * accel/tcg: Preserve PAGE_ANON when changing page permissions
 * target/arm: Check PAGE_WRITE_ORG for MTE writeability
 * exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1

----------------------------------------------------------------
Richard Henderson (3):
      accel/tcg: Preserve PAGE_ANON when changing page permissions
      target/arm: Check PAGE_WRITE_ORG for MTE writeability
      exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1

Zenghui Yu (2):
      hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
      hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs

 include/exec/cpu-all.h            |  4 ++--
 tests/tcg/aarch64/mte.h           |  3 ++-
 accel/tcg/translate-all.c         |  9 ++++++--
 hw/arm/smmuv3.c                   | 12 +++++++----
 hw/arm/virt-acpi-build.c          |  4 ++--
 target/arm/mte_helper.c           |  2 +-
 tests/tcg/aarch64/mte-6.c         | 43 +++++++++++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  2 +-
 8 files changed, 66 insertions(+), 13 deletions(-)
 create mode 100644 tests/tcg/aarch64/mte-6.c

Re: [PULL 0/5] target-arm queue

[Peter Maydell]

On Tue, 30 Mar 2021 at 14:25, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit 7993b0f83fe5c3f8555e79781d5d098f99751a94:
>
>   Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-for-6.0-pull-request' into staging (2021-03-29 18:45:12 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20210330
>
> for you to fetch changes up to b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1:
>
>   hw/timer/renesas_tmr: Add default-case asserts in read_tcnt() (2021-03-30 14:05:34 +0100)
>
> ----------------------------------------------------------------
>  * net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
>  * hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
>  * hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
>  * target/arm: Make number of counters in PMCR follow the CPU
>  * hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

[PULL 0/5] target-arm queue

[Peter Maydell]

The following changes since commit 7993b0f83fe5c3f8555e79781d5d098f99751a94:

  Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-for-6.0-pull-request' into staging (2021-03-29 18:45:12 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20210330

for you to fetch changes up to b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1:

  hw/timer/renesas_tmr: Add default-case asserts in read_tcnt() (2021-03-30 14:05:34 +0100)

----------------------------------------------------------------
 * net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
 * hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
 * hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
 * target/arm: Make number of counters in PMCR follow the CPU
 * hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()

----------------------------------------------------------------
Doug Evans (1):
      net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set

Peter Maydell (2):
      target/arm: Make number of counters in PMCR follow the CPU
      hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()

Philippe Mathieu-Daudé (1):
      hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()

Zenghui Yu (1):
      hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()

 hw/arm/smmuv3-internal.h       |  7 -------
 target/arm/cpu.h               |  1 +
 hw/display/xlnx_dp.c           |  9 +++++++++
 hw/net/npcm7xx_emc.c           |  4 +++-
 hw/timer/renesas_tmr.c         |  4 ++++
 target/arm/cpu64.c             |  3 +++
 target/arm/cpu_tcg.c           |  5 +++++
 target/arm/helper.c            | 29 +++++++++++++++++------------
 target/arm/kvm64.c             |  2 ++
 tests/qtest/npcm7xx_emc-test.c | 30 +++++++++++++++++++++---------
 10 files changed, 65 insertions(+), 29 deletions(-)

Re: [PULL 0/5] target-arm queue

[Peter Maydell]

On Mon, 23 Mar 2020 at 17:40, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Just a few minor bugfixes, but we might as well get them in
> for rc0 tomorrow.
>
> -- PMM
>
> The following changes since commit 787f82407c5056a8b1097e39e53d01dd1abe406b:
>
>   Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200323' into staging (2020-03-23 15:38:30 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200323
>
> for you to fetch changes up to 550a04893c2bd4442211b353680b9a6408d94dba:
>
>   target/arm: Move computation of index in handle_simd_dupe (2020-03-23 17:22:30 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * target/arm: avoid undefined behaviour shift in watchpoint code
>  * target/arm: avoid undefined behaviour shift in handle_simd_dupe()
>  * target/arm: add assert that immh != 0 in disas_simd_shift_imm()
>  * aspeed/smc: Fix DMA support for AST2600
>  * hw/arm/bcm283x: Correct the license text ('and' vs 'or')


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM

[PULL 0/5] target-arm queue

[Peter Maydell]

Just a few minor bugfixes, but we might as well get them in
for rc0 tomorrow.

-- PMM

The following changes since commit 787f82407c5056a8b1097e39e53d01dd1abe406b:

  Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200323' into staging (2020-03-23 15:38:30 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200323

for you to fetch changes up to 550a04893c2bd4442211b353680b9a6408d94dba:

  target/arm: Move computation of index in handle_simd_dupe (2020-03-23 17:22:30 +0000)

----------------------------------------------------------------
target-arm queue:
 * target/arm: avoid undefined behaviour shift in watchpoint code
 * target/arm: avoid undefined behaviour shift in handle_simd_dupe()
 * target/arm: add assert that immh != 0 in disas_simd_shift_imm()
 * aspeed/smc: Fix DMA support for AST2600
 * hw/arm/bcm283x: Correct the license text ('and' vs 'or')

----------------------------------------------------------------
Cédric Le Goater (1):
      aspeed/smc: Fix DMA support for AST2600

Philippe Mathieu-Daudé (1):
      hw/arm/bcm283x: Correct the license text

Richard Henderson (3):
      target/arm: Rearrange disabled check for watchpoints
      target/arm: Assert immh != 0 in disas_simd_shift_imm
      target/arm: Move computation of index in handle_simd_dupe

 include/hw/arm/bcm2835_peripherals.h |  3 ++-
 include/hw/arm/bcm2836.h             |  3 ++-
 include/hw/char/bcm2835_aux.h        |  3 ++-
 include/hw/display/bcm2835_fb.h      |  3 ++-
 include/hw/dma/bcm2835_dma.h         |  4 +++-
 include/hw/intc/bcm2835_ic.h         |  4 +++-
 include/hw/intc/bcm2836_control.h    |  3 ++-
 include/hw/misc/bcm2835_mbox.h       |  4 +++-
 include/hw/misc/bcm2835_mbox_defs.h  |  4 +++-
 include/hw/misc/bcm2835_property.h   |  4 +++-
 hw/arm/aspeed_ast2600.c              |  6 ++++++
 hw/arm/bcm2835_peripherals.c         |  3 ++-
 hw/arm/bcm2836.c                     |  3 ++-
 hw/arm/raspi.c                       |  3 ++-
 hw/display/bcm2835_fb.c              |  1 -
 hw/dma/bcm2835_dma.c                 |  4 +++-
 hw/intc/bcm2835_ic.c                 |  4 ++--
 hw/intc/bcm2836_control.c            |  4 +++-
 hw/misc/bcm2835_mbox.c               |  4 +++-
 hw/misc/bcm2835_property.c           |  4 +++-
 hw/ssi/aspeed_smc.c                  | 15 +++++++++++++--
 target/arm/helper.c                  | 11 ++++++-----
 target/arm/translate-a64.c           |  6 +++++-
 hw/ssi/trace-events                  |  1 +
 24 files changed, 76 insertions(+), 28 deletions(-)