* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2015-09-04 15:05 Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 01/27] arm: Use g_new() & friends where that makes obvious sense Peter Maydell
` (27 more replies)
0 siblings, 28 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
Another target-arm queue flush. I expect there'll be another
lot next week...
The following changes since commit b041066421e8dcc7d080dfcfd83551c9c9f24ade:
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging (2015-09-03 16:17:28 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150904
for you to fetch changes up to d9fd6f3874a326033a446a6db8cd113bf4015e6a:
arm/virt: Add full-sized CPU affinity handling (2015-09-04 15:49:54 +0100)
----------------------------------------------------------------
target-arm queue:
* cleanup to use g_new() and friends
* support semihosting in A64
* add SMBIOS support to mach-virt
* remove hw_error() usages
* fix bug in the AArch32:AArch64 register mapping
* add a second PCI memory window in highmem on virt board
* fix bug in arm_excp_unmasked()
* add i.MX31 SoC
* remove restriction on handling affinity values in virt board
----------------------------------------------------------------
Christopher Covington (1):
target-arm: Improve semihosting debug prints
Jean-Christophe Dubois (8):
i.MX: Add SOC support for i.MX31
i.MX: KZM: use standalone i.MX31 SOC support
i.MX: Add I2C controller emulator
i.MX: Add FEC Ethernet Emulator
i.MX: Add SOC support for i.MX25
i.MX: Add the i.MX25 PDK platform
i.MX: Add qtest support for I2C device emulator.
i.MX: Add i2C devices to i.MX31 SOC
Markus Armbruster (1):
arm: Use g_new() & friends where that makes obvious sense
Pavel Fedin (3):
hw/arm/virt: Add high MMIO PCI region, 512G in size
target-arm: Refactor CPU affinity handling
arm/virt: Add full-sized CPU affinity handling
Peter Crosthwaite (2):
arm: cpu: assert() on no-EL2 virt IRQ error condition.
arm: Remove hw_error() usages.
Peter Maydell (8):
target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
gdbstub: Implement gdb_do_syscallv()
target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
include/exec/softmmu-semi.h: Add support for 64-bit values
target-arm/arm-semi.c: Support widening APIs to 64 bits
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
Sergey Sorokin (2):
target-arm: Fix AArch32:AArch64 general-purpose register mapping
target-arm: Fix arm_excp_unmasked() function
Wei Huang (2):
smbios: add smbios 3.0 support
smbios: implement smbios support for mach-virt
default-configs/arm-softmmu.mak | 7 +
gdbstub.c | 14 +-
hw/arm/Makefile.objs | 4 +-
hw/arm/fsl-imx25.c | 273 +++++++++++++++
hw/arm/fsl-imx31.c | 246 ++++++++++++++
hw/arm/imx25_pdk.c | 159 +++++++++
hw/arm/kzm.c | 205 ++++++-----
hw/arm/omap1.c | 30 +-
hw/arm/omap2.c | 15 +-
hw/arm/pxa2xx.c | 11 +-
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/arm/virt-acpi-build.c | 17 +-
hw/arm/virt.c | 126 ++++++-
hw/char/imx_serial.c | 35 --
hw/char/omap_uart.c | 3 +-
hw/display/omap_dss.c | 3 +-
hw/display/omap_lcdc.c | 3 +-
hw/dma/omap_dma.c | 6 +-
hw/gpio/omap_gpio.c | 4 +-
hw/i2c/Makefile.objs | 1 +
hw/i2c/imx_i2c.c | 339 +++++++++++++++++++
hw/i386/pc_piix.c | 3 +-
hw/i386/pc_q35.c | 3 +-
hw/input/stellaris_input.c | 4 +-
hw/misc/omap_clk.c | 2 +-
hw/misc/omap_gpmc.c | 3 +-
hw/misc/omap_sdrc.c | 3 +-
hw/net/Makefile.objs | 1 +
hw/net/imx_fec.c | 709 +++++++++++++++++++++++++++++++++++++++
hw/sd/omap_mmc.c | 6 +-
hw/smbios/smbios.c | 84 +++--
hw/ssi/omap_spi.c | 3 +-
hw/timer/imx_epit.c | 11 -
hw/timer/imx_gpt.c | 11 -
hw/timer/omap_gptimer.c | 3 +-
include/exec/gdbstub.h | 27 ++
include/exec/softmmu-semi.h | 18 +
include/hw/arm/fsl-imx25.h | 234 +++++++++++++
include/hw/arm/fsl-imx31.h | 110 ++++++
include/hw/arm/imx.h | 26 --
include/hw/arm/virt-acpi-build.h | 1 +
include/hw/arm/virt.h | 1 +
include/hw/i2c/imx_i2c.h | 87 +++++
include/hw/net/imx_fec.h | 113 +++++++
include/hw/smbios/smbios.h | 62 +++-
linux-user/main.c | 3 +
qemu-options.hx | 2 +-
target-arm/arm-semi.c | 171 +++++++---
target-arm/cpu-qom.h | 13 +
target-arm/cpu.c | 11 +-
target-arm/cpu.h | 9 +-
target-arm/helper-a64.c | 6 +
target-arm/helper.c | 78 +++--
target-arm/internals.h | 2 +
target-arm/kvm32.c | 3 +-
target-arm/kvm64.c | 3 +-
target-arm/translate-a64.c | 24 +-
tests/Makefile | 3 +
tests/bios-tables-test.c | 6 +-
tests/ds1338-test.c | 78 +++++
tests/libqos/i2c-imx.c | 209 ++++++++++++
tests/libqos/i2c.h | 3 +
63 files changed, 3248 insertions(+), 406 deletions(-)
create mode 100644 hw/arm/fsl-imx25.c
create mode 100644 hw/arm/fsl-imx31.c
create mode 100644 hw/arm/imx25_pdk.c
create mode 100644 hw/i2c/imx_i2c.c
create mode 100644 hw/net/imx_fec.c
create mode 100644 include/hw/arm/fsl-imx25.h
create mode 100644 include/hw/arm/fsl-imx31.h
delete mode 100644 include/hw/arm/imx.h
create mode 100644 include/hw/i2c/imx_i2c.h
create mode 100644 include/hw/net/imx_fec.h
create mode 100644 tests/ds1338-test.c
create mode 100644 tests/libqos/i2c-imx.c
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 01/27] arm: Use g_new() & friends where that makes obvious sense
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 02/27] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb Peter Maydell
` (26 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Markus Armbruster <armbru@redhat.com>
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer,
for two reasons. One, it catches multiplication overflowing size_t.
Two, it returns T * rather than void *, which lets the compiler catch
more type errors.
This commit only touches allocations with size arguments of the form
sizeof(T).
Coccinelle semantic patch:
@@
type T;
@@
-g_malloc(sizeof(T))
+g_new(T, 1)
@@
type T;
@@
-g_try_malloc(sizeof(T))
+g_try_new(T, 1)
@@
type T;
@@
-g_malloc0(sizeof(T))
+g_new0(T, 1)
@@
type T;
@@
-g_try_malloc0(sizeof(T))
+g_try_new0(T, 1)
@@
type T;
expression n;
@@
-g_malloc(sizeof(T) * (n))
+g_new(T, n)
@@
type T;
expression n;
@@
-g_try_malloc(sizeof(T) * (n))
+g_try_new(T, n)
@@
type T;
expression n;
@@
-g_malloc0(sizeof(T) * (n))
+g_new0(T, n)
@@
type T;
expression n;
@@
-g_try_malloc0(sizeof(T) * (n))
+g_try_new0(T, n)
@@
type T;
expression p, n;
@@
-g_realloc(p, sizeof(T) * (n))
+g_renew(T, p, n)
@@
type T;
expression p, n;
@@
-g_try_realloc(p, sizeof(T) * (n))
+g_try_renew(T, p, n)
@@
type T;
expression n;
@@
-(T *)g_new(T, n)
+g_new(T, n)
@@
type T;
expression n;
@@
-(T *)g_new0(T, n)
+g_new0(T, n)
@@
type T;
expression p, n;
@@
-(T *)g_renew(T, p, n)
+g_renew(T, p, n)
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-id: 1440524394-15640-1-git-send-email-armbru@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/omap1.c | 30 ++++++++++--------------------
hw/arm/omap2.c | 15 +++++----------
hw/arm/pxa2xx.c | 11 +++++------
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/char/omap_uart.c | 3 +--
hw/display/omap_dss.c | 3 +--
hw/display/omap_lcdc.c | 3 +--
hw/dma/omap_dma.c | 6 ++----
hw/gpio/omap_gpio.c | 4 ++--
hw/input/stellaris_input.c | 4 ++--
hw/misc/omap_clk.c | 2 +-
hw/misc/omap_gpmc.c | 3 +--
hw/misc/omap_sdrc.c | 3 +--
hw/sd/omap_mmc.c | 6 ++----
hw/ssi/omap_spi.c | 3 +--
hw/timer/omap_gptimer.c | 3 +--
17 files changed, 38 insertions(+), 65 deletions(-)
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index de2b289..8873f94 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -258,8 +258,7 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
- struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
- g_malloc0(sizeof(struct omap_mpu_timer_s));
+ struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1);
s->irq = irq;
s->clk = clk;
@@ -388,8 +387,7 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
- struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
- g_malloc0(sizeof(struct omap_watchdog_timer_s));
+ struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1);
s->timer.irq = irq;
s->timer.clk = clk;
@@ -495,8 +493,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
hwaddr base,
qemu_irq irq, omap_clk clk)
{
- struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
- g_malloc0(sizeof(struct omap_32khz_timer_s));
+ struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1);
s->timer.irq = irq;
s->timer.clk = clk;
@@ -1236,8 +1233,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
MemoryRegion *memory, hwaddr base,
qemu_irq abort_irq, omap_clk clk)
{
- struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
- g_malloc0(sizeof(struct omap_tipb_bridge_s));
+ struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1);
s->abort = abort_irq;
omap_tipb_bridge_reset(s);
@@ -2099,8 +2095,7 @@ static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
- struct omap_mpuio_s *s = (struct omap_mpuio_s *)
- g_malloc0(sizeof(struct omap_mpuio_s));
+ struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1);
s->irq = gpio_int;
s->kbd_irq = kbd_int;
@@ -2292,8 +2287,7 @@ static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
qemu_irq dma,
omap_clk clk)
{
- struct omap_uwire_s *s = (struct omap_uwire_s *)
- g_malloc0(sizeof(struct omap_uwire_s));
+ struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1);
s->txirq = txirq;
s->rxirq = rxirq;
@@ -2932,8 +2926,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
qemu_irq timerirq, qemu_irq alarmirq,
omap_clk clk)
{
- struct omap_rtc_s *s = (struct omap_rtc_s *)
- g_malloc0(sizeof(struct omap_rtc_s));
+ struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1);
s->irq = timerirq;
s->alarm = alarmirq;
@@ -3468,8 +3461,7 @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq *dma, omap_clk clk)
{
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
- g_malloc0(sizeof(struct omap_mcbsp_s));
+ struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1);
s->txirq = txirq;
s->rxirq = rxirq;
@@ -3648,8 +3640,7 @@ static void omap_lpg_clk_update(void *opaque, int line, int on)
static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
hwaddr base, omap_clk clk)
{
- struct omap_lpg_s *s = (struct omap_lpg_s *)
- g_malloc0(sizeof(struct omap_lpg_s));
+ struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1);
s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s);
@@ -3853,8 +3844,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
const char *core)
{
int i;
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
- g_malloc0(sizeof(struct omap_mpu_state_s));
+ struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
SysBusDevice *busdev;
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index e39b317..1ee2d61 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -596,8 +596,7 @@ static const MemoryRegionOps omap_eac_ops = {
static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
- struct omap_eac_s *s = (struct omap_eac_s *)
- g_malloc0(sizeof(struct omap_eac_s));
+ struct omap_eac_s *s = g_new0(struct omap_eac_s, 1);
s->irq = irq;
s->codec.rxdrq = *drq ++;
@@ -788,8 +787,7 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
hwaddr channel_base, qemu_irq irq, omap_clk clk,
CharDriverState *chr)
{
- struct omap_sti_s *s = (struct omap_sti_s *)
- g_malloc0(sizeof(struct omap_sti_s));
+ struct omap_sti_s *s = g_new0(struct omap_sti_s, 1);
s->irq = irq;
omap_sti_reset(s);
@@ -1806,8 +1804,7 @@ static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
struct omap_mpu_state_s *mpu)
{
- struct omap_prcm_s *s = (struct omap_prcm_s *)
- g_malloc0(sizeof(struct omap_prcm_s));
+ struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1);
s->irq[0] = mpu_int;
s->irq[1] = dsp_int;
@@ -2185,8 +2182,7 @@ static void omap_sysctl_reset(struct omap_sysctl_s *s)
static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
omap_clk iclk, struct omap_mpu_state_s *mpu)
{
- struct omap_sysctl_s *s = (struct omap_sysctl_s *)
- g_malloc0(sizeof(struct omap_sysctl_s));
+ struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1);
s->mpu = mpu;
omap_sysctl_reset(s);
@@ -2248,8 +2244,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
unsigned long sdram_size,
const char *core)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
- g_malloc0(sizeof(struct omap_mpu_state_s));
+ struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
qemu_irq dma_irqs[4];
DriveInfo *dinfo;
int i;
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index ec353f7..ec56b61 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -1731,8 +1731,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
hwaddr base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
{
- PXA2xxI2SState *s = (PXA2xxI2SState *)
- g_malloc0(sizeof(PXA2xxI2SState));
+ PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1);
s->irq = irq;
s->rx_dma = rx_dma;
@@ -2061,7 +2060,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
PXA2xxState *s;
int i;
DriveInfo *dinfo;
- s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
+ s = g_new0(PXA2xxState, 1);
if (revision && strncmp(revision, "pxa27", 5)) {
fprintf(stderr, "Machine requires a PXA27x processor.\n");
@@ -2157,7 +2156,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
for (i = 0; pxa27x_ssp[i].io_base; i ++);
- s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
+ s->ssp = g_new0(SSIBus *, i);
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
DeviceState *dev;
dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
@@ -2202,7 +2201,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
int i;
DriveInfo *dinfo;
- s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
+ s = g_new0(PXA2xxState, 1);
s->cpu = cpu_arm_init("pxa255");
if (s->cpu == NULL) {
@@ -2290,7 +2289,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
for (i = 0; pxa255_ssp[i].io_base; i ++);
- s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
+ s->ssp = g_new0(SSIBus *, i);
for (i = 0; pxa255_ssp[i].io_base; i ++) {
DeviceState *dev;
dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index cb515ec..ca4628b 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -675,7 +675,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
{
ssys_state *s;
- s = (ssys_state *)g_malloc0(sizeof(ssys_state));
+ s = g_new0(ssys_state, 1);
s->irq = irq;
s->board = board;
/* Most devices come preprogrammed with a MAC address in the user data. */
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index da9fc1d..9624ecb 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -1588,7 +1588,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
StrongARMState *s;
int i;
- s = g_malloc0(sizeof(StrongARMState));
+ s = g_new0(StrongARMState, 1);
if (!rev) {
rev = "sa1110-b5";
diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
index 88f2094..278ce36 100644
--- a/hw/char/omap_uart.c
+++ b/hw/char/omap_uart.c
@@ -55,8 +55,7 @@ struct omap_uart_s *omap_uart_init(hwaddr base,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
{
- struct omap_uart_s *s = (struct omap_uart_s *)
- g_malloc0(sizeof(struct omap_uart_s));
+ struct omap_uart_s *s = g_new0(struct omap_uart_s, 1);
s->base = base;
s->fclk = fclk;
diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c
index f1fef27..b1c7af5 100644
--- a/hw/display/omap_dss.c
+++ b/hw/display/omap_dss.c
@@ -1051,8 +1051,7 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)
{
- struct omap_dss_s *s = (struct omap_dss_s *)
- g_malloc0(sizeof(struct omap_dss_s));
+ struct omap_dss_s *s = g_new0(struct omap_dss_s, 1);
s->irq = irq;
s->drq = drq;
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
index a7c6cd7..678f9a1 100644
--- a/hw/display/omap_lcdc.c
+++ b/hw/display/omap_lcdc.c
@@ -403,8 +403,7 @@ struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk)
{
- struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
- g_malloc0(sizeof(struct omap_lcd_panel_s));
+ struct omap_lcd_panel_s *s = g_new0(struct omap_lcd_panel_s, 1);
s->irq = irq;
s->dma = dma;
diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
index 97c57a0..db68730 100644
--- a/hw/dma/omap_dma.c
+++ b/hw/dma/omap_dma.c
@@ -1626,8 +1626,7 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
enum omap_dma_model model)
{
int num_irqs, memsize, i;
- struct omap_dma_s *s = (struct omap_dma_s *)
- g_malloc0(sizeof(struct omap_dma_s));
+ struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);
if (model <= omap_dma_3_1) {
num_irqs = 6;
@@ -2061,8 +2060,7 @@ struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
int chans, omap_clk iclk, omap_clk fclk)
{
int i;
- struct omap_dma_s *s = (struct omap_dma_s *)
- g_malloc0(sizeof(struct omap_dma_s));
+ struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);
s->model = omap_dma_4;
s->chans = chans;
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
index d92f8cf..3c53898 100644
--- a/hw/gpio/omap_gpio.c
+++ b/hw/gpio/omap_gpio.c
@@ -710,8 +710,8 @@ static int omap2_gpio_init(SysBusDevice *sbd)
} else {
s->modulecount = 6;
}
- s->modules = g_malloc0(s->modulecount * sizeof(struct omap2_gpio_s));
- s->handler = g_malloc0(s->modulecount * 32 * sizeof(qemu_irq));
+ s->modules = g_new0(struct omap2_gpio_s, s->modulecount);
+ s->handler = g_new0(qemu_irq, s->modulecount * 32);
qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32);
qdev_init_gpio_out(dev, s->handler, s->modulecount * 32);
for (i = 0; i < s->modulecount; i++) {
diff --git a/hw/input/stellaris_input.c b/hw/input/stellaris_input.c
index 0609e80..c719b92 100644
--- a/hw/input/stellaris_input.c
+++ b/hw/input/stellaris_input.c
@@ -75,8 +75,8 @@ void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode)
gamepad_state *s;
int i;
- s = (gamepad_state *)g_malloc0(sizeof (gamepad_state));
- s->buttons = (gamepad_button *)g_malloc0(n * sizeof (gamepad_button));
+ s = g_new0(gamepad_state, 1);
+ s->buttons = g_new0(gamepad_button, n);
for (i = 0; i < n; i++) {
s->buttons[i].irq = irq[i];
s->buttons[i].keycode = keycode[i];
diff --git a/hw/misc/omap_clk.c b/hw/misc/omap_clk.c
index 80a3c50..73d4f8b 100644
--- a/hw/misc/omap_clk.c
+++ b/hw/misc/omap_clk.c
@@ -1239,7 +1239,7 @@ void omap_clk_init(struct omap_mpu_state_s *mpu)
for (i = onchip_clks, count = 0; *i; i ++)
if ((*i)->flags & flag)
count ++;
- mpu->clks = (struct clk *) g_malloc0(sizeof(struct clk) * (count + 1));
+ mpu->clks = g_new0(struct clk, count + 1);
for (i = onchip_clks, j = mpu->clks; *i; i ++)
if ((*i)->flags & flag) {
memcpy(j, *i, sizeof(struct clk));
diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c
index 74fc91c..8960f1b 100644
--- a/hw/misc/omap_gpmc.c
+++ b/hw/misc/omap_gpmc.c
@@ -826,8 +826,7 @@ struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
qemu_irq irq, qemu_irq drq)
{
int cs;
- struct omap_gpmc_s *s = (struct omap_gpmc_s *)
- g_malloc0(sizeof(struct omap_gpmc_s));
+ struct omap_gpmc_s *s = g_new0(struct omap_gpmc_s, 1);
memory_region_init_io(&s->iomem, NULL, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
memory_region_add_subregion(get_system_memory(), base, &s->iomem);
diff --git a/hw/misc/omap_sdrc.c b/hw/misc/omap_sdrc.c
index 3de0c0e..bca2530 100644
--- a/hw/misc/omap_sdrc.c
+++ b/hw/misc/omap_sdrc.c
@@ -157,8 +157,7 @@ static const MemoryRegionOps omap_sdrc_ops = {
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
hwaddr base)
{
- struct omap_sdrc_s *s = (struct omap_sdrc_s *)
- g_malloc0(sizeof(struct omap_sdrc_s));
+ struct omap_sdrc_s *s = g_new0(struct omap_sdrc_s, 1);
omap_sdrc_reset(s);
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
index d072dec..35d8033 100644
--- a/hw/sd/omap_mmc.c
+++ b/hw/sd/omap_mmc.c
@@ -578,8 +578,7 @@ struct omap_mmc_s *omap_mmc_init(hwaddr base,
BlockBackend *blk,
qemu_irq irq, qemu_irq dma[], omap_clk clk)
{
- struct omap_mmc_s *s = (struct omap_mmc_s *)
- g_malloc0(sizeof(struct omap_mmc_s));
+ struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
s->irq = irq;
s->dma = dma;
@@ -605,8 +604,7 @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
omap_clk fclk, omap_clk iclk)
{
- struct omap_mmc_s *s = (struct omap_mmc_s *)
- g_malloc0(sizeof(struct omap_mmc_s));
+ struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
s->irq = irq;
s->dma = dma;
diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c
index 119e325..2726329 100644
--- a/hw/ssi/omap_spi.c
+++ b/hw/ssi/omap_spi.c
@@ -342,8 +342,7 @@ static const MemoryRegionOps omap_mcspi_ops = {
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
- struct omap_mcspi_s *s = (struct omap_mcspi_s *)
- g_malloc0(sizeof(struct omap_mcspi_s));
+ struct omap_mcspi_s *s = g_new0(struct omap_mcspi_s, 1);
struct omap_mcspi_ch_s *ch = s->ch;
s->irq = irq;
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
index b8c8c01..dcf706c 100644
--- a/hw/timer/omap_gptimer.c
+++ b/hw/timer/omap_gptimer.c
@@ -468,8 +468,7 @@ static const MemoryRegionOps omap_gp_timer_ops = {
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk)
{
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)
- g_malloc0(sizeof(struct omap_gp_timer_s));
+ struct omap_gp_timer_s *s = g_new0(struct omap_gp_timer_s, 1);
s->ta = ta;
s->irq = irq;
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 02/27] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 01/27] arm: Use g_new() & friends where that makes obvious sense Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 03/27] target-arm: Improve semihosting debug prints Peter Maydell
` (25 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
A spurious trailing "\n" in the gdb syscall format string used
for SYS_WRITE0 meant that gdb would reject the remote syscall,
with the effect that the output from the guest was silently dropped.
Remove the newline so that gdb accepts the packet.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/arm-semi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index a2a7369..42522a7 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -260,7 +260,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
return (uint32_t)-1;
len = strlen(s);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "write,2,%x,%x\n", args, len);
+ gdb_do_syscall(arm_semi_cb, "write,2,%x,%x", args, len);
ret = env->regs[0];
} else {
ret = write(STDERR_FILENO, s, len);
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 03/27] target-arm: Improve semihosting debug prints
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 01/27] arm: Use g_new() & friends where that makes obvious sense Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 02/27] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 04/27] gdbstub: Implement gdb_do_syscallv() Peter Maydell
` (24 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Christopher Covington <christopher.covington@linaro.org>
Print semihosting debugging information before the
do_arm_semihosting() call so that angel_SWIreason_ReportException,
which causes the function to not return, gets the same debug prints as
other semihosting calls. Also print out the semihosting call number.
Signed-off-by: Christopher Covington <christopher.covington@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-3-git-send-email-peter.maydell@linaro.org
---
target-arm/helper.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7df1f06..114d56e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5228,8 +5228,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
if (nr == 0xab) {
env->regs[15] += 2;
+ qemu_log_mask(CPU_LOG_INT,
+ "...handling as semihosting call 0x%x\n",
+ env->regs[0]);
env->regs[0] = do_arm_semihosting(env);
- qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
return;
}
}
@@ -5549,8 +5551,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
if (((mask == 0x123456 && !env->thumb)
|| (mask == 0xab && env->thumb))
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
+ qemu_log_mask(CPU_LOG_INT,
+ "...handling as semihosting call 0x%x\n",
+ env->regs[0]);
env->regs[0] = do_arm_semihosting(env);
- qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
return;
}
}
@@ -5567,8 +5571,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
if (mask == 0xab
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
env->regs[15] += 2;
+ qemu_log_mask(CPU_LOG_INT,
+ "...handling as semihosting call 0x%x\n",
+ env->regs[0]);
env->regs[0] = do_arm_semihosting(env);
- qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
return;
}
}
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 04/27] gdbstub: Implement gdb_do_syscallv()
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 03/27] target-arm: Improve semihosting debug prints Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]' Peter Maydell
` (23 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
Implement a variant of the existing gdb_do_syscall() which
takes a va_list.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-4-git-send-email-peter.maydell@linaro.org
---
gdbstub.c | 14 ++++++++++----
include/exec/gdbstub.h | 27 +++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index ffe7e6e..eee9b25 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1301,9 +1301,8 @@ send_packet:
%x - target_ulong argument printed in hex.
%lx - 64-bit argument printed in hex.
%s - string pointer (target_ulong) and length (int) pair. */
-void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
+void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va)
{
- va_list va;
char *p;
char *p_end;
target_ulong addr;
@@ -1317,7 +1316,6 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
#ifndef CONFIG_USER_ONLY
vm_stop(RUN_STATE_DEBUG);
#endif
- va_start(va, fmt);
p = s->syscall_buf;
p_end = &s->syscall_buf[sizeof(s->syscall_buf)];
*(p++) = 'F';
@@ -1351,7 +1349,6 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
}
}
*p = 0;
- va_end(va);
#ifdef CONFIG_USER_ONLY
put_packet(s, s->syscall_buf);
gdb_handlesig(s->c_cpu, 0);
@@ -1366,6 +1363,15 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
#endif
}
+void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
+{
+ va_list va;
+
+ va_start(va, fmt);
+ gdb_do_syscallv(cb, fmt, va);
+ va_end(va);
+}
+
static void gdb_read_byte(GDBState *s, int ch)
{
int i, csum;
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 05f57c2..d9e8cf7 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -14,7 +14,34 @@
typedef void (*gdb_syscall_complete_cb)(CPUState *cpu,
target_ulong ret, target_ulong err);
+/**
+ * gdb_do_syscall:
+ * @cb: function to call when the system call has completed
+ * @fmt: gdb syscall format string
+ * ...: list of arguments to interpolate into @fmt
+ *
+ * Send a GDB syscall request. This function will return immediately;
+ * the callback function will be called later when the remote system
+ * call has completed.
+ *
+ * @fmt should be in the 'call-id,parameter,parameter...' format documented
+ * for the F request packet in the GDB remote protocol. A limited set of
+ * printf-style format specifiers is supported:
+ * %x - target_ulong argument printed in hex
+ * %lx - 64-bit argument printed in hex
+ * %s - string pointer (target_ulong) and length (int) pair
+ */
void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...);
+/**
+ * gdb_do_syscallv:
+ * @cb: function to call when the system call has completed
+ * @fmt: gdb syscall format string
+ * @va: arguments to interpolate into @fmt
+ *
+ * As gdb_do_syscall, but taking a va_list rather than a variable
+ * argument list.
+ */
+void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va);
int use_gdb_syscalls(void);
void gdb_set_stop_cpu(CPUState *cpu);
void gdb_exit(CPUArchState *, int);
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 04/27] gdbstub: Implement gdb_do_syscallv() Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 06/27] include/exec/softmmu-semi.h: Add support for 64-bit values Peter Maydell
` (22 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
Factor out a repeated pattern in the semihosting code:
gdb_do_syscall(arm_semi_cb, "system,%s", arg0, (int)arg1+1);
/* arm_semi_cb sets env->regs[0] to the syscall return value */
return env->regs[0];
For A64 the return value will go in a different register; pull
the sequence out into its own function that passes the return
value in a static variable rather than overloading regs[0]
for the purpose, so the code will work on both A32/T32 and A64.
Note that the lack-of-synchronization bug noted in the FIXME
comment is not introduced by this commit, but was already present.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-5-git-send-email-peter.maydell@linaro.org
---
target-arm/arm-semi.c | 79 ++++++++++++++++++++++++++++++---------------------
1 file changed, 47 insertions(+), 32 deletions(-)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 42522a7..dbdc211 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -134,6 +134,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
#ifdef CONFIG_USER_ONLY
TaskState *ts = cs->opaque;
#endif
+ target_ulong reg0 = env->regs[0];
if (ret == (target_ulong)-1) {
#ifdef CONFIG_USER_ONLY
@@ -141,22 +142,23 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
#else
syscall_err = err;
#endif
- env->regs[0] = ret;
+ reg0 = ret;
} else {
/* Fixup syscalls that use nonstardard return conventions. */
- switch (env->regs[0]) {
+ switch (reg0) {
case TARGET_SYS_WRITE:
case TARGET_SYS_READ:
- env->regs[0] = arm_semi_syscall_len - ret;
+ reg0 = arm_semi_syscall_len - ret;
break;
case TARGET_SYS_SEEK:
- env->regs[0] = 0;
+ reg0 = 0;
break;
default:
- env->regs[0] = ret;
+ reg0 = ret;
break;
}
}
+ env->regs[0] = reg0;
}
static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
@@ -175,6 +177,25 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
#endif
}
+static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb,
+ const char *fmt, ...)
+{
+ va_list va;
+ CPUARMState *env = &cpu->env;
+
+ va_start(va, fmt);
+ gdb_do_syscallv(cb, fmt, va);
+ va_end(va);
+
+ /* FIXME: we are implicitly relying on the syscall completing
+ * before this point, which is not guaranteed. We should
+ * put in an explicit synchronization between this and
+ * the callback function.
+ */
+
+ return env->regs[0];
+}
+
/* Read the input value from the argument block; fail the semihosting
* call if the memory read fails.
*/
@@ -223,9 +244,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
return result_fileno;
}
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "open,%s,%x,1a4", arg0,
- (int)arg2+1, gdb_open_modeflags[arg1]);
- ret = env->regs[0];
+ ret = arm_gdb_syscall(cpu, arm_semi_cb, "open,%s,%x,1a4", arg0,
+ (int)arg2+1, gdb_open_modeflags[arg1]);
} else {
ret = set_swi_errno(ts, open(s, open_modeflags[arg1], 0644));
}
@@ -234,8 +254,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
case TARGET_SYS_CLOSE:
GET_ARG(0);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "close,%x", arg0);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", arg0);
} else {
return set_swi_errno(ts, close(arg0));
}
@@ -248,8 +267,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
return (uint32_t)-1;
/* Write to debug console. stderr is near enough. */
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "write,2,%x,1", args);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "write,2,%x,1", args);
} else {
return write(STDERR_FILENO, &c, 1);
}
@@ -260,8 +278,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
return (uint32_t)-1;
len = strlen(s);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "write,2,%x,%x", args, len);
- ret = env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "write,2,%x,%x",
+ args, len);
} else {
ret = write(STDERR_FILENO, s, len);
}
@@ -274,8 +292,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
len = arg2;
if (use_gdb_syscalls()) {
arm_semi_syscall_len = len;
- gdb_do_syscall(arm_semi_cb, "write,%x,%x,%x", arg0, arg1, len);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x",
+ arg0, arg1, len);
} else {
s = lock_user(VERIFY_READ, arg1, len, 1);
if (!s) {
@@ -295,8 +313,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
len = arg2;
if (use_gdb_syscalls()) {
arm_semi_syscall_len = len;
- gdb_do_syscall(arm_semi_cb, "read,%x,%x,%x", arg0, arg1, len);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x",
+ arg0, arg1, len);
} else {
s = lock_user(VERIFY_WRITE, arg1, len, 0);
if (!s) {
@@ -317,8 +335,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
case TARGET_SYS_ISTTY:
GET_ARG(0);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "isatty,%x", arg0);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", arg0);
} else {
return isatty(arg0);
}
@@ -326,8 +343,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
GET_ARG(0);
GET_ARG(1);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "lseek,%x,%x,0", arg0, arg1);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0",
+ arg0, arg1);
} else {
ret = set_swi_errno(ts, lseek(arg0, arg1, SEEK_SET));
if (ret == (uint32_t)-1)
@@ -337,9 +354,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
case TARGET_SYS_FLEN:
GET_ARG(0);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_flen_cb, "fstat,%x,%x",
- arg0, env->regs[13]-64);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x",
+ arg0, env->regs[13]-64);
} else {
struct stat buf;
ret = set_swi_errno(ts, fstat(arg0, &buf));
@@ -354,8 +370,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
GET_ARG(0);
GET_ARG(1);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "unlink,%s", arg0, (int)arg1+1);
- ret = env->regs[0];
+ ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
+ arg0, (int)arg1+1);
} else {
s = lock_user_string(arg0);
if (!s) {
@@ -372,9 +388,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
GET_ARG(2);
GET_ARG(3);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "rename,%s,%s",
- arg0, (int)arg1+1, arg2, (int)arg3+1);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
+ arg0, (int)arg1+1, arg2, (int)arg3+1);
} else {
char *s2;
s = lock_user_string(arg0);
@@ -398,8 +413,8 @@ uint32_t do_arm_semihosting(CPUARMState *env)
GET_ARG(0);
GET_ARG(1);
if (use_gdb_syscalls()) {
- gdb_do_syscall(arm_semi_cb, "system,%s", arg0, (int)arg1+1);
- return env->regs[0];
+ return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
+ arg0, (int)arg1+1);
} else {
s = lock_user_string(arg0);
if (!s) {
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 06/27] include/exec/softmmu-semi.h: Add support for 64-bit values
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]' Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 07/27] target-arm/arm-semi.c: Support widening APIs to 64 bits Peter Maydell
` (21 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
Add support for getting and setting 64-bit values in the
softmmu semihosting support functions. This will be needed
for 64-bit ARM semihosting.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-6-git-send-email-peter.maydell@linaro.org
---
include/exec/softmmu-semi.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h
index 1819cc2..3a58c3f 100644
--- a/include/exec/softmmu-semi.h
+++ b/include/exec/softmmu-semi.h
@@ -9,6 +9,14 @@
#ifndef SOFTMMU_SEMI_H
#define SOFTMMU_SEMI_H 1
+static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr)
+{
+ uint64_t val;
+
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0);
+ return tswap64(val);
+}
+
static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)
{
uint32_t val;
@@ -16,6 +24,7 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)
cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);
return tswap32(val);
}
+
static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr)
{
uint8_t val;
@@ -24,16 +33,25 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr)
return val;
}
+#define get_user_u64(arg, p) ({ arg = softmmu_tget64(env, p); 0; })
#define get_user_u32(arg, p) ({ arg = softmmu_tget32(env, p) ; 0; })
#define get_user_u8(arg, p) ({ arg = softmmu_tget8(env, p) ; 0; })
#define get_user_ual(arg, p) get_user_u32(arg, p)
+static inline void softmmu_tput64(CPUArchState *env,
+ target_ulong addr, uint64_t val)
+{
+ val = tswap64(val);
+ cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1);
+}
+
static inline void softmmu_tput32(CPUArchState *env,
target_ulong addr, uint32_t val)
{
val = tswap32(val);
cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
}
+#define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; })
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
#define put_user_ual(arg, p) put_user_u32(arg, p)
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 07/27] target-arm/arm-semi.c: Support widening APIs to 64 bits
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 06/27] include/exec/softmmu-semi.h: Add support for 64-bit values Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call Peter Maydell
` (20 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
The 64-bit A64 semihosting API has some pervasive changes from
the 32-bit version:
* all parameter blocks are arrays of 64-bit values, not 32-bit
* the semihosting call number is passed in W0
* the return value is a 64-bit value in X0
Implement the necessary handling for this widening.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-7-git-send-email-peter.maydell@linaro.org
---
target-arm/arm-semi.c | 69 ++++++++++++++++++++++++++++++++++++++++++---------
target-arm/cpu.h | 2 +-
2 files changed, 58 insertions(+), 13 deletions(-)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index dbdc211..1d4cc59 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -134,7 +134,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
#ifdef CONFIG_USER_ONLY
TaskState *ts = cs->opaque;
#endif
- target_ulong reg0 = env->regs[0];
+ target_ulong reg0 = is_a64(env) ? env->xregs[0] : env->regs[0];
if (ret == (target_ulong)-1) {
#ifdef CONFIG_USER_ONLY
@@ -158,7 +158,30 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
break;
}
}
- env->regs[0] = reg0;
+ if (is_a64(env)) {
+ env->xregs[0] = reg0;
+ } else {
+ env->regs[0] = reg0;
+ }
+}
+
+static target_ulong arm_flen_buf(ARMCPU *cpu)
+{
+ /* Return an address in target memory of 64 bytes where the remote
+ * gdb should write its stat struct. (The format of this structure
+ * is defined by GDB's remote protocol and is not target-specific.)
+ * We put this on the guest's stack just below SP.
+ */
+ CPUARMState *env = &cpu->env;
+ target_ulong sp;
+
+ if (is_a64(env)) {
+ sp = env->xregs[31];
+ } else {
+ sp = env->regs[13];
+ }
+
+ return sp - 64;
}
static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
@@ -168,8 +191,13 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
/* The size is always stored in big-endian order, extract
the value. We assume the size always fit in 32 bits. */
uint32_t size;
- cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0);
- env->regs[0] = be32_to_cpu(size);
+ cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0);
+ size = be32_to_cpu(size);
+ if (is_a64(env)) {
+ env->xregs[0] = size;
+ } else {
+ env->regs[0] = size;
+ }
#ifdef CONFIG_USER_ONLY
((TaskState *)cs->opaque)->swi_errno = err;
#else
@@ -193,20 +221,30 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb,
* the callback function.
*/
- return env->regs[0];
+ return is_a64(env) ? env->xregs[0] : env->regs[0];
}
/* Read the input value from the argument block; fail the semihosting
* call if the memory read fails.
*/
#define GET_ARG(n) do { \
- if (get_user_ual(arg ## n, args + (n) * 4)) { \
- return (uint32_t)-1; \
+ if (is_a64(env)) { \
+ if (get_user_u64(arg ## n, args + (n) * 8)) { \
+ return -1; \
+ } \
+ } else { \
+ if (get_user_u32(arg ## n, args + (n) * 4)) { \
+ return -1; \
+ } \
} \
} while (0)
-#define SET_ARG(n, val) put_user_ual(val, args + (n) * 4)
-uint32_t do_arm_semihosting(CPUARMState *env)
+#define SET_ARG(n, val) \
+ (is_a64(env) ? \
+ put_user_u64(val, args + (n) * 8) : \
+ put_user_u32(val, args + (n) * 4))
+
+target_ulong do_arm_semihosting(CPUARMState *env)
{
ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu);
@@ -222,8 +260,15 @@ uint32_t do_arm_semihosting(CPUARMState *env)
CPUARMState *ts = env;
#endif
- nr = env->regs[0];
- args = env->regs[1];
+ if (is_a64(env)) {
+ /* Note that the syscall number is in W0, not X0 */
+ nr = env->xregs[0] & 0xffffffffU;
+ args = env->xregs[1];
+ } else {
+ nr = env->regs[0];
+ args = env->regs[1];
+ }
+
switch (nr) {
case TARGET_SYS_OPEN:
GET_ARG(0);
@@ -355,7 +400,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
GET_ARG(0);
if (use_gdb_syscalls()) {
return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x",
- arg0, env->regs[13]-64);
+ arg0, arm_flen_buf(cpu));
} else {
struct stat buf;
ret = set_swi_errno(ts, fstat(arg0, &buf));
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 31825d3..0a25335 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -504,7 +504,7 @@ typedef struct CPUARMState {
ARMCPU *cpu_arm_init(const char *cpu_model);
int cpu_arm_exec(CPUState *cpu);
-uint32_t do_arm_semihosting(CPUARMState *env);
+target_ulong do_arm_semihosting(CPUARMState *env);
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 07/27] target-arm/arm-semi.c: Support widening APIs to 64 bits Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block Peter Maydell
` (19 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-8-git-send-email-peter.maydell@linaro.org
---
target-arm/arm-semi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 1d4cc59..1d0d7aa 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -58,6 +58,7 @@
#define TARGET_SYS_GET_CMDLINE 0x15
#define TARGET_SYS_HEAPINFO 0x16
#define TARGET_SYS_EXIT 0x18
+#define TARGET_SYS_SYNCCACHE 0x19
/* ADP_Stopped_ApplicationExit is used for exit(0),
* anything else is implemented as exit(1) */
@@ -623,6 +624,15 @@ target_ulong do_arm_semihosting(CPUARMState *env)
ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1;
gdb_exit(env, ret);
exit(ret);
+ case TARGET_SYS_SYNCCACHE:
+ /* Clean the D-cache and invalidate the I-cache for the specified
+ * virtual address range. This is a nop for us since we don't
+ * implement caches. This is only present on A64.
+ */
+ if (is_a64(env)) {
+ return 0;
+ }
+ /* fall through -- invalid for A32/T32 */
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
cpu_dump_state(cs, stderr, fprintf, 0);
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 10/27] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction Peter Maydell
` (18 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
The A64 semihosting API changes the interface for SYS_EXIT so
that instead of taking a single exception type in a register,
it takes a parameter block containing the exception type and
a sub-code. Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-9-git-send-email-peter.maydell@linaro.org
---
target-arm/arm-semi.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 1d0d7aa..d7cff3d 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -619,9 +619,24 @@ target_ulong do_arm_semihosting(CPUARMState *env)
return 0;
}
case TARGET_SYS_EXIT:
- /* ARM specifies only Stopped_ApplicationExit as normal
- * exit, everything else is considered an error */
- ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1;
+ if (is_a64(env)) {
+ /* The A64 version of this call takes a parameter block,
+ * so the application-exit type can return a subcode which
+ * is the exit status code from the application.
+ */
+ GET_ARG(0);
+ GET_ARG(1);
+
+ if (arg0 == ADP_Stopped_ApplicationExit) {
+ ret = arg1;
+ } else {
+ ret = 1;
+ }
+ } else {
+ /* ARM specifies only Stopped_ApplicationExit as normal
+ * exit, everything else is considered an error */
+ ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1;
+ }
gdb_exit(env, ret);
exit(ret);
case TARGET_SYS_SYNCCACHE:
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 10/27] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 11/27] smbios: add smbios 3.0 support Peter Maydell
` (17 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
For the A64 instruction set, the semihosting call instruction
is 'HLT 0xf000'. Wire this up to call do_arm_semihosting()
if semihosting is enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-10-git-send-email-peter.maydell@linaro.org
---
linux-user/main.c | 3 +++
target-arm/cpu.h | 1 +
target-arm/helper-a64.c | 6 ++++++
target-arm/internals.h | 2 ++
target-arm/translate-a64.c | 24 ++++++++++++++++++++++--
5 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 2c9658e..06dd296 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1052,6 +1052,9 @@ void cpu_loop(CPUARMState *env)
queue_signal(env, info.si_signo, &info);
}
break;
+ case EXCP_SEMIHOST:
+ env->xregs[0] = do_arm_semihosting(env);
+ break;
default:
fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
trapnr);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 0a25335..c794afc 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -56,6 +56,7 @@
#define EXCP_SMC 13 /* Secure Monitor Call */
#define EXCP_VIRQ 14
#define EXCP_VFIQ 15
+#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 08c95a3..02fc9b4 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -514,6 +514,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
case EXCP_VFIQ:
addr += 0x100;
break;
+ case EXCP_SEMIHOST:
+ qemu_log_mask(CPU_LOG_INT,
+ "...handling as semihosting call 0x%" PRIx64 "\n",
+ env->xregs[0]);
+ env->xregs[0] = do_arm_semihosting(env);
+ return;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 924aff9..36a56aa 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -36,6 +36,7 @@ static inline bool excp_is_internal(int excp)
|| excp == EXCP_HALTED
|| excp == EXCP_EXCEPTION_EXIT
|| excp == EXCP_KERNEL_TRAP
+ || excp == EXCP_SEMIHOST
|| excp == EXCP_STREX;
}
@@ -58,6 +59,7 @@ static const char * const excnames[] = {
[EXCP_SMC] = "Secure Monitor Call",
[EXCP_VIRQ] = "Virtual IRQ",
[EXCP_VFIQ] = "Virtual FIQ",
+ [EXCP_SEMIHOST] = "Semihosting call",
};
static inline void arm_log_exception(int idx)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 5c13e15..529bb0c 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -30,6 +30,7 @@
#include "internals.h"
#include "qemu/host-utils.h"
+#include "exec/semihost.h"
#include "exec/gen-icount.h"
#include "exec/helper-proto.h"
@@ -1553,8 +1554,27 @@ static void disas_exc(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
break;
}
- /* HLT */
- unsupported_encoding(s, insn);
+ /* HLT. This has two purposes.
+ * Architecturally, it is an external halting debug instruction.
+ * Since QEMU doesn't implement external debug, we treat this as
+ * it is required for halting debug disabled: it will UNDEF.
+ * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
+ */
+ if (semihosting_enabled() && imm16 == 0xf000) {
+#ifndef CONFIG_USER_ONLY
+ /* In system mode, don't allow userspace access to semihosting,
+ * to provide some semblance of security (and for consistency
+ * with our 32-bit semihosting).
+ */
+ if (s->current_el == 0) {
+ unsupported_encoding(s, insn);
+ break;
+ }
+#endif
+ gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
+ } else {
+ unsupported_encoding(s, insn);
+ }
break;
case 5:
if (op2_ll < 1 || op2_ll > 3) {
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 11/27] smbios: add smbios 3.0 support
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 10/27] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 12/27] smbios: implement smbios support for mach-virt Peter Maydell
` (16 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Wei Huang <wei@redhat.com>
This patch adds support for SMBIOS 3.0 entry point. When caller invokes
smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
smbios_get_tables() will return the entry point table in right format.
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Wei Huang <wei@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Message-id: 1440615870-9518-2-git-send-email-wei@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/i386/pc_piix.c | 3 +-
hw/i386/pc_q35.c | 3 +-
hw/smbios/smbios.c | 84 +++++++++++++++++++++++++++++++++-------------
include/hw/smbios/smbios.h | 62 ++++++++++++++++++++++++++--------
tests/bios-tables-test.c | 6 ++--
5 files changed, 116 insertions(+), 42 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 9558467..b82921d 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -173,7 +173,8 @@ static void pc_init1(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
/* These values are guest ABI, do not change */
smbios_set_defaults("QEMU", "Standard PC (i440FX + PIIX, 1996)",
- mc->name, smbios_legacy_mode, smbios_uuid_encoded);
+ mc->name, smbios_legacy_mode, smbios_uuid_encoded,
+ SMBIOS_ENTRY_POINT_21);
}
/* allocate ram and load rom/bios */
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index c07d65b..7217cbf 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -165,7 +165,8 @@ static void pc_q35_init(MachineState *machine)
if (smbios_defaults) {
/* These values are guest ABI, do not change */
smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
- mc->name, smbios_legacy_mode, smbios_uuid_encoded);
+ mc->name, smbios_legacy_mode, smbios_uuid_encoded,
+ SMBIOS_ENTRY_POINT_21);
}
/* allocate ram and load rom/bios */
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index efdbb5d..b81a1d3 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -55,7 +55,9 @@ static uint8_t *smbios_tables;
static size_t smbios_tables_len;
static unsigned smbios_table_max;
static unsigned smbios_table_cnt;
-static struct smbios_entry_point ep;
+static SmbiosEntryPointType smbios_ep_type = SMBIOS_ENTRY_POINT_21;
+
+static SmbiosEntryPoint ep;
static int smbios_type4_count = 0;
static bool smbios_immutable;
@@ -771,11 +773,12 @@ void smbios_set_cpuid(uint32_t version, uint32_t features)
void smbios_set_defaults(const char *manufacturer, const char *product,
const char *version, bool legacy_mode,
- bool uuid_encoded)
+ bool uuid_encoded, SmbiosEntryPointType ep_type)
{
smbios_have_defaults = true;
smbios_legacy = legacy_mode;
smbios_uuid_encoded = uuid_encoded;
+ smbios_ep_type = ep_type;
/* drop unwanted version of command-line file blob(s) */
if (smbios_legacy) {
@@ -808,26 +811,53 @@ void smbios_set_defaults(const char *manufacturer, const char *product,
static void smbios_entry_point_setup(void)
{
- memcpy(ep.anchor_string, "_SM_", 4);
- memcpy(ep.intermediate_anchor_string, "_DMI_", 5);
- ep.length = sizeof(struct smbios_entry_point);
- ep.entry_point_revision = 0; /* formatted_area reserved, per spec v2.1+ */
- memset(ep.formatted_area, 0, 5);
-
- /* compliant with smbios spec v2.8 */
- ep.smbios_major_version = 2;
- ep.smbios_minor_version = 8;
- ep.smbios_bcd_revision = 0x28;
-
- /* set during table construction, but BIOS may override: */
- ep.structure_table_length = cpu_to_le16(smbios_tables_len);
- ep.max_structure_size = cpu_to_le16(smbios_table_max);
- ep.number_of_structures = cpu_to_le16(smbios_table_cnt);
-
- /* BIOS must recalculate: */
- ep.checksum = 0;
- ep.intermediate_checksum = 0;
- ep.structure_table_address = cpu_to_le32(0);
+ switch (smbios_ep_type) {
+ case SMBIOS_ENTRY_POINT_21:
+ memcpy(ep.ep21.anchor_string, "_SM_", 4);
+ memcpy(ep.ep21.intermediate_anchor_string, "_DMI_", 5);
+ ep.ep21.length = sizeof(struct smbios_21_entry_point);
+ ep.ep21.entry_point_revision = 0; /* formatted_area reserved */
+ memset(ep.ep21.formatted_area, 0, 5);
+
+ /* compliant with smbios spec v2.8 */
+ ep.ep21.smbios_major_version = 2;
+ ep.ep21.smbios_minor_version = 8;
+ ep.ep21.smbios_bcd_revision = 0x28;
+
+ /* set during table construction, but BIOS may override: */
+ ep.ep21.structure_table_length = cpu_to_le16(smbios_tables_len);
+ ep.ep21.max_structure_size = cpu_to_le16(smbios_table_max);
+ ep.ep21.number_of_structures = cpu_to_le16(smbios_table_cnt);
+
+ /* BIOS must recalculate */
+ ep.ep21.checksum = 0;
+ ep.ep21.intermediate_checksum = 0;
+ ep.ep21.structure_table_address = cpu_to_le32(0);
+
+ break;
+ case SMBIOS_ENTRY_POINT_30:
+ memcpy(ep.ep30.anchor_string, "_SM3_", 5);
+ ep.ep30.length = sizeof(struct smbios_30_entry_point);
+ ep.ep30.entry_point_revision = 1;
+ ep.ep30.reserved = 0;
+
+ /* compliant with smbios spec 3.0 */
+ ep.ep30.smbios_major_version = 3;
+ ep.ep30.smbios_minor_version = 0;
+ ep.ep30.smbios_doc_rev = 0;
+
+ /* set during table construct, but BIOS might override */
+ ep.ep30.structure_table_max_size = cpu_to_le32(smbios_tables_len);
+
+ /* BIOS must recalculate */
+ ep.ep30.checksum = 0;
+ ep.ep30.structure_table_address = cpu_to_le64(0);
+
+ break;
+ default:
+ abort();
+ break;
+ }
}
void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
@@ -885,7 +915,15 @@ void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
*tables = smbios_tables;
*tables_len = smbios_tables_len;
*anchor = (uint8_t *)&ep;
- *anchor_len = sizeof(struct smbios_entry_point);
+
+ /* calculate length based on anchor string */
+ if (!strncmp((char *)&ep, "_SM_", 4)) {
+ *anchor_len = sizeof(struct smbios_21_entry_point);
+ } else if (!strncmp((char *)&ep, "_SM3_", 5)) {
+ *anchor_len = sizeof(struct smbios_30_entry_point);
+ } else {
+ abort();
+ }
}
static void save_opt(const char **dest, QemuOpts *opts, const char *name)
diff --git a/include/hw/smbios/smbios.h b/include/hw/smbios/smbios.h
index 4269aab..76ccf70 100644
--- a/include/hw/smbios/smbios.h
+++ b/include/hw/smbios/smbios.h
@@ -23,25 +23,27 @@ struct smbios_phys_mem_area {
uint64_t length;
};
-void smbios_entry_add(QemuOpts *opts);
-void smbios_set_cpuid(uint32_t version, uint32_t features);
-void smbios_set_defaults(const char *manufacturer, const char *product,
- const char *version, bool legacy_mode,
- bool uuid_encoded);
-uint8_t *smbios_get_table_legacy(size_t *length);
-void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
- const unsigned int mem_array_size,
- uint8_t **tables, size_t *tables_len,
- uint8_t **anchor, size_t *anchor_len);
-
/*
* SMBIOS spec defined tables
*/
+typedef enum SmbiosEntryPointType {
+ SMBIOS_ENTRY_POINT_21,
+ SMBIOS_ENTRY_POINT_30,
+} SmbiosEntryPointType;
+
+/* SMBIOS Entry Point
+ * There are two types of entry points defined in the SMBIOS specification
+ * (see below). BIOS must place the entry point(s) at a 16-bit-aligned
+ * address between 0xf0000 and 0xfffff. Note that either entry point type
+ * can be used in a 64-bit target system, except that SMBIOS 2.1 entry point
+ * only allows the SMBIOS struct table to reside below 4GB address space.
+ */
-/* SMBIOS entry point (anchor).
- * BIOS must place this at a 16-bit-aligned address between 0xf0000 and 0xfffff.
+/* SMBIOS 2.1 (32-bit) Entry Point
+ * - introduced since SMBIOS 2.1
+ * - supports structure table below 4GB only
*/
-struct smbios_entry_point {
+struct smbios_21_entry_point {
uint8_t anchor_string[4];
uint8_t checksum;
uint8_t length;
@@ -58,6 +60,28 @@ struct smbios_entry_point {
uint8_t smbios_bcd_revision;
} QEMU_PACKED;
+/* SMBIOS 3.0 (64-bit) Entry Point
+ * - introduced since SMBIOS 3.0
+ * - supports structure table at 64-bit address space
+ */
+struct smbios_30_entry_point {
+ uint8_t anchor_string[5];
+ uint8_t checksum;
+ uint8_t length;
+ uint8_t smbios_major_version;
+ uint8_t smbios_minor_version;
+ uint8_t smbios_doc_rev;
+ uint8_t entry_point_revision;
+ uint8_t reserved;
+ uint32_t structure_table_max_size;
+ uint64_t structure_table_address;
+} QEMU_PACKED;
+
+typedef union {
+ struct smbios_21_entry_point ep21;
+ struct smbios_30_entry_point ep30;
+} QEMU_PACKED SmbiosEntryPoint;
+
/* This goes at the beginning of every SMBIOS structure. */
struct smbios_structure_header {
uint8_t type;
@@ -232,4 +256,14 @@ struct smbios_type_127 {
struct smbios_structure_header header;
} QEMU_PACKED;
+void smbios_entry_add(QemuOpts *opts);
+void smbios_set_cpuid(uint32_t version, uint32_t features);
+void smbios_set_defaults(const char *manufacturer, const char *product,
+ const char *version, bool legacy_mode,
+ bool uuid_encoded, SmbiosEntryPointType ep_type);
+uint8_t *smbios_get_table_legacy(size_t *length);
+void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
+ const unsigned int mem_array_size,
+ uint8_t **tables, size_t *tables_len,
+ uint8_t **anchor, size_t *anchor_len);
#endif /*QEMU_SMBIOS_H */
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index 613867a..9686328 100644
--- a/tests/bios-tables-test.c
+++ b/tests/bios-tables-test.c
@@ -50,7 +50,7 @@ typedef struct {
int rsdt_tables_nr;
GArray *tables;
uint32_t smbios_ep_addr;
- struct smbios_entry_point smbios_ep_table;
+ struct smbios_21_entry_point smbios_ep_table;
} test_data;
#define LOW(x) ((x) & 0xff)
@@ -601,7 +601,7 @@ static void test_acpi_asl(test_data *data)
static bool smbios_ep_table_ok(test_data *data)
{
- struct smbios_entry_point *ep_table = &data->smbios_ep_table;
+ struct smbios_21_entry_point *ep_table = &data->smbios_ep_table;
uint32_t addr = data->smbios_ep_addr;
ACPI_READ_ARRAY(ep_table->anchor_string, addr);
@@ -681,7 +681,7 @@ static inline bool smbios_single_instance(uint8_t type)
static void test_smbios_structs(test_data *data)
{
DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
- struct smbios_entry_point *ep_table = &data->smbios_ep_table;
+ struct smbios_21_entry_point *ep_table = &data->smbios_ep_table;
uint32_t addr = ep_table->structure_table_address;
int i, len, max_len = 0;
uint8_t type, prv, crt;
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 12/27] smbios: implement smbios support for mach-virt
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 11/27] smbios: add smbios 3.0 support Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 13/27] arm: cpu: assert() on no-EL2 virt IRQ error condition Peter Maydell
` (15 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Wei Huang <wei@redhat.com>
This patch generates smbios tables for ARM mach-virt. Also add
CONFIG_SMBIOS=y for ARM default config.
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Wei Huang <wei@redhat.com>
Message-id: 1440615870-9518-3-git-send-email-wei@redhat.com
[PMM: Added missing braces around an if().]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/virt.c | 26 ++++++++++++++++++++++++++
qemu-options.hx | 2 +-
3 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 74f1db3..99b41e9 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -102,3 +102,4 @@ CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
CONFIG_ACPI=y
+CONFIG_SMBIOS=y
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d5a8417..bbd061b 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -50,6 +50,7 @@
#include "hw/arm/fdt.h"
#include "hw/intc/arm_gic_common.h"
#include "kvm_arm.h"
+#include "hw/smbios/smbios.h"
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 256
@@ -788,12 +789,37 @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
return board->fdt;
}
+static void virt_build_smbios(VirtGuestInfo *guest_info)
+{
+ FWCfgState *fw_cfg = guest_info->fw_cfg;
+ uint8_t *smbios_tables, *smbios_anchor;
+ size_t smbios_tables_len, smbios_anchor_len;
+
+ if (!fw_cfg) {
+ return;
+ }
+
+ smbios_set_defaults("QEMU", "QEMU Virtual Machine",
+ "1.0", false, true, SMBIOS_ENTRY_POINT_30);
+
+ smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
+ &smbios_anchor, &smbios_anchor_len);
+
+ if (smbios_anchor) {
+ fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
+ smbios_tables, smbios_tables_len);
+ fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
+ smbios_anchor, smbios_anchor_len);
+ }
+}
+
static
void virt_guest_info_machine_done(Notifier *notifier, void *data)
{
VirtGuestInfoState *guest_info_state = container_of(notifier,
VirtGuestInfoState, machine_done);
virt_acpi_setup(&guest_info_state->info);
+ virt_build_smbios(&guest_info_state->info);
}
static void machvirt_init(MachineState *machine)
diff --git a/qemu-options.hx b/qemu-options.hx
index 77f5853..efce775 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1412,7 +1412,7 @@ DEF("smbios", HAS_ARG, QEMU_OPTION_smbios,
"-smbios type=17[,loc_pfx=str][,bank=str][,manufacturer=str][,serial=str]\n"
" [,asset=str][,part=str][,speed=%d]\n"
" specify SMBIOS type 17 fields\n",
- QEMU_ARCH_I386)
+ QEMU_ARCH_I386 | QEMU_ARCH_ARM)
STEXI
@item -smbios file=@var{binary}
@findex -smbios
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 13/27] arm: cpu: assert() on no-EL2 virt IRQ error condition.
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 12/27] smbios: implement smbios support for mach-virt Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 14/27] arm: Remove hw_error() usages Peter Maydell
` (14 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Peter Crosthwaite <crosthwaitepeter@gmail.com>
Replace the hw_error() for no-EL2 VIRQ with an assert.
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 93b6acdee6cafe8ff0422a294a5640c3d35f0e17.1440842587.git.crosthwaite.peter@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index cc6c6f3..4ba5929 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -331,10 +331,7 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level)
switch (irq) {
case ARM_CPU_VIRQ:
case ARM_CPU_VFIQ:
- if (!arm_feature(env, ARM_FEATURE_EL2)) {
- hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
- __func__, irq);
- }
+ assert(arm_feature(env, ARM_FEATURE_EL2));
/* fall through */
case ARM_CPU_IRQ:
case ARM_CPU_FIQ:
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 14/27] arm: Remove hw_error() usages.
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 13/27] arm: cpu: assert() on no-EL2 virt IRQ error condition Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 15/27] target-arm: Fix AArch32:AArch64 general-purpose register mapping Peter Maydell
` (13 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Peter Crosthwaite <crosthwaitepeter@gmail.com>
All of these hw_errors are fatal and indicate something wrong with
QEMU implementation.
Convert to g_assert_not_reached.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 169194d09017e5725535d31a1507d454c0043706.1440842587.git.crosthwaite.peter@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 4 ++--
target-arm/helper.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 4ba5929..7da29f5 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -342,7 +342,7 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level)
}
break;
default:
- hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
+ g_assert_not_reached();
}
}
@@ -361,7 +361,7 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
break;
default:
- hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
+ g_assert_not_reached();
}
kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 114d56e..0df4dac 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4990,7 +4990,7 @@ int bank_number(int mode)
case ARM_CPU_MODE_MON:
return 7;
}
- hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
+ g_assert_not_reached();
}
void switch_mode(CPUARMState *env, int mode)
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 15/27] target-arm: Fix AArch32:AArch64 general-purpose register mapping
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 14/27] arm: Remove hw_error() usages Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 16/27] hw/arm/virt: Add high MMIO PCI region, 512G in size Peter Maydell
` (12 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Sergey Sorokin <afarallax@yandex.ru>
There is an error in functions aarch64_sync_32_to_64() and
aarch64_sync_64_to_32() with mapping of registers between AArch32 and
AArch64. This commit fixes the mapping to match the v8 ARM ARM
section D1.20.1 (table D1-77).
Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
Message-id: 1440796451-15276-1-git-send-email-afarallax@yandex.ru
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tidied commit message a bit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 64 ++++++++++++++++++++++++++---------------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0df4dac..040bc70 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5324,35 +5324,35 @@ void aarch64_sync_32_to_64(CPUARMState *env)
}
if (mode == ARM_CPU_MODE_IRQ) {
- env->xregs[16] = env->regs[13];
- env->xregs[17] = env->regs[14];
+ env->xregs[16] = env->regs[14];
+ env->xregs[17] = env->regs[13];
} else {
- env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
- env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
+ env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
+ env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
}
if (mode == ARM_CPU_MODE_SVC) {
- env->xregs[18] = env->regs[13];
- env->xregs[19] = env->regs[14];
+ env->xregs[18] = env->regs[14];
+ env->xregs[19] = env->regs[13];
} else {
- env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
- env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
+ env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
+ env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
}
if (mode == ARM_CPU_MODE_ABT) {
- env->xregs[20] = env->regs[13];
- env->xregs[21] = env->regs[14];
+ env->xregs[20] = env->regs[14];
+ env->xregs[21] = env->regs[13];
} else {
- env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
- env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
+ env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
+ env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
}
if (mode == ARM_CPU_MODE_UND) {
- env->xregs[22] = env->regs[13];
- env->xregs[23] = env->regs[14];
+ env->xregs[22] = env->regs[14];
+ env->xregs[23] = env->regs[13];
} else {
- env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
- env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
+ env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
+ env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
}
/* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
@@ -5429,35 +5429,35 @@ void aarch64_sync_64_to_32(CPUARMState *env)
}
if (mode == ARM_CPU_MODE_IRQ) {
- env->regs[13] = env->xregs[16];
- env->regs[14] = env->xregs[17];
+ env->regs[14] = env->xregs[16];
+ env->regs[13] = env->xregs[17];
} else {
- env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
- env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
+ env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
+ env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
}
if (mode == ARM_CPU_MODE_SVC) {
- env->regs[13] = env->xregs[18];
- env->regs[14] = env->xregs[19];
+ env->regs[14] = env->xregs[18];
+ env->regs[13] = env->xregs[19];
} else {
- env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
- env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
+ env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
+ env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
}
if (mode == ARM_CPU_MODE_ABT) {
- env->regs[13] = env->xregs[20];
- env->regs[14] = env->xregs[21];
+ env->regs[14] = env->xregs[20];
+ env->regs[13] = env->xregs[21];
} else {
- env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
- env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
+ env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
+ env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
}
if (mode == ARM_CPU_MODE_UND) {
- env->regs[13] = env->xregs[22];
- env->regs[14] = env->xregs[23];
+ env->regs[14] = env->xregs[22];
+ env->regs[13] = env->xregs[23];
} else {
- env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
- env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
+ env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
+ env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
}
/* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 16/27] hw/arm/virt: Add high MMIO PCI region, 512G in size
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 15/27] target-arm: Fix AArch32:AArch64 general-purpose register mapping Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function Peter Maydell
` (11 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Pavel Fedin <p.fedin@samsung.com>
This large region is necessary for some devices like ivshmem and video cards
32-bit kernels can be built without LPAE support. In this case such a kernel
will not be able to use PCI controller which has windows in high addresses.
In order to work around the problem, "highmem" option is introduced. It
defaults to on on, but can be manually set to off in order to be able to run
those old 32-bit guests.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
[PMM: Added missing ULL suffixes and a comment to the a15memmap[] entry]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt-acpi-build.c | 17 +++++++++--
hw/arm/virt.c | 66 +++++++++++++++++++++++++++++++++++-----
include/hw/arm/virt-acpi-build.h | 1 +
include/hw/arm/virt.h | 1 +
4 files changed, 76 insertions(+), 9 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index f365140..9088248 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -159,7 +159,8 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
}
-static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq)
+static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq,
+ bool use_highmem)
{
Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
int i, bus_no;
@@ -234,6 +235,17 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq)
AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
size_pio));
+ if (use_highmem) {
+ hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
+ hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
+
+ aml_append(rbuf,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
+ base_mmio_high, base_mmio_high, 0x0000,
+ size_mmio_high));
+ }
+
aml_append(method, aml_name_decl("RBUF", rbuf));
aml_append(method, aml_return(rbuf));
aml_append(dev, method);
@@ -510,7 +522,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
- acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE));
+ acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
+ guest_info->use_highmem);
aml_append(dsdt, scope);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index bbd061b..60736c2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -80,6 +80,7 @@ typedef struct {
typedef struct {
MachineState parent;
bool secure;
+ bool highmem;
} VirtMachineState;
#define TYPE_VIRT_MACHINE "virt"
@@ -120,6 +121,8 @@ static const MemMapEntry a15memmap[] = {
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
[VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
+ /* Second PCIe window, 512GB wide at the 512GB boundary */
+ [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
};
static const int a15irqmap[] = {
@@ -667,10 +670,13 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
0x7 /* PCI irq */);
}
-static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic)
+static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
+ bool use_highmem)
{
hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base;
hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size;
+ hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base;
+ hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size;
hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base;
hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size;
hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base;
@@ -707,6 +713,16 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic)
mmio_reg, base_mmio, size_mmio);
memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
+ if (use_highmem) {
+ /* Map high MMIO space */
+ MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
+
+ memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
+ mmio_reg, base_mmio_high, size_mmio_high);
+ memory_region_add_subregion(get_system_memory(), base_mmio_high,
+ high_mmio_alias);
+ }
+
/* Map IO port space */
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
@@ -728,11 +744,23 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic)
qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
2, base_ecam, 2, size_ecam);
- qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
- 1, FDT_PCI_RANGE_IOPORT, 2, 0,
- 2, base_pio, 2, size_pio,
- 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
- 2, base_mmio, 2, size_mmio);
+
+ if (use_highmem) {
+ qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
+ 1, FDT_PCI_RANGE_IOPORT, 2, 0,
+ 2, base_pio, 2, size_pio,
+ 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
+ 2, base_mmio, 2, size_mmio,
+ 1, FDT_PCI_RANGE_MMIO_64BIT,
+ 2, base_mmio_high,
+ 2, base_mmio_high, 2, size_mmio_high);
+ } else {
+ qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
+ 1, FDT_PCI_RANGE_IOPORT, 2, 0,
+ 2, base_pio, 2, size_pio,
+ 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
+ 2, base_mmio, 2, size_mmio);
+ }
qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1);
create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename);
@@ -915,7 +943,7 @@ static void machvirt_init(MachineState *machine)
create_rtc(vbi, pic);
- create_pcie(vbi, pic);
+ create_pcie(vbi, pic, vms->highmem);
/* Create mmio transports, so the user can create virtio backends
* (which will be automatically plugged in to the transports). If
@@ -930,6 +958,7 @@ static void machvirt_init(MachineState *machine)
guest_info->fw_cfg = fw_cfg_find();
guest_info->memmap = vbi->memmap;
guest_info->irqmap = vbi->irqmap;
+ guest_info->use_highmem = vms->highmem;
guest_info_state->machine_done.notify = virt_guest_info_machine_done;
qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
@@ -967,6 +996,20 @@ static void virt_set_secure(Object *obj, bool value, Error **errp)
vms->secure = value;
}
+static bool virt_get_highmem(Object *obj, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ return vms->highmem;
+}
+
+static void virt_set_highmem(Object *obj, bool value, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ vms->highmem = value;
+}
+
static void virt_instance_init(Object *obj)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -979,6 +1022,15 @@ static void virt_instance_init(Object *obj)
"Set on/off to enable/disable the ARM "
"Security Extensions (TrustZone)",
NULL);
+
+ /* High memory is enabled by default */
+ vms->highmem = true;
+ object_property_add_bool(obj, "highmem", virt_get_highmem,
+ virt_set_highmem, NULL);
+ object_property_set_description(obj, "highmem",
+ "Set on/off to enable/disable using "
+ "physical address space above 32 bits",
+ NULL);
}
static void virt_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
index 04f174d..19b68a4 100644
--- a/include/hw/arm/virt-acpi-build.h
+++ b/include/hw/arm/virt-acpi-build.h
@@ -31,6 +31,7 @@ typedef struct VirtGuestInfo {
FWCfgState *fw_cfg;
const MemMapEntry *memmap;
const int *irqmap;
+ bool use_highmem;
} VirtGuestInfo;
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index d22fd8e..808753f0 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -56,6 +56,7 @@ enum {
VIRT_PCIE_ECAM,
VIRT_GIC_V2M,
VIRT_PLATFORM_BUS,
+ VIRT_PCIE_MMIO_HIGH,
};
typedef struct MemMapEntry {
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 16/27] hw/arm/virt: Add high MMIO PCI region, 512G in size Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 18/27] i.MX: Add SOC support for i.MX31 Peter Maydell
` (10 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Sergey Sorokin <afarallax@yandex.ru>
There is an error in arm_excp_unmasked() function:
bitwise operator & is used with integer and bool operands
causing an incorrect zeroed result.
The patch fixes it.
Signed-off-by: Sergey Sorokin <afarallax@yandex.ru>
Message-id: 1441209238-16881-1-git-send-email-afarallax@yandex.ru
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c794afc..4bd5dc8 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1520,8 +1520,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
- uint32_t scr;
- uint32_t hcr;
+ bool scr;
+ bool hcr;
bool pstate_unmasked;
int8_t unmasked = 0;
@@ -1548,7 +1548,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
* set then FIQs can be masked by CPSR.F when non-secure but only
* when FIQs are only routed to EL3.
*/
- scr &= !((env->cp15.scr_el3 & SCR_FW) && !hcr);
+ scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
pstate_unmasked = !(env->daif & PSTATE_F);
break;
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 18/27] i.MX: Add SOC support for i.MX31
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 19/27] i.MX: KZM: use standalone i.MX31 SOC support Peter Maydell
` (9 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
For now we support the following devices:
* CPU: ARM1136
* Interrupt Controller: AVIC
* CCM
* UART x 2
* EPIT x 2
* GPT
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: f146d819594e41568daec42a1d0f440cdfe3df76.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 2 +
hw/arm/Makefile.objs | 3 +-
hw/arm/fsl-imx31.c | 216 ++++++++++++++++++++++++++++++++++++++++
include/hw/arm/fsl-imx31.h | 98 ++++++++++++++++++
4 files changed, 318 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/fsl-imx31.c
create mode 100644 include/hw/arm/fsl-imx31.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 99b41e9..e2fa1ee 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -98,6 +98,8 @@ CONFIG_ALLWINNER_A10_PIT=y
CONFIG_ALLWINNER_A10_PIC=y
CONFIG_ALLWINNER_A10=y
+CONFIG_FSL_IMX31=y
+
CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index cf346c1..2fbe344 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -1,6 +1,6 @@
obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o
obj-$(CONFIG_DIGIC) += digic_boards.o
-obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
+obj-y += integratorcp.o mainstone.o musicpal.o nseries.o
obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
obj-$(CONFIG_ACPI) += virt-acpi-build.o
@@ -13,3 +13,4 @@ obj-y += omap1.o omap2.o strongarm.o
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
+obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
new file mode 100644
index 0000000..1681ecf
--- /dev/null
+++ b/hw/arm/fsl-imx31.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * i.MX31 SOC emulation.
+ *
+ * Based on hw/arm/fsl-imx31.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/arm/fsl-imx31.h"
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "sysemu/char.h"
+
+static void fsl_imx31_init(Object *obj)
+{
+ FslIMX31State *s = FSL_IMX31(obj);
+ int i;
+
+ object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
+
+ object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
+ qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
+
+ object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM);
+ qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
+
+ for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
+ object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
+ qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
+ }
+
+ object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
+ qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
+
+ for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
+ object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
+ qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
+ }
+}
+
+static void fsl_imx31_realize(DeviceState *dev, Error **errp)
+{
+ FslIMX31State *s = FSL_IMX31(dev);
+ uint16_t i;
+ Error *err = NULL;
+
+ object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
+ qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
+ qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
+
+ object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
+
+ /* Initialize all UARTS */
+ for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } serial_table[FSL_IMX31_NUM_UARTS] = {
+ { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
+ { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
+ };
+
+ if (i < MAX_SERIAL_PORTS) {
+ CharDriverState *chr;
+
+ chr = serial_hds[i];
+
+ if (!chr) {
+ char label[20];
+ snprintf(label, sizeof(label), "imx31.uart%d", i);
+ chr = qemu_chr_new(label, "null", NULL);
+ }
+
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+ }
+
+ object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ serial_table[i].irq));
+ }
+
+ s->gpt.ccm = DEVICE(&s->ccm);
+
+ object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
+
+ /* Initialize all EPIT timers */
+ for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } epit_table[FSL_IMX31_NUM_EPITS] = {
+ { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
+ { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
+ };
+
+ s->epit[i].ccm = DEVICE(&s->ccm);
+
+ object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ epit_table[i].irq));
+ }
+
+ /* On a real system, the first 16k is a `secure boot rom' */
+ memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL,
+ "imx31.secure_rom",
+ FSL_IMX31_SECURE_ROM_SIZE, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
+ &s->secure_rom);
+
+ /* There is also a 16k ROM */
+ memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx31.rom",
+ FSL_IMX31_ROM_SIZE, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
+ &s->rom);
+
+ /* initialize internal RAM (16 KB) */
+ memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
+ &s->iram);
+ vmstate_register_ram_global(&s->iram);
+
+ /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
+ memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
+ &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
+ &s->iram_alias);
+}
+
+static void fsl_imx31_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = fsl_imx31_realize;
+}
+
+static const TypeInfo fsl_imx31_type_info = {
+ .name = TYPE_FSL_IMX31,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(FslIMX31State),
+ .instance_init = fsl_imx31_init,
+ .class_init = fsl_imx31_class_init,
+};
+
+static void fsl_imx31_register_types(void)
+{
+ type_register_static(&fsl_imx31_type_info);
+}
+
+type_init(fsl_imx31_register_types)
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
new file mode 100644
index 0000000..09508e3
--- /dev/null
+++ b/include/hw/arm/fsl-imx31.h
@@ -0,0 +1,98 @@
+/*
+ * Freescale i.MX31 SoC emulation
+ *
+ * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef FSL_IMX31_H
+#define FSL_IMX31_H
+
+#include "hw/arm/arm.h"
+#include "hw/intc/imx_avic.h"
+#include "hw/misc/imx_ccm.h"
+#include "hw/char/imx_serial.h"
+#include "hw/timer/imx_gpt.h"
+#include "hw/timer/imx_epit.h"
+#include "exec/memory.h"
+
+#define TYPE_FSL_IMX31 "fsl,imx31"
+#define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)
+
+#define FSL_IMX31_NUM_UARTS 2
+#define FSL_IMX31_NUM_EPITS 2
+
+typedef struct FslIMX31State {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ ARMCPU cpu;
+ IMXAVICState avic;
+ IMXCCMState ccm;
+ IMXSerialState uart[FSL_IMX31_NUM_UARTS];
+ IMXGPTState gpt;
+ IMXEPITState epit[FSL_IMX31_NUM_EPITS];
+ MemoryRegion secure_rom;
+ MemoryRegion rom;
+ MemoryRegion iram;
+ MemoryRegion iram_alias;
+} FslIMX31State;
+
+#define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
+#define FSL_IMX31_SECURE_ROM_SIZE 0x4000
+#define FSL_IMX31_ROM_ADDR 0x00404000
+#define FSL_IMX31_ROM_SIZE 0x4000
+#define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000
+#define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
+#define FSL_IMX31_IRAM_ADDR 0x1FFFC000
+#define FSL_IMX31_IRAM_SIZE 0x4000
+#define FSL_IMX31_UART1_ADDR 0x43F90000
+#define FSL_IMX31_UART1_SIZE 0x4000
+#define FSL_IMX31_UART2_ADDR 0x43F94000
+#define FSL_IMX31_UART2_SIZE 0x4000
+#define FSL_IMX31_CCM_ADDR 0x53F80000
+#define FSL_IMX31_CCM_SIZE 0x4000
+#define FSL_IMX31_GPT_ADDR 0x53F90000
+#define FSL_IMX31_GPT_SIZE 0x4000
+#define FSL_IMX31_EPIT1_ADDR 0x53F94000
+#define FSL_IMX31_EPIT1_SIZE 0x4000
+#define FSL_IMX31_EPIT2_ADDR 0x53F98000
+#define FSL_IMX31_EPIT2_SIZE 0x4000
+#define FSL_IMX31_AVIC_ADDR 0x68000000
+#define FSL_IMX31_AVIC_SIZE 0x100
+#define FSL_IMX31_SDRAM0_ADDR 0x80000000
+#define FSL_IMX31_SDRAM0_SIZE 0x10000000
+#define FSL_IMX31_SDRAM1_ADDR 0x90000000
+#define FSL_IMX31_SDRAM1_SIZE 0x10000000
+#define FSL_IMX31_FLASH0_ADDR 0xA0000000
+#define FSL_IMX31_FLASH0_SIZE 0x8000000
+#define FSL_IMX31_FLASH1_ADDR 0xA8000000
+#define FSL_IMX31_FLASH1_SIZE 0x8000000
+#define FSL_IMX31_CS2_ADDR 0xB0000000
+#define FSL_IMX31_CS2_SIZE 0x2000000
+#define FSL_IMX31_CS3_ADDR 0xB2000000
+#define FSL_IMX31_CS3_SIZE 0x2000000
+#define FSL_IMX31_CS4_ADDR 0xB4000000
+#define FSL_IMX31_CS4_SIZE 0x2000000
+#define FSL_IMX31_CS5_ADDR 0xB6000000
+#define FSL_IMX31_CS5_SIZE 0x2000000
+#define FSL_IMX31_NAND_ADDR 0xB8000000
+#define FSL_IMX31_NAND_SIZE 0x1000
+
+#define FSL_IMX31_EPIT2_IRQ 27
+#define FSL_IMX31_EPIT1_IRQ 28
+#define FSL_IMX31_GPT_IRQ 29
+#define FSL_IMX31_UART2_IRQ 32
+#define FSL_IMX31_UART1_IRQ 45
+
+#endif /* FSL_IMX31_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 19/27] i.MX: KZM: use standalone i.MX31 SOC support
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 18/27] i.MX: Add SOC support for i.MX31 Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 20/27] i.MX: Add I2C controller emulator Peter Maydell
` (8 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
Convert the KZM board to use the i.MX31 SoC defintition instead of
redefining the entire SoC on the machine level. Major rewrite of the
machine init code.
While touching the memory map comment de-indent to the correct level
of indentation.
This obsoletes the legacy i.MX device device creation helpers which are removed.
Tested by booting a minimal Linux system on the emulated platform
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 5e783561f092e1c939562fdff001f1ab1194b07f.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/kzm.c | 205 +++++++++++++++++++++++++--------------------------
hw/char/imx_serial.c | 35 ---------
hw/timer/imx_epit.c | 11 ---
hw/timer/imx_gpt.c | 11 ---
include/hw/arm/imx.h | 26 -------
5 files changed, 102 insertions(+), 186 deletions(-)
delete mode 100644 include/hw/arm/imx.h
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index d7af230..241b1d7 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -13,131 +13,130 @@
* i.MX31 SoC
*/
-#include "hw/sysbus.h"
+#include "hw/arm/fsl-imx31.h"
+#include "hw/boards.h"
+#include "qemu/error-report.h"
#include "exec/address-spaces.h"
-#include "hw/hw.h"
-#include "hw/arm/arm.h"
-#include "hw/devices.h"
#include "net/net.h"
-#include "sysemu/sysemu.h"
-#include "hw/boards.h"
+#include "hw/devices.h"
#include "hw/char/serial.h"
-#include "hw/intc/imx_avic.h"
-#include "hw/arm/imx.h"
-
- /* Memory map for Kzm Emulation Baseboard:
- * 0x00000000-0x00003fff 16k secure ROM IGNORED
- * 0x00004000-0x00407fff Reserved IGNORED
- * 0x00404000-0x00407fff ROM IGNORED
- * 0x00408000-0x0fffffff Reserved IGNORED
- * 0x10000000-0x1fffbfff RAM aliasing IGNORED
- * 0x1fffc000-0x1fffffff RAM EMULATED
- * 0x20000000-0x2fffffff Reserved IGNORED
- * 0x30000000-0x7fffffff I.MX31 Internal Register Space
- * 0x43f00000 IO_AREA0
- * 0x43f90000 UART1 EMULATED
- * 0x43f94000 UART2 EMULATED
- * 0x68000000 AVIC EMULATED
- * 0x53f80000 CCM EMULATED
- * 0x53f94000 PIT 1 EMULATED
- * 0x53f98000 PIT 2 EMULATED
- * 0x53f90000 GPT EMULATED
- * 0x80000000-0x87ffffff RAM EMULATED
- * 0x88000000-0x8fffffff RAM Aliasing EMULATED
- * 0xa0000000-0xafffffff NAND Flash IGNORED
- * 0xb0000000-0xb3ffffff Unavailable IGNORED
- * 0xb4000000-0xb4000fff 8-bit free space IGNORED
- * 0xb4001000-0xb400100f Board control IGNORED
- * 0xb4001003 DIP switch
- * 0xb4001010-0xb400101f 7-segment LED IGNORED
- * 0xb4001020-0xb400102f LED IGNORED
- * 0xb4001030-0xb400103f LED IGNORED
- * 0xb4001040-0xb400104f FPGA, UART EMULATED
- * 0xb4001050-0xb400105f FPGA, UART EMULATED
- * 0xb4001060-0xb40fffff FPGA IGNORED
- * 0xb6000000-0xb61fffff LAN controller EMULATED
- * 0xb6200000-0xb62fffff FPGA NAND Controller IGNORED
- * 0xb6300000-0xb7ffffff Free IGNORED
- * 0xb8000000-0xb8004fff Memory control registers IGNORED
- * 0xc0000000-0xc3ffffff PCMCIA/CF IGNORED
- * 0xc4000000-0xffffffff Reserved IGNORED
- */
-
-#define KZM_RAMADDRESS (0x80000000)
-#define KZM_FPGA (0xb4001040)
+#include "sysemu/qtest.h"
+
+/* Memory map for Kzm Emulation Baseboard:
+ * 0x00000000-0x7fffffff See i.MX31 SOC for support
+ * 0x80000000-0x8fffffff RAM EMULATED
+ * 0x90000000-0x9fffffff RAM EMULATED
+ * 0xa0000000-0xafffffff Flash IGNORED
+ * 0xb0000000-0xb3ffffff Unavailable IGNORED
+ * 0xb4000000-0xb4000fff 8-bit free space IGNORED
+ * 0xb4001000-0xb400100f Board control IGNORED
+ * 0xb4001003 DIP switch
+ * 0xb4001010-0xb400101f 7-segment LED IGNORED
+ * 0xb4001020-0xb400102f LED IGNORED
+ * 0xb4001030-0xb400103f LED IGNORED
+ * 0xb4001040-0xb400104f FPGA, UART EMULATED
+ * 0xb4001050-0xb400105f FPGA, UART EMULATED
+ * 0xb4001060-0xb40fffff FPGA IGNORED
+ * 0xb6000000-0xb61fffff LAN controller EMULATED
+ * 0xb6200000-0xb62fffff FPGA NAND Controller IGNORED
+ * 0xb6300000-0xb7ffffff Free IGNORED
+ * 0xb8000000-0xb8004fff Memory control registers IGNORED
+ * 0xc0000000-0xc3ffffff PCMCIA/CF IGNORED
+ * 0xc4000000-0xffffffff Reserved IGNORED
+ */
+
+typedef struct IMX31KZM {
+ FslIMX31State soc;
+ MemoryRegion ram;
+ MemoryRegion ram_alias;
+} IMX31KZM;
+
+#define KZM_RAM_ADDR (FSL_IMX31_SDRAM0_ADDR)
+#define KZM_FPGA_ADDR (FSL_IMX31_CS4_ADDR + 0x1040)
+#define KZM_LAN9118_ADDR (FSL_IMX31_CS5_ADDR)
static struct arm_boot_info kzm_binfo = {
- .loader_start = KZM_RAMADDRESS,
+ .loader_start = KZM_RAM_ADDR,
.board_id = 1722,
};
static void kzm_init(MachineState *machine)
{
- ram_addr_t ram_size = machine->ram_size;
- const char *cpu_model = machine->cpu_model;
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
- ARMCPU *cpu;
- MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
- MemoryRegion *sram = g_new(MemoryRegion, 1);
- MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
- DeviceState *dev;
- DeviceState *ccm;
-
- if (!cpu_model) {
- cpu_model = "arm1136";
- }
-
- cpu = cpu_arm_init(cpu_model);
- if (!cpu) {
- fprintf(stderr, "Unable to find CPU definition\n");
+ IMX31KZM *s = g_new0(IMX31KZM, 1);
+ Error *err = NULL;
+ unsigned int ram_size;
+ unsigned int alias_offset;
+ unsigned int i;
+
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX31);
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
+ &error_abort);
+
+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
+ if (err != NULL) {
+ error_report("%s", error_get_pretty(err));
exit(1);
}
- /* On a real system, the first 16k is a `secure boot rom' */
-
- memory_region_allocate_system_memory(ram, NULL, "kzm.ram", ram_size);
- memory_region_add_subregion(address_space_mem, KZM_RAMADDRESS, ram);
-
- memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
- memory_region_add_subregion(address_space_mem, 0x88000000, ram_alias);
-
- memory_region_init_ram(sram, NULL, "kzm.sram", 0x4000, &error_abort);
- memory_region_add_subregion(address_space_mem, 0x1FFFC000, sram);
-
- dev = sysbus_create_varargs(TYPE_IMX_AVIC, 0x68000000,
- qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
- qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
- NULL);
-
- imx_serial_create(0, 0x43f90000, qdev_get_gpio_in(dev, 45));
- imx_serial_create(1, 0x43f94000, qdev_get_gpio_in(dev, 32));
-
- ccm = sysbus_create_simple(TYPE_IMX_CCM, 0x53f80000, NULL);
+ /* Check the amount of memory is compatible with the SOC */
+ if (machine->ram_size > (FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE)) {
+ error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
+ "reduced to %x", machine->ram_size,
+ FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE);
+ machine->ram_size = FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE;
+ }
- imx_timerp_create(0x53f94000, qdev_get_gpio_in(dev, 28), ccm);
- imx_timerp_create(0x53f98000, qdev_get_gpio_in(dev, 27), ccm);
- imx_timerg_create(0x53f90000, qdev_get_gpio_in(dev, 29), ccm);
+ memory_region_allocate_system_memory(&s->ram, NULL, "kzm.ram",
+ machine->ram_size);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX31_SDRAM0_ADDR,
+ &s->ram);
+
+ /* initialize the alias memory if any */
+ for (i = 0, ram_size = machine->ram_size, alias_offset = 0;
+ (i < 2) && ram_size; i++) {
+ unsigned int size;
+ static const struct {
+ hwaddr addr;
+ unsigned int size;
+ } ram[2] = {
+ { FSL_IMX31_SDRAM0_ADDR, FSL_IMX31_SDRAM0_SIZE },
+ { FSL_IMX31_SDRAM1_ADDR, FSL_IMX31_SDRAM1_SIZE },
+ };
+
+ size = MIN(ram_size, ram[i].size);
+
+ ram_size -= size;
+
+ if (size < ram[i].size) {
+ memory_region_init_alias(&s->ram_alias, NULL, "ram.alias",
+ &s->ram, alias_offset, ram[i].size - size);
+ memory_region_add_subregion(get_system_memory(),
+ ram[i].addr + size, &s->ram_alias);
+ }
+
+ alias_offset += ram[i].size;
+ }
if (nd_table[0].used) {
- lan9118_init(&nd_table[0], 0xb6000000, qdev_get_gpio_in(dev, 52));
+ lan9118_init(&nd_table[0], KZM_LAN9118_ADDR,
+ qdev_get_gpio_in(DEVICE(&s->soc.avic), 52));
}
if (serial_hds[2]) { /* touchscreen */
- serial_mm_init(address_space_mem, KZM_FPGA+0x10, 0,
- qdev_get_gpio_in(dev, 52),
- 14745600, serial_hds[2],
- DEVICE_NATIVE_ENDIAN);
+ serial_mm_init(get_system_memory(), KZM_FPGA_ADDR+0x10, 0,
+ qdev_get_gpio_in(DEVICE(&s->soc.avic), 52),
+ 14745600, serial_hds[2], DEVICE_NATIVE_ENDIAN);
}
- kzm_binfo.ram_size = ram_size;
- kzm_binfo.kernel_filename = kernel_filename;
- kzm_binfo.kernel_cmdline = kernel_cmdline;
- kzm_binfo.initrd_filename = initrd_filename;
+ kzm_binfo.ram_size = machine->ram_size;
+ kzm_binfo.kernel_filename = machine->kernel_filename;
+ kzm_binfo.kernel_cmdline = machine->kernel_cmdline;
+ kzm_binfo.initrd_filename = machine->initrd_filename;
kzm_binfo.nb_cpus = 1;
- arm_load_kernel(cpu, &kzm_binfo);
+
+ if (!qtest_enabled()) {
+ arm_load_kernel(&s->soc.cpu, &kzm_binfo);
+ }
}
static QEMUMachine kzm_machine = {
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 801156d..e8f32c4 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -21,7 +21,6 @@
#include "hw/char/imx_serial.h"
#include "sysemu/sysemu.h"
#include "sysemu/char.h"
-#include "hw/arm/imx.h"
//#define DEBUG_SERIAL 1
#ifdef DEBUG_SERIAL
@@ -334,40 +333,6 @@ static void imx_serial_init(Object *obj)
sysbus_init_irq(sbd, &s->irq);
}
-void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
-{
- DeviceState *dev;
- SysBusDevice *bus;
- CharDriverState *chr;
- const char chr_name[] = "serial";
- char label[ARRAY_SIZE(chr_name) + 1];
-
- dev = qdev_create(NULL, TYPE_IMX_SERIAL);
-
- if (uart >= MAX_SERIAL_PORTS) {
- hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
- uart, MAX_SERIAL_PORTS);
- }
- chr = serial_hds[uart];
- if (!chr) {
- snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart);
- chr = qemu_chr_new(label, "null", NULL);
- if (!(chr)) {
- hw_error("Can't assign serial port to imx-uart%d.\n", uart);
- }
- }
-
- qdev_prop_set_chr(dev, "chardev", chr);
- bus = SYS_BUS_DEVICE(dev);
- qdev_init_nofail(dev);
- if (addr != (hwaddr)-1) {
- sysbus_mmio_map(bus, 0, addr);
- }
- sysbus_connect_irq(bus, 0, irq);
-
-}
-
-
static Property imx_serial_properties[] = {
DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
DEFINE_PROP_END_OF_LIST(),
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 10c5d2b..9649851 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -12,7 +12,6 @@
*
*/
-#include "hw/arm/imx.h"
#include "hw/timer/imx_epit.h"
#include "hw/misc/imx_ccm.h"
#include "qemu/main-loop.h"
@@ -287,16 +286,6 @@ static void imx_epit_cmp(void *opaque)
imx_epit_update_int(s);
}
-void imx_timerp_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm)
-{
- IMXEPITState *pp;
- DeviceState *dev;
-
- dev = sysbus_create_simple(TYPE_IMX_EPIT, addr, irq);
- pp = IMX_EPIT(dev);
- pp->ccm = ccm;
-}
-
static const MemoryRegionOps imx_epit_ops = {
.read = imx_epit_read,
.write = imx_epit_write,
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 01f802e..4bac67d 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -12,7 +12,6 @@
*
*/
-#include "hw/arm/imx.h"
#include "hw/timer/imx_gpt.h"
#include "hw/misc/imx_ccm.h"
#include "qemu/main-loop.h"
@@ -449,16 +448,6 @@ static void imx_gpt_realize(DeviceState *dev, Error **errp)
s->timer = ptimer_init(bh);
}
-void imx_timerg_create(const hwaddr addr, qemu_irq irq, DeviceState *ccm)
-{
- IMXGPTState *pp;
- DeviceState *dev;
-
- dev = sysbus_create_simple(TYPE_IMX_GPT, addr, irq);
- pp = IMX_GPT(dev);
- pp->ccm = ccm;
-}
-
static void imx_gpt_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/include/hw/arm/imx.h b/include/hw/arm/imx.h
deleted file mode 100644
index b188560..0000000
--- a/include/hw/arm/imx.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * i.MX31 emulation
- *
- * Copyright (C) 2012 Peter Chubb
- * NICTA
- *
- * This code is released under the GPL, version 2.0 or later
- * See the file `../COPYING' for details.
- */
-
-#ifndef IMX_H
-#define IMX_H
-
-#include "hw/misc/imx_ccm.h"
-
-void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
-
-void imx_timerp_create(const hwaddr addr,
- qemu_irq irq,
- DeviceState *ccm);
-void imx_timerg_create(const hwaddr addr,
- qemu_irq irq,
- DeviceState *ccm);
-
-
-#endif /* IMX_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 20/27] i.MX: Add I2C controller emulator
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 19/27] i.MX: KZM: use standalone i.MX31 SOC support Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 21/27] i.MX: Add FEC Ethernet Emulator Peter Maydell
` (7 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
The slave mode is not implemented.
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 508dbf2ebe26ec383d3a12a1db5a7890ac8acf20.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 2 +
hw/i2c/Makefile.objs | 1 +
hw/i2c/imx_i2c.c | 339 ++++++++++++++++++++++++++++++++++++++++
include/hw/i2c/imx_i2c.h | 87 +++++++++++
4 files changed, 429 insertions(+)
create mode 100644 hw/i2c/imx_i2c.c
create mode 100644 include/hw/i2c/imx_i2c.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index e2fa1ee..df3ba8c 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -100,6 +100,8 @@ CONFIG_ALLWINNER_A10=y
CONFIG_FSL_IMX31=y
+CONFIG_IMX_I2C=y
+
CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index 0f13060..aeb8f38 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -4,4 +4,5 @@ common-obj-$(CONFIG_ACPI_X86) += smbus_ich9.o
common-obj-$(CONFIG_APM) += pm_smbus.o
common-obj-$(CONFIG_BITBANG_I2C) += bitbang_i2c.o
common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o
+common-obj-$(CONFIG_IMX_I2C) += imx_i2c.o
obj-$(CONFIG_OMAP) += omap_i2c.o
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
new file mode 100644
index 0000000..2568837
--- /dev/null
+++ b/hw/i2c/imx_i2c.c
@@ -0,0 +1,339 @@
+/*
+ * i.MX I2C Bus Serial Interface Emulation
+ *
+ * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "hw/i2c/imx_i2c.h"
+#include "hw/i2c/i2c.h"
+
+#ifndef IMX_I2C_DEBUG
+#define IMX_I2C_DEBUG 0
+#endif
+
+#if IMX_I2C_DEBUG
+#define DPRINT(fmt, args...) \
+ do { fprintf(stderr, "%s: "fmt, __func__, ## args); } while (0)
+
+static const char *imx_i2c_get_regname(unsigned offset)
+{
+ switch (offset) {
+ case IADR_ADDR:
+ return "IADR";
+ case IFDR_ADDR:
+ return "IFDR";
+ case I2CR_ADDR:
+ return "I2CR";
+ case I2SR_ADDR:
+ return "I2SR";
+ case I2DR_ADDR:
+ return "I2DR";
+ default:
+ return "[?]";
+ }
+}
+#else
+#define DPRINT(fmt, args...) do { } while (0)
+#endif
+
+static inline bool imx_i2c_is_enabled(IMXI2CState *s)
+{
+ return s->i2cr & I2CR_IEN;
+}
+
+static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s)
+{
+ return s->i2cr & I2CR_IIEN;
+}
+
+static inline bool imx_i2c_is_master(IMXI2CState *s)
+{
+ return s->i2cr & I2CR_MSTA;
+}
+
+static inline bool imx_i2c_direction_is_tx(IMXI2CState *s)
+{
+ return s->i2cr & I2CR_MTX;
+}
+
+static void imx_i2c_reset(DeviceState *dev)
+{
+ IMXI2CState *s = IMX_I2C(dev);
+
+ if (s->address != ADDR_RESET) {
+ i2c_end_transfer(s->bus);
+ }
+
+ s->address = ADDR_RESET;
+ s->iadr = IADR_RESET;
+ s->ifdr = IFDR_RESET;
+ s->i2cr = I2CR_RESET;
+ s->i2sr = I2SR_RESET;
+ s->i2dr_read = I2DR_RESET;
+ s->i2dr_write = I2DR_RESET;
+}
+
+static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
+{
+ /*
+ * raise an interrupt if the device is enabled and it is configured
+ * to generate some interrupts.
+ */
+ if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
+ s->i2sr |= I2SR_IIF;
+ qemu_irq_raise(s->irq);
+ }
+}
+
+static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint16_t value;
+ IMXI2CState *s = IMX_I2C(opaque);
+
+ switch (offset) {
+ case IADR_ADDR:
+ value = s->iadr;
+ break;
+ case IFDR_ADDR:
+ value = s->ifdr;
+ break;
+ case I2CR_ADDR:
+ value = s->i2cr;
+ break;
+ case I2SR_ADDR:
+ value = s->i2sr;
+ break;
+ case I2DR_ADDR:
+ value = s->i2dr_read;
+
+ if (imx_i2c_is_master(s)) {
+ int ret = 0xff;
+
+ if (s->address == ADDR_RESET) {
+ /* something is wrong as the address is not set */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Trying to read "
+ "without specifying the slave address\n",
+ TYPE_IMX_I2C, __func__);
+ } else if (s->i2cr & I2CR_MTX) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Trying to read "
+ "but MTX is set\n", TYPE_IMX_I2C, __func__);
+ } else {
+ /* get the next byte */
+ ret = i2c_recv(s->bus);
+
+ if (ret >= 0) {
+ imx_i2c_raise_interrupt(s);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: read failed "
+ "for device 0x%02x\n", TYPE_IMX_I2C,
+ __func__, s->address);
+ ret = 0xff;
+ }
+ }
+
+ s->i2dr_read = ret;
+ } else {
+ qemu_log_mask(LOG_UNIMP, "%s[%s]: slave mode not implemented\n",
+ TYPE_IMX_I2C, __func__);
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
+ TYPE_IMX_I2C, __func__, s->address);
+ value = 0;
+ break;
+ }
+
+ DPRINT("read %s [0x%02x] -> 0x%02x\n", imx_i2c_get_regname(offset),
+ (unsigned int)offset, value);
+
+ return (uint64_t)value;
+}
+
+static void imx_i2c_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ IMXI2CState *s = IMX_I2C(opaque);
+
+ DPRINT("write %s [0x%02x] <- 0x%02x\n", imx_i2c_get_regname(offset),
+ (unsigned int)offset, (int)value);
+
+ value &= 0xff;
+
+ switch (offset) {
+ case IADR_ADDR:
+ s->iadr = value & IADR_MASK;
+ /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
+ break;
+ case IFDR_ADDR:
+ s->ifdr = value & IFDR_MASK;
+ break;
+ case I2CR_ADDR:
+ if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) {
+ /* This is a soft reset. IADR is preserved during soft resets */
+ uint16_t iadr = s->iadr;
+ imx_i2c_reset(DEVICE(s));
+ s->iadr = iadr;
+ } else { /* normal write */
+ s->i2cr = value & I2CR_MASK;
+
+ if (imx_i2c_is_master(s)) {
+ /* set the bus to busy */
+ s->i2sr |= I2SR_IBB;
+ } else { /* slave mode */
+ /* bus is not busy anymore */
+ s->i2sr &= ~I2SR_IBB;
+
+ /*
+ * if we unset the master mode then it ends the ongoing
+ * transfer if any
+ */
+ if (s->address != ADDR_RESET) {
+ i2c_end_transfer(s->bus);
+ s->address = ADDR_RESET;
+ }
+ }
+
+ if (s->i2cr & I2CR_RSTA) { /* Restart */
+ /* if this is a restart then it ends the ongoing transfer */
+ if (s->address != ADDR_RESET) {
+ i2c_end_transfer(s->bus);
+ s->address = ADDR_RESET;
+ s->i2cr &= ~I2CR_RSTA;
+ }
+ }
+ }
+ break;
+ case I2SR_ADDR:
+ /*
+ * if the user writes 0 to IIF then lower the interrupt and
+ * reset the bit
+ */
+ if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) {
+ s->i2sr &= ~I2SR_IIF;
+ qemu_irq_lower(s->irq);
+ }
+
+ /*
+ * if the user writes 0 to IAL, reset the bit
+ */
+ if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) {
+ s->i2sr &= ~I2SR_IAL;
+ }
+
+ break;
+ case I2DR_ADDR:
+ /* if the device is not enabled, nothing to do */
+ if (!imx_i2c_is_enabled(s)) {
+ break;
+ }
+
+ s->i2dr_write = value & I2DR_MASK;
+
+ if (imx_i2c_is_master(s)) {
+ /* If this is the first write cycle then it is the slave addr */
+ if (s->address == ADDR_RESET) {
+ if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7),
+ extract32(s->i2dr_write, 0, 1))) {
+ /* if non zero is returned, the adress is not valid */
+ s->i2sr |= I2SR_RXAK;
+ } else {
+ s->address = s->i2dr_write;
+ s->i2sr &= ~I2SR_RXAK;
+ imx_i2c_raise_interrupt(s);
+ }
+ } else { /* This is a normal data write */
+ if (i2c_send(s->bus, s->i2dr_write)) {
+ /* if the target return non zero then end the transfer */
+ s->i2sr |= I2SR_RXAK;
+ s->address = ADDR_RESET;
+ i2c_end_transfer(s->bus);
+ } else {
+ s->i2sr &= ~I2SR_RXAK;
+ imx_i2c_raise_interrupt(s);
+ }
+ }
+ } else {
+ qemu_log_mask(LOG_UNIMP, "%s[%s]: slave mode not implemented\n",
+ TYPE_IMX_I2C, __func__);
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
+ TYPE_IMX_I2C, __func__, s->address);
+ break;
+ }
+}
+
+static const MemoryRegionOps imx_i2c_ops = {
+ .read = imx_i2c_read,
+ .write = imx_i2c_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 2,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription imx_i2c_vmstate = {
+ .name = TYPE_IMX_I2C,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16(address, IMXI2CState),
+ VMSTATE_UINT16(iadr, IMXI2CState),
+ VMSTATE_UINT16(ifdr, IMXI2CState),
+ VMSTATE_UINT16(i2cr, IMXI2CState),
+ VMSTATE_UINT16(i2sr, IMXI2CState),
+ VMSTATE_UINT16(i2dr_read, IMXI2CState),
+ VMSTATE_UINT16(i2dr_write, IMXI2CState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void imx_i2c_realize(DeviceState *dev, Error **errp)
+{
+ IMXI2CState *s = IMX_I2C(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
+ IMX_I2C_MEM_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
+ s->bus = i2c_init_bus(DEVICE(dev), "i2c");
+}
+
+static void imx_i2c_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &imx_i2c_vmstate;
+ dc->reset = imx_i2c_reset;
+ dc->realize = imx_i2c_realize;
+}
+
+static const TypeInfo imx_i2c_type_info = {
+ .name = TYPE_IMX_I2C,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMXI2CState),
+ .class_init = imx_i2c_class_init,
+};
+
+static void imx_i2c_register_types(void)
+{
+ type_register_static(&imx_i2c_type_info);
+}
+
+type_init(imx_i2c_register_types)
diff --git a/include/hw/i2c/imx_i2c.h b/include/hw/i2c/imx_i2c.h
new file mode 100644
index 0000000..e2ee8ea
--- /dev/null
+++ b/include/hw/i2c/imx_i2c.h
@@ -0,0 +1,87 @@
+/*
+ * i.MX I2C Bus Serial Interface registers definition
+ *
+ * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef __IMX_I2C_H_
+#define __IMX_I2C_H_
+
+#include <hw/sysbus.h>
+
+#define TYPE_IMX_I2C "imx.i2c"
+#define IMX_I2C(obj) OBJECT_CHECK(IMXI2CState, (obj), TYPE_IMX_I2C)
+
+#define IMX_I2C_MEM_SIZE 0x14
+
+/* i.MX I2C memory map */
+#define IADR_ADDR 0x00 /* address register */
+#define IFDR_ADDR 0x04 /* frequency divider register */
+#define I2CR_ADDR 0x08 /* control register */
+#define I2SR_ADDR 0x0c /* status register */
+#define I2DR_ADDR 0x10 /* data register */
+
+#define IADR_MASK 0xFE
+#define IADR_RESET 0
+
+#define IFDR_MASK 0x3F
+#define IFDR_RESET 0
+
+#define I2CR_IEN (1 << 7)
+#define I2CR_IIEN (1 << 6)
+#define I2CR_MSTA (1 << 5)
+#define I2CR_MTX (1 << 4)
+#define I2CR_TXAK (1 << 3)
+#define I2CR_RSTA (1 << 2)
+#define I2CR_MASK 0xFC
+#define I2CR_RESET 0
+
+#define I2SR_ICF (1 << 7)
+#define I2SR_IAAF (1 << 6)
+#define I2SR_IBB (1 << 5)
+#define I2SR_IAL (1 << 4)
+#define I2SR_SRW (1 << 2)
+#define I2SR_IIF (1 << 1)
+#define I2SR_RXAK (1 << 0)
+#define I2SR_MASK 0xE9
+#define I2SR_RESET 0x81
+
+#define I2DR_MASK 0xFF
+#define I2DR_RESET 0
+
+#define ADDR_RESET 0xFF00
+
+typedef struct IMXI2CState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ I2CBus *bus;
+ qemu_irq irq;
+
+ uint16_t address;
+
+ uint16_t iadr;
+ uint16_t ifdr;
+ uint16_t i2cr;
+ uint16_t i2sr;
+ uint16_t i2dr_read;
+ uint16_t i2dr_write;
+} IMXI2CState;
+
+#endif /* __IMX_I2C_H_ */
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 21/27] i.MX: Add FEC Ethernet Emulator
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 20/27] i.MX: Add I2C controller emulator Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 22/27] i.MX: Add SOC support for i.MX25 Peter Maydell
` (6 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
This is based on mcf_fec.c FEC implementation for Coldfire
* A generic PHY was added (borrowwed from LAN9118)
* The buffer management is also modified as buffers are
slightly different between Coldfire and i.MX
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: fb314f8a120aa49f8f6ad886f312c649b484fb5a.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/net/Makefile.objs | 1 +
hw/net/imx_fec.c | 709 ++++++++++++++++++++++++++++++++++++++++
include/hw/net/imx_fec.h | 113 +++++++
4 files changed, 824 insertions(+)
create mode 100644 hw/net/imx_fec.c
create mode 100644 include/hw/net/imx_fec.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index df3ba8c..7d900f5 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -28,6 +28,7 @@ CONFIG_SSI_M25P80=y
CONFIG_LAN9118=y
CONFIG_SMC91C111=y
CONFIG_ALLWINNER_EMAC=y
+CONFIG_IMX_FEC=y
CONFIG_DS1338=y
CONFIG_PFLASH_CFI01=y
CONFIG_PFLASH_CFI02=y
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
index 9880173..64d0449 100644
--- a/hw/net/Makefile.objs
+++ b/hw/net/Makefile.objs
@@ -19,6 +19,7 @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
common-obj-$(CONFIG_MIPSNET) += mipsnet.o
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
common-obj-$(CONFIG_ALLWINNER_EMAC) += allwinner_emac.o
+common-obj-$(CONFIG_IMX_FEC) += imx_fec.o
common-obj-$(CONFIG_CADENCE) += cadence_gem.o
common-obj-$(CONFIG_STELLARIS_ENET) += stellaris_enet.o
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
new file mode 100644
index 0000000..725f3fa
--- /dev/null
+++ b/hw/net/imx_fec.c
@@ -0,0 +1,709 @@
+/*
+ * i.MX Fast Ethernet Controller emulation.
+ *
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
+ *
+ * Based on Coldfire Fast Ethernet Controller emulation.
+ *
+ * Copyright (c) 2007 CodeSourcery.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/net/imx_fec.h"
+#include "sysemu/dma.h"
+
+/* For crc32 */
+#include <zlib.h>
+
+#ifndef IMX_FEC_DEBUG
+#define IMX_FEC_DEBUG 0
+#endif
+
+#ifndef IMX_PHY_DEBUG
+#define IMX_PHY_DEBUG 0
+#endif
+
+#if IMX_FEC_DEBUG
+#define FEC_PRINTF(fmt, ...) \
+ do { fprintf(stderr, "%s[%s]: " fmt , TYPE_IMX_FEC, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define FEC_PRINTF(fmt, ...) do {} while (0)
+#endif
+
+#if IMX_PHY_DEBUG
+#define PHY_PRINTF(fmt, ...) \
+ do { fprintf(stderr, "%s.phy[%s]: " fmt , TYPE_IMX_FEC, __func__, \
+ ## __VA_ARGS__); \
+ } while (0)
+#else
+#define PHY_PRINTF(fmt, ...) do {} while (0)
+#endif
+
+static const VMStateDescription vmstate_imx_fec = {
+ .name = TYPE_IMX_FEC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(irq_state, IMXFECState),
+ VMSTATE_UINT32(eir, IMXFECState),
+ VMSTATE_UINT32(eimr, IMXFECState),
+ VMSTATE_UINT32(rx_enabled, IMXFECState),
+ VMSTATE_UINT32(rx_descriptor, IMXFECState),
+ VMSTATE_UINT32(tx_descriptor, IMXFECState),
+ VMSTATE_UINT32(ecr, IMXFECState),
+ VMSTATE_UINT32(mmfr, IMXFECState),
+ VMSTATE_UINT32(mscr, IMXFECState),
+ VMSTATE_UINT32(mibc, IMXFECState),
+ VMSTATE_UINT32(rcr, IMXFECState),
+ VMSTATE_UINT32(tcr, IMXFECState),
+ VMSTATE_UINT32(tfwr, IMXFECState),
+ VMSTATE_UINT32(frsr, IMXFECState),
+ VMSTATE_UINT32(erdsr, IMXFECState),
+ VMSTATE_UINT32(etdsr, IMXFECState),
+ VMSTATE_UINT32(emrbr, IMXFECState),
+ VMSTATE_UINT32(miigsk_cfgr, IMXFECState),
+ VMSTATE_UINT32(miigsk_enr, IMXFECState),
+
+ VMSTATE_UINT32(phy_status, IMXFECState),
+ VMSTATE_UINT32(phy_control, IMXFECState),
+ VMSTATE_UINT32(phy_advertise, IMXFECState),
+ VMSTATE_UINT32(phy_int, IMXFECState),
+ VMSTATE_UINT32(phy_int_mask, IMXFECState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+#define PHY_INT_ENERGYON (1 << 7)
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
+#define PHY_INT_FAULT (1 << 5)
+#define PHY_INT_DOWN (1 << 4)
+#define PHY_INT_AUTONEG_LP (1 << 3)
+#define PHY_INT_PARFAULT (1 << 2)
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
+
+static void imx_fec_update(IMXFECState *s);
+
+/*
+ * The MII phy could raise a GPIO to the processor which in turn
+ * could be handled as an interrpt by the OS.
+ * For now we don't handle any GPIO/interrupt line, so the OS will
+ * have to poll for the PHY status.
+ */
+static void phy_update_irq(IMXFECState *s)
+{
+ imx_fec_update(s);
+}
+
+static void phy_update_link(IMXFECState *s)
+{
+ /* Autonegotiation status mirrors link status. */
+ if (qemu_get_queue(s->nic)->link_down) {
+ PHY_PRINTF("link is down\n");
+ s->phy_status &= ~0x0024;
+ s->phy_int |= PHY_INT_DOWN;
+ } else {
+ PHY_PRINTF("link is up\n");
+ s->phy_status |= 0x0024;
+ s->phy_int |= PHY_INT_ENERGYON;
+ s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
+ }
+ phy_update_irq(s);
+}
+
+static void imx_fec_set_link(NetClientState *nc)
+{
+ phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
+}
+
+static void phy_reset(IMXFECState *s)
+{
+ s->phy_status = 0x7809;
+ s->phy_control = 0x3000;
+ s->phy_advertise = 0x01e1;
+ s->phy_int_mask = 0;
+ s->phy_int = 0;
+ phy_update_link(s);
+}
+
+static uint32_t do_phy_read(IMXFECState *s, int reg)
+{
+ uint32_t val;
+
+ if (reg > 31) {
+ /* we only advertise one phy */
+ return 0;
+ }
+
+ switch (reg) {
+ case 0: /* Basic Control */
+ val = s->phy_control;
+ break;
+ case 1: /* Basic Status */
+ val = s->phy_status;
+ break;
+ case 2: /* ID1 */
+ val = 0x0007;
+ break;
+ case 3: /* ID2 */
+ val = 0xc0d1;
+ break;
+ case 4: /* Auto-neg advertisement */
+ val = s->phy_advertise;
+ break;
+ case 5: /* Auto-neg Link Partner Ability */
+ val = 0x0f71;
+ break;
+ case 6: /* Auto-neg Expansion */
+ val = 1;
+ break;
+ case 29: /* Interrupt source. */
+ val = s->phy_int;
+ s->phy_int = 0;
+ phy_update_irq(s);
+ break;
+ case 30: /* Interrupt mask */
+ val = s->phy_int_mask;
+ break;
+ case 17:
+ case 18:
+ case 27:
+ case 31:
+ qemu_log_mask(LOG_UNIMP, "%s.phy[%s]: reg %d not implemented\n",
+ TYPE_IMX_FEC, __func__, reg);
+ val = 0;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
+ TYPE_IMX_FEC, __func__, reg);
+ val = 0;
+ break;
+ }
+
+ PHY_PRINTF("read 0x%04x @ %d\n", val, reg);
+
+ return val;
+}
+
+static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
+{
+ PHY_PRINTF("write 0x%04x @ %d\n", val, reg);
+
+ if (reg > 31) {
+ /* we only advertise one phy */
+ return;
+ }
+
+ switch (reg) {
+ case 0: /* Basic Control */
+ if (val & 0x8000) {
+ phy_reset(s);
+ } else {
+ s->phy_control = val & 0x7980;
+ /* Complete autonegotiation immediately. */
+ if (val & 0x1000) {
+ s->phy_status |= 0x0020;
+ }
+ }
+ break;
+ case 4: /* Auto-neg advertisement */
+ s->phy_advertise = (val & 0x2d7f) | 0x80;
+ break;
+ case 30: /* Interrupt mask */
+ s->phy_int_mask = val & 0xff;
+ phy_update_irq(s);
+ break;
+ case 17:
+ case 18:
+ case 27:
+ case 31:
+ qemu_log_mask(LOG_UNIMP, "%s.phy[%s]: reg %d not implemented\n",
+ TYPE_IMX_FEC, __func__, reg);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s.phy[%s]: Bad address at offset %d\n",
+ TYPE_IMX_FEC, __func__, reg);
+ break;
+ }
+}
+
+static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
+{
+ dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd));
+}
+
+static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr)
+{
+ dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd));
+}
+
+static void imx_fec_update(IMXFECState *s)
+{
+ uint32_t active;
+ uint32_t changed;
+
+ active = s->eir & s->eimr;
+ changed = active ^ s->irq_state;
+ if (changed) {
+ qemu_set_irq(s->irq, active);
+ }
+ s->irq_state = active;
+}
+
+static void imx_fec_do_tx(IMXFECState *s)
+{
+ int frame_size = 0;
+ uint8_t frame[FEC_MAX_FRAME_SIZE];
+ uint8_t *ptr = frame;
+ uint32_t addr = s->tx_descriptor;
+
+ while (1) {
+ IMXFECBufDesc bd;
+ int len;
+
+ imx_fec_read_bd(&bd, addr);
+ FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n",
+ addr, bd.flags, bd.length, bd.data);
+ if ((bd.flags & FEC_BD_R) == 0) {
+ /* Run out of descriptors to transmit. */
+ break;
+ }
+ len = bd.length;
+ if (frame_size + len > FEC_MAX_FRAME_SIZE) {
+ len = FEC_MAX_FRAME_SIZE - frame_size;
+ s->eir |= FEC_INT_BABT;
+ }
+ dma_memory_read(&address_space_memory, bd.data, ptr, len);
+ ptr += len;
+ frame_size += len;
+ if (bd.flags & FEC_BD_L) {
+ /* Last buffer in frame. */
+ qemu_send_packet(qemu_get_queue(s->nic), frame, len);
+ ptr = frame;
+ frame_size = 0;
+ s->eir |= FEC_INT_TXF;
+ }
+ s->eir |= FEC_INT_TXB;
+ bd.flags &= ~FEC_BD_R;
+ /* Write back the modified descriptor. */
+ imx_fec_write_bd(&bd, addr);
+ /* Advance to the next descriptor. */
+ if ((bd.flags & FEC_BD_W) != 0) {
+ addr = s->etdsr;
+ } else {
+ addr += 8;
+ }
+ }
+
+ s->tx_descriptor = addr;
+
+ imx_fec_update(s);
+}
+
+static void imx_fec_enable_rx(IMXFECState *s)
+{
+ IMXFECBufDesc bd;
+ uint32_t tmp;
+
+ imx_fec_read_bd(&bd, s->rx_descriptor);
+
+ tmp = ((bd.flags & FEC_BD_E) != 0);
+
+ if (!tmp) {
+ FEC_PRINTF("RX buffer full\n");
+ } else if (!s->rx_enabled) {
+ qemu_flush_queued_packets(qemu_get_queue(s->nic));
+ }
+
+ s->rx_enabled = tmp;
+}
+
+static void imx_fec_reset(DeviceState *d)
+{
+ IMXFECState *s = IMX_FEC(d);
+
+ /* Reset the FEC */
+ s->eir = 0;
+ s->eimr = 0;
+ s->rx_enabled = 0;
+ s->ecr = 0;
+ s->mscr = 0;
+ s->mibc = 0xc0000000;
+ s->rcr = 0x05ee0001;
+ s->tcr = 0;
+ s->tfwr = 0;
+ s->frsr = 0x500;
+ s->miigsk_cfgr = 0;
+ s->miigsk_enr = 0x6;
+
+ /* We also reset the PHY */
+ phy_reset(s);
+}
+
+static uint64_t imx_fec_read(void *opaque, hwaddr addr, unsigned size)
+{
+ IMXFECState *s = IMX_FEC(opaque);
+
+ FEC_PRINTF("reading from @ 0x%03x\n", (int)addr);
+
+ switch (addr & 0x3ff) {
+ case 0x004:
+ return s->eir;
+ case 0x008:
+ return s->eimr;
+ case 0x010:
+ return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
+ case 0x014:
+ return 0; /* TDAR */
+ case 0x024:
+ return s->ecr;
+ case 0x040:
+ return s->mmfr;
+ case 0x044:
+ return s->mscr;
+ case 0x064:
+ return s->mibc; /* MIBC */
+ case 0x084:
+ return s->rcr;
+ case 0x0c4:
+ return s->tcr;
+ case 0x0e4: /* PALR */
+ return (s->conf.macaddr.a[0] << 24)
+ | (s->conf.macaddr.a[1] << 16)
+ | (s->conf.macaddr.a[2] << 8)
+ | s->conf.macaddr.a[3];
+ break;
+ case 0x0e8: /* PAUR */
+ return (s->conf.macaddr.a[4] << 24)
+ | (s->conf.macaddr.a[5] << 16)
+ | 0x8808;
+ case 0x0ec:
+ return 0x10000; /* OPD */
+ case 0x118:
+ return 0;
+ case 0x11c:
+ return 0;
+ case 0x120:
+ return 0;
+ case 0x124:
+ return 0;
+ case 0x144:
+ return s->tfwr;
+ case 0x14c:
+ return 0x600;
+ case 0x150:
+ return s->frsr;
+ case 0x180:
+ return s->erdsr;
+ case 0x184:
+ return s->etdsr;
+ case 0x188:
+ return s->emrbr;
+ case 0x300:
+ return s->miigsk_cfgr;
+ case 0x308:
+ return s->miigsk_enr;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
+ TYPE_IMX_FEC, __func__, (int)addr);
+ return 0;
+ }
+}
+
+static void imx_fec_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ IMXFECState *s = IMX_FEC(opaque);
+
+ FEC_PRINTF("writing 0x%08x @ 0x%03x\n", (int)value, (int)addr);
+
+ switch (addr & 0x3ff) {
+ case 0x004: /* EIR */
+ s->eir &= ~value;
+ break;
+ case 0x008: /* EIMR */
+ s->eimr = value;
+ break;
+ case 0x010: /* RDAR */
+ if ((s->ecr & FEC_EN) && !s->rx_enabled) {
+ imx_fec_enable_rx(s);
+ }
+ break;
+ case 0x014: /* TDAR */
+ if (s->ecr & FEC_EN) {
+ imx_fec_do_tx(s);
+ }
+ break;
+ case 0x024: /* ECR */
+ s->ecr = value;
+ if (value & FEC_RESET) {
+ imx_fec_reset(DEVICE(s));
+ }
+ if ((s->ecr & FEC_EN) == 0) {
+ s->rx_enabled = 0;
+ }
+ break;
+ case 0x040: /* MMFR */
+ /* store the value */
+ s->mmfr = value;
+ if (extract32(value, 28, 1)) {
+ do_phy_write(s, extract32(value, 18, 9), extract32(value, 0, 16));
+ } else {
+ s->mmfr = do_phy_read(s, extract32(value, 18, 9));
+ }
+ /* raise the interrupt as the PHY operation is done */
+ s->eir |= FEC_INT_MII;
+ break;
+ case 0x044: /* MSCR */
+ s->mscr = value & 0xfe;
+ break;
+ case 0x064: /* MIBC */
+ /* TODO: Implement MIB. */
+ s->mibc = (value & 0x80000000) ? 0xc0000000 : 0;
+ break;
+ case 0x084: /* RCR */
+ s->rcr = value & 0x07ff003f;
+ /* TODO: Implement LOOP mode. */
+ break;
+ case 0x0c4: /* TCR */
+ /* We transmit immediately, so raise GRA immediately. */
+ s->tcr = value;
+ if (value & 1) {
+ s->eir |= FEC_INT_GRA;
+ }
+ break;
+ case 0x0e4: /* PALR */
+ s->conf.macaddr.a[0] = value >> 24;
+ s->conf.macaddr.a[1] = value >> 16;
+ s->conf.macaddr.a[2] = value >> 8;
+ s->conf.macaddr.a[3] = value;
+ break;
+ case 0x0e8: /* PAUR */
+ s->conf.macaddr.a[4] = value >> 24;
+ s->conf.macaddr.a[5] = value >> 16;
+ break;
+ case 0x0ec: /* OPDR */
+ break;
+ case 0x118: /* IAUR */
+ case 0x11c: /* IALR */
+ case 0x120: /* GAUR */
+ case 0x124: /* GALR */
+ /* TODO: implement MAC hash filtering. */
+ break;
+ case 0x144: /* TFWR */
+ s->tfwr = value & 3;
+ break;
+ case 0x14c: /* FRBR */
+ /* FRBR writes ignored. */
+ break;
+ case 0x150: /* FRSR */
+ s->frsr = (value & 0x3fc) | 0x400;
+ break;
+ case 0x180: /* ERDSR */
+ s->erdsr = value & ~3;
+ s->rx_descriptor = s->erdsr;
+ break;
+ case 0x184: /* ETDSR */
+ s->etdsr = value & ~3;
+ s->tx_descriptor = s->etdsr;
+ break;
+ case 0x188: /* EMRBR */
+ s->emrbr = value & 0x7f0;
+ break;
+ case 0x300: /* MIIGSK_CFGR */
+ s->miigsk_cfgr = value & 0x53;
+ break;
+ case 0x308: /* MIIGSK_ENR */
+ s->miigsk_enr = (value & 0x2) ? 0x6 : 0;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad address at offset %d\n",
+ TYPE_IMX_FEC, __func__, (int)addr);
+ break;
+ }
+
+ imx_fec_update(s);
+}
+
+static int imx_fec_can_receive(NetClientState *nc)
+{
+ IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc));
+
+ return s->rx_enabled;
+}
+
+static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
+ size_t len)
+{
+ IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc));
+ IMXFECBufDesc bd;
+ uint32_t flags = 0;
+ uint32_t addr;
+ uint32_t crc;
+ uint32_t buf_addr;
+ uint8_t *crc_ptr;
+ unsigned int buf_len;
+ size_t size = len;
+
+ FEC_PRINTF("len %d\n", (int)size);
+
+ if (!s->rx_enabled) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Unexpected packet\n",
+ TYPE_IMX_FEC, __func__);
+ return 0;
+ }
+
+ /* 4 bytes for the CRC. */
+ size += 4;
+ crc = cpu_to_be32(crc32(~0, buf, size));
+ crc_ptr = (uint8_t *) &crc;
+
+ /* Huge frames are truncted. */
+ if (size > FEC_MAX_FRAME_SIZE) {
+ size = FEC_MAX_FRAME_SIZE;
+ flags |= FEC_BD_TR | FEC_BD_LG;
+ }
+
+ /* Frames larger than the user limit just set error flags. */
+ if (size > (s->rcr >> 16)) {
+ flags |= FEC_BD_LG;
+ }
+
+ addr = s->rx_descriptor;
+ while (size > 0) {
+ imx_fec_read_bd(&bd, addr);
+ if ((bd.flags & FEC_BD_E) == 0) {
+ /* No descriptors available. Bail out. */
+ /*
+ * FIXME: This is wrong. We should probably either
+ * save the remainder for when more RX buffers are
+ * available, or flag an error.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Lost end of frame\n",
+ TYPE_IMX_FEC, __func__);
+ break;
+ }
+ buf_len = (size <= s->emrbr) ? size : s->emrbr;
+ bd.length = buf_len;
+ size -= buf_len;
+ FEC_PRINTF("rx_bd %x length %d\n", addr, bd.length);
+ /* The last 4 bytes are the CRC. */
+ if (size < 4) {
+ buf_len += size - 4;
+ }
+ buf_addr = bd.data;
+ dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
+ buf += buf_len;
+ if (size < 4) {
+ dma_memory_write(&address_space_memory, buf_addr + buf_len,
+ crc_ptr, 4 - size);
+ crc_ptr += 4 - size;
+ }
+ bd.flags &= ~FEC_BD_E;
+ if (size == 0) {
+ /* Last buffer in frame. */
+ bd.flags |= flags | FEC_BD_L;
+ FEC_PRINTF("rx frame flags %04x\n", bd.flags);
+ s->eir |= FEC_INT_RXF;
+ } else {
+ s->eir |= FEC_INT_RXB;
+ }
+ imx_fec_write_bd(&bd, addr);
+ /* Advance to the next descriptor. */
+ if ((bd.flags & FEC_BD_W) != 0) {
+ addr = s->erdsr;
+ } else {
+ addr += 8;
+ }
+ }
+ s->rx_descriptor = addr;
+ imx_fec_enable_rx(s);
+ imx_fec_update(s);
+ return len;
+}
+
+static const MemoryRegionOps imx_fec_ops = {
+ .read = imx_fec_read,
+ .write = imx_fec_write,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void imx_fec_cleanup(NetClientState *nc)
+{
+ IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc));
+
+ s->nic = NULL;
+}
+
+static NetClientInfo net_imx_fec_info = {
+ .type = NET_CLIENT_OPTIONS_KIND_NIC,
+ .size = sizeof(NICState),
+ .can_receive = imx_fec_can_receive,
+ .receive = imx_fec_receive,
+ .cleanup = imx_fec_cleanup,
+ .link_status_changed = imx_fec_set_link,
+};
+
+
+static void imx_fec_realize(DeviceState *dev, Error **errp)
+{
+ IMXFECState *s = IMX_FEC(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(dev), &imx_fec_ops, s,
+ TYPE_IMX_FEC, 0x400);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
+
+ s->conf.peers.ncs[0] = nd_table[0].netdev;
+
+ s->nic = qemu_new_nic(&net_imx_fec_info, &s->conf,
+ object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
+ s);
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
+}
+
+static Property imx_fec_properties[] = {
+ DEFINE_NIC_PROPERTIES(IMXFECState, conf),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void imx_fec_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_imx_fec;
+ dc->reset = imx_fec_reset;
+ dc->props = imx_fec_properties;
+ dc->realize = imx_fec_realize;
+}
+
+static const TypeInfo imx_fec_info = {
+ .name = TYPE_IMX_FEC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMXFECState),
+ .class_init = imx_fec_class_init,
+};
+
+static void imx_fec_register_types(void)
+{
+ type_register_static(&imx_fec_info);
+}
+
+type_init(imx_fec_register_types)
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
new file mode 100644
index 0000000..cbf8650
--- /dev/null
+++ b/include/hw/net/imx_fec.h
@@ -0,0 +1,113 @@
+/*
+ * i.MX Fast Ethernet Controller emulation.
+ *
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
+ *
+ * Based on Coldfire Fast Ethernet Controller emulation.
+ *
+ * Copyright (c) 2007 CodeSourcery.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef IMX_FEC_H
+#define IMX_FEC_H
+
+#define TYPE_IMX_FEC "imx.fec"
+#define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC)
+
+#include "hw/sysbus.h"
+#include "net/net.h"
+
+#define FEC_MAX_FRAME_SIZE 2032
+
+#define FEC_INT_HB (1 << 31)
+#define FEC_INT_BABR (1 << 30)
+#define FEC_INT_BABT (1 << 29)
+#define FEC_INT_GRA (1 << 28)
+#define FEC_INT_TXF (1 << 27)
+#define FEC_INT_TXB (1 << 26)
+#define FEC_INT_RXF (1 << 25)
+#define FEC_INT_RXB (1 << 24)
+#define FEC_INT_MII (1 << 23)
+#define FEC_INT_EBERR (1 << 22)
+#define FEC_INT_LC (1 << 21)
+#define FEC_INT_RL (1 << 20)
+#define FEC_INT_UN (1 << 19)
+
+#define FEC_EN 2
+#define FEC_RESET 1
+
+/* Buffer Descriptor. */
+typedef struct {
+ uint16_t length;
+ uint16_t flags;
+ uint32_t data;
+} IMXFECBufDesc;
+
+#define FEC_BD_R (1 << 15)
+#define FEC_BD_E (1 << 15)
+#define FEC_BD_O1 (1 << 14)
+#define FEC_BD_W (1 << 13)
+#define FEC_BD_O2 (1 << 12)
+#define FEC_BD_L (1 << 11)
+#define FEC_BD_TC (1 << 10)
+#define FEC_BD_ABC (1 << 9)
+#define FEC_BD_M (1 << 8)
+#define FEC_BD_BC (1 << 7)
+#define FEC_BD_MC (1 << 6)
+#define FEC_BD_LG (1 << 5)
+#define FEC_BD_NO (1 << 4)
+#define FEC_BD_CR (1 << 2)
+#define FEC_BD_OV (1 << 1)
+#define FEC_BD_TR (1 << 0)
+
+typedef struct IMXFECState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ NICState *nic;
+ NICConf conf;
+ qemu_irq irq;
+ MemoryRegion iomem;
+
+ uint32_t irq_state;
+ uint32_t eir;
+ uint32_t eimr;
+ uint32_t rx_enabled;
+ uint32_t rx_descriptor;
+ uint32_t tx_descriptor;
+ uint32_t ecr;
+ uint32_t mmfr;
+ uint32_t mscr;
+ uint32_t mibc;
+ uint32_t rcr;
+ uint32_t tcr;
+ uint32_t tfwr;
+ uint32_t frsr;
+ uint32_t erdsr;
+ uint32_t etdsr;
+ uint32_t emrbr;
+ uint32_t miigsk_cfgr;
+ uint32_t miigsk_enr;
+
+ uint32_t phy_status;
+ uint32_t phy_control;
+ uint32_t phy_advertise;
+ uint32_t phy_int;
+ uint32_t phy_int_mask;
+} IMXFECState;
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 22/27] i.MX: Add SOC support for i.MX25
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 21/27] i.MX: Add FEC Ethernet Emulator Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform Peter Maydell
` (5 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
For now we support the following devices:
* CPU: ARM926
* Interrupt Controller: AVIC
* CCM
* UART x 5
* EPIT x 2
* GPT x 4
* FEC
* I2C x 3
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 62218bfa90f9101f79098e768c3d58bd92dcb7f3.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs | 1 +
hw/arm/fsl-imx25.c | 273 ++++++++++++++++++++++++++++++++++++++++
include/hw/arm/fsl-imx25.h | 234 ++++++++++++++++++++++++++++++++++
4 files changed, 509 insertions(+)
create mode 100644 hw/arm/fsl-imx25.c
create mode 100644 include/hw/arm/fsl-imx25.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 7d900f5..d9b90a5 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -100,6 +100,7 @@ CONFIG_ALLWINNER_A10_PIC=y
CONFIG_ALLWINNER_A10=y
CONFIG_FSL_IMX31=y
+CONFIG_FSL_IMX25=y
CONFIG_IMX_I2C=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 2fbe344..b83aaca 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -13,4 +13,5 @@ obj-y += omap1.o omap2.o strongarm.o
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
+obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
new file mode 100644
index 0000000..6d157c9
--- /dev/null
+++ b/hw/arm/fsl-imx25.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * i.MX25 SOC emulation.
+ *
+ * Based on hw/arm/xlnx-zynqmp.c
+ *
+ * Copyright (C) 2015 Xilinx Inc
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/arm/fsl-imx25.h"
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "sysemu/char.h"
+
+static void fsl_imx25_init(Object *obj)
+{
+ FslIMX25State *s = FSL_IMX25(obj);
+ int i;
+
+ object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
+
+ object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
+ qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
+
+ object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM);
+ qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
+
+ for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
+ object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
+ qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
+ }
+
+ for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
+ object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT);
+ qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
+ }
+
+ for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
+ object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
+ qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
+ }
+
+ object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC);
+ qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default());
+
+ for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
+ object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
+ qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
+ }
+}
+
+static void fsl_imx25_realize(DeviceState *dev, Error **errp)
+{
+ FslIMX25State *s = FSL_IMX25(dev);
+ uint8_t i;
+ Error *err = NULL;
+
+ object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
+ qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
+ qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
+
+ object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
+
+ /* Initialize all UARTs */
+ for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } serial_table[FSL_IMX25_NUM_UARTS] = {
+ { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
+ { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
+ { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
+ { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
+ { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
+ };
+
+ if (i < MAX_SERIAL_PORTS) {
+ CharDriverState *chr;
+
+ chr = serial_hds[i];
+
+ if (!chr) {
+ char label[20];
+ snprintf(label, sizeof(label), "imx31.uart%d", i);
+ chr = qemu_chr_new(label, "null", NULL);
+ }
+
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+ }
+
+ object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ serial_table[i].irq));
+ }
+
+ /* Initialize all GPT timers */
+ for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } gpt_table[FSL_IMX25_NUM_GPTS] = {
+ { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
+ { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
+ { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
+ { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
+ };
+
+ s->gpt[i].ccm = DEVICE(&s->ccm);
+
+ object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ gpt_table[i].irq));
+ }
+
+ /* Initialize all EPIT timers */
+ for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } epit_table[FSL_IMX25_NUM_EPITS] = {
+ { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
+ { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
+ };
+
+ s->epit[i].ccm = DEVICE(&s->ccm);
+
+ object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ epit_table[i].irq));
+ }
+
+ qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
+ object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
+
+
+ /* Initialize all I2C */
+ for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } i2c_table[FSL_IMX25_NUM_I2CS] = {
+ { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
+ { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
+ { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
+ };
+
+ object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ i2c_table[i].irq));
+ }
+
+ /* initialize 2 x 16 KB ROM */
+ memory_region_init_rom_device(&s->rom[0], NULL, NULL, NULL,
+ "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
+ &s->rom[0]);
+ memory_region_init_rom_device(&s->rom[1], NULL, NULL, NULL,
+ "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
+ &s->rom[1]);
+
+ /* initialize internal RAM (128 KB) */
+ memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
+ &s->iram);
+ vmstate_register_ram_global(&s->iram);
+
+ /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
+ memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
+ &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
+ &s->iram_alias);
+}
+
+static void fsl_imx25_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = fsl_imx25_realize;
+}
+
+static const TypeInfo fsl_imx25_type_info = {
+ .name = TYPE_FSL_IMX25,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(FslIMX25State),
+ .instance_init = fsl_imx25_init,
+ .class_init = fsl_imx25_class_init,
+};
+
+static void fsl_imx25_register_types(void)
+{
+ type_register_static(&fsl_imx25_type_info);
+}
+
+type_init(fsl_imx25_register_types)
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
new file mode 100644
index 0000000..7f6bb64
--- /dev/null
+++ b/include/hw/arm/fsl-imx25.h
@@ -0,0 +1,234 @@
+/*
+ * Freescale i.MX25 SoC emulation
+ *
+ * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef FSL_IMX25_H
+#define FSL_IMX25_H
+
+#include "hw/arm/arm.h"
+#include "hw/intc/imx_avic.h"
+#include "hw/misc/imx_ccm.h"
+#include "hw/char/imx_serial.h"
+#include "hw/timer/imx_gpt.h"
+#include "hw/timer/imx_epit.h"
+#include "hw/net/imx_fec.h"
+#include "hw/i2c/imx_i2c.h"
+#include "exec/memory.h"
+
+#define TYPE_FSL_IMX25 "fsl,imx25"
+#define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)
+
+#define FSL_IMX25_NUM_UARTS 5
+#define FSL_IMX25_NUM_GPTS 4
+#define FSL_IMX25_NUM_EPITS 2
+#define FSL_IMX25_NUM_I2CS 3
+
+typedef struct FslIMX25State {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ ARMCPU cpu;
+ IMXAVICState avic;
+ IMXCCMState ccm;
+ IMXSerialState uart[FSL_IMX25_NUM_UARTS];
+ IMXGPTState gpt[FSL_IMX25_NUM_GPTS];
+ IMXEPITState epit[FSL_IMX25_NUM_EPITS];
+ IMXFECState fec;
+ IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
+ MemoryRegion rom[2];
+ MemoryRegion iram;
+ MemoryRegion iram_alias;
+} FslIMX25State;
+
+/**
+ * i.MX25 memory map
+ ****************************************************************
+ * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)
+ * 0x0000_4000 0x0040_3FFF 4 Mbytes Reserved
+ * 0x0040_4000 0x0040_8FFF 20 Kbytes ROM (36 Kbytes)
+ * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved
+ * 0x1000_0000 0x1FFF_FFFF 256 Mbytes Reserved
+ * 0x2000_0000 0x2FFF_FFFF 256 Mbytes Reserved
+ * 0x3000_0000 0x3FFF_FFFF 256 Mbytes Reserved
+ * 0x4000_0000 0x43EF_FFFF 63 Mbytes Reserved
+ * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
+ * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX
+ * 0x43F0_8000 0x43F0_BFFF 16 Kbytes ARM926 platform CLKCTL
+ * 0x43F0_C000 0x43F0_FFFF 16 Kbytes ARM926 platform ETB registers
+ * 0x43F1_0000 0x43F1_3FFF 16 Kbytes ARM926 platform ETB memory
+ * 0x43F1_4000 0x43F1_7FFF 16 Kbytes ARM926 platform AAPE registers
+ * 0x43F1_8000 0x43F7_FFFF 416 Kbytes Reserved
+ * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1
+ * 0x43F8_4000 0x43F8_7FFF 16 Kbytes I2C-3
+ * 0x43F8_8000 0x43F8_BFFF 16 Kbytes CAN-1
+ * 0x43F8_C000 0x43F8_FFFF 16 Kbytes CAN-2
+ * 0x43F9_0000 0x43F9_3FFF 16 Kbytes UART-1
+ * 0x43F9_4000 0x43F9_7FFF 16 Kbytes UART-2
+ * 0x43F9_8000 0x43F9_BFFF 16 Kbytes I2C-2
+ * 0x43F9_C000 0x43F9_FFFF 16 Kbytes 1-Wire
+ * 0x43FA_0000 0x43FA_3FFF 16 Kbytes ATA (CPU side)
+ * 0x43FA_4000 0x43FA_7FFF 16 Kbytes CSPI-1
+ * 0x43FA_8000 0x43FA_BFFF 16 Kbytes KPP
+ * 0x43FA_C000 0x43FA_FFFF 16 Kbytes IOMUXC
+ * 0x43FB_0000 0x43FB_3FFF 16 Kbytes AUDMUX
+ * 0x43FB_4000 0x43FB_7FFF 16 Kbytes Reserved
+ * 0x43FB_8000 0x43FB_BFFF 16 Kbytes ECT (IP BUS A)
+ * 0x43FB_C000 0x43FB_FFFF 16 Kbytes ECT (IP BUS B)
+ * 0x43FC_0000 0x43FF_FFFF 256 Kbytes Reserved AIPS A off-platform slots
+ * 0x4400_0000 0x4FFF_FFFF 192 Mbytes Reserved
+ * 0x5000_0000 0x5000_3FFF 16 Kbytes SPBA base address
+ * 0x5000_4000 0x5000_7FFF 16 Kbytes CSPI-3
+ * 0x5000_8000 0x5000_BFFF 16 Kbytes UART-4
+ * 0x5000_C000 0x5000_FFFF 16 Kbytes UART-3
+ * 0x5001_0000 0x5001_3FFF 16 Kbytes CSPI-2
+ * 0x5001_4000 0x5001_7FFF 16 Kbytes SSI-2
+ * 0x5001_C000 0x5001_FFFF 16 Kbytes Reserved
+ * 0x5002_0000 0x5002_3FFF 16 Kbytes ATA
+ * 0x5002_4000 0x5002_7FFF 16 Kbytes SIM-1
+ * 0x5002_8000 0x5002_BFFF 16 Kbytes SIM-2
+ * 0x5002_C000 0x5002_FFFF 16 Kbytes UART-5
+ * 0x5003_0000 0x5003_3FFF 16 Kbytes TSC
+ * 0x5003_4000 0x5003_7FFF 16 Kbytes SSI-1
+ * 0x5003_8000 0x5003_BFFF 16 Kbytes FEC
+ * 0x5003_C000 0x5003_FFFF 16 Kbytes SPBA registers
+ * 0x5004_0000 0x51FF_FFFF 32 Mbytes (minus 256 Kbytes)
+ * 0x5200_0000 0x53EF_FFFF 31 Mbytes Reserved
+ * 0x53F0_0000 0x53F0_3FFF 16 Kbytes AIPS B control registers
+ * 0x53F0_4000 0x53F7_FFFF 496 Kbytes Reserved
+ * 0x53F8_0000 0x53F8_3FFF 16 Kbytes CCM
+ * 0x53F8_4000 0x53F8_7FFF 16 Kbytes GPT-4
+ * 0x53F8_8000 0x53F8_BFFF 16 Kbytes GPT-3
+ * 0x53F8_C000 0x53F8_FFFF 16 Kbytes GPT-2
+ * 0x53F9_0000 0x53F9_3FFF 16 Kbytes GPT-1
+ * 0x53F9_4000 0x53F9_7FFF 16 Kbytes EPIT-1
+ * 0x53F9_8000 0x53F9_BFFF 16 Kbytes EPIT-2
+ * 0x53F9_C000 0x53F9_FFFF 16 Kbytes GPIO-4
+ * 0x53FA_0000 0x53FA_3FFF 16 Kbytes PWM-2
+ * 0x53FA_4000 0x53FA_7FFF 16 Kbytes GPIO-3
+ * 0x53FA_8000 0x53FA_BFFF 16 Kbytes PWM-3
+ * 0x53FA_C000 0x53FA_FFFF 16 Kbytes SCC
+ * 0x53FB_0000 0x53FB_3FFF 16 Kbytes RNGB
+ * 0x53FB_4000 0x53FB_7FFF 16 Kbytes eSDHC-1
+ * 0x53FB_8000 0x53FB_BFFF 16 Kbytes eSDHC-2
+ * 0x53FB_C000 0x53FB_FFFF 16 Kbytes LCDC
+ * 0x53FC_0000 0x53FC_3FFF 16 Kbytes SLCDC
+ * 0x53FC_4000 0x53FC_7FFF 16 Kbytes Reserved
+ * 0x53FC_8000 0x53FC_BFFF 16 Kbytes PWM-4
+ * 0x53FC_C000 0x53FC_FFFF 16 Kbytes GPIO-1
+ * 0x53FD_0000 0x53FD_3FFF 16 Kbytes GPIO-2
+ * 0x53FD_4000 0x53FD_7FFF 16 Kbytes SDMA
+ * 0x53FD_8000 0x53FD_BFFF 16 Kbytes Reserved
+ * 0x53FD_C000 0x53FD_FFFF 16 Kbytes WDOG
+ * 0x53FE_0000 0x53FE_3FFF 16 Kbytes PWM-1
+ * 0x53FE_4000 0x53FE_7FFF 16 Kbytes Reserved
+ * 0x53FE_8000 0x53FE_BFFF 16 Kbytes Reserved
+ * 0x53FE_C000 0x53FE_FFFF 16 Kbytes RTICv3
+ * 0x53FF_0000 0x53FF_3FFF 16 Kbytes IIM
+ * 0x53FF_4000 0x53FF_7FFF 16 Kbytes USB
+ * 0x53FF_8000 0x53FF_BFFF 16 Kbytes CSI
+ * 0x53FF_C000 0x53FF_FFFF 16 Kbytes DryIce
+ * 0x5400_0000 0x5FFF_FFFF 192 Mbytes Reserved (aliased AIPS B slots)
+ * 0x6000_0000 0x67FF_FFFF 128 Mbytes ARM926 platform ROMPATCH
+ * 0x6800_0000 0x6FFF_FFFF 128 Mbytes ARM926 platform ASIC
+ * 0x7000_0000 0x77FF_FFFF 128 Mbytes Reserved
+ * 0x7800_0000 0x7801_FFFF 128 Kbytes RAM
+ * 0x7802_0000 0x7FFF_FFFF 128 Mbytes (minus 128 Kbytes)
+ * 0x8000_0000 0x8FFF_FFFF 256 Mbytes SDRAM bank 0
+ * 0x9000_0000 0x9FFF_FFFF 256 Mbytes SDRAM bank 1
+ * 0xA000_0000 0xA7FF_FFFF 128 Mbytes WEIM CS0 (flash 128) 1
+ * 0xA800_0000 0xAFFF_FFFF 128 Mbytes WEIM CS1 (flash 64) 1
+ * 0xB000_0000 0xB1FF_FFFF 32 Mbytes WEIM CS2 (SRAM)
+ * 0xB200_0000 0xB3FF_FFFF 32 Mbytes WEIM CS3 (SRAM)
+ * 0xB400_0000 0xB5FF_FFFF 32 Mbytes WEIM CS4
+ * 0xB600_0000 0xB7FF_FFFF 32 Mbytes Reserved
+ * 0xB800_0000 0xB800_0FFF 4 Kbytes Reserved
+ * 0xB800_1000 0xB800_1FFF 4 Kbytes SDRAM control registers
+ * 0xB800_2000 0xB800_2FFF 4 Kbytes WEIM control registers
+ * 0xB800_3000 0xB800_3FFF 4 Kbytes M3IF control registers
+ * 0xB800_4000 0xB800_4FFF 4 Kbytes EMI control registers
+ * 0xB800_5000 0xBAFF_FFFF 32 Mbytes (minus 20 Kbytes)
+ * 0xBB00_0000 0xBB00_0FFF 4 Kbytes NAND flash main area buffer
+ * 0xBB00_1000 0xBB00_11FF 512 B NAND flash spare area buffer
+ * 0xBB00_1200 0xBB00_1DFF 3 Kbytes Reserved
+ * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control regisers
+ * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
+ * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes Reserved
+ */
+
+#define FSL_IMX25_ROM0_ADDR 0x00000000
+#define FSL_IMX25_ROM0_SIZE 0x4000
+#define FSL_IMX25_ROM1_ADDR 0x00404000
+#define FSL_IMX25_ROM1_SIZE 0x4000
+#define FSL_IMX25_I2C1_ADDR 0x43F80000
+#define FSL_IMX25_I2C1_SIZE 0x4000
+#define FSL_IMX25_I2C3_ADDR 0x43F84000
+#define FSL_IMX25_I2C3_SIZE 0x4000
+#define FSL_IMX25_UART1_ADDR 0x43F90000
+#define FSL_IMX25_UART1_SIZE 0x4000
+#define FSL_IMX25_UART2_ADDR 0x43F94000
+#define FSL_IMX25_UART2_SIZE 0x4000
+#define FSL_IMX25_I2C2_ADDR 0x43F98000
+#define FSL_IMX25_I2C2_SIZE 0x4000
+#define FSL_IMX25_UART4_ADDR 0x50008000
+#define FSL_IMX25_UART4_SIZE 0x4000
+#define FSL_IMX25_UART3_ADDR 0x5000C000
+#define FSL_IMX25_UART3_SIZE 0x4000
+#define FSL_IMX25_UART5_ADDR 0x5002C000
+#define FSL_IMX25_UART5_SIZE 0x4000
+#define FSL_IMX25_FEC_ADDR 0x50038000
+#define FSL_IMX25_FEC_SIZE 0x4000
+#define FSL_IMX25_CCM_ADDR 0x53F80000
+#define FSL_IMX25_CCM_SIZE 0x4000
+#define FSL_IMX25_GPT4_ADDR 0x53F84000
+#define FSL_IMX25_GPT4_SIZE 0x4000
+#define FSL_IMX25_GPT3_ADDR 0x53F88000
+#define FSL_IMX25_GPT3_SIZE 0x4000
+#define FSL_IMX25_GPT2_ADDR 0x53F8C000
+#define FSL_IMX25_GPT2_SIZE 0x4000
+#define FSL_IMX25_GPT1_ADDR 0x53F90000
+#define FSL_IMX25_GPT1_SIZE 0x4000
+#define FSL_IMX25_EPIT1_ADDR 0x53F94000
+#define FSL_IMX25_EPIT1_SIZE 0x4000
+#define FSL_IMX25_EPIT2_ADDR 0x53F98000
+#define FSL_IMX25_EPIT2_SIZE 0x4000
+#define FSL_IMX25_AVIC_ADDR 0x68000000
+#define FSL_IMX25_AVIC_SIZE 0x4000
+#define FSL_IMX25_IRAM_ADDR 0x78000000
+#define FSL_IMX25_IRAM_SIZE 0x20000
+#define FSL_IMX25_IRAM_ALIAS_ADDR 0x78020000
+#define FSL_IMX25_IRAM_ALIAS_SIZE 0x7FE0000
+#define FSL_IMX25_SDRAM0_ADDR 0x80000000
+#define FSL_IMX25_SDRAM0_SIZE 0x10000000
+#define FSL_IMX25_SDRAM1_ADDR 0x90000000
+#define FSL_IMX25_SDRAM1_SIZE 0x10000000
+
+#define FSL_IMX25_UART1_IRQ 45
+#define FSL_IMX25_UART2_IRQ 32
+#define FSL_IMX25_UART3_IRQ 18
+#define FSL_IMX25_UART4_IRQ 5
+#define FSL_IMX25_UART5_IRQ 40
+#define FSL_IMX25_GPT1_IRQ 54
+#define FSL_IMX25_GPT2_IRQ 53
+#define FSL_IMX25_GPT3_IRQ 29
+#define FSL_IMX25_GPT4_IRQ 1
+#define FSL_IMX25_EPIT1_IRQ 28
+#define FSL_IMX25_EPIT2_IRQ 27
+#define FSL_IMX25_FEC_IRQ 57
+#define FSL_IMX25_I2C1_IRQ 3
+#define FSL_IMX25_I2C2_IRQ 4
+#define FSL_IMX25_I2C3_IRQ 10
+
+#endif /* FSL_IMX25_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 22/27] i.MX: Add SOC support for i.MX25 Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-27 19:48 ` Peter Crosthwaite
2015-09-04 15:05 ` [Qemu-devel] [PULL 24/27] i.MX: Add qtest support for I2C device emulator Peter Maydell
` (4 subsequent siblings)
27 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
Tested by booting a minimal Linux system on the emulated platform
Tested by booting the Xvisor hypervisor on the emulated platform
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: d27347300d253509d921bc27a6d0a14db877478b.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/Makefile.objs | 2 +-
hw/arm/imx25_pdk.c | 159 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 160 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/imx25_pdk.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index b83aaca..2195b60 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -13,5 +13,5 @@ obj-y += omap1.o omap2.o strongarm.o
obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
-obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o
+obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
new file mode 100644
index 0000000..c34667f
--- /dev/null
+++ b/hw/arm/imx25_pdk.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * PDK Board System emulation.
+ *
+ * Based on hw/arm/kzm.c
+ *
+ * Copyright (c) 2008 OKL and 2011 NICTA
+ * Written by Hans at OK-Labs
+ * Updated by Peter Chubb.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/arm/fsl-imx25.h"
+#include "hw/boards.h"
+#include "qemu/error-report.h"
+#include "exec/address-spaces.h"
+#include "sysemu/qtest.h"
+#include "hw/i2c/i2c.h"
+
+/* Memory map for PDK Emulation Baseboard:
+ * 0x00000000-0x7fffffff See i.MX25 SOC fr support
+ * 0x80000000-0x87ffffff RAM + Alias EMULATED
+ * 0x90000000-0x9fffffff RAM + Alias EMULATED
+ * 0xa0000000-0xa7ffffff Flash IGNORED
+ * 0xa8000000-0xafffffff Flash IGNORED
+ * 0xb0000000-0xb1ffffff SRAM IGNORED
+ * 0xb2000000-0xb3ffffff SRAM IGNORED
+ * 0xb4000000-0xb5ffffff CS4 IGNORED
+ * 0xb6000000-0xb8000fff Reserved IGNORED
+ * 0xb8001000-0xb8001fff SDRAM CTRL reg IGNORED
+ * 0xb8002000-0xb8002fff WEIM CTRL reg IGNORED
+ * 0xb8003000-0xb8003fff M3IF CTRL reg IGNORED
+ * 0xb8004000-0xb8004fff EMI CTRL reg IGNORED
+ * 0xb8005000-0xbaffffff Reserved IGNORED
+ * 0xbb000000-0xbb000fff NAND flash area buf IGNORED
+ * 0xbb001000-0xbb0011ff NAND flash reserved IGNORED
+ * 0xbb001200-0xbb001dff Reserved IGNORED
+ * 0xbb001e00-0xbb001fff NAN flash CTRL reg IGNORED
+ * 0xbb012000-0xbfffffff Reserved IGNORED
+ * 0xc0000000-0xffffffff Reserved IGNORED
+ */
+
+typedef struct IMX25PDK {
+ FslIMX25State soc;
+ MemoryRegion ram;
+ MemoryRegion ram_alias;
+} IMX25PDK;
+
+static struct arm_boot_info imx25_pdk_binfo;
+
+static void imx25_pdk_init(MachineState *machine)
+{
+ IMX25PDK *s = g_new0(IMX25PDK, 1);
+ Error *err = NULL;
+ unsigned int ram_size;
+ unsigned int alias_offset;
+ int i;
+
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX25);
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
+ &error_abort);
+
+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
+ if (err != NULL) {
+ error_report("%s", error_get_pretty(err));
+ exit(1);
+ }
+
+ /* We need to initialize our memory */
+ if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) {
+ error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
+ "reduced to %x", machine->ram_size,
+ FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE);
+ machine->ram_size = FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE;
+ }
+
+ memory_region_allocate_system_memory(&s->ram, NULL, "imx25.ram",
+ machine->ram_size);
+ memory_region_add_subregion(get_system_memory(), FSL_IMX25_SDRAM0_ADDR,
+ &s->ram);
+
+ /* initialize the alias memory if any */
+ for (i = 0, ram_size = machine->ram_size, alias_offset = 0;
+ (i < 2) && ram_size; i++) {
+ unsigned int size;
+ static const struct {
+ hwaddr addr;
+ unsigned int size;
+ } ram[2] = {
+ { FSL_IMX25_SDRAM0_ADDR, FSL_IMX25_SDRAM0_SIZE },
+ { FSL_IMX25_SDRAM1_ADDR, FSL_IMX25_SDRAM1_SIZE },
+ };
+
+ size = MIN(ram_size, ram[i].size);
+
+ ram_size -= size;
+
+ if (size < ram[i].size) {
+ memory_region_init_alias(&s->ram_alias, NULL, "ram.alias",
+ &s->ram, alias_offset, ram[i].size - size);
+ memory_region_add_subregion(get_system_memory(),
+ ram[i].addr + size, &s->ram_alias);
+ }
+
+ alias_offset += ram[i].size;
+ }
+
+ imx25_pdk_binfo.ram_size = machine->ram_size;
+ imx25_pdk_binfo.kernel_filename = machine->kernel_filename;
+ imx25_pdk_binfo.kernel_cmdline = machine->kernel_cmdline;
+ imx25_pdk_binfo.initrd_filename = machine->initrd_filename;
+ imx25_pdk_binfo.loader_start = FSL_IMX25_SDRAM0_ADDR;
+ imx25_pdk_binfo.board_id = 1771,
+ imx25_pdk_binfo.nb_cpus = 1;
+
+ /*
+ * We test explicitly for qtest here as it is not done (yet?) in
+ * arm_load_kernel(). Without this the "make check" command would
+ * fail.
+ */
+ if (!qtest_enabled()) {
+ arm_load_kernel(&s->soc.cpu, &imx25_pdk_binfo);
+ } else {
+ /*
+ * This I2C device doesn't exist on the real board.
+ * We add it here (only on qtest usage) to be able to do a bit
+ * of simple qtest. See "make check" for details.
+ */
+ i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(&s->soc.i2c[0]),
+ "i2c"),
+ "ds1338", 0x68);
+ }
+}
+
+static QEMUMachine imx25_pdk_machine = {
+ .name = "imx25_pdk",
+ .desc = "ARM i.MX25 PDK board (ARM926)",
+ .init = imx25_pdk_init,
+};
+
+static void imx25_pdk_machine_init(void)
+{
+ qemu_register_machine(&imx25_pdk_machine);
+}
+
+machine_init(imx25_pdk_machine_init)
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 24/27] i.MX: Add qtest support for I2C device emulator.
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 25/27] i.MX: Add i2C devices to i.MX31 SOC Peter Maydell
` (3 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
This is using a ds1338 RTC chip on the I2C bus. This RTC chip is
not present on the real 3DS PDK board.
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Acked-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 05601683a2a95c881cbc9f22651a044d969bd0ae.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/fsl-imx31.h | 1 +
tests/Makefile | 3 +
tests/ds1338-test.c | 78 +++++++++++++++++
tests/libqos/i2c-imx.c | 209 +++++++++++++++++++++++++++++++++++++++++++++
tests/libqos/i2c.h | 3 +
5 files changed, 294 insertions(+)
create mode 100644 tests/ds1338-test.c
create mode 100644 tests/libqos/i2c-imx.c
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index 09508e3..128006f 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -23,6 +23,7 @@
#include "hw/char/imx_serial.h"
#include "hw/timer/imx_gpt.h"
#include "hw/timer/imx_epit.h"
+#include "hw/i2c/imx_i2c.h"
#include "exec/memory.h"
#define TYPE_FSL_IMX31 "fsl,imx31"
diff --git a/tests/Makefile b/tests/Makefile
index 5271123..30f5108 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -201,6 +201,7 @@ check-qtest-sparc64-y = tests/endianness-test$(EXESUF)
gcov-files-sparc-y += hw/timer/m48t59.c
gcov-files-sparc64-y += hw/timer/m48t59.c
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
+check-qtest-arm-y = tests/ds1338-test$(EXESUF)
gcov-files-arm-y += hw/misc/tmp105.c
check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
gcov-files-arm-y += arm-softmmu/hw/block/virtio-blk.c
@@ -354,6 +355,7 @@ libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o
libqos-pc-obj-y += tests/libqos/ahci.o
libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o
+libqos-imx-obj-y = $(libqos-obj-y) tests/libqos/i2c-imx.o
libqos-usb-obj-y = $(libqos-pc-obj-y) tests/libqos/usb.o
libqos-virtio-obj-y = $(libqos-pc-obj-y) tests/libqos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/libqos/malloc-generic.o
@@ -368,6 +370,7 @@ tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
+tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y)
diff --git a/tests/ds1338-test.c b/tests/ds1338-test.c
new file mode 100644
index 0000000..a7fb415
--- /dev/null
+++ b/tests/ds1338-test.c
@@ -0,0 +1,78 @@
+/*
+ * QTest testcase for the DS1338 RTC
+ *
+ * Copyright (c) 2013 Jean-Christophe Dubois
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "libqtest.h"
+#include "libqos/i2c.h"
+
+#include <glib.h>
+
+#define IMX25_I2C_0_BASE 0x43F80000
+
+#define DS1338_ADDR 0x68
+
+static I2CAdapter *i2c;
+static uint8_t addr;
+
+static inline uint8_t bcd2bin(uint8_t x)
+{
+ return ((x) & 0x0f) + ((x) >> 4) * 10;
+}
+
+static void send_and_receive(void)
+{
+ uint8_t cmd[1];
+ uint8_t resp[7];
+ time_t now = time(NULL);
+ struct tm *tm_ptr = gmtime(&now);
+
+ /* reset the index in the RTC memory */
+ cmd[0] = 0;
+ i2c_send(i2c, addr, cmd, 1);
+
+ /* retrieve the date */
+ i2c_recv(i2c, addr, resp, 7);
+
+ /* check retrieved time againt local time */
+ g_assert_cmpuint(bcd2bin(resp[4]), == , tm_ptr->tm_mday);
+ g_assert_cmpuint(bcd2bin(resp[5]), == , 1 + tm_ptr->tm_mon);
+ g_assert_cmpuint(2000 + bcd2bin(resp[6]), == , 1900 + tm_ptr->tm_year);
+}
+
+int main(int argc, char **argv)
+{
+ QTestState *s = NULL;
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+
+ s = qtest_start("-display none -machine imx25_pdk");
+ i2c = imx_i2c_create(IMX25_I2C_0_BASE);
+ addr = DS1338_ADDR;
+
+ qtest_add_func("/ds1338/tx-rx", send_and_receive);
+
+ ret = g_test_run();
+
+ if (s) {
+ qtest_quit(s);
+ }
+ g_free(i2c);
+
+ return ret;
+}
diff --git a/tests/libqos/i2c-imx.c b/tests/libqos/i2c-imx.c
new file mode 100644
index 0000000..b5cef66
--- /dev/null
+++ b/tests/libqos/i2c-imx.c
@@ -0,0 +1,209 @@
+/*
+ * QTest i.MX I2C driver
+ *
+ * Copyright (c) 2013 Jean-Christophe Dubois
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "libqos/i2c.h"
+
+#include <glib.h>
+#include <string.h>
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+
+#include "hw/i2c/imx_i2c.h"
+
+enum IMXI2CDirection {
+ IMX_I2C_READ,
+ IMX_I2C_WRITE,
+};
+
+typedef struct IMXI2C {
+ I2CAdapter parent;
+
+ uint64_t addr;
+} IMXI2C;
+
+
+static void imx_i2c_set_slave_addr(IMXI2C *s, uint8_t addr,
+ enum IMXI2CDirection direction)
+{
+ writeb(s->addr + I2DR_ADDR, (addr << 1) |
+ (direction == IMX_I2C_READ ? 1 : 0));
+}
+
+static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,
+ const uint8_t *buf, uint16_t len)
+{
+ IMXI2C *s = (IMXI2C *)i2c;
+ uint8_t data;
+ uint8_t status;
+ uint16_t size = 0;
+
+ if (!len) {
+ return;
+ }
+
+ /* set the bus for write */
+ data = I2CR_IEN |
+ I2CR_IIEN |
+ I2CR_MSTA |
+ I2CR_MTX |
+ I2CR_TXAK;
+
+ writeb(s->addr + I2CR_ADDR, data);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IBB) != 0);
+
+ /* set the slave address */
+ imx_i2c_set_slave_addr(s, addr, IMX_I2C_WRITE);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) != 0);
+ g_assert((status & I2SR_RXAK) == 0);
+
+ /* ack the interrupt */
+ writeb(s->addr + I2SR_ADDR, 0);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) == 0);
+
+ while (size < len) {
+ /* check we are still busy */
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IBB) != 0);
+
+ /* write the data */
+ writeb(s->addr + I2DR_ADDR, buf[size]);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) != 0);
+ g_assert((status & I2SR_RXAK) == 0);
+
+ /* ack the interrupt */
+ writeb(s->addr + I2SR_ADDR, 0);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) == 0);
+
+ size++;
+ }
+
+ /* release the bus */
+ data &= ~(I2CR_MSTA | I2CR_MTX);
+ writeb(s->addr + I2CR_ADDR, data);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IBB) == 0);
+}
+
+static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,
+ uint8_t *buf, uint16_t len)
+{
+ IMXI2C *s = (IMXI2C *)i2c;
+ uint8_t data;
+ uint8_t status;
+ uint16_t size = 0;
+
+ if (!len) {
+ return;
+ }
+
+ /* set the bus for write */
+ data = I2CR_IEN |
+ I2CR_IIEN |
+ I2CR_MSTA |
+ I2CR_MTX |
+ I2CR_TXAK;
+
+ writeb(s->addr + I2CR_ADDR, data);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IBB) != 0);
+
+ /* set the slave address */
+ imx_i2c_set_slave_addr(s, addr, IMX_I2C_READ);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) != 0);
+ g_assert((status & I2SR_RXAK) == 0);
+
+ /* ack the interrupt */
+ writeb(s->addr + I2SR_ADDR, 0);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) == 0);
+
+ /* set the bus for read */
+ data &= ~I2CR_MTX;
+ /* if only one byte don't ack */
+ if (len != 1) {
+ data &= ~I2CR_TXAK;
+ }
+ writeb(s->addr + I2CR_ADDR, data);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IBB) != 0);
+
+ /* dummy read */
+ readb(s->addr + I2DR_ADDR);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) != 0);
+
+ /* ack the interrupt */
+ writeb(s->addr + I2SR_ADDR, 0);
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) == 0);
+
+ while (size < len) {
+ /* check we are still busy */
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IBB) != 0);
+
+ if (size == (len - 1)) {
+ /* stop the read transaction */
+ data &= ~(I2CR_MSTA | I2CR_MTX);
+ } else {
+ /* ack the data read */
+ data |= I2CR_TXAK;
+ }
+ writeb(s->addr + I2CR_ADDR, data);
+
+ /* read the data */
+ buf[size] = readb(s->addr + I2DR_ADDR);
+
+ if (size != (len - 1)) {
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) != 0);
+
+ /* ack the interrupt */
+ writeb(s->addr + I2SR_ADDR, 0);
+ }
+
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IIF) == 0);
+
+ size++;
+ }
+
+ status = readb(s->addr + I2SR_ADDR);
+ g_assert((status & I2SR_IBB) == 0);
+}
+
+I2CAdapter *imx_i2c_create(uint64_t addr)
+{
+ IMXI2C *s = g_malloc0(sizeof(*s));
+ I2CAdapter *i2c = (I2CAdapter *)s;
+
+ s->addr = addr;
+
+ i2c->send = imx_i2c_send;
+ i2c->recv = imx_i2c_recv;
+
+ return i2c;
+}
diff --git a/tests/libqos/i2c.h b/tests/libqos/i2c.h
index 1ce9af4..c21f1dc 100644
--- a/tests/libqos/i2c.h
+++ b/tests/libqos/i2c.h
@@ -27,4 +27,7 @@ void i2c_recv(I2CAdapter *i2c, uint8_t addr,
/* libi2c-omap.c */
I2CAdapter *omap_i2c_create(uint64_t addr);
+/* libi2c-imx.c */
+I2CAdapter *imx_i2c_create(uint64_t addr);
+
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 25/27] i.MX: Add i2C devices to i.MX31 SOC
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 24/27] i.MX: Add qtest support for I2C device emulator Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 26/27] target-arm: Refactor CPU affinity handling Peter Maydell
` (2 subsequent siblings)
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Jean-Christophe Dubois <jcd@tribudubois.net>
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: fb20e6bf5cf946c4530b2cfb55c7e37f5a0fc051.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/fsl-imx31.c | 30 ++++++++++++++++++++++++++++++
include/hw/arm/fsl-imx31.h | 11 +++++++++++
2 files changed, 41 insertions(+)
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index 1681ecf..87548c8 100644
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -50,6 +50,11 @@ static void fsl_imx31_init(Object *obj)
object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
}
+
+ for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
+ object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
+ qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
+ }
}
static void fsl_imx31_realize(DeviceState *dev, Error **errp)
@@ -154,6 +159,31 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
epit_table[i].irq));
}
+ /* Initialize all I2C */
+ for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } i2c_table[FSL_IMX31_NUM_I2CS] = {
+ { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
+ { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
+ { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
+ };
+
+ /* Initialize the I2C */
+ object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ /* Map I2C memory */
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
+ /* Connect I2C IRQ to PIC */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ i2c_table[i].irq));
+ }
+
/* On a real system, the first 16k is a `secure boot rom' */
memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL,
"imx31.secure_rom",
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index 128006f..891166f 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -31,6 +31,7 @@
#define FSL_IMX31_NUM_UARTS 2
#define FSL_IMX31_NUM_EPITS 2
+#define FSL_IMX31_NUM_I2CS 3
typedef struct FslIMX31State {
/*< private >*/
@@ -43,6 +44,7 @@ typedef struct FslIMX31State {
IMXSerialState uart[FSL_IMX31_NUM_UARTS];
IMXGPTState gpt;
IMXEPITState epit[FSL_IMX31_NUM_EPITS];
+ IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
MemoryRegion secure_rom;
MemoryRegion rom;
MemoryRegion iram;
@@ -57,10 +59,16 @@ typedef struct FslIMX31State {
#define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
#define FSL_IMX31_IRAM_ADDR 0x1FFFC000
#define FSL_IMX31_IRAM_SIZE 0x4000
+#define FSL_IMX31_I2C1_ADDR 0x43F80000
+#define FSL_IMX31_I2C1_SIZE 0x4000
+#define FSL_IMX31_I2C3_ADDR 0x43F84000
+#define FSL_IMX31_I2C3_SIZE 0x4000
#define FSL_IMX31_UART1_ADDR 0x43F90000
#define FSL_IMX31_UART1_SIZE 0x4000
#define FSL_IMX31_UART2_ADDR 0x43F94000
#define FSL_IMX31_UART2_SIZE 0x4000
+#define FSL_IMX31_I2C2_ADDR 0x43F98000
+#define FSL_IMX31_I2C2_SIZE 0x4000
#define FSL_IMX31_CCM_ADDR 0x53F80000
#define FSL_IMX31_CCM_SIZE 0x4000
#define FSL_IMX31_GPT_ADDR 0x53F90000
@@ -95,5 +103,8 @@ typedef struct FslIMX31State {
#define FSL_IMX31_GPT_IRQ 29
#define FSL_IMX31_UART2_IRQ 32
#define FSL_IMX31_UART1_IRQ 45
+#define FSL_IMX31_I2C1_IRQ 10
+#define FSL_IMX31_I2C2_IRQ 4
+#define FSL_IMX31_I2C3_IRQ 3
#endif /* FSL_IMX31_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 26/27] target-arm: Refactor CPU affinity handling
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 25/27] i.MX: Add i2C devices to i.MX31 SOC Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 27/27] arm/virt: Add full-sized " Peter Maydell
2015-09-07 9:40 ` [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Pavel Fedin <p.fedin@samsung.com>
Introduces reusable definitions for CPU affinity masks/shifts and gets rid
of hardcoded magic numbers.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Message-id: 7e6def4d0d91ae64615cdd2035b94d408d0a23c6.1441366248.git.p.fedin@samsung.com
[PMM: folded overlong line]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu-qom.h | 13 +++++++++++++
target-arm/cpu.c | 2 +-
target-arm/kvm32.c | 3 +--
target-arm/kvm64.c | 3 +--
4 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 00c0716..25fb1ce 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -227,6 +227,19 @@ void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
void arm_gt_stimer_cb(void *opaque);
+#define ARM_AFF0_SHIFT 0
+#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
+#define ARM_AFF1_SHIFT 8
+#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
+#define ARM_AFF2_SHIFT 16
+#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
+#define ARM_AFF3_SHIFT 32
+#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
+
+#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
+#define ARM64_AFFINITY_MASK \
+ (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
+
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7da29f5..d7b4445 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -456,7 +456,7 @@ static void arm_cpu_initfn(Object *obj)
*/
Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
- cpu->mp_affinity = (Aff1 << 8) | Aff0;
+ cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
#ifndef CONFIG_USER_ONLY
/* Our inbound IRQ and FIQ lines */
diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c
index 421ce0e..3ae57a6 100644
--- a/target-arm/kvm32.c
+++ b/target-arm/kvm32.c
@@ -181,7 +181,6 @@ int kvm_arm_cpreg_level(uint64_t regidx)
return KVM_PUT_RUNTIME_STATE;
}
-#define ARM_MPIDR_HWID_BITMASK 0xFFFFFF
#define ARM_CPU_ID_MPIDR 0, 0, 0, 5
int kvm_arch_init_vcpu(CPUState *cs)
@@ -234,7 +233,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (ret) {
return ret;
}
- cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK;
+ cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
return kvm_arm_init_cpreg_list(cpu);
}
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index bd60889..ceebfeb 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -77,7 +77,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
return true;
}
-#define ARM_MPIDR_HWID_BITMASK 0xFF00FFFFFFULL
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
int kvm_arch_init_vcpu(CPUState *cs)
@@ -120,7 +119,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (ret) {
return ret;
}
- cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK;
+ cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
return kvm_arm_init_cpreg_list(cpu);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 27/27] arm/virt: Add full-sized CPU affinity handling
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 26/27] target-arm: Refactor CPU affinity handling Peter Maydell
@ 2015-09-04 15:05 ` Peter Maydell
2015-09-07 9:40 ` [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
From: Pavel Fedin <p.fedin@samsung.com>
At least with KVM, currently there's no reason why QEMU would not be
capable of handling Aff3 != 0. This commit fixes up FDT creation in such
a case.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Message-id: eef5a86e6d9a313780dbc23b35fcb65df42a3e9e.1441366248.git.p.fedin@samsung.com
[PMM: folded two overlong lines]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 60736c2..91e45e0 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -288,9 +288,32 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
{
int cpu;
+ int addr_cells = 1;
+
+ /*
+ * From Documentation/devicetree/bindings/arm/cpus.txt
+ * On ARM v8 64-bit systems value should be set to 2,
+ * that corresponds to the MPIDR_EL1 register size.
+ * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
+ * in the system, #address-cells can be set to 1, since
+ * MPIDR_EL1[63:32] bits are not used for CPUs
+ * identification.
+ *
+ * Here we actually don't know whether our system is 32- or 64-bit one.
+ * The simplest way to go is to examine affinity IDs of all our CPUs. If
+ * at least one of them has Aff3 populated, we set #address-cells to 2.
+ */
+ for (cpu = 0; cpu < vbi->smp_cpus; cpu++) {
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
+
+ if (armcpu->mp_affinity & ARM_AFF3_MASK) {
+ addr_cells = 2;
+ break;
+ }
+ }
qemu_fdt_add_subnode(vbi->fdt, "/cpus");
- qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells);
qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0);
for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) {
@@ -307,7 +330,14 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
"enable-method", "psci");
}
- qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", armcpu->mp_affinity);
+ if (addr_cells == 2) {
+ qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg",
+ armcpu->mp_affinity);
+ } else {
+ qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg",
+ armcpu->mp_affinity);
+ }
+
g_free(nodename);
}
}
--
1.9.1
^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2015-09-04 15:05 ` [Qemu-devel] [PULL 27/27] arm/virt: Add full-sized " Peter Maydell
@ 2015-09-07 9:40 ` Peter Maydell
27 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-07 9:40 UTC (permalink / raw)
To: QEMU Developers; +Cc: Jean-Christophe Dubois
On 4 September 2015 at 16:05, Peter Maydell <peter.maydell@linaro.org> wrote:
> Another target-arm queue flush. I expect there'll be another
> lot next week...
>
>
> The following changes since commit b041066421e8dcc7d080dfcfd83551c9c9f24ade:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging (2015-09-03 16:17:28 +0100)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150904
>
> for you to fetch changes up to d9fd6f3874a326033a446a6db8cd113bf4015e6a:
>
> arm/virt: Add full-sized CPU affinity handling (2015-09-04 15:49:54 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * cleanup to use g_new() and friends
> * support semihosting in A64
> * add SMBIOS support to mach-virt
> * remove hw_error() usages
> * fix bug in the AArch32:AArch64 register mapping
> * add a second PCI memory window in highmem on virt board
> * fix bug in arm_excp_unmasked()
> * add i.MX31 SoC
> * remove restriction on handling affinity values in virt board
The clang build complains about an unused function in imx_i2c.c.
I'm going to squash in this fix to the offending patch and resend
the pullreq (cover letter).
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
index 2568837..8474872 100644
--- a/hw/i2c/imx_i2c.c
+++ b/hw/i2c/imx_i2c.c
@@ -65,11 +65,6 @@ static inline bool imx_i2c_is_master(IMXI2CState *s)
return s->i2cr & I2CR_MSTA;
}
-static inline bool imx_i2c_direction_is_tx(IMXI2CState *s)
-{
- return s->i2cr & I2CR_MTX;
-}
-
static void imx_i2c_reset(DeviceState *dev)
{
IMXI2CState *s = IMX_I2C(dev);
thanks
-- PMM
^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform
2015-09-04 15:05 ` [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform Peter Maydell
@ 2015-09-27 19:48 ` Peter Crosthwaite
2015-09-27 19:52 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Crosthwaite @ 2015-09-27 19:48 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel@nongnu.org Developers
On Fri, Sep 4, 2015 at 8:05 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> From: Jean-Christophe Dubois <jcd@tribudubois.net>
>
> Tested by booting a minimal Linux system on the emulated platform
> Tested by booting the Xvisor hypervisor on the emulated platform
>
> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
> Message-id: d27347300d253509d921bc27a6d0a14db877478b.1441057361.git.jcd@tribudubois.net
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/Makefile.objs | 2 +-
> hw/arm/imx25_pdk.c | 159 +++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 160 insertions(+), 1 deletion(-)
> create mode 100644 hw/arm/imx25_pdk.c
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index b83aaca..2195b60 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -13,5 +13,5 @@ obj-y += omap1.o omap2.o strongarm.o
> obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
> obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
> obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
> -obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o
> +obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
> obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
> new file mode 100644
> index 0000000..c34667f
> --- /dev/null
> +++ b/hw/arm/imx25_pdk.c
> @@ -0,0 +1,159 @@
> +/*
> + * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
> + *
> + * PDK Board System emulation.
> + *
> + * Based on hw/arm/kzm.c
> + *
> + * Copyright (c) 2008 OKL and 2011 NICTA
> + * Written by Hans at OK-Labs
> + * Updated by Peter Chubb.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "hw/arm/fsl-imx25.h"
> +#include "hw/boards.h"
> +#include "qemu/error-report.h"
> +#include "exec/address-spaces.h"
> +#include "sysemu/qtest.h"
> +#include "hw/i2c/i2c.h"
> +
> +/* Memory map for PDK Emulation Baseboard:
> + * 0x00000000-0x7fffffff See i.MX25 SOC fr support
> + * 0x80000000-0x87ffffff RAM + Alias EMULATED
> + * 0x90000000-0x9fffffff RAM + Alias EMULATED
> + * 0xa0000000-0xa7ffffff Flash IGNORED
> + * 0xa8000000-0xafffffff Flash IGNORED
> + * 0xb0000000-0xb1ffffff SRAM IGNORED
> + * 0xb2000000-0xb3ffffff SRAM IGNORED
> + * 0xb4000000-0xb5ffffff CS4 IGNORED
> + * 0xb6000000-0xb8000fff Reserved IGNORED
> + * 0xb8001000-0xb8001fff SDRAM CTRL reg IGNORED
> + * 0xb8002000-0xb8002fff WEIM CTRL reg IGNORED
> + * 0xb8003000-0xb8003fff M3IF CTRL reg IGNORED
> + * 0xb8004000-0xb8004fff EMI CTRL reg IGNORED
> + * 0xb8005000-0xbaffffff Reserved IGNORED
> + * 0xbb000000-0xbb000fff NAND flash area buf IGNORED
> + * 0xbb001000-0xbb0011ff NAND flash reserved IGNORED
> + * 0xbb001200-0xbb001dff Reserved IGNORED
> + * 0xbb001e00-0xbb001fff NAN flash CTRL reg IGNORED
> + * 0xbb012000-0xbfffffff Reserved IGNORED
> + * 0xc0000000-0xffffffff Reserved IGNORED
> + */
> +
> +typedef struct IMX25PDK {
> + FslIMX25State soc;
> + MemoryRegion ram;
> + MemoryRegion ram_alias;
> +} IMX25PDK;
> +
> +static struct arm_boot_info imx25_pdk_binfo;
> +
> +static void imx25_pdk_init(MachineState *machine)
> +{
> + IMX25PDK *s = g_new0(IMX25PDK, 1);
> + Error *err = NULL;
> + unsigned int ram_size;
> + unsigned int alias_offset;
> + int i;
> +
> + object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX25);
> + object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
> + &error_abort);
> +
> + object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
> + if (err != NULL) {
> + error_report("%s", error_get_pretty(err));
> + exit(1);
> + }
> +
> + /* We need to initialize our memory */
> + if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) {
> + error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
> + "reduced to %x", machine->ram_size,
> + FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE);
> + machine->ram_size = FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE;
> + }
> +
> + memory_region_allocate_system_memory(&s->ram, NULL, "imx25.ram",
> + machine->ram_size);
> + memory_region_add_subregion(get_system_memory(), FSL_IMX25_SDRAM0_ADDR,
> + &s->ram);
> +
> + /* initialize the alias memory if any */
> + for (i = 0, ram_size = machine->ram_size, alias_offset = 0;
> + (i < 2) && ram_size; i++) {
> + unsigned int size;
> + static const struct {
> + hwaddr addr;
> + unsigned int size;
> + } ram[2] = {
> + { FSL_IMX25_SDRAM0_ADDR, FSL_IMX25_SDRAM0_SIZE },
> + { FSL_IMX25_SDRAM1_ADDR, FSL_IMX25_SDRAM1_SIZE },
> + };
> +
> + size = MIN(ram_size, ram[i].size);
> +
> + ram_size -= size;
> +
> + if (size < ram[i].size) {
> + memory_region_init_alias(&s->ram_alias, NULL, "ram.alias",
> + &s->ram, alias_offset, ram[i].size - size);
> + memory_region_add_subregion(get_system_memory(),
> + ram[i].addr + size, &s->ram_alias);
> + }
> +
> + alias_offset += ram[i].size;
> + }
> +
> + imx25_pdk_binfo.ram_size = machine->ram_size;
> + imx25_pdk_binfo.kernel_filename = machine->kernel_filename;
> + imx25_pdk_binfo.kernel_cmdline = machine->kernel_cmdline;
> + imx25_pdk_binfo.initrd_filename = machine->initrd_filename;
> + imx25_pdk_binfo.loader_start = FSL_IMX25_SDRAM0_ADDR;
> + imx25_pdk_binfo.board_id = 1771,
> + imx25_pdk_binfo.nb_cpus = 1;
> +
> + /*
> + * We test explicitly for qtest here as it is not done (yet?) in
> + * arm_load_kernel(). Without this the "make check" command would
> + * fail.
> + */
> + if (!qtest_enabled()) {
> + arm_load_kernel(&s->soc.cpu, &imx25_pdk_binfo);
> + } else {
> + /*
> + * This I2C device doesn't exist on the real board.
> + * We add it here (only on qtest usage) to be able to do a bit
> + * of simple qtest. See "make check" for details.
> + */
> + i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(&s->soc.i2c[0]),
> + "i2c"),
> + "ds1338", 0x68);
> + }
> +}
> +
> +static QEMUMachine imx25_pdk_machine = {
> + .name = "imx25_pdk",
I'm looking at the full ARM board list, and all other use - instead of
_. Can we fix this before this board sees a release?
Regards,
Peter
> + .desc = "ARM i.MX25 PDK board (ARM926)",
> + .init = imx25_pdk_init,
> +};
> +
> +static void imx25_pdk_machine_init(void)
> +{
> + qemu_register_machine(&imx25_pdk_machine);
> +}
> +
> +machine_init(imx25_pdk_machine_init)
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform
2015-09-27 19:48 ` Peter Crosthwaite
@ 2015-09-27 19:52 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-27 19:52 UTC (permalink / raw)
To: Peter Crosthwaite
Cc: qemu-devel@nongnu.org Developers, Jean-Christophe Dubois
On 27 September 2015 at 20:48, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Fri, Sep 4, 2015 at 8:05 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> From: Jean-Christophe Dubois <jcd@tribudubois.net>
>>
>> Tested by booting a minimal Linux system on the emulated platform
>> Tested by booting the Xvisor hypervisor on the emulated platform
>>
>> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
>> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
>> Message-id: d27347300d253509d921bc27a6d0a14db877478b.1441057361.git.jcd@tribudubois.net
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> +static QEMUMachine imx25_pdk_machine = {
>> + .name = "imx25_pdk",
>
> I'm looking at the full ARM board list, and all other use - instead of
> _. Can we fix this before this board sees a release?
Makes sense. Are you going to send a patch?
thanks
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (20 preceding siblings ...)
2019-02-15 2:24 ` no-reply
@ 2019-02-15 2:43 ` no-reply
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 2:43 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
79f823dd50 gdbstub: Send a reply to the vKill packet.
54055c690e target/arm: Add missing clear_tail calls
256e4557f2 target/arm: Use vector operations for saturation
dac47f6b64 target/arm: Split out FPSCR.QC to a vector field
dffbd3cd1b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
003ad968a8 target/arm: Split out flags setting from vfp compares
8e2cdb45d1 target/arm: Fix arm_cpu_dump_state vs FPSCR
c6859c1a84 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
6a0a150b2d target/arm: Remove neon min/max helpers
ced3d5e3d9 target/arm: Use tcg integer min/max primitives for neon
0f1a572c84 target/arm: Use vector minmax expanders for aarch32
66e0205bc3 target/arm: Use vector minmax expanders for aarch64
2ce0e8773f target/arm: Rely on optimization within tcg_gen_gvec_or
6bd399ef3d hw/arm/armsse: Fix miswiring of expansion IRQs
ee3a0f2e15 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
f2bd89cfd3 MAINTAINERS: Remove Peter Crosthwaite from various entries
0d2f803513 arm: Allow system registers for KVM guests to be changed by QEMU code
8d7c1af9f3 linux-user/elfload: enable HWCAP_CPUID for AArch64
87d553b62c target/arm: expose remaining CPUID registers as RAZ
2296abadfb target/arm: expose MPIDR_EL1 to userspace
682347fb9e target/arm: expose CPUID registers to userspace
61e1e876ae target/arm: relax permission checks for HWCAP_CPUID registers
a03d01166b target/arm: Restructure disas_fp_int_conv
49c75fb14d target/arm: Force result size into dp after operation
b311548ce5 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
6d9154655f target/arm: Implement HACR_EL2
b6a2f6e7d0 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit b6a2f6e7d009 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 6d9154655f8f (target/arm: Implement HACR_EL2)
3/27 Checking commit b311548ce515 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 49c75fb14d08 (target/arm: Force result size into dp after operation)
5/27 Checking commit a03d01166b02 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 61e1e876ae47 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 682347fb9e39 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 2296abadfb9a (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 87d553b62c30 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 8d7c1af9f3f9 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 0d2f8035130d (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit f2bd89cfd3fb (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit ee3a0f2e1566 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 6bd399ef3d57 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 2ce0e8773f22 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 66e0205bc37e (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 0f1a572c8401 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit ced3d5e3d9eb (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 6a0a150b2da5 (target/arm: Remove neon min/max helpers)
20/27 Checking commit c6859c1a849d (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 8e2cdb45d186 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 003ad968a808 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit dffbd3cd1b4d (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit dac47f6b645f (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 256e4557f2e8 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 54055c690e1f (target/arm: Add missing clear_tail calls)
27/27 Checking commit 79f823dd5021 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (19 preceding siblings ...)
2019-02-15 2:19 ` no-reply
@ 2019-02-15 2:24 ` no-reply
2019-02-15 2:43 ` no-reply
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 2:24 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
6035ee1d0b gdbstub: Send a reply to the vKill packet.
6abc10e3cf target/arm: Add missing clear_tail calls
3b446a483a target/arm: Use vector operations for saturation
5ae122d95f target/arm: Split out FPSCR.QC to a vector field
dcf4734824 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
93f672cd3e target/arm: Split out flags setting from vfp compares
a4923fb2a2 target/arm: Fix arm_cpu_dump_state vs FPSCR
59b60a009c target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
2d72031bc3 target/arm: Remove neon min/max helpers
0dc3071aa6 target/arm: Use tcg integer min/max primitives for neon
12249be0d4 target/arm: Use vector minmax expanders for aarch32
210b86c4d0 target/arm: Use vector minmax expanders for aarch64
ec442a042e target/arm: Rely on optimization within tcg_gen_gvec_or
ec303c3244 hw/arm/armsse: Fix miswiring of expansion IRQs
8a6530ed11 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
375c511d5e MAINTAINERS: Remove Peter Crosthwaite from various entries
2a062aa5d8 arm: Allow system registers for KVM guests to be changed by QEMU code
fde061cf2a linux-user/elfload: enable HWCAP_CPUID for AArch64
345f47dc8b target/arm: expose remaining CPUID registers as RAZ
b96e5b9001 target/arm: expose MPIDR_EL1 to userspace
06c582053e target/arm: expose CPUID registers to userspace
8aeda9f436 target/arm: relax permission checks for HWCAP_CPUID registers
e3ceeef98a target/arm: Restructure disas_fp_int_conv
49958fb0df target/arm: Force result size into dp after operation
fc1287b91f target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
fa29b1076a target/arm: Implement HACR_EL2
95fcc314e3 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 95fcc314e34d (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit fa29b1076a08 (target/arm: Implement HACR_EL2)
3/27 Checking commit fc1287b91f25 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 49958fb0df5d (target/arm: Force result size into dp after operation)
5/27 Checking commit e3ceeef98ab2 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 8aeda9f436db (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 06c582053ec6 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit b96e5b900130 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 345f47dc8bac (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit fde061cf2ae3 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 2a062aa5d85a (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 375c511d5ef0 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 8a6530ed11d6 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit ec303c324426 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit ec442a042e1b (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 210b86c4d0a5 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 12249be0d48f (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 0dc3071aa652 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 2d72031bc357 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 59b60a009c37 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit a4923fb2a25e (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 93f672cd3e36 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit dcf4734824cb (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 5ae122d95fb6 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 3b446a483a40 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 6abc10e3cfa5 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 6035ee1d0be8 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (18 preceding siblings ...)
2019-02-15 2:15 ` no-reply
@ 2019-02-15 2:19 ` no-reply
2019-02-15 2:24 ` no-reply
2019-02-15 2:43 ` no-reply
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 2:19 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
1e820f4 gdbstub: Send a reply to the vKill packet.
4b56c88 target/arm: Add missing clear_tail calls
e143845 target/arm: Use vector operations for saturation
a14a04e target/arm: Split out FPSCR.QC to a vector field
b9fc85b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
29d6aa1 target/arm: Split out flags setting from vfp compares
13dc2aa target/arm: Fix arm_cpu_dump_state vs FPSCR
bc2c229 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
e53cd7d target/arm: Remove neon min/max helpers
bf7d4d0 target/arm: Use tcg integer min/max primitives for neon
c592edc target/arm: Use vector minmax expanders for aarch32
cb8987e target/arm: Use vector minmax expanders for aarch64
f6edfc4 target/arm: Rely on optimization within tcg_gen_gvec_or
45a5069 hw/arm/armsse: Fix miswiring of expansion IRQs
eabbdbb hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
8f90489 MAINTAINERS: Remove Peter Crosthwaite from various entries
43cd666 arm: Allow system registers for KVM guests to be changed by QEMU code
14ff7ec linux-user/elfload: enable HWCAP_CPUID for AArch64
a3ad95f target/arm: expose remaining CPUID registers as RAZ
a72a7f2 target/arm: expose MPIDR_EL1 to userspace
5cff337 target/arm: expose CPUID registers to userspace
56a00d6 target/arm: relax permission checks for HWCAP_CPUID registers
4d6cbb2 target/arm: Restructure disas_fp_int_conv
3a6c815 target/arm: Force result size into dp after operation
58d010b target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
07c4523 target/arm: Implement HACR_EL2
4c11ba7 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 4c11ba7a474f (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 07c45234c380 (target/arm: Implement HACR_EL2)
3/27 Checking commit 58d010bbd1a4 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 3a6c8150ed4a (target/arm: Force result size into dp after operation)
5/27 Checking commit 4d6cbb28c5ba (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 56a00d6429b0 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 5cff3370be15 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit a72a7f23daec (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit a3ad95ffd508 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 14ff7ecc19f0 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 43cd666a9ee0 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 8f9048912404 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit eabbdbb6db70 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 45a5069fad23 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit f6edfc43420c (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit cb8987e56aae (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit c592edc6dd12 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit bf7d4d099b2c (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit e53cd7d0b768 (target/arm: Remove neon min/max helpers)
20/27 Checking commit bc2c229b10ce (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 13dc2aabab5f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 29d6aa1c6b90 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit b9fc85bc9f7a (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit a14a04e6bde9 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit e1438456d444 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 4b56c889a3e1 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 1e820f425d28 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (17 preceding siblings ...)
2019-02-15 1:56 ` no-reply
@ 2019-02-15 2:15 ` no-reply
2019-02-15 2:19 ` no-reply
` (2 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 2:15 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
1e820f425d gdbstub: Send a reply to the vKill packet.
4b56c889a3 target/arm: Add missing clear_tail calls
e1438456d4 target/arm: Use vector operations for saturation
a14a04e6bd target/arm: Split out FPSCR.QC to a vector field
b9fc85bc9f target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
29d6aa1c6b target/arm: Split out flags setting from vfp compares
13dc2aabab target/arm: Fix arm_cpu_dump_state vs FPSCR
bc2c229b10 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
e53cd7d0b7 target/arm: Remove neon min/max helpers
bf7d4d099b target/arm: Use tcg integer min/max primitives for neon
c592edc6dd target/arm: Use vector minmax expanders for aarch32
cb8987e56a target/arm: Use vector minmax expanders for aarch64
f6edfc4342 target/arm: Rely on optimization within tcg_gen_gvec_or
45a5069fad hw/arm/armsse: Fix miswiring of expansion IRQs
eabbdbb6db hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
8f90489124 MAINTAINERS: Remove Peter Crosthwaite from various entries
43cd666a9e arm: Allow system registers for KVM guests to be changed by QEMU code
14ff7ecc19 linux-user/elfload: enable HWCAP_CPUID for AArch64
a3ad95ffd5 target/arm: expose remaining CPUID registers as RAZ
a72a7f23da target/arm: expose MPIDR_EL1 to userspace
5cff3370be target/arm: expose CPUID registers to userspace
56a00d6429 target/arm: relax permission checks for HWCAP_CPUID registers
4d6cbb28c5 target/arm: Restructure disas_fp_int_conv
3a6c8150ed target/arm: Force result size into dp after operation
58d010bbd1 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
07c45234c3 target/arm: Implement HACR_EL2
4c11ba7a47 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 4c11ba7a474f (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 07c45234c380 (target/arm: Implement HACR_EL2)
3/27 Checking commit 58d010bbd1a4 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 3a6c8150ed4a (target/arm: Force result size into dp after operation)
5/27 Checking commit 4d6cbb28c5ba (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 56a00d6429b0 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 5cff3370be15 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit a72a7f23daec (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit a3ad95ffd508 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 14ff7ecc19f0 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 43cd666a9ee0 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 8f9048912404 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit eabbdbb6db70 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 45a5069fad23 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit f6edfc43420c (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit cb8987e56aae (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit c592edc6dd12 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit bf7d4d099b2c (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit e53cd7d0b768 (target/arm: Remove neon min/max helpers)
20/27 Checking commit bc2c229b10ce (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 13dc2aabab5f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 29d6aa1c6b90 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit b9fc85bc9f7a (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit a14a04e6bde9 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit e1438456d444 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 4b56c889a3e1 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 1e820f425d28 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (16 preceding siblings ...)
2019-02-15 1:48 ` no-reply
@ 2019-02-15 1:56 ` no-reply
2019-02-15 2:15 ` no-reply
` (3 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:56 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
11ea4f3150 gdbstub: Send a reply to the vKill packet.
be0c840de4 target/arm: Add missing clear_tail calls
23ca71bf65 target/arm: Use vector operations for saturation
32960e7603 target/arm: Split out FPSCR.QC to a vector field
1145bf059b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
754737362f target/arm: Split out flags setting from vfp compares
9eae8889db target/arm: Fix arm_cpu_dump_state vs FPSCR
0ce5d35ee2 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
02666e516f target/arm: Remove neon min/max helpers
4d27e98f16 target/arm: Use tcg integer min/max primitives for neon
8e31e0c833 target/arm: Use vector minmax expanders for aarch32
be6d1d7c04 target/arm: Use vector minmax expanders for aarch64
9c42a28eca target/arm: Rely on optimization within tcg_gen_gvec_or
df0e032414 hw/arm/armsse: Fix miswiring of expansion IRQs
84a7951b4a hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
514aa8eda1 MAINTAINERS: Remove Peter Crosthwaite from various entries
b9286febf7 arm: Allow system registers for KVM guests to be changed by QEMU code
7f9135d2ce linux-user/elfload: enable HWCAP_CPUID for AArch64
9fd22cfa69 target/arm: expose remaining CPUID registers as RAZ
9c0d85264b target/arm: expose MPIDR_EL1 to userspace
fb5effe844 target/arm: expose CPUID registers to userspace
ebebfe1ea5 target/arm: relax permission checks for HWCAP_CPUID registers
6ba2008b2f target/arm: Restructure disas_fp_int_conv
dfa0134d29 target/arm: Force result size into dp after operation
035fc662c1 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
bd1643769b target/arm: Implement HACR_EL2
5d9278ba69 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 5d9278ba6904 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit bd1643769bf4 (target/arm: Implement HACR_EL2)
3/27 Checking commit 035fc662c10f (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit dfa0134d2938 (target/arm: Force result size into dp after operation)
5/27 Checking commit 6ba2008b2f9f (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit ebebfe1ea53d (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit fb5effe8444a (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 9c0d85264bd2 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 9fd22cfa696b (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 7f9135d2ce3c (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit b9286febf73f (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 514aa8eda196 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 84a7951b4a75 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit df0e032414fb (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 9c42a28eca48 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit be6d1d7c044b (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 8e31e0c83344 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 4d27e98f164d (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 02666e516fbe (target/arm: Remove neon min/max helpers)
20/27 Checking commit 0ce5d35ee28b (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 9eae8889dbe3 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 754737362f1b (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 1145bf059b88 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 32960e760343 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 23ca71bf6538 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit be0c840de44a (target/arm: Add missing clear_tail calls)
27/27 Checking commit 11ea4f315038 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (15 preceding siblings ...)
2019-02-15 1:32 ` no-reply
@ 2019-02-15 1:48 ` no-reply
2019-02-15 1:56 ` no-reply
` (4 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:48 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
73ac529141 gdbstub: Send a reply to the vKill packet.
4b247465c1 target/arm: Add missing clear_tail calls
89be70063e target/arm: Use vector operations for saturation
e77ac93de2 target/arm: Split out FPSCR.QC to a vector field
c22864f292 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
ff918185bd target/arm: Split out flags setting from vfp compares
11f919937a target/arm: Fix arm_cpu_dump_state vs FPSCR
dd99a43005 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
e004fed65e target/arm: Remove neon min/max helpers
8f4545ca63 target/arm: Use tcg integer min/max primitives for neon
ab9ebe5a3d target/arm: Use vector minmax expanders for aarch32
72d6045bf1 target/arm: Use vector minmax expanders for aarch64
a7e7d40b7b target/arm: Rely on optimization within tcg_gen_gvec_or
990b62b71d hw/arm/armsse: Fix miswiring of expansion IRQs
ea4ce7fac8 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
40282cba68 MAINTAINERS: Remove Peter Crosthwaite from various entries
530553605c arm: Allow system registers for KVM guests to be changed by QEMU code
cf4f6b485e linux-user/elfload: enable HWCAP_CPUID for AArch64
c38db4cedc target/arm: expose remaining CPUID registers as RAZ
bc98ce37e8 target/arm: expose MPIDR_EL1 to userspace
5b3cbe3a2c target/arm: expose CPUID registers to userspace
3cbbe863dd target/arm: relax permission checks for HWCAP_CPUID registers
9054387819 target/arm: Restructure disas_fp_int_conv
72c798db01 target/arm: Force result size into dp after operation
9b1c8067b0 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
c2f33f799d target/arm: Implement HACR_EL2
5d803e29a6 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 5d803e29a608 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit c2f33f799db1 (target/arm: Implement HACR_EL2)
3/27 Checking commit 9b1c8067b058 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 72c798db0186 (target/arm: Force result size into dp after operation)
5/27 Checking commit 905438781946 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 3cbbe863ddc4 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 5b3cbe3a2cb1 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit bc98ce37e86a (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit c38db4cedc34 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit cf4f6b485e7d (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 530553605c71 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 40282cba687a (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit ea4ce7fac88a (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 990b62b71dd4 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit a7e7d40b7b98 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 72d6045bf127 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit ab9ebe5a3d40 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 8f4545ca6381 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit e004fed65e8b (target/arm: Remove neon min/max helpers)
20/27 Checking commit dd99a430053c (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 11f919937a85 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit ff918185bd76 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit c22864f2927f (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit e77ac93de248 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 89be70063eac (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 4b247465c1e0 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 73ac529141df (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (14 preceding siblings ...)
2019-02-15 1:28 ` no-reply
@ 2019-02-15 1:32 ` no-reply
2019-02-15 1:48 ` no-reply
` (5 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:32 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
6553235 gdbstub: Send a reply to the vKill packet.
c94c565 target/arm: Add missing clear_tail calls
026b9af target/arm: Use vector operations for saturation
c075e4f target/arm: Split out FPSCR.QC to a vector field
682ec57 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
8e880e0 target/arm: Split out flags setting from vfp compares
87c2a20 target/arm: Fix arm_cpu_dump_state vs FPSCR
0918b54 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
2b68e10 target/arm: Remove neon min/max helpers
6e628b4 target/arm: Use tcg integer min/max primitives for neon
b98c382 target/arm: Use vector minmax expanders for aarch32
b5f8871 target/arm: Use vector minmax expanders for aarch64
bb7653f target/arm: Rely on optimization within tcg_gen_gvec_or
cddac75 hw/arm/armsse: Fix miswiring of expansion IRQs
2a5cd58 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
83f6ca0 MAINTAINERS: Remove Peter Crosthwaite from various entries
f66e7b2 arm: Allow system registers for KVM guests to be changed by QEMU code
8f129e3 linux-user/elfload: enable HWCAP_CPUID for AArch64
82b82f4 target/arm: expose remaining CPUID registers as RAZ
2632f88 target/arm: expose MPIDR_EL1 to userspace
4430a67 target/arm: expose CPUID registers to userspace
1ed25cb target/arm: relax permission checks for HWCAP_CPUID registers
705b021 target/arm: Restructure disas_fp_int_conv
8cb3bd0 target/arm: Force result size into dp after operation
579d84d target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
6544e76 target/arm: Implement HACR_EL2
75e724d target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 75e724d7297a (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 6544e760c431 (target/arm: Implement HACR_EL2)
3/27 Checking commit 579d84d2eaa8 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 8cb3bd05da03 (target/arm: Force result size into dp after operation)
5/27 Checking commit 705b021f0005 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 1ed25cbabab7 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 4430a6761146 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 2632f88ceebd (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 82b82f40c0c9 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 8f129e350d23 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit f66e7b248819 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 83f6ca0a1ebf (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 2a5cd585f1d3 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit cddac7511c9e (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit bb7653f060ac (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit b5f88711f2a2 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit b98c382660f7 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 6e628b4a95f8 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 2b68e10ae9c7 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 0918b540445f (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 87c2a204a651 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 8e880e02c632 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 682ec57ab2cf (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit c075e4f90bb4 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 026b9afc537c (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit c94c5655eef4 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 6553235a7219 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (13 preceding siblings ...)
2019-02-15 1:24 ` no-reply
@ 2019-02-15 1:28 ` no-reply
2019-02-15 1:32 ` no-reply
` (6 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:28 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
6553235a72 gdbstub: Send a reply to the vKill packet.
c94c5655ee target/arm: Add missing clear_tail calls
026b9afc53 target/arm: Use vector operations for saturation
c075e4f90b target/arm: Split out FPSCR.QC to a vector field
682ec57ab2 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
8e880e02c6 target/arm: Split out flags setting from vfp compares
87c2a204a6 target/arm: Fix arm_cpu_dump_state vs FPSCR
0918b54044 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
2b68e10ae9 target/arm: Remove neon min/max helpers
6e628b4a95 target/arm: Use tcg integer min/max primitives for neon
b98c382660 target/arm: Use vector minmax expanders for aarch32
b5f88711f2 target/arm: Use vector minmax expanders for aarch64
bb7653f060 target/arm: Rely on optimization within tcg_gen_gvec_or
cddac7511c hw/arm/armsse: Fix miswiring of expansion IRQs
2a5cd585f1 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
83f6ca0a1e MAINTAINERS: Remove Peter Crosthwaite from various entries
f66e7b2488 arm: Allow system registers for KVM guests to be changed by QEMU code
8f129e350d linux-user/elfload: enable HWCAP_CPUID for AArch64
82b82f40c0 target/arm: expose remaining CPUID registers as RAZ
2632f88cee target/arm: expose MPIDR_EL1 to userspace
4430a67611 target/arm: expose CPUID registers to userspace
1ed25cbaba target/arm: relax permission checks for HWCAP_CPUID registers
705b021f00 target/arm: Restructure disas_fp_int_conv
8cb3bd05da target/arm: Force result size into dp after operation
579d84d2ea target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
6544e760c4 target/arm: Implement HACR_EL2
75e724d729 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 75e724d7297a (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 6544e760c431 (target/arm: Implement HACR_EL2)
3/27 Checking commit 579d84d2eaa8 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 8cb3bd05da03 (target/arm: Force result size into dp after operation)
5/27 Checking commit 705b021f0005 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 1ed25cbabab7 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 4430a6761146 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 2632f88ceebd (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 82b82f40c0c9 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 8f129e350d23 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit f66e7b248819 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 83f6ca0a1ebf (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 2a5cd585f1d3 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit cddac7511c9e (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit bb7653f060ac (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit b5f88711f2a2 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit b98c382660f7 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 6e628b4a95f8 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 2b68e10ae9c7 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 0918b540445f (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 87c2a204a651 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 8e880e02c632 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 682ec57ab2cf (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit c075e4f90bb4 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 026b9afc537c (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit c94c5655eef4 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 6553235a7219 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (12 preceding siblings ...)
2019-02-15 1:20 ` no-reply
@ 2019-02-15 1:24 ` no-reply
2019-02-15 1:28 ` no-reply
` (7 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:24 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190214102816.3393-1-peter.maydell@linaro.org -> patchew/20190214102816.3393-1-peter.maydell@linaro.org
- [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
8fd00e6 gdbstub: Send a reply to the vKill packet.
34aa54e target/arm: Add missing clear_tail calls
3846dbe target/arm: Use vector operations for saturation
781e41b target/arm: Split out FPSCR.QC to a vector field
95ef691 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
d640c73 target/arm: Split out flags setting from vfp compares
a556351 target/arm: Fix arm_cpu_dump_state vs FPSCR
6e9dcb5 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
bd99640 target/arm: Remove neon min/max helpers
5246212 target/arm: Use tcg integer min/max primitives for neon
28d1ed9 target/arm: Use vector minmax expanders for aarch32
f835440 target/arm: Use vector minmax expanders for aarch64
2fc345a target/arm: Rely on optimization within tcg_gen_gvec_or
5aafc65 hw/arm/armsse: Fix miswiring of expansion IRQs
c85153c hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
4ec0189 MAINTAINERS: Remove Peter Crosthwaite from various entries
45ab292 arm: Allow system registers for KVM guests to be changed by QEMU code
3382e5f linux-user/elfload: enable HWCAP_CPUID for AArch64
1d9bc81 target/arm: expose remaining CPUID registers as RAZ
ba7bf1b target/arm: expose MPIDR_EL1 to userspace
9ee0c2a target/arm: expose CPUID registers to userspace
a443302 target/arm: relax permission checks for HWCAP_CPUID registers
f59f8c9 target/arm: Restructure disas_fp_int_conv
e9d6907 target/arm: Force result size into dp after operation
aeaa89a target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7124a83 target/arm: Implement HACR_EL2
8820060 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 88200603a8cb (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7124a830e497 (target/arm: Implement HACR_EL2)
3/27 Checking commit aeaa89ad8291 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit e9d6907528aa (target/arm: Force result size into dp after operation)
5/27 Checking commit f59f8c968ae5 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit a44330292615 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 9ee0c2aab31c (target/arm: expose CPUID registers to userspace)
8/27 Checking commit ba7bf1bc03e1 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 1d9bc813e57b (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 3382e5fb3a55 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 45ab2928675e (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 4ec0189e9352 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit c85153c2d903 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 5aafc658edab (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 2fc345aa780c (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit f8354404a2f8 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 28d1ed93b13a (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 524621238d29 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit bd9964085387 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 6e9dcb58eb81 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit a5563518a586 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit d640c730a965 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 95ef6915a6d0 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 781e41b075a0 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 3846dbef44da (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 34aa54edfa31 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 8fd00e6381cf (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (11 preceding siblings ...)
2019-02-15 1:01 ` no-reply
@ 2019-02-15 1:20 ` no-reply
2019-02-15 1:24 ` no-reply
` (8 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:20 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
8fd00e6381 gdbstub: Send a reply to the vKill packet.
34aa54edfa target/arm: Add missing clear_tail calls
3846dbef44 target/arm: Use vector operations for saturation
781e41b075 target/arm: Split out FPSCR.QC to a vector field
95ef6915a6 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
d640c730a9 target/arm: Split out flags setting from vfp compares
a5563518a5 target/arm: Fix arm_cpu_dump_state vs FPSCR
6e9dcb58eb target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
bd99640853 target/arm: Remove neon min/max helpers
524621238d target/arm: Use tcg integer min/max primitives for neon
28d1ed93b1 target/arm: Use vector minmax expanders for aarch32
f8354404a2 target/arm: Use vector minmax expanders for aarch64
2fc345aa78 target/arm: Rely on optimization within tcg_gen_gvec_or
5aafc658ed hw/arm/armsse: Fix miswiring of expansion IRQs
c85153c2d9 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
4ec0189e93 MAINTAINERS: Remove Peter Crosthwaite from various entries
45ab292867 arm: Allow system registers for KVM guests to be changed by QEMU code
3382e5fb3a linux-user/elfload: enable HWCAP_CPUID for AArch64
1d9bc813e5 target/arm: expose remaining CPUID registers as RAZ
ba7bf1bc03 target/arm: expose MPIDR_EL1 to userspace
9ee0c2aab3 target/arm: expose CPUID registers to userspace
a443302926 target/arm: relax permission checks for HWCAP_CPUID registers
f59f8c968a target/arm: Restructure disas_fp_int_conv
e9d6907528 target/arm: Force result size into dp after operation
aeaa89ad82 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7124a830e4 target/arm: Implement HACR_EL2
88200603a8 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 88200603a8cb (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7124a830e497 (target/arm: Implement HACR_EL2)
3/27 Checking commit aeaa89ad8291 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit e9d6907528aa (target/arm: Force result size into dp after operation)
5/27 Checking commit f59f8c968ae5 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit a44330292615 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 9ee0c2aab31c (target/arm: expose CPUID registers to userspace)
8/27 Checking commit ba7bf1bc03e1 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 1d9bc813e57b (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 3382e5fb3a55 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 45ab2928675e (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 4ec0189e9352 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit c85153c2d903 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 5aafc658edab (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 2fc345aa780c (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit f8354404a2f8 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 28d1ed93b13a (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 524621238d29 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit bd9964085387 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 6e9dcb58eb81 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit a5563518a586 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit d640c730a965 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 95ef6915a6d0 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 781e41b075a0 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 3846dbef44da (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 34aa54edfa31 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 8fd00e6381cf (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (10 preceding siblings ...)
2019-02-15 0:38 ` no-reply
@ 2019-02-15 1:01 ` no-reply
2019-02-15 1:20 ` no-reply
` (9 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:01 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
b22c3da64b gdbstub: Send a reply to the vKill packet.
db616b3cea target/arm: Add missing clear_tail calls
240db5cc11 target/arm: Use vector operations for saturation
88a9504b9f target/arm: Split out FPSCR.QC to a vector field
e9d315769a target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
78d9813d1a target/arm: Split out flags setting from vfp compares
7addfd4039 target/arm: Fix arm_cpu_dump_state vs FPSCR
930c986b1b target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
a034668e9b target/arm: Remove neon min/max helpers
bb77972f61 target/arm: Use tcg integer min/max primitives for neon
d4bcca5e91 target/arm: Use vector minmax expanders for aarch32
58c8e77c23 target/arm: Use vector minmax expanders for aarch64
c75e5516d5 target/arm: Rely on optimization within tcg_gen_gvec_or
a3de217232 hw/arm/armsse: Fix miswiring of expansion IRQs
de29583b07 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
8fb1a5bac0 MAINTAINERS: Remove Peter Crosthwaite from various entries
acc80866a5 arm: Allow system registers for KVM guests to be changed by QEMU code
05e851518b linux-user/elfload: enable HWCAP_CPUID for AArch64
1e0293cc26 target/arm: expose remaining CPUID registers as RAZ
0443bd4878 target/arm: expose MPIDR_EL1 to userspace
ad0122bcbf target/arm: expose CPUID registers to userspace
1cc2635c69 target/arm: relax permission checks for HWCAP_CPUID registers
592467aa65 target/arm: Restructure disas_fp_int_conv
af2989a366 target/arm: Force result size into dp after operation
f26458f2fa target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
ee1b241af9 target/arm: Implement HACR_EL2
845bd274c6 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 845bd274c624 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit ee1b241af96d (target/arm: Implement HACR_EL2)
3/27 Checking commit f26458f2fa7e (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit af2989a36697 (target/arm: Force result size into dp after operation)
5/27 Checking commit 592467aa6590 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 1cc2635c6964 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit ad0122bcbfcd (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 0443bd48780a (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 1e0293cc26e0 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 05e851518be8 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit acc80866a588 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 8fb1a5bac0c0 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit de29583b07df (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit a3de21723286 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit c75e5516d5de (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 58c8e77c23c0 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit d4bcca5e9117 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit bb77972f618b (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit a034668e9b5d (target/arm: Remove neon min/max helpers)
20/27 Checking commit 930c986b1b61 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 7addfd403939 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 78d9813d1a48 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit e9d315769a5c (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 88a9504b9f85 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 240db5cc1112 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit db616b3ceae7 (target/arm: Add missing clear_tail calls)
27/27 Checking commit b22c3da64b53 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (9 preceding siblings ...)
2019-02-15 0:34 ` no-reply
@ 2019-02-15 0:38 ` no-reply
2019-02-15 1:01 ` no-reply
` (10 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 0:38 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
f74396d gdbstub: Send a reply to the vKill packet.
52c1857 target/arm: Add missing clear_tail calls
2f1aef9 target/arm: Use vector operations for saturation
80683e5 target/arm: Split out FPSCR.QC to a vector field
5d1d26f target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
06fe487 target/arm: Split out flags setting from vfp compares
d0ce625 target/arm: Fix arm_cpu_dump_state vs FPSCR
f382917 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
21c80ed target/arm: Remove neon min/max helpers
822434e target/arm: Use tcg integer min/max primitives for neon
ec47e8c target/arm: Use vector minmax expanders for aarch32
8e1c96f target/arm: Use vector minmax expanders for aarch64
5ce1275 target/arm: Rely on optimization within tcg_gen_gvec_or
7cf21d5 hw/arm/armsse: Fix miswiring of expansion IRQs
fc4f4fb hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
df4e1ca MAINTAINERS: Remove Peter Crosthwaite from various entries
0818f54 arm: Allow system registers for KVM guests to be changed by QEMU code
29ae44a linux-user/elfload: enable HWCAP_CPUID for AArch64
f5eb2f7 target/arm: expose remaining CPUID registers as RAZ
ac0a143 target/arm: expose MPIDR_EL1 to userspace
0263d9a target/arm: expose CPUID registers to userspace
9b69c06 target/arm: relax permission checks for HWCAP_CPUID registers
d616286 target/arm: Restructure disas_fp_int_conv
385be0d target/arm: Force result size into dp after operation
1cc6b86 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
2d2b73d target/arm: Implement HACR_EL2
86f75dd target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 86f75ddfddfc (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 2d2b73dc4d6c (target/arm: Implement HACR_EL2)
3/27 Checking commit 1cc6b8631d42 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 385be0d0977a (target/arm: Force result size into dp after operation)
5/27 Checking commit d61628698a25 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 9b69c06e28d4 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 0263d9ab2de9 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit ac0a14313eb2 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit f5eb2f7c5740 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 29ae44a5951b (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 0818f544d6cd (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit df4e1ca71de6 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit fc4f4fbe1c98 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 7cf21d564829 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 5ce1275e65ee (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 8e1c96f68344 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit ec47e8c9169b (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 822434eb2677 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 21c80ed9cd6e (target/arm: Remove neon min/max helpers)
20/27 Checking commit f38291710529 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit d0ce62513eae (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 06fe48799dc0 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 5d1d26f9eba9 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 80683e5bc15a (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 2f1aef96ec10 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 52c1857391d8 (target/arm: Add missing clear_tail calls)
27/27 Checking commit f74396d1168a (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (8 preceding siblings ...)
2019-02-15 0:11 ` no-reply
@ 2019-02-15 0:34 ` no-reply
2019-02-15 0:38 ` no-reply
` (11 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 0:34 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
f74396d116 gdbstub: Send a reply to the vKill packet.
52c1857391 target/arm: Add missing clear_tail calls
2f1aef96ec target/arm: Use vector operations for saturation
80683e5bc1 target/arm: Split out FPSCR.QC to a vector field
5d1d26f9eb target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
06fe48799d target/arm: Split out flags setting from vfp compares
d0ce62513e target/arm: Fix arm_cpu_dump_state vs FPSCR
f382917105 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
21c80ed9cd target/arm: Remove neon min/max helpers
822434eb26 target/arm: Use tcg integer min/max primitives for neon
ec47e8c916 target/arm: Use vector minmax expanders for aarch32
8e1c96f683 target/arm: Use vector minmax expanders for aarch64
5ce1275e65 target/arm: Rely on optimization within tcg_gen_gvec_or
7cf21d5648 hw/arm/armsse: Fix miswiring of expansion IRQs
fc4f4fbe1c hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
df4e1ca71d MAINTAINERS: Remove Peter Crosthwaite from various entries
0818f544d6 arm: Allow system registers for KVM guests to be changed by QEMU code
29ae44a595 linux-user/elfload: enable HWCAP_CPUID for AArch64
f5eb2f7c57 target/arm: expose remaining CPUID registers as RAZ
ac0a14313e target/arm: expose MPIDR_EL1 to userspace
0263d9ab2d target/arm: expose CPUID registers to userspace
9b69c06e28 target/arm: relax permission checks for HWCAP_CPUID registers
d61628698a target/arm: Restructure disas_fp_int_conv
385be0d097 target/arm: Force result size into dp after operation
1cc6b8631d target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
2d2b73dc4d target/arm: Implement HACR_EL2
86f75ddfdd target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 86f75ddfddfc (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 2d2b73dc4d6c (target/arm: Implement HACR_EL2)
3/27 Checking commit 1cc6b8631d42 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 385be0d0977a (target/arm: Force result size into dp after operation)
5/27 Checking commit d61628698a25 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 9b69c06e28d4 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 0263d9ab2de9 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit ac0a14313eb2 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit f5eb2f7c5740 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 29ae44a5951b (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 0818f544d6cd (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit df4e1ca71de6 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit fc4f4fbe1c98 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 7cf21d564829 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 5ce1275e65ee (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 8e1c96f68344 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit ec47e8c9169b (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 822434eb2677 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 21c80ed9cd6e (target/arm: Remove neon min/max helpers)
20/27 Checking commit f38291710529 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit d0ce62513eae (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 06fe48799dc0 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 5d1d26f9eba9 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 80683e5bc15a (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 2f1aef96ec10 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 52c1857391d8 (target/arm: Add missing clear_tail calls)
27/27 Checking commit f74396d1168a (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (7 preceding siblings ...)
2019-02-15 0:07 ` no-reply
@ 2019-02-15 0:11 ` no-reply
2019-02-15 0:34 ` no-reply
` (12 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 0:11 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
0d3e41d..0266c73 master -> master
- [tag update] patchew/20190214051440.59167-1-aik@ozlabs.ru -> patchew/20190214051440.59167-1-aik@ozlabs.ru
- [tag update] patchew/20190214154053.15050-1-marcel.apfelbaum@gmail.com -> patchew/20190214154053.15050-1-marcel.apfelbaum@gmail.com
* [new tag] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
* [new tag] patchew/20190214201939.494-1-philmd@redhat.com -> patchew/20190214201939.494-1-philmd@redhat.com
* [new tag] patchew/20190214220453.15858-1-svens@stackframe.org -> patchew/20190214220453.15858-1-svens@stackframe.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
3fb84ac gdbstub: Send a reply to the vKill packet.
1b05bfa target/arm: Add missing clear_tail calls
3306632 target/arm: Use vector operations for saturation
585d823 target/arm: Split out FPSCR.QC to a vector field
0a651b3 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
f1e2193 target/arm: Split out flags setting from vfp compares
cc71f73 target/arm: Fix arm_cpu_dump_state vs FPSCR
e5abdca target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
71ab631 target/arm: Remove neon min/max helpers
d64f047 target/arm: Use tcg integer min/max primitives for neon
565ffb8 target/arm: Use vector minmax expanders for aarch32
f07a332 target/arm: Use vector minmax expanders for aarch64
8566cb4 target/arm: Rely on optimization within tcg_gen_gvec_or
a5516fe hw/arm/armsse: Fix miswiring of expansion IRQs
e7ac553 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
bcc7967 MAINTAINERS: Remove Peter Crosthwaite from various entries
f88d98d arm: Allow system registers for KVM guests to be changed by QEMU code
351c302 linux-user/elfload: enable HWCAP_CPUID for AArch64
5927860 target/arm: expose remaining CPUID registers as RAZ
1629af9 target/arm: expose MPIDR_EL1 to userspace
b9d5d58 target/arm: expose CPUID registers to userspace
44e3fc2 target/arm: relax permission checks for HWCAP_CPUID registers
705c2b3 target/arm: Restructure disas_fp_int_conv
d249dc5 target/arm: Force result size into dp after operation
b7be3ad target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7f06ec4f target/arm: Implement HACR_EL2
8f1fa8a target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 8f1fa8a2d44d (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7f06ec4f82fc (target/arm: Implement HACR_EL2)
3/27 Checking commit b7be3ad1569d (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit d249dc5f667b (target/arm: Force result size into dp after operation)
5/27 Checking commit 705c2b3ae778 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 44e3fc28e6b9 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit b9d5d582d0b8 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 1629af984d31 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 5927860dc734 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 351c302ef060 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit f88d98d2500b (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit bcc7967dcbce (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit e7ac553c2731 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit a5516fece4af (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 8566cb485cc1 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit f07a3327aeb2 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 565ffb817594 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit d64f04762c4e (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 71ab631c3993 (target/arm: Remove neon min/max helpers)
20/27 Checking commit e5abdca84207 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit cc71f739fff8 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit f1e2193373cd (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 0a651b397b27 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 585d8235c31a (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 330663235d62 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 1b05bfa0b021 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 3fb84accb10d (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (6 preceding siblings ...)
2019-02-14 23:39 ` no-reply
@ 2019-02-15 0:07 ` no-reply
2019-02-15 0:11 ` no-reply
` (13 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 0:07 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
3fb84accb1 gdbstub: Send a reply to the vKill packet.
1b05bfa0b0 target/arm: Add missing clear_tail calls
330663235d target/arm: Use vector operations for saturation
585d8235c3 target/arm: Split out FPSCR.QC to a vector field
0a651b397b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
f1e2193373 target/arm: Split out flags setting from vfp compares
cc71f739ff target/arm: Fix arm_cpu_dump_state vs FPSCR
e5abdca842 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
71ab631c39 target/arm: Remove neon min/max helpers
d64f04762c target/arm: Use tcg integer min/max primitives for neon
565ffb8175 target/arm: Use vector minmax expanders for aarch32
f07a3327ae target/arm: Use vector minmax expanders for aarch64
8566cb485c target/arm: Rely on optimization within tcg_gen_gvec_or
a5516fece4 hw/arm/armsse: Fix miswiring of expansion IRQs
e7ac553c27 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
bcc7967dcb MAINTAINERS: Remove Peter Crosthwaite from various entries
f88d98d250 arm: Allow system registers for KVM guests to be changed by QEMU code
351c302ef0 linux-user/elfload: enable HWCAP_CPUID for AArch64
5927860dc7 target/arm: expose remaining CPUID registers as RAZ
1629af984d target/arm: expose MPIDR_EL1 to userspace
b9d5d582d0 target/arm: expose CPUID registers to userspace
44e3fc28e6 target/arm: relax permission checks for HWCAP_CPUID registers
705c2b3ae7 target/arm: Restructure disas_fp_int_conv
d249dc5f66 target/arm: Force result size into dp after operation
b7be3ad156 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7f06ec4f82 target/arm: Implement HACR_EL2
8f1fa8a2d4 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 8f1fa8a2d44d (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7f06ec4f82fc (target/arm: Implement HACR_EL2)
3/27 Checking commit b7be3ad1569d (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit d249dc5f667b (target/arm: Force result size into dp after operation)
5/27 Checking commit 705c2b3ae778 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 44e3fc28e6b9 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit b9d5d582d0b8 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 1629af984d31 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 5927860dc734 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 351c302ef060 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit f88d98d2500b (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit bcc7967dcbce (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit e7ac553c2731 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit a5516fece4af (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 8566cb485cc1 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit f07a3327aeb2 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 565ffb817594 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit d64f04762c4e (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 71ab631c3993 (target/arm: Remove neon min/max helpers)
20/27 Checking commit e5abdca84207 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit cc71f739fff8 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit f1e2193373cd (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 0a651b397b27 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 585d8235c31a (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 330663235d62 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 1b05bfa0b021 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 3fb84accb10d (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (5 preceding siblings ...)
2019-02-14 22:18 ` no-reply
@ 2019-02-14 23:39 ` no-reply
2019-02-15 0:07 ` no-reply
` (14 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 23:39 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
1fcacb9030 gdbstub: Send a reply to the vKill packet.
facc45d026 target/arm: Add missing clear_tail calls
fe47ae1ac0 target/arm: Use vector operations for saturation
beb3acb4a2 target/arm: Split out FPSCR.QC to a vector field
8187800f5f target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
61090e681c target/arm: Split out flags setting from vfp compares
753b33ef6a target/arm: Fix arm_cpu_dump_state vs FPSCR
a6ac25752e target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
70ae1e5a51 target/arm: Remove neon min/max helpers
aa0575d473 target/arm: Use tcg integer min/max primitives for neon
00d818ea1d target/arm: Use vector minmax expanders for aarch32
7e76c6e511 target/arm: Use vector minmax expanders for aarch64
26a48e84cf target/arm: Rely on optimization within tcg_gen_gvec_or
17db94065e hw/arm/armsse: Fix miswiring of expansion IRQs
f5b0afe7e5 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
dafa19baa4 MAINTAINERS: Remove Peter Crosthwaite from various entries
3e133e44a1 arm: Allow system registers for KVM guests to be changed by QEMU code
f2cfb74b09 linux-user/elfload: enable HWCAP_CPUID for AArch64
ca0002eebc target/arm: expose remaining CPUID registers as RAZ
4b893eb212 target/arm: expose MPIDR_EL1 to userspace
9d5e5704e0 target/arm: expose CPUID registers to userspace
b1a6cabff4 target/arm: relax permission checks for HWCAP_CPUID registers
a252f2d3f9 target/arm: Restructure disas_fp_int_conv
095c71f97a target/arm: Force result size into dp after operation
dbb6c95fc5 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
0319bf2a5a target/arm: Implement HACR_EL2
1e79fd6dec target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 1e79fd6decaa (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 0319bf2a5af5 (target/arm: Implement HACR_EL2)
3/27 Checking commit dbb6c95fc539 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 095c71f97a76 (target/arm: Force result size into dp after operation)
5/27 Checking commit a252f2d3f9f7 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit b1a6cabff49f (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 9d5e5704e04b (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 4b893eb21287 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit ca0002eebc43 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit f2cfb74b0916 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 3e133e44a1b8 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit dafa19baa45b (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit f5b0afe7e5f6 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 17db94065e2f (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 26a48e84cf68 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 7e76c6e5113a (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 00d818ea1d8a (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit aa0575d473a8 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 70ae1e5a51e0 (target/arm: Remove neon min/max helpers)
20/27 Checking commit a6ac25752edc (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 753b33ef6a9f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 61090e681cb1 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 8187800f5f67 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit beb3acb4a272 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit fe47ae1ac0ef (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit facc45d0266a (target/arm: Add missing clear_tail calls)
27/27 Checking commit 1fcacb90300d (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (4 preceding siblings ...)
2019-02-14 21:51 ` no-reply
@ 2019-02-14 22:18 ` no-reply
2019-02-14 23:39 ` no-reply
` (15 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 22:18 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
* [new tag] patchew/20190214220453.15858-1-svens@stackframe.org -> patchew/20190214220453.15858-1-svens@stackframe.org
Switched to a new branch 'test'
107d0c1054 gdbstub: Send a reply to the vKill packet.
1cefa94d4c target/arm: Add missing clear_tail calls
2d7acfba65 target/arm: Use vector operations for saturation
4cacb6d477 target/arm: Split out FPSCR.QC to a vector field
af552d5a9a target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
889e25cedd target/arm: Split out flags setting from vfp compares
08ed30fcbd target/arm: Fix arm_cpu_dump_state vs FPSCR
58c34834b4 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
37ba9384f4 target/arm: Remove neon min/max helpers
3fe3bcd56e target/arm: Use tcg integer min/max primitives for neon
7917081632 target/arm: Use vector minmax expanders for aarch32
7be5894710 target/arm: Use vector minmax expanders for aarch64
3dc77fca6e target/arm: Rely on optimization within tcg_gen_gvec_or
0aa85c83b5 hw/arm/armsse: Fix miswiring of expansion IRQs
a171b85781 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
535a7c3670 MAINTAINERS: Remove Peter Crosthwaite from various entries
824e72655d arm: Allow system registers for KVM guests to be changed by QEMU code
c4582c22e5 linux-user/elfload: enable HWCAP_CPUID for AArch64
835edbcab5 target/arm: expose remaining CPUID registers as RAZ
00813a218f target/arm: expose MPIDR_EL1 to userspace
2fad8a0685 target/arm: expose CPUID registers to userspace
876f185d5f target/arm: relax permission checks for HWCAP_CPUID registers
1a8296d2a7 target/arm: Restructure disas_fp_int_conv
9ef7368140 target/arm: Force result size into dp after operation
e6ffe03733 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
0588209db8 target/arm: Implement HACR_EL2
8be75be4ad target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 8be75be4ad21 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 0588209db891 (target/arm: Implement HACR_EL2)
3/27 Checking commit e6ffe03733b4 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 9ef736814077 (target/arm: Force result size into dp after operation)
5/27 Checking commit 1a8296d2a731 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 876f185d5fde (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 2fad8a068527 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 00813a218f3d (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 835edbcab59c (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit c4582c22e533 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 824e72655d47 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 535a7c36704b (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit a171b857817d (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 0aa85c83b58c (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 3dc77fca6e12 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 7be5894710ec (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 7917081632bd (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 3fe3bcd56e94 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 37ba9384f40b (target/arm: Remove neon min/max helpers)
20/27 Checking commit 58c34834b47f (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 08ed30fcbd5f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 889e25cedd73 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit af552d5a9a15 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 4cacb6d47706 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 2d7acfba6561 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 1cefa94d4c1d (target/arm: Add missing clear_tail calls)
27/27 Checking commit 107d0c10546a (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (3 preceding siblings ...)
2019-02-14 21:24 ` no-reply
@ 2019-02-14 21:51 ` no-reply
2019-02-14 22:18 ` no-reply
` (16 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 21:51 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
acf570635b gdbstub: Send a reply to the vKill packet.
cfd8f55e95 target/arm: Add missing clear_tail calls
259bb867b8 target/arm: Use vector operations for saturation
6b04328ef7 target/arm: Split out FPSCR.QC to a vector field
de7292c5a8 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
999ec7bd2d target/arm: Split out flags setting from vfp compares
20031f4d81 target/arm: Fix arm_cpu_dump_state vs FPSCR
7f2ccbe2fc target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
3652215042 target/arm: Remove neon min/max helpers
a2f9ae9d00 target/arm: Use tcg integer min/max primitives for neon
2a97616341 target/arm: Use vector minmax expanders for aarch32
0cbd8e1d73 target/arm: Use vector minmax expanders for aarch64
60dbc19c09 target/arm: Rely on optimization within tcg_gen_gvec_or
612e1a64f9 hw/arm/armsse: Fix miswiring of expansion IRQs
79033fb4ff hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
b0353d09d8 MAINTAINERS: Remove Peter Crosthwaite from various entries
1f2b02b2cd arm: Allow system registers for KVM guests to be changed by QEMU code
06a5266ef7 linux-user/elfload: enable HWCAP_CPUID for AArch64
60eef60261 target/arm: expose remaining CPUID registers as RAZ
dfe0bf2269 target/arm: expose MPIDR_EL1 to userspace
027c283aef target/arm: expose CPUID registers to userspace
641715c1a5 target/arm: relax permission checks for HWCAP_CPUID registers
0fce875951 target/arm: Restructure disas_fp_int_conv
743fa18abf target/arm: Force result size into dp after operation
93602e2cd3 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
59084e04e5 target/arm: Implement HACR_EL2
7150f17967 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 7150f17967aa (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 59084e04e5d6 (target/arm: Implement HACR_EL2)
3/27 Checking commit 93602e2cd3f5 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 743fa18abfb8 (target/arm: Force result size into dp after operation)
5/27 Checking commit 0fce87595153 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 641715c1a53d (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 027c283aef86 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit dfe0bf226921 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 60eef60261b6 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 06a5266ef754 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 1f2b02b2cd7a (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit b0353d09d85b (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 79033fb4ff44 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 612e1a64f9e9 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 60dbc19c096f (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 0cbd8e1d7369 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 2a976163412b (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit a2f9ae9d00dc (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 3652215042cd (target/arm: Remove neon min/max helpers)
20/27 Checking commit 7f2ccbe2fc14 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 20031f4d81ce (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 999ec7bd2d81 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit de7292c5a8d3 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 6b04328ef702 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 259bb867b8c7 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit cfd8f55e9599 (target/arm: Add missing clear_tail calls)
27/27 Checking commit acf570635b34 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (2 preceding siblings ...)
2019-02-14 20:57 ` no-reply
@ 2019-02-14 21:24 ` no-reply
2019-02-14 21:51 ` no-reply
` (17 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 21:24 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
4a5fa28330 gdbstub: Send a reply to the vKill packet.
377a1b0e65 target/arm: Add missing clear_tail calls
f7d3af4abb target/arm: Use vector operations for saturation
df8ca3278b target/arm: Split out FPSCR.QC to a vector field
09d6eda7b5 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
08ed43f236 target/arm: Split out flags setting from vfp compares
13d1fa231c target/arm: Fix arm_cpu_dump_state vs FPSCR
89c3c77cc7 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
9ef6297e49 target/arm: Remove neon min/max helpers
409e13e7c6 target/arm: Use tcg integer min/max primitives for neon
dbcd048d95 target/arm: Use vector minmax expanders for aarch32
35d58be2dc target/arm: Use vector minmax expanders for aarch64
ac2c4a327a target/arm: Rely on optimization within tcg_gen_gvec_or
081212958f hw/arm/armsse: Fix miswiring of expansion IRQs
425d5d76ea hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
1b1ca68043 MAINTAINERS: Remove Peter Crosthwaite from various entries
d313b64e06 arm: Allow system registers for KVM guests to be changed by QEMU code
ad6e481428 linux-user/elfload: enable HWCAP_CPUID for AArch64
ec69944c2a target/arm: expose remaining CPUID registers as RAZ
59b0c47736 target/arm: expose MPIDR_EL1 to userspace
38948116f6 target/arm: expose CPUID registers to userspace
de5c25835f target/arm: relax permission checks for HWCAP_CPUID registers
f2d76c5e1d target/arm: Restructure disas_fp_int_conv
f71a727256 target/arm: Force result size into dp after operation
5a52d23be1 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
b7f2a14413 target/arm: Implement HACR_EL2
eb86b450b4 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit eb86b450b4d2 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit b7f2a1441331 (target/arm: Implement HACR_EL2)
3/27 Checking commit 5a52d23be1a7 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit f71a72725699 (target/arm: Force result size into dp after operation)
5/27 Checking commit f2d76c5e1d0e (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit de5c25835ff7 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 38948116f604 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 59b0c4773654 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit ec69944c2adf (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit ad6e481428ed (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit d313b64e0651 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 1b1ca680431d (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 425d5d76ea60 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 081212958fd9 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit ac2c4a327a45 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 35d58be2dcb7 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit dbcd048d9559 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 409e13e7c607 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 9ef6297e49d3 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 89c3c77cc712 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 13d1fa231c8e (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 08ed43f236ec (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 09d6eda7b5ab (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit df8ca3278b2c (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit f7d3af4abb72 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 377a1b0e655a (target/arm: Add missing clear_tail calls)
27/27 Checking commit 4a5fa2833065 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
2019-02-14 19:56 ` no-reply
2019-02-14 20:30 ` no-reply
@ 2019-02-14 20:57 ` no-reply
2019-02-14 21:24 ` no-reply
` (18 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 20:57 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
8b28bf8c02 gdbstub: Send a reply to the vKill packet.
35e9a92f59 target/arm: Add missing clear_tail calls
679145406a target/arm: Use vector operations for saturation
a14d6bfaf2 target/arm: Split out FPSCR.QC to a vector field
f8fbccbba5 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
ba0918dc3a target/arm: Split out flags setting from vfp compares
97f0d8db7d target/arm: Fix arm_cpu_dump_state vs FPSCR
fcc5258d65 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
496ebd96d8 target/arm: Remove neon min/max helpers
57606e781d target/arm: Use tcg integer min/max primitives for neon
fb20fb9747 target/arm: Use vector minmax expanders for aarch32
09fe9b2ce9 target/arm: Use vector minmax expanders for aarch64
76ee8fbab5 target/arm: Rely on optimization within tcg_gen_gvec_or
a9bf743839 hw/arm/armsse: Fix miswiring of expansion IRQs
a2989bb924 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
d58f7f8928 MAINTAINERS: Remove Peter Crosthwaite from various entries
0db6bcf0f7 arm: Allow system registers for KVM guests to be changed by QEMU code
cc4082ee0d linux-user/elfload: enable HWCAP_CPUID for AArch64
a317a40397 target/arm: expose remaining CPUID registers as RAZ
50b5ab0dc0 target/arm: expose MPIDR_EL1 to userspace
424e73b993 target/arm: expose CPUID registers to userspace
f8c3d064cd target/arm: relax permission checks for HWCAP_CPUID registers
944dfb207b target/arm: Restructure disas_fp_int_conv
770275cef8 target/arm: Force result size into dp after operation
86975d477f target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
0fad7188ea target/arm: Implement HACR_EL2
df8c887922 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit df8c88792230 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 0fad7188ea17 (target/arm: Implement HACR_EL2)
3/27 Checking commit 86975d477ff0 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 770275cef89b (target/arm: Force result size into dp after operation)
5/27 Checking commit 944dfb207b6b (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit f8c3d064cd92 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 424e73b99329 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 50b5ab0dc071 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit a317a4039735 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit cc4082ee0d10 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 0db6bcf0f7ac (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit d58f7f89287b (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit a2989bb92474 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit a9bf743839e7 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 76ee8fbab5cf (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 09fe9b2ce988 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit fb20fb9747a0 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 57606e781d78 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 496ebd96d8f5 (target/arm: Remove neon min/max helpers)
20/27 Checking commit fcc5258d65aa (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 97f0d8db7d84 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit ba0918dc3a40 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit f8fbccbba569 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit a14d6bfaf27b (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 679145406ae5 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 35e9a92f5916 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 8b28bf8c02b6 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
2019-02-14 19:56 ` no-reply
@ 2019-02-14 20:30 ` no-reply
2019-02-14 20:57 ` no-reply
` (19 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 20:30 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
fb39c2e90f gdbstub: Send a reply to the vKill packet.
86563bda9d target/arm: Add missing clear_tail calls
866f1958b4 target/arm: Use vector operations for saturation
7fadd905a7 target/arm: Split out FPSCR.QC to a vector field
3bbf4384f9 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
178fe16ac8 target/arm: Split out flags setting from vfp compares
1fb9548fec target/arm: Fix arm_cpu_dump_state vs FPSCR
c045bbe35f target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
0bfb764ba7 target/arm: Remove neon min/max helpers
4a40d71633 target/arm: Use tcg integer min/max primitives for neon
9eaba50860 target/arm: Use vector minmax expanders for aarch32
e222548533 target/arm: Use vector minmax expanders for aarch64
e77230191f target/arm: Rely on optimization within tcg_gen_gvec_or
3f7cda73b2 hw/arm/armsse: Fix miswiring of expansion IRQs
d93ebe8185 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
cce31aab3d MAINTAINERS: Remove Peter Crosthwaite from various entries
9891e5f6c7 arm: Allow system registers for KVM guests to be changed by QEMU code
ab703f0d5a linux-user/elfload: enable HWCAP_CPUID for AArch64
b4301eab08 target/arm: expose remaining CPUID registers as RAZ
7abf3c8631 target/arm: expose MPIDR_EL1 to userspace
d17bc752d8 target/arm: expose CPUID registers to userspace
721d2c2056 target/arm: relax permission checks for HWCAP_CPUID registers
70d62fd729 target/arm: Restructure disas_fp_int_conv
907d999506 target/arm: Force result size into dp after operation
a20dcecfa6 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
d42d84b7b1 target/arm: Implement HACR_EL2
f1dfc8484b target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit f1dfc8484bc4 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit d42d84b7b110 (target/arm: Implement HACR_EL2)
3/27 Checking commit a20dcecfa649 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 907d99950666 (target/arm: Force result size into dp after operation)
5/27 Checking commit 70d62fd72937 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 721d2c20567e (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit d17bc752d844 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 7abf3c863143 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit b4301eab085b (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit ab703f0d5a46 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 9891e5f6c709 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit cce31aab3d66 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit d93ebe8185a4 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 3f7cda73b20a (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit e77230191f43 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit e222548533b0 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 9eaba5086098 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 4a40d7163314 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 0bfb764ba772 (target/arm: Remove neon min/max helpers)
20/27 Checking commit c045bbe35fd4 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 1fb9548fec41 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 178fe16ac872 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 3bbf4384f995 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 7fadd905a7f3 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 866f1958b4d7 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 86563bda9da9 (target/arm: Add missing clear_tail calls)
27/27 Checking commit fb39c2e90f66 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
@ 2019-02-14 19:56 ` no-reply
2019-02-14 20:30 ` no-reply
` (20 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 19:56 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
0d3e41d5ef..0266c739ab master -> master
* [new tag] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
c903d16f69 gdbstub: Send a reply to the vKill packet.
f41dbe7001 target/arm: Add missing clear_tail calls
a3938310ec target/arm: Use vector operations for saturation
9b991d3ba4 target/arm: Split out FPSCR.QC to a vector field
268d1b9f5d target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
f1d08942ee target/arm: Split out flags setting from vfp compares
91e223f0f1 target/arm: Fix arm_cpu_dump_state vs FPSCR
764d782f4d target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
47067fd53b target/arm: Remove neon min/max helpers
05f1c9b528 target/arm: Use tcg integer min/max primitives for neon
1f1543646b target/arm: Use vector minmax expanders for aarch32
06f27fadf8 target/arm: Use vector minmax expanders for aarch64
fc2e976aa2 target/arm: Rely on optimization within tcg_gen_gvec_or
1afa20583c hw/arm/armsse: Fix miswiring of expansion IRQs
fdd25e9b24 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
1827768bd1 MAINTAINERS: Remove Peter Crosthwaite from various entries
991af7236f arm: Allow system registers for KVM guests to be changed by QEMU code
a9636655dd linux-user/elfload: enable HWCAP_CPUID for AArch64
5112145efe target/arm: expose remaining CPUID registers as RAZ
12fd99a4ba target/arm: expose MPIDR_EL1 to userspace
aff8cd32cc target/arm: expose CPUID registers to userspace
1ef1d6626a target/arm: relax permission checks for HWCAP_CPUID registers
ba75efcd06 target/arm: Restructure disas_fp_int_conv
a1f51e1111 target/arm: Force result size into dp after operation
50d5b46b34 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
847bae167b target/arm: Implement HACR_EL2
db698e8bd5 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit db698e8bd558 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 847bae167b24 (target/arm: Implement HACR_EL2)
3/27 Checking commit 50d5b46b34cb (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit a1f51e11115a (target/arm: Force result size into dp after operation)
5/27 Checking commit ba75efcd0632 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 1ef1d6626a73 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit aff8cd32cc4a (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 12fd99a4baf8 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 5112145efe84 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit a9636655dd31 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 991af7236fdf (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 1827768bd11f (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit fdd25e9b24c8 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 1afa20583c29 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit fc2e976aa28e (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 06f27fadf836 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 1f1543646b22 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 05f1c9b5283e (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 47067fd53bc4 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 764d782f4d64 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 91e223f0f1af (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit f1d08942ee79 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 268d1b9f5d61 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 9b991d3ba404 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit a3938310ec20 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit f41dbe70013f (target/arm: Add missing clear_tail calls)
27/27 Checking commit c903d16f6993 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2019-02-14 19:05 Peter Maydell
2019-02-14 19:56 ` no-reply
` (21 more replies)
0 siblings, 22 replies; 67+ messages in thread
From: Peter Maydell @ 2019-02-14 19:05 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 0d3e41d5efd638a0c5682f6813b26448c3c51624:
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-02-14 17:42:25 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190214
for you to fetch changes up to 497bc12b1b374ecd62903bf062229bd93f8924af:
gdbstub: Send a reply to the vKill packet. (2019-02-14 18:45:49 +0000)
----------------------------------------------------------------
target-arm queue:
* gdbstub: Send a reply to the vKill packet
* Improve codegen for neon min/max and saturating arithmetic
* Fix a bug in clearing FPSCR exception status bits
* hw/arm/armsse: Fix miswiring of expansion IRQs
* hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
* MAINTAINERS: Remove Peter Crosthwaite from various entries
* arm: Allow system registers for KVM guests to be changed by QEMU code
* linux-user: support HWCAP_CPUID which exposes ID registers to user code
* Fix bug in 128-bit cmpxchg for BE Arm guests
* Implement (no-op) HACR_EL2
* Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
----------------------------------------------------------------
Aaron Lindsay OS (1):
target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
Alex Bennée (5):
target/arm: relax permission checks for HWCAP_CPUID registers
target/arm: expose CPUID registers to userspace
target/arm: expose MPIDR_EL1 to userspace
target/arm: expose remaining CPUID registers as RAZ
linux-user/elfload: enable HWCAP_CPUID for AArch64
Catherine Ho (1):
target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
Peter Maydell (5):
target/arm: Implement HACR_EL2
arm: Allow system registers for KVM guests to be changed by QEMU code
MAINTAINERS: Remove Peter Crosthwaite from various entries
hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
hw/arm/armsse: Fix miswiring of expansion IRQs
Richard Henderson (14):
target/arm: Force result size into dp after operation
target/arm: Restructure disas_fp_int_conv
target/arm: Rely on optimization within tcg_gen_gvec_or
target/arm: Use vector minmax expanders for aarch64
target/arm: Use vector minmax expanders for aarch32
target/arm: Use tcg integer min/max primitives for neon
target/arm: Remove neon min/max helpers
target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
target/arm: Fix arm_cpu_dump_state vs FPSCR
target/arm: Split out flags setting from vfp compares
target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
target/arm: Split out FPSCR.QC to a vector field
target/arm: Use vector operations for saturation
target/arm: Add missing clear_tail calls
Sandra Loosemore (1):
gdbstub: Send a reply to the vKill packet.
target/arm/cpu.h | 50 ++++++++-
target/arm/helper.h | 45 +++++---
target/arm/translate.h | 4 +
gdbstub.c | 1 +
hw/arm/armsse.c | 2 +-
hw/intc/armv7m_nvic.c | 4 +-
linux-user/elfload.c | 1 +
target/arm/helper-a64.c | 4 +-
target/arm/helper.c | 228 ++++++++++++++++++++++++++++++++--------
target/arm/kvm32.c | 20 +---
target/arm/kvm64.c | 2 +
target/arm/machine.c | 2 +-
target/arm/neon_helper.c | 14 +--
target/arm/translate-a64.c | 171 +++++++++++++++---------------
target/arm/translate-sve.c | 6 +-
target/arm/translate.c | 251 ++++++++++++++++++++++++++++++++++-----------
target/arm/vec_helper.c | 134 +++++++++++++++++++++++-
MAINTAINERS | 4 -
18 files changed, 687 insertions(+), 256 deletions(-)
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2017-06-01 17:10 Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2017-06-01 17:10 UTC (permalink / raw)
To: qemu-devel
ARM pullreq; contains some patches that arrived while I
was on holiday, plus the series I sent off before going
away, which got reviewed while I was away.
thanks
-- PMM
The following changes since commit c077a998eb3fcae2d048e3baeb5bc592d30fddde:
Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20170531' into staging (2017-06-01 15:50:40 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170601
for you to fetch changes up to cdc58be430b0bdeaef282e2e70f8135ae531616d:
hw/arm/virt: fdt: generate distance-map when needed (2017-06-01 17:27:07 +0100)
----------------------------------------------------------------
target-arm queue:
* virt: numa: provide ACPI distance info when needed
* aspeed: fix i2c controller bugs
* aspeed: add temperature sensor device
* M profile: support MPU
* gicv3: fix mishandling of BPR1, VBPR1
* load_uboot_image: don't assume a full header read
* libvixl: Correct build failures on NetBSD
----------------------------------------------------------------
Andrew Jones (3):
load_uboot_image: don't assume a full header read
hw/arm/virt-acpi-build: build SLIT when needed
hw/arm/virt: fdt: generate distance-map when needed
Cédric Le Goater (6):
aspeed/i2c: improve command handling
aspeed/i2c: handle LAST command under the RX command
aspeed/i2c: introduce a state machine
aspeed: add some I2C devices to the Aspeed machines
hw/misc: add a TMP42{1,2,3} device model
aspeed: add a temp sensor device on I2C bus 3
Kamil Rytarowski (1):
libvixl: Correct build failures on NetBSD
Michael Davidsaver (4):
armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
armv7m: Implement M profile default memory map
armv7m: Classify faults as MemManage or BusFault
arm: add MPU support to M profile CPUs
Peter Maydell (12):
hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
arm: Add support for M profile CPUs having different MMU index semantics
arm: Use different ARMMMUIdx values for M profile
arm: Clean up handling of no-MPU PMSA CPUs
arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
arm: Don't let no-MPU PMSA cores write to SCTLR.M
arm: Remove unnecessary check on cpu->pmsav7_dregion
arm: All M profile cores are PMSA
arm: Implement HFNMIENA support for M profile MPU
Wei Huang (1):
target/arm: clear PMUVER field of AA64DFR0 when vPMU=off
disas/libvixl/Makefile.objs | 3 +
hw/misc/Makefile.objs | 1 +
target/arm/cpu.h | 118 ++++++++++--
target/arm/translate.h | 2 +-
hw/arm/aspeed.c | 36 ++++
hw/arm/virt-acpi-build.c | 4 +
hw/arm/virt.c | 21 +++
hw/core/loader.c | 3 +-
hw/i2c/aspeed_i2c.c | 65 ++++++-
hw/intc/arm_gicv3_cpuif.c | 50 ++++-
hw/intc/armv7m_nvic.c | 104 +++++++++++
hw/misc/tmp421.c | 401 ++++++++++++++++++++++++++++++++++++++++
target/arm/cpu.c | 28 ++-
target/arm/helper.c | 338 ++++++++++++++++++++++-----------
target/arm/machine.c | 7 +-
target/arm/op_helper.c | 3 +-
target/arm/translate-a64.c | 18 +-
target/arm/translate.c | 14 +-
default-configs/arm-softmmu.mak | 1 +
19 files changed, 1060 insertions(+), 157 deletions(-)
create mode 100644 hw/misc/tmp421.c
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2017-02-28 12:41 Peter Maydell
@ 2017-02-28 15:59 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2017-02-28 15:59 UTC (permalink / raw)
To: QEMU Developers
On 28 February 2017 at 12:41, Peter Maydell <peter.maydell@linaro.org> wrote:
> v1->v2 changes: drop the sd card-reparenting patch
> and the 2 raspi2 patches that depend on it.
>
> -- PMM
>
> The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
>
> for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
>
> hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * raspi2: implement RNG module
> * raspi2: implement new SD card controller (but don't wire it up)
> * sdhci: bugfixes for block transfers
> * virt: fix cpu object reference leak
> * Add missing fp_access_check() to aarch64 crypto instructions
> * cputlb: Don't assume do_unassigned_access() never returns
> * virt: Add a user option to disallow ITS instantiation
> * i.MX timers: fix reset handling
> * ARMv7M NVIC: rewrite to fix broken priority handling and masking
> * exynos: Fix proper mapping of CPUs by providing real cluster ID
> * exynos: Fix Linux kernel division by zero for PLLs
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2017-02-28 12:41 Peter Maydell
2017-02-28 15:59 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2017-02-28 12:41 UTC (permalink / raw)
To: qemu-devel
v1->v2 changes: drop the sd card-reparenting patch
and the 2 raspi2 patches that depend on it.
-- PMM
The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
----------------------------------------------------------------
target-arm queue:
* raspi2: implement RNG module
* raspi2: implement new SD card controller (but don't wire it up)
* sdhci: bugfixes for block transfers
* virt: fix cpu object reference leak
* Add missing fp_access_check() to aarch64 crypto instructions
* cputlb: Don't assume do_unassigned_access() never returns
* virt: Add a user option to disallow ITS instantiation
* i.MX timers: fix reset handling
* ARMv7M NVIC: rewrite to fix broken priority handling and masking
* exynos: Fix proper mapping of CPUs by providing real cluster ID
* exynos: Fix Linux kernel division by zero for PLLs
----------------------------------------------------------------
Clement Deschamps (1):
bcm2835_sdhost: add bcm2835 sdhost controller
Eric Auger (1):
hw/arm/virt: Add a user option to disallow ITS instantiation
Igor Mammedov (1):
hw/arm/virt: fix cpu object reference leak
Krzysztof Kozlowski (2):
hw/arm/exynos: Fix Linux kernel division by zero for PLLs
hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
Kurban Mallachiev (1):
ARM i.MX timers: fix reset handling
Marcin Chojnacki (1):
target-arm: Implement BCM2835 hardware RNG
Michael Davidsaver (5):
armv7m: Rewrite NVIC to not use any GIC code
arm: gic: Remove references to NVIC
armv7m: Escalate exceptions to HardFault if necessary
armv7m: Simpler and faster exception start
armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
Nick Reilly (1):
Add missing fp_access_check() to aarch64 crypto instructions
Peter Maydell (10):
bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
cputlb: Don't assume do_unassigned_access() never returns
armv7m: Rename nvic_state to NVICState
armv7m: Implement reading and writing of PRIGROUP
armv7m: Fix condition check for taking exceptions
armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
armv7m: Extract "exception taken" code into functions
armv7m: Check exception return consistency
armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
armv7m: Allow SHCSR writes to change pending and active bits
Prasad J Pandit (4):
sd: sdhci: mask transfer mode register value
sd: sdhci: check transfer mode register in multi block transfer
sd: sdhci: conditionally invoke multi block transfer
sd: sdhci: Remove block count enable check in single block transfers
hw/misc/Makefile.objs | 3 +-
hw/sd/Makefile.objs | 1 +
hw/intc/gic_internal.h | 7 +-
include/hw/arm/bcm2835_peripherals.h | 2 +
include/hw/arm/virt.h | 1 +
include/hw/misc/bcm2835_rng.h | 27 ++
include/hw/sd/bcm2835_sdhost.h | 48 ++
target/arm/cpu.h | 23 +-
cputlb.c | 15 +-
hw/arm/bcm2835_peripherals.c | 15 +
hw/arm/exynos4210.c | 18 +
hw/arm/virt.c | 32 +-
hw/intc/arm_gic.c | 31 +-
hw/intc/arm_gic_common.c | 23 +-
hw/intc/armv7m_nvic.c | 885 ++++++++++++++++++++++++++++-------
hw/misc/bcm2835_rng.c | 149 ++++++
hw/misc/exynos4210_clk.c | 164 +++++++
hw/sd/bcm2835_sdhost.c | 429 +++++++++++++++++
hw/sd/sdhci.c | 25 +-
hw/timer/imx_gpt.c | 33 +-
linux-user/main.c | 1 +
target/arm/cpu.c | 16 +-
target/arm/helper.c | 245 +++++++---
target/arm/translate-a64.c | 12 +
target/arm/translate.c | 8 +-
hw/intc/trace-events | 15 +
26 files changed, 1897 insertions(+), 331 deletions(-)
create mode 100644 include/hw/misc/bcm2835_rng.h
create mode 100644 include/hw/sd/bcm2835_sdhost.h
create mode 100644 hw/misc/bcm2835_rng.c
create mode 100644 hw/misc/exynos4210_clk.c
create mode 100644 hw/sd/bcm2835_sdhost.c
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2016-10-04 12:42 Peter Maydell
2016-10-04 13:19 ` no-reply
@ 2016-10-04 13:24 ` Peter Maydell
1 sibling, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 13:24 UTC (permalink / raw)
To: QEMU Developers
On 4 October 2016 at 13:42, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM patch queue, notably including the Netduino 2 updates
> and support for in-kernel ITS with GICv3.
>
> -- PMM
>
> The following changes since commit 1bb47107057c645945971cf4e13eb8b524915b71:
>
> Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2016-10-04 11:28:30 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161004
>
> for you to fetch changes up to 9b6a3ea7a699594162ed3d11e4e04b98568dc5c0:
>
> target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 (2016-10-04 13:28:10 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Netduino 2 improvements (SPI, ADC devices)
> * fix some Mainstone key mappings
> * vmstateify tsc210x, tsc2005
> * virt: add 2.8 machine type
> * virt: support in-kernel GICv3 ITS
> * generic-loader device
> * A64: fix iss_sf decoding in disas_ld_lit
> * correctly handle 'sub pc, pc, 1' for ARMv6
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2016-10-04 12:42 Peter Maydell
@ 2016-10-04 13:19 ` no-reply
2016-10-04 13:24 ` Peter Maydell
1 sibling, 0 replies; 67+ messages in thread
From: no-reply @ 2016-10-04 13:19 UTC (permalink / raw)
To: peter.maydell; +Cc: famz, qemu-devel
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1475584975-25099-1-git-send-email-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1475584975-25099-1-git-send-email-peter.maydell@linaro.org -> patchew/1475584975-25099-1-git-send-email-peter.maydell@linaro.org
- [tag update] patchew/20160930161013.9832-1-rkrcmar@redhat.com -> patchew/20160930161013.9832-1-rkrcmar@redhat.com
Switched to a new branch 'test'
de37b98 target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
4dd068d target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
97e3be7 cadence_gem: Fix priority queue out of bounds access
f4e8f92 docs: Add a generic loader explanation document
c2660d7 generic-loader: Add a generic loader
63a3f35 ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
6f1d2f4 ACPI: Add GIC Interrupt Translation Service Structure definition
68dea69 arm/virt: Add ITS to the virt board
4030908 hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
2d52823 kvm-all: Pass requester ID to MSI routing functions
2ec8320 target-arm: move gicv3_class_name from machine to kvm_arm.h
0525eb4 hw/intc/arm_gicv3_its: Implement ITS base class
bfc5ce8 hw/intc/arm_gic(v3)_kvm: Initialize gsi routing
949e404 hw/arm/virt: add 2.8 machine type
64d15c7 vmstateify tsc210x
935a655 vmstateify tsc2005
8d069b9 hw/arm: Fix Integrator/CM initialization
c2aa9be mainstone: Add mapping for dot, slash and backspace.
d924114 mainstone: Fix incorrect key mapping for Enter key.
ffdc92f MAINTAINERS: Add Alistair to the maintainers list
70b0fee STM32F205: Connect the SPI devices
0d1eee4 STM32F205: Connect the ADC devices
15cbf04 irq: Add a new irq device that allows the ORing of lines
d780156 STM32F2xx: Add the SPI device
19a0f11 STM32F2xx: Add the ADC device
5b4ba91 STM32F2xx: Display PWM duty cycle from timer
f7881a5 STM32F205: Remove the individual device variables
=== OUTPUT BEGIN ===
Checking PATCH 1/27: STM32F205: Remove the individual device variables...
Checking PATCH 2/27: STM32F2xx: Display PWM duty cycle from timer...
Checking PATCH 3/27: STM32F2xx: Add the ADC device...
Checking PATCH 4/27: STM32F2xx: Add the SPI device...
Checking PATCH 5/27: irq: Add a new irq device that allows the ORing of lines...
Checking PATCH 6/27: STM32F205: Connect the ADC devices...
Checking PATCH 7/27: STM32F205: Connect the SPI devices...
Checking PATCH 8/27: MAINTAINERS: Add Alistair to the maintainers list...
Checking PATCH 9/27: mainstone: Fix incorrect key mapping for Enter key....
ERROR: space required after that ',' (ctx:VxV)
#25: FILE: hw/arm/mainstone.c:91:
+ [0x1c] = {5,4}, /* enter */
^
total: 1 errors, 0 warnings, 8 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 10/27: mainstone: Add mapping for dot, slash and backspace....
ERROR: space required after that ',' (ctx:VxV)
#23: FILE: hw/arm/mainstone.c:76:
+ [0x34] = {4,0}, /* . */
^
ERROR: space required after that ',' (ctx:VxV)
#26: FILE: hw/arm/mainstone.c:79:
+ [0x35] = {4,4}, /* / */
^
ERROR: space required after that ',' (ctx:VxV)
#34: FILE: hw/arm/mainstone.c:94:
+ [0x0e] = {5,5}, /* backspace */
^
total: 3 errors, 0 warnings, 17 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 11/27: hw/arm: Fix Integrator/CM initialization...
Checking PATCH 12/27: vmstateify tsc2005...
Checking PATCH 13/27: vmstateify tsc210x...
Checking PATCH 14/27: hw/arm/virt: add 2.8 machine type...
Checking PATCH 15/27: hw/intc/arm_gic(v3)_kvm: Initialize gsi routing...
Checking PATCH 16/27: hw/intc/arm_gicv3_its: Implement ITS base class...
Checking PATCH 17/27: target-arm: move gicv3_class_name from machine to kvm_arm.h...
Checking PATCH 18/27: kvm-all: Pass requester ID to MSI routing functions...
Checking PATCH 19/27: hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation...
Checking PATCH 20/27: arm/virt: Add ITS to the virt board...
Checking PATCH 21/27: ACPI: Add GIC Interrupt Translation Service Structure definition...
Checking PATCH 22/27: ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table...
Checking PATCH 23/27: generic-loader: Add a generic loader...
Checking PATCH 24/27: docs: Add a generic loader explanation document...
Checking PATCH 25/27: cadence_gem: Fix priority queue out of bounds access...
Checking PATCH 26/27: target-arm: A64: Fix decoding of iss_sf in disas_ld_lit...
Checking PATCH 27/27: target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2016-10-04 12:42 Peter Maydell
2016-10-04 13:19 ` no-reply
2016-10-04 13:24 ` Peter Maydell
0 siblings, 2 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
ARM patch queue, notably including the Netduino 2 updates
and support for in-kernel ITS with GICv3.
-- PMM
The following changes since commit 1bb47107057c645945971cf4e13eb8b524915b71:
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2016-10-04 11:28:30 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161004
for you to fetch changes up to 9b6a3ea7a699594162ed3d11e4e04b98568dc5c0:
target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 (2016-10-04 13:28:10 +0100)
----------------------------------------------------------------
target-arm queue:
* Netduino 2 improvements (SPI, ADC devices)
* fix some Mainstone key mappings
* vmstateify tsc210x, tsc2005
* virt: add 2.8 machine type
* virt: support in-kernel GICv3 ITS
* generic-loader device
* A64: fix iss_sf decoding in disas_ld_lit
* correctly handle 'sub pc, pc, 1' for ARMv6
----------------------------------------------------------------
Alistair Francis (11):
STM32F205: Remove the individual device variables
STM32F2xx: Display PWM duty cycle from timer
STM32F2xx: Add the ADC device
STM32F2xx: Add the SPI device
irq: Add a new irq device that allows the ORing of lines
STM32F205: Connect the ADC devices
STM32F205: Connect the SPI devices
MAINTAINERS: Add Alistair to the maintainers list
generic-loader: Add a generic loader
docs: Add a generic loader explanation document
cadence_gem: Fix priority queue out of bounds access
Andrew Jones (1):
hw/arm/virt: add 2.8 machine type
Dr. David Alan Gilbert (2):
vmstateify tsc2005
vmstateify tsc210x
Edgar E. Iglesias (1):
target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
Eric Auger (2):
hw/intc/arm_gic(v3)_kvm: Initialize gsi routing
target-arm: move gicv3_class_name from machine to kvm_arm.h
Jakub Jermar (1):
hw/arm: Fix Integrator/CM initialization
Pavel Fedin (4):
hw/intc/arm_gicv3_its: Implement ITS base class
kvm-all: Pass requester ID to MSI routing functions
hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
arm/virt: Add ITS to the virt board
Peter Maydell (1):
target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
Shannon Zhao (2):
ACPI: Add GIC Interrupt Translation Service Structure definition
ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
Vijay Kumar B (2):
mainstone: Fix incorrect key mapping for Enter key.
mainstone: Add mapping for dot, slash and backspace.
MAINTAINERS | 21 +++
default-configs/arm-softmmu.mak | 2 +
docs/generic-loader.txt | 84 +++++++++
hw/Makefile.objs | 1 +
hw/adc/Makefile.objs | 1 +
hw/adc/stm32f2xx_adc.c | 306 +++++++++++++++++++++++++++++++++
hw/arm/integratorcp.c | 35 ++--
hw/arm/mainstone.c | 5 +-
hw/arm/stm32f205_soc.c | 92 ++++++++--
hw/arm/virt-acpi-build.c | 12 ++
hw/arm/virt.c | 66 ++++++-
hw/core/Makefile.objs | 3 +
hw/core/generic-loader.c | 211 +++++++++++++++++++++++
hw/core/or-irq.c | 107 ++++++++++++
hw/input/tsc2005.c | 190 ++++++++------------
hw/input/tsc210x.c | 227 +++++++++++-------------
hw/intc/Makefile.objs | 2 +
hw/intc/arm_gic_kvm.c | 12 ++
hw/intc/arm_gicv3_its_common.c | 148 ++++++++++++++++
hw/intc/arm_gicv3_its_kvm.c | 121 +++++++++++++
hw/intc/arm_gicv3_kvm.c | 13 ++
hw/net/cadence_gem.c | 22 +--
hw/ssi/Makefile.objs | 1 +
hw/ssi/stm32f2xx_spi.c | 225 ++++++++++++++++++++++++
hw/timer/stm32f2xx_timer.c | 9 +
include/hw/acpi/acpi-defs.h | 13 +-
include/hw/adc/stm32f2xx_adc.h | 87 ++++++++++
include/hw/arm/stm32f205_soc.h | 9 +
include/hw/core/generic-loader.h | 46 +++++
include/hw/intc/arm_gicv3_its_common.h | 78 +++++++++
include/hw/or-irq.h | 44 +++++
include/hw/ssi/stm32f2xx_spi.h | 72 ++++++++
include/sysemu/kvm.h | 9 +
kvm-all.c | 9 +
kvm-stub.c | 1 +
target-arm/kvm_arm.h | 35 +++-
target-arm/machine.c | 15 --
target-arm/translate-a64.c | 2 +-
target-arm/translate.c | 7 +-
39 files changed, 2027 insertions(+), 316 deletions(-)
create mode 100644 docs/generic-loader.txt
create mode 100644 hw/adc/Makefile.objs
create mode 100644 hw/adc/stm32f2xx_adc.c
create mode 100644 hw/core/generic-loader.c
create mode 100644 hw/core/or-irq.c
create mode 100644 hw/intc/arm_gicv3_its_common.c
create mode 100644 hw/intc/arm_gicv3_its_kvm.c
create mode 100644 hw/ssi/stm32f2xx_spi.c
create mode 100644 include/hw/adc/stm32f2xx_adc.h
create mode 100644 include/hw/core/generic-loader.h
create mode 100644 include/hw/intc/arm_gicv3_its_common.h
create mode 100644 include/hw/or-irq.h
create mode 100644 include/hw/ssi/stm32f2xx_spi.h
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-10-27 15:57 ` Peter Maydell
@ 2015-10-27 16:00 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-10-27 16:00 UTC (permalink / raw)
To: QEMU Developers; +Cc: Jean-Christophe Dubois
On 27 October 2015 at 15:57, Peter Maydell <peter.maydell@linaro.org> wrote:
> I will squash in the fix:
>
> diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
> index 45cf00d..261608d 100644
> --- a/hw/char/imx_serial.c
> +++ b/hw/char/imx_serial.c
> @@ -318,8 +318,7 @@ static void imx_serial_realize(DeviceState *dev,
> Error **errp)
> qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
> imx_event, s);
> } else {
> - DPRINTF("No char dev for uart at 0x%" HWADDR_PRIx "\n",
> - s->iomem.ram_addr);
> + DPRINTF("No char dev for uart"\n");
> }
> }
...without the stray extra '"', obviously :-)
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-10-27 14:33 Peter Maydell
@ 2015-10-27 15:57 ` Peter Maydell
2015-10-27 16:00 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-10-27 15:57 UTC (permalink / raw)
To: QEMU Developers; +Cc: Jean-Christophe Dubois
On 27 October 2015 at 14:33, Peter Maydell <peter.maydell@linaro.org> wrote:
> Here's the target-arm queue for 2.5.
>
> Edgar's stage 2 patchset has been on list in various forms for
> a while, and in any case the code doesn't kick in unless the
> CPU has the EL2 feature bit set, which nothing in master does.
>
> I'm probably going to start getting a bit stricter about only
> small features or bug fixes now, with a week and a half to hardfreeze.
>
> thanks
> -- PMM
>
> The following changes since commit 7e038b94e74e1c2d1b3598e2e4b0b5c8b79a7278:
>
> Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2015-10-27 10:10:46 +0000)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151027
>
> for you to fetch changes up to e194d166b4bc00fb0ce75f21eed67a9e94a25f65:
>
> target-arm: Add support for S1 + S2 MMU translations (2015-10-27 14:04:19 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * more EL2 preparation: handling for stage 2 translations
> * standardize debug macros in i.MX devices
> * improve error message in a corner case for virt board
> * disable live migration of KVM GIC if the kernel can't handle it
> * add SPSR_(ABT|UND|IRQ|FIQ) registers
> * handle non-executable page-straddling Thumb instructions
> * fix a "no 64-bit EL2" assumption in arm_excp_unmasked()
There's a format string error in the i.MX patches which means
it won't compile on 32-bit systems or OSX:
/home/petmay01/qemu/hw/char/imx_serial.c: In function 'imx_serial_realize':
/home/petmay01/qemu/hw/char/imx_serial.c:321:9: error: format '%llx'
expects argument of type 'long long unsigned int', but argument 5 has
type 'ram_addr_t' [-Werror=format=]
DPRINTF("No char dev for uart at 0x%" HWADDR_PRIx "\n",
^
We could fix this just by fixing the format string (to
"0x" RAM_ADDR_FMT rather than "0x%" HWADDR_PRIx), but this
code is wrong anyway, because it is fishing in the MemoryRegion
struct, which is clearly documented as:
/* All fields are private - violators will be prosecuted */
So we should just drop that.
I will squash in the fix:
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 45cf00d..261608d 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -318,8 +318,7 @@ static void imx_serial_realize(DeviceState *dev,
Error **errp)
qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
imx_event, s);
} else {
- DPRINTF("No char dev for uart at 0x%" HWADDR_PRIx "\n",
- s->iomem.ram_addr);
+ DPRINTF("No char dev for uart"\n");
}
}
and respin.
thanks
-- PMM
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2015-10-27 14:33 Peter Maydell
2015-10-27 15:57 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-10-27 14:33 UTC (permalink / raw)
To: qemu-devel
Here's the target-arm queue for 2.5.
Edgar's stage 2 patchset has been on list in various forms for
a while, and in any case the code doesn't kick in unless the
CPU has the EL2 feature bit set, which nothing in master does.
I'm probably going to start getting a bit stricter about only
small features or bug fixes now, with a week and a half to hardfreeze.
thanks
-- PMM
The following changes since commit 7e038b94e74e1c2d1b3598e2e4b0b5c8b79a7278:
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2015-10-27 10:10:46 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151027
for you to fetch changes up to e194d166b4bc00fb0ce75f21eed67a9e94a25f65:
target-arm: Add support for S1 + S2 MMU translations (2015-10-27 14:04:19 +0000)
----------------------------------------------------------------
target-arm queue:
* more EL2 preparation: handling for stage 2 translations
* standardize debug macros in i.MX devices
* improve error message in a corner case for virt board
* disable live migration of KVM GIC if the kernel can't handle it
* add SPSR_(ABT|UND|IRQ|FIQ) registers
* handle non-executable page-straddling Thumb instructions
* fix a "no 64-bit EL2" assumption in arm_excp_unmasked()
----------------------------------------------------------------
Andrew Jones (1):
hw/arm/virt: don't use a15memmap directly
Edgar E. Iglesias (14):
target-arm: Add HPFAR_EL2
target-arm: lpae: Make t0sz and t1sz signed integers
target-arm: lpae: Move declaration of t0sz and t1sz
target-arm: Add support for AArch32 S2 negative t0sz
target-arm: lpae: Replace tsz with computed inputsize
target-arm: lpae: Rename granule_sz to stride
target-arm: Add computation of starting level for S2 PTW
target-arm: Add support for S2 page-table protection bits
target-arm: Avoid inline for get_phys_addr
target-arm: Add ARMMMUFaultInfo
target-arm: Add S2 translation to 64bit S1 PTWs
target-arm: Add S2 translation to 32bit S1 PTWs
target-arm: Route S2 MMU faults to EL2
target-arm: Add support for S1 + S2 MMU translations
Jean-Christophe Dubois (8):
i.MX: Standardize i.MX serial debug.
i.MX: Standardize i.MX GPIO debug
i.MX: Standardize i.MX I2C debug
i.MX: Standardize i.MX AVIC debug
i.MX: Standardize i.MX CCM debug
i.MX: Standardize i.MX FEC debug
i.MX: Standardize i.MX EPIT debug
i.MX: Standardize i.MX GPT debug
Pavel Fedin (1):
arm_gic_kvm: Disable live migration if not supported
Peter Maydell (2):
target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked()
target-arm/translate.c: Handle non-executable page-straddling Thumb insns
Soren Brinkmann (1):
target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)
hw/arm/virt.c | 25 ++-
hw/char/imx_serial.c | 51 +++--
hw/gpio/imx_gpio.c | 27 +--
hw/i2c/imx_i2c.c | 43 ++---
hw/intc/arm_gic_kvm.c | 22 +--
hw/intc/imx_avic.c | 44 ++---
hw/misc/imx_ccm.c | 34 ++--
hw/net/imx_fec.c | 64 +++----
hw/timer/imx_epit.c | 48 ++---
hw/timer/imx_gpt.c | 56 +++---
include/hw/intc/arm_gic_common.h | 1 +
target-arm/cpu.h | 83 ++++++---
target-arm/helper.c | 388 ++++++++++++++++++++++++++++++++-------
target-arm/internals.h | 40 +++-
target-arm/op_helper.c | 18 +-
target-arm/translate.c | 45 ++++-
16 files changed, 680 insertions(+), 309 deletions(-)
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-09-07 9:43 Peter Maydell
@ 2015-09-07 10:22 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-07 10:22 UTC (permalink / raw)
To: QEMU Developers
On 7 September 2015 at 10:43, Peter Maydell <peter.maydell@linaro.org> wrote:
> Version 2 of this pullreq, with a trivial fix squashed in to delete
> an unused function imx_i2c_direction_is_tx().
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2015-09-07 9:43 Peter Maydell
2015-09-07 10:22 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-09-07 9:43 UTC (permalink / raw)
To: qemu-devel
Version 2 of this pullreq, with a trivial fix squashed in to delete
an unused function imx_i2c_direction_is_tx().
thanks
-- PMM
The following changes since commit b597aa037dbd98014c8dec3d69a5e2240f432533:
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2015-09-04' into staging (2015-09-04 17:37:50 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150907
for you to fetch changes up to 8d45c54d4fd3612bd616afcc5c278394f312927b:
arm/virt: Add full-sized CPU affinity handling (2015-09-07 10:39:31 +0100)
----------------------------------------------------------------
target-arm queue:
* cleanup to use g_new() and friends
* support semihosting in A64
* add SMBIOS support to mach-virt
* remove hw_error() usages
* fix bug in the AArch32:AArch64 register mapping
* add a second PCI memory window in highmem on virt board
* fix bug in arm_excp_unmasked()
* add i.MX31 SoC
* remove restriction on handling affinity values in virt board
----------------------------------------------------------------
Christopher Covington (1):
target-arm: Improve semihosting debug prints
Jean-Christophe Dubois (8):
i.MX: Add SOC support for i.MX31
i.MX: KZM: use standalone i.MX31 SOC support
i.MX: Add I2C controller emulator
i.MX: Add FEC Ethernet Emulator
i.MX: Add SOC support for i.MX25
i.MX: Add the i.MX25 PDK platform
i.MX: Add qtest support for I2C device emulator.
i.MX: Add i2C devices to i.MX31 SOC
Markus Armbruster (1):
arm: Use g_new() & friends where that makes obvious sense
Pavel Fedin (3):
hw/arm/virt: Add high MMIO PCI region, 512G in size
target-arm: Refactor CPU affinity handling
arm/virt: Add full-sized CPU affinity handling
Peter Crosthwaite (2):
arm: cpu: assert() on no-EL2 virt IRQ error condition.
arm: Remove hw_error() usages.
Peter Maydell (8):
target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
gdbstub: Implement gdb_do_syscallv()
target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
include/exec/softmmu-semi.h: Add support for 64-bit values
target-arm/arm-semi.c: Support widening APIs to 64 bits
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
Sergey Sorokin (2):
target-arm: Fix AArch32:AArch64 general-purpose register mapping
target-arm: Fix arm_excp_unmasked() function
Wei Huang (2):
smbios: add smbios 3.0 support
smbios: implement smbios support for mach-virt
default-configs/arm-softmmu.mak | 7 +
gdbstub.c | 14 +-
hw/arm/Makefile.objs | 4 +-
hw/arm/fsl-imx25.c | 273 +++++++++++++++
hw/arm/fsl-imx31.c | 246 ++++++++++++++
hw/arm/imx25_pdk.c | 159 +++++++++
hw/arm/kzm.c | 205 ++++++-----
hw/arm/omap1.c | 30 +-
hw/arm/omap2.c | 15 +-
hw/arm/pxa2xx.c | 11 +-
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/arm/virt-acpi-build.c | 17 +-
hw/arm/virt.c | 126 ++++++-
hw/char/imx_serial.c | 35 --
hw/char/omap_uart.c | 3 +-
hw/display/omap_dss.c | 3 +-
hw/display/omap_lcdc.c | 3 +-
hw/dma/omap_dma.c | 6 +-
hw/gpio/omap_gpio.c | 4 +-
hw/i2c/Makefile.objs | 1 +
hw/i2c/imx_i2c.c | 334 ++++++++++++++++++
hw/i386/pc_piix.c | 3 +-
hw/i386/pc_q35.c | 3 +-
hw/input/stellaris_input.c | 4 +-
hw/misc/omap_clk.c | 2 +-
hw/misc/omap_gpmc.c | 3 +-
hw/misc/omap_sdrc.c | 3 +-
hw/net/Makefile.objs | 1 +
hw/net/imx_fec.c | 709 +++++++++++++++++++++++++++++++++++++++
hw/sd/omap_mmc.c | 6 +-
hw/smbios/smbios.c | 84 +++--
hw/ssi/omap_spi.c | 3 +-
hw/timer/imx_epit.c | 11 -
hw/timer/imx_gpt.c | 11 -
hw/timer/omap_gptimer.c | 3 +-
include/exec/gdbstub.h | 27 ++
include/exec/softmmu-semi.h | 18 +
include/hw/arm/fsl-imx25.h | 234 +++++++++++++
include/hw/arm/fsl-imx31.h | 110 ++++++
include/hw/arm/imx.h | 26 --
include/hw/arm/virt-acpi-build.h | 1 +
include/hw/arm/virt.h | 1 +
include/hw/i2c/imx_i2c.h | 87 +++++
include/hw/net/imx_fec.h | 113 +++++++
include/hw/smbios/smbios.h | 62 +++-
linux-user/main.c | 3 +
qemu-options.hx | 2 +-
target-arm/arm-semi.c | 171 +++++++---
target-arm/cpu-qom.h | 13 +
target-arm/cpu.c | 11 +-
target-arm/cpu.h | 9 +-
target-arm/helper-a64.c | 6 +
target-arm/helper.c | 78 +++--
target-arm/internals.h | 2 +
target-arm/kvm32.c | 3 +-
target-arm/kvm64.c | 3 +-
target-arm/translate-a64.c | 24 +-
tests/Makefile | 3 +
tests/bios-tables-test.c | 6 +-
tests/ds1338-test.c | 78 +++++
tests/libqos/i2c-imx.c | 209 ++++++++++++
tests/libqos/i2c.h | 3 +
63 files changed, 3243 insertions(+), 406 deletions(-)
create mode 100644 hw/arm/fsl-imx25.c
create mode 100644 hw/arm/fsl-imx31.c
create mode 100644 hw/arm/imx25_pdk.c
create mode 100644 hw/i2c/imx_i2c.c
create mode 100644 hw/net/imx_fec.c
create mode 100644 include/hw/arm/fsl-imx25.h
create mode 100644 include/hw/arm/fsl-imx31.h
delete mode 100644 include/hw/arm/imx.h
create mode 100644 include/hw/i2c/imx_i2c.h
create mode 100644 include/hw/net/imx_fec.h
create mode 100644 tests/ds1338-test.c
create mode 100644 tests/libqos/i2c-imx.c
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-08-13 10:44 Peter Maydell
@ 2015-08-13 14:06 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-08-13 14:06 UTC (permalink / raw)
To: QEMU Developers
On 13 August 2015 at 11:44, Peter Maydell <peter.maydell@linaro.org> wrote:
> Flushing the accumulated changes from during the 2.4 freeze...
>
> -- PMM
>
> The following changes since commit ca0e5d8b0d065a95d0f9042f71b2ace45b015596:
>
> Open 2.5 development tree (2015-08-11 23:15:55 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150813
>
> for you to fetch changes up to f7a6785e12d834d05200b0595070db453344b25d:
>
> i.MX: Fix UART driver to work with unitialized "chardev" device (2015-08-13 11:26:22 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * i.MX code cleanup/refactorings
> * i.MX UART fix to work with uninitialized chardev
> * minor GIC code refactorings
> * implement the ARM Secure physical timer
> * implement the ARM Hypervisor timer
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2015-08-13 10:44 Peter Maydell
2015-08-13 14:06 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-08-13 10:44 UTC (permalink / raw)
To: qemu-devel
Flushing the accumulated changes from during the 2.4 freeze...
-- PMM
The following changes since commit ca0e5d8b0d065a95d0f9042f71b2ace45b015596:
Open 2.5 development tree (2015-08-11 23:15:55 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150813
for you to fetch changes up to f7a6785e12d834d05200b0595070db453344b25d:
i.MX: Fix UART driver to work with unitialized "chardev" device (2015-08-13 11:26:22 +0100)
----------------------------------------------------------------
target-arm queue:
* i.MX code cleanup/refactorings
* i.MX UART fix to work with uninitialized chardev
* minor GIC code refactorings
* implement the ARM Secure physical timer
* implement the ARM Hypervisor timer
----------------------------------------------------------------
Edgar E. Iglesias (7):
target-arm: Add CNTVOFF_EL2
target-arm: Add CNTHCTL_EL2
target-arm: Rename and move gt_cnt_reset
target-arm: Pass timeridx as argument to various timer functions
target-arm: Add the Hypervisor timer
hw/arm/virt: Replace magic IRQ constants with macros
hw/arm/virt: Connect the Hypervisor timer
Jean-Christophe Dubois (12):
i.MX: Split UART emulator in a header file and a source file
i.MX: Move serial initialization to init/realize of DeviceClass.
i.MX:Fix Coding style for UART emulator.
i.MX: Split AVIC emulator in a header file and a source file
i.MX: Fix Coding style for AVIC emulator.
i.MX: Split CCM emulator in a header file and a source file
i.MX: Fix Coding style for CCM emulator
i.MX: Split EPIT emulator in a header file and a source file
i.MX: Fix Coding style for EPIT emulator
i.MX: Split GPT emulator in a header file and a source file
i.MX: Fix Coding style for GPT emulator
i.MX: Fix UART driver to work with unitialized "chardev" device
Pavel Fedin (3):
Merge memory_region_init_reservation() into memory_region_init_io()
hw/arm/gic: Kill code duplication
Introduce gic_class_name() instead of repeating condition
Peter Maydell (5):
target-arm: Add debug check for mismatched cpreg resets
target-arm: Add the AArch64 view of the Secure physical timer
target-arm: Add AArch32 banked register access to secure physical timer
hw/arm/virt: Wire up secure timer interrupt
hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts
hw/arm/kzm.c | 5 +-
hw/arm/virt.c | 32 ++--
hw/char/imx_serial.c | 159 +++++------------
hw/cpu/a15mpcore.c | 29 ++--
hw/intc/arm_gic.c | 64 ++-----
hw/intc/arm_gic_common.c | 41 +++++
hw/intc/arm_gic_kvm.c | 28 +--
hw/intc/imx_avic.c | 56 ++----
hw/misc/imx_ccm.c | 81 +--------
hw/timer/imx_epit.c | 64 +------
hw/timer/imx_gpt.c | 85 +--------
include/exec/memory.h | 14 +-
include/hw/arm/imx.h | 12 +-
include/hw/char/imx_serial.h | 102 +++++++++++
include/hw/intc/arm_gic_common.h | 3 +
include/hw/intc/imx_avic.h | 55 ++++++
include/hw/misc/imx_ccm.h | 91 ++++++++++
include/hw/timer/imx_epit.h | 79 +++++++++
include/hw/timer/imx_gpt.h | 107 ++++++++++++
memory.c | 10 +-
target-arm/cpu-qom.h | 2 +
target-arm/cpu.c | 27 +++
target-arm/cpu.h | 9 +-
target-arm/helper.c | 367 +++++++++++++++++++++++++++++++++++----
target-arm/kvm_arm.h | 5 +
25 files changed, 1003 insertions(+), 524 deletions(-)
create mode 100644 include/hw/char/imx_serial.h
create mode 100644 include/hw/intc/imx_avic.h
create mode 100644 include/hw/misc/imx_ccm.h
create mode 100644 include/hw/timer/imx_epit.h
create mode 100644 include/hw/timer/imx_gpt.h
^ permalink raw reply [flat|nested] 67+ messages in thread
end of thread, other threads:[~2019-02-15 2:45 UTC | newest]
Thread overview: 67+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-09-04 15:05 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 01/27] arm: Use g_new() & friends where that makes obvious sense Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 02/27] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 03/27] target-arm: Improve semihosting debug prints Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 04/27] gdbstub: Implement gdb_do_syscallv() Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]' Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 06/27] include/exec/softmmu-semi.h: Add support for 64-bit values Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 07/27] target-arm/arm-semi.c: Support widening APIs to 64 bits Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 10/27] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 11/27] smbios: add smbios 3.0 support Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 12/27] smbios: implement smbios support for mach-virt Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 13/27] arm: cpu: assert() on no-EL2 virt IRQ error condition Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 14/27] arm: Remove hw_error() usages Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 15/27] target-arm: Fix AArch32:AArch64 general-purpose register mapping Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 16/27] hw/arm/virt: Add high MMIO PCI region, 512G in size Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 18/27] i.MX: Add SOC support for i.MX31 Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 19/27] i.MX: KZM: use standalone i.MX31 SOC support Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 20/27] i.MX: Add I2C controller emulator Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 21/27] i.MX: Add FEC Ethernet Emulator Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 22/27] i.MX: Add SOC support for i.MX25 Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform Peter Maydell
2015-09-27 19:48 ` Peter Crosthwaite
2015-09-27 19:52 ` Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 24/27] i.MX: Add qtest support for I2C device emulator Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 25/27] i.MX: Add i2C devices to i.MX31 SOC Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 26/27] target-arm: Refactor CPU affinity handling Peter Maydell
2015-09-04 15:05 ` [Qemu-devel] [PULL 27/27] arm/virt: Add full-sized " Peter Maydell
2015-09-07 9:40 ` [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2019-02-14 19:05 Peter Maydell
2019-02-14 19:56 ` no-reply
2019-02-14 20:30 ` no-reply
2019-02-14 20:57 ` no-reply
2019-02-14 21:24 ` no-reply
2019-02-14 21:51 ` no-reply
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2019-02-15 1:48 ` no-reply
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2019-02-15 2:15 ` no-reply
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2019-02-15 2:43 ` no-reply
2017-06-01 17:10 Peter Maydell
2017-02-28 12:41 Peter Maydell
2017-02-28 15:59 ` Peter Maydell
2016-10-04 12:42 Peter Maydell
2016-10-04 13:19 ` no-reply
2016-10-04 13:24 ` Peter Maydell
2015-10-27 14:33 Peter Maydell
2015-10-27 15:57 ` Peter Maydell
2015-10-27 16:00 ` Peter Maydell
2015-09-07 9:43 Peter Maydell
2015-09-07 10:22 ` Peter Maydell
2015-08-13 10:44 Peter Maydell
2015-08-13 14:06 ` Peter Maydell
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