* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2016-10-04 12:42 Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 01/27] STM32F205: Remove the individual device variables Peter Maydell
` (28 more replies)
0 siblings, 29 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
ARM patch queue, notably including the Netduino 2 updates
and support for in-kernel ITS with GICv3.
-- PMM
The following changes since commit 1bb47107057c645945971cf4e13eb8b524915b71:
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2016-10-04 11:28:30 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161004
for you to fetch changes up to 9b6a3ea7a699594162ed3d11e4e04b98568dc5c0:
target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 (2016-10-04 13:28:10 +0100)
----------------------------------------------------------------
target-arm queue:
* Netduino 2 improvements (SPI, ADC devices)
* fix some Mainstone key mappings
* vmstateify tsc210x, tsc2005
* virt: add 2.8 machine type
* virt: support in-kernel GICv3 ITS
* generic-loader device
* A64: fix iss_sf decoding in disas_ld_lit
* correctly handle 'sub pc, pc, 1' for ARMv6
----------------------------------------------------------------
Alistair Francis (11):
STM32F205: Remove the individual device variables
STM32F2xx: Display PWM duty cycle from timer
STM32F2xx: Add the ADC device
STM32F2xx: Add the SPI device
irq: Add a new irq device that allows the ORing of lines
STM32F205: Connect the ADC devices
STM32F205: Connect the SPI devices
MAINTAINERS: Add Alistair to the maintainers list
generic-loader: Add a generic loader
docs: Add a generic loader explanation document
cadence_gem: Fix priority queue out of bounds access
Andrew Jones (1):
hw/arm/virt: add 2.8 machine type
Dr. David Alan Gilbert (2):
vmstateify tsc2005
vmstateify tsc210x
Edgar E. Iglesias (1):
target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
Eric Auger (2):
hw/intc/arm_gic(v3)_kvm: Initialize gsi routing
target-arm: move gicv3_class_name from machine to kvm_arm.h
Jakub Jermar (1):
hw/arm: Fix Integrator/CM initialization
Pavel Fedin (4):
hw/intc/arm_gicv3_its: Implement ITS base class
kvm-all: Pass requester ID to MSI routing functions
hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
arm/virt: Add ITS to the virt board
Peter Maydell (1):
target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
Shannon Zhao (2):
ACPI: Add GIC Interrupt Translation Service Structure definition
ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
Vijay Kumar B (2):
mainstone: Fix incorrect key mapping for Enter key.
mainstone: Add mapping for dot, slash and backspace.
MAINTAINERS | 21 +++
default-configs/arm-softmmu.mak | 2 +
docs/generic-loader.txt | 84 +++++++++
hw/Makefile.objs | 1 +
hw/adc/Makefile.objs | 1 +
hw/adc/stm32f2xx_adc.c | 306 +++++++++++++++++++++++++++++++++
hw/arm/integratorcp.c | 35 ++--
hw/arm/mainstone.c | 5 +-
hw/arm/stm32f205_soc.c | 92 ++++++++--
hw/arm/virt-acpi-build.c | 12 ++
hw/arm/virt.c | 66 ++++++-
hw/core/Makefile.objs | 3 +
hw/core/generic-loader.c | 211 +++++++++++++++++++++++
hw/core/or-irq.c | 107 ++++++++++++
hw/input/tsc2005.c | 190 ++++++++------------
hw/input/tsc210x.c | 227 +++++++++++-------------
hw/intc/Makefile.objs | 2 +
hw/intc/arm_gic_kvm.c | 12 ++
hw/intc/arm_gicv3_its_common.c | 148 ++++++++++++++++
hw/intc/arm_gicv3_its_kvm.c | 121 +++++++++++++
hw/intc/arm_gicv3_kvm.c | 13 ++
hw/net/cadence_gem.c | 22 +--
hw/ssi/Makefile.objs | 1 +
hw/ssi/stm32f2xx_spi.c | 225 ++++++++++++++++++++++++
hw/timer/stm32f2xx_timer.c | 9 +
include/hw/acpi/acpi-defs.h | 13 +-
include/hw/adc/stm32f2xx_adc.h | 87 ++++++++++
include/hw/arm/stm32f205_soc.h | 9 +
include/hw/core/generic-loader.h | 46 +++++
include/hw/intc/arm_gicv3_its_common.h | 78 +++++++++
include/hw/or-irq.h | 44 +++++
include/hw/ssi/stm32f2xx_spi.h | 72 ++++++++
include/sysemu/kvm.h | 9 +
kvm-all.c | 9 +
kvm-stub.c | 1 +
target-arm/kvm_arm.h | 35 +++-
target-arm/machine.c | 15 --
target-arm/translate-a64.c | 2 +-
target-arm/translate.c | 7 +-
39 files changed, 2027 insertions(+), 316 deletions(-)
create mode 100644 docs/generic-loader.txt
create mode 100644 hw/adc/Makefile.objs
create mode 100644 hw/adc/stm32f2xx_adc.c
create mode 100644 hw/core/generic-loader.c
create mode 100644 hw/core/or-irq.c
create mode 100644 hw/intc/arm_gicv3_its_common.c
create mode 100644 hw/intc/arm_gicv3_its_kvm.c
create mode 100644 hw/ssi/stm32f2xx_spi.c
create mode 100644 include/hw/adc/stm32f2xx_adc.h
create mode 100644 include/hw/core/generic-loader.h
create mode 100644 include/hw/intc/arm_gicv3_its_common.h
create mode 100644 include/hw/or-irq.h
create mode 100644 include/hw/ssi/stm32f2xx_spi.h
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 01/27] STM32F205: Remove the individual device variables
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 02/27] STM32F2xx: Display PWM duty cycle from timer Peter Maydell
` (27 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
Cleanup the individual DeviceState and SysBusDevice
variables to re-use the same variable for each
device.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: fc5d75a57d320b69704df2c1146ff0fd482e4a88.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stm32f205_soc.c | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index de26b8c..5b6fa3b 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -62,8 +62,8 @@ static void stm32f205_soc_initfn(Object *obj)
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
{
STM32F205State *s = STM32F205_SOC(dev_soc);
- DeviceState *syscfgdev, *usartdev, *timerdev, *nvic;
- SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
+ DeviceState *dev, *nvic;
+ SysBusDevice *busdev;
Error *err = NULL;
int i;
@@ -94,44 +94,43 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
s->kernel_filename, s->cpu_model);
/* System configuration controller */
- syscfgdev = DEVICE(&s->syscfg);
+ dev = DEVICE(&s->syscfg);
object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
- syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
- sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
- sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71));
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, 0x40013800);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
/* Attach UART (uses USART registers) and USART controllers */
for (i = 0; i < STM_NUM_USARTS; i++) {
- usartdev = DEVICE(&(s->usart[i]));
- qdev_prop_set_chr(usartdev, "chardev", i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL);
+ dev = DEVICE(&(s->usart[i]));
+ qdev_prop_set_chr(dev, "chardev",
+ i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL);
object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
- usartbusdev = SYS_BUS_DEVICE(usartdev);
- sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
- sysbus_connect_irq(usartbusdev, 0,
- qdev_get_gpio_in(nvic, usart_irq[i]));
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, usart_addr[i]);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
}
/* Timer 2 to 5 */
for (i = 0; i < STM_NUM_TIMERS; i++) {
- timerdev = DEVICE(&(s->timer[i]));
- qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
+ dev = DEVICE(&(s->timer[i]));
+ qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
- timerbusdev = SYS_BUS_DEVICE(timerdev);
- sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
- sysbus_connect_irq(timerbusdev, 0,
- qdev_get_gpio_in(nvic, timer_irq[i]));
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, timer_addr[i]);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
}
}
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 02/27] STM32F2xx: Display PWM duty cycle from timer
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 01/27] STM32F205: Remove the individual device variables Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 03/27] STM32F2xx: Add the ADC device Peter Maydell
` (26 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
If correctly configured allow the STM32F2xx timer to print
out the PWM duty cycle information.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: cdb59039a25e061615713a94b40797baa12ea9f9.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/stm32f2xx_timer.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index bf0fb28..8c4c1f9 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -51,6 +51,15 @@ static void stm32f2xx_timer_interrupt(void *opaque)
qemu_irq_pulse(s->irq);
stm32f2xx_timer_set_alarm(s, s->hit_time);
}
+
+ if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) &&
+ !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) &&
+ s->tim_ccmr1 & TIM_CCMR1_OC2PE &&
+ s->tim_ccer & TIM_CCER_CC2E) {
+ /* PWM 2 - Mode 1 */
+ DB_PRINT("PWM2 Duty Cycle: %d%%\n",
+ s->tim_ccr2 / (100 * (s->tim_psc + 1)));
+ }
}
static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 03/27] STM32F2xx: Add the ADC device
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 01/27] STM32F205: Remove the individual device variables Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 02/27] STM32F2xx: Display PWM duty cycle from timer Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 04/27] STM32F2xx: Add the SPI device Peter Maydell
` (25 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
Add the STM32F2xx ADC device. This device randomly
generates values on each read.
This also includes creating a hw/adc directory.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/Makefile.objs | 1 +
hw/adc/Makefile.objs | 1 +
hw/adc/stm32f2xx_adc.c | 306 ++++++++++++++++++++++++++++++++++++++++
include/hw/adc/stm32f2xx_adc.h | 87 ++++++++++++
5 files changed, 396 insertions(+)
create mode 100644 hw/adc/Makefile.objs
create mode 100644 hw/adc/stm32f2xx_adc.c
create mode 100644 include/hw/adc/stm32f2xx_adc.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index e124360..3379b55 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -86,6 +86,7 @@ CONFIG_ZYNQ=y
CONFIG_STM32F2XX_TIMER=y
CONFIG_STM32F2XX_USART=y
CONFIG_STM32F2XX_SYSCFG=y
+CONFIG_STM32F2XX_ADC=y
CONFIG_STM32F205_SOC=y
CONFIG_VERSATILE_PCI=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 4a07ed4..0ffd281 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -1,5 +1,6 @@
devices-dirs-$(call land, $(CONFIG_VIRTIO),$(call land,$(CONFIG_VIRTFS),$(CONFIG_PCI))) += 9pfs/
devices-dirs-$(CONFIG_ACPI) += acpi/
+devices-dirs-$(CONFIG_SOFTMMU) += adc/
devices-dirs-$(CONFIG_SOFTMMU) += audio/
devices-dirs-$(CONFIG_SOFTMMU) += block/
devices-dirs-$(CONFIG_SOFTMMU) += bt/
diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs
new file mode 100644
index 0000000..3f6dfde
--- /dev/null
+++ b/hw/adc/Makefile.objs
@@ -0,0 +1 @@
+obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o
diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c
new file mode 100644
index 0000000..90fe9de
--- /dev/null
+++ b/hw/adc/stm32f2xx_adc.c
@@ -0,0 +1,306 @@
+/*
+ * STM32F2XX ADC
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "hw/adc/stm32f2xx_adc.h"
+
+#ifndef STM_ADC_ERR_DEBUG
+#define STM_ADC_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_ADC_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_adc_reset(DeviceState *dev)
+{
+ STM32F2XXADCState *s = STM32F2XX_ADC(dev);
+
+ s->adc_sr = 0x00000000;
+ s->adc_cr1 = 0x00000000;
+ s->adc_cr2 = 0x00000000;
+ s->adc_smpr1 = 0x00000000;
+ s->adc_smpr2 = 0x00000000;
+ s->adc_jofr[0] = 0x00000000;
+ s->adc_jofr[1] = 0x00000000;
+ s->adc_jofr[2] = 0x00000000;
+ s->adc_jofr[3] = 0x00000000;
+ s->adc_htr = 0x00000FFF;
+ s->adc_ltr = 0x00000000;
+ s->adc_sqr1 = 0x00000000;
+ s->adc_sqr2 = 0x00000000;
+ s->adc_sqr3 = 0x00000000;
+ s->adc_jsqr = 0x00000000;
+ s->adc_jdr[0] = 0x00000000;
+ s->adc_jdr[1] = 0x00000000;
+ s->adc_jdr[2] = 0x00000000;
+ s->adc_jdr[3] = 0x00000000;
+ s->adc_dr = 0x00000000;
+}
+
+static uint32_t stm32f2xx_adc_generate_value(STM32F2XXADCState *s)
+{
+ /* Attempts to fake some ADC values */
+ s->adc_dr = s->adc_dr + 7;
+
+ switch ((s->adc_cr1 & ADC_CR1_RES) >> 24) {
+ case 0:
+ /* 12-bit */
+ s->adc_dr &= 0xFFF;
+ break;
+ case 1:
+ /* 10-bit */
+ s->adc_dr &= 0x3FF;
+ break;
+ case 2:
+ /* 8-bit */
+ s->adc_dr &= 0xFF;
+ break;
+ default:
+ /* 6-bit */
+ s->adc_dr &= 0x3F;
+ }
+
+ if (s->adc_cr2 & ADC_CR2_ALIGN) {
+ return (s->adc_dr << 1) & 0xFFF0;
+ } else {
+ return s->adc_dr;
+ }
+}
+
+static uint64_t stm32f2xx_adc_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32F2XXADCState *s = opaque;
+
+ DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
+
+ if (addr >= ADC_COMMON_ADDRESS) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: ADC Common Register Unsupported\n", __func__);
+ }
+
+ switch (addr) {
+ case ADC_SR:
+ return s->adc_sr;
+ case ADC_CR1:
+ return s->adc_cr1;
+ case ADC_CR2:
+ return s->adc_cr2 & 0xFFFFFFF;
+ case ADC_SMPR1:
+ return s->adc_smpr1;
+ case ADC_SMPR2:
+ return s->adc_smpr2;
+ case ADC_JOFR1:
+ case ADC_JOFR2:
+ case ADC_JOFR3:
+ case ADC_JOFR4:
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "Injection ADC is not implemented, the registers are " \
+ "included for compatibility\n", __func__);
+ return s->adc_jofr[(addr - ADC_JOFR1) / 4];
+ case ADC_HTR:
+ return s->adc_htr;
+ case ADC_LTR:
+ return s->adc_ltr;
+ case ADC_SQR1:
+ return s->adc_sqr1;
+ case ADC_SQR2:
+ return s->adc_sqr2;
+ case ADC_SQR3:
+ return s->adc_sqr3;
+ case ADC_JSQR:
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "Injection ADC is not implemented, the registers are " \
+ "included for compatibility\n", __func__);
+ return s->adc_jsqr;
+ case ADC_JDR1:
+ case ADC_JDR2:
+ case ADC_JDR3:
+ case ADC_JDR4:
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "Injection ADC is not implemented, the registers are " \
+ "included for compatibility\n", __func__);
+ return s->adc_jdr[(addr - ADC_JDR1) / 4] -
+ s->adc_jofr[(addr - ADC_JDR1) / 4];
+ case ADC_DR:
+ if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) {
+ s->adc_cr2 ^= ADC_CR2_SWSTART;
+ return stm32f2xx_adc_generate_value(s);
+ } else {
+ return 0;
+ }
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ }
+
+ return 0;
+}
+
+static void stm32f2xx_adc_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32F2XXADCState *s = opaque;
+ uint32_t value = (uint32_t) val64;
+
+ DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n",
+ addr, value);
+
+ if (addr >= 0x100) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: ADC Common Register Unsupported\n", __func__);
+ }
+
+ switch (addr) {
+ case ADC_SR:
+ s->adc_sr &= (value & 0x3F);
+ break;
+ case ADC_CR1:
+ s->adc_cr1 = value;
+ break;
+ case ADC_CR2:
+ s->adc_cr2 = value;
+ break;
+ case ADC_SMPR1:
+ s->adc_smpr1 = value;
+ break;
+ case ADC_SMPR2:
+ s->adc_smpr2 = value;
+ break;
+ case ADC_JOFR1:
+ case ADC_JOFR2:
+ case ADC_JOFR3:
+ case ADC_JOFR4:
+ s->adc_jofr[(addr - ADC_JOFR1) / 4] = (value & 0xFFF);
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "Injection ADC is not implemented, the registers are " \
+ "included for compatibility\n", __func__);
+ break;
+ case ADC_HTR:
+ s->adc_htr = value;
+ break;
+ case ADC_LTR:
+ s->adc_ltr = value;
+ break;
+ case ADC_SQR1:
+ s->adc_sqr1 = value;
+ break;
+ case ADC_SQR2:
+ s->adc_sqr2 = value;
+ break;
+ case ADC_SQR3:
+ s->adc_sqr3 = value;
+ break;
+ case ADC_JSQR:
+ s->adc_jsqr = value;
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "Injection ADC is not implemented, the registers are " \
+ "included for compatibility\n", __func__);
+ break;
+ case ADC_JDR1:
+ case ADC_JDR2:
+ case ADC_JDR3:
+ case ADC_JDR4:
+ s->adc_jdr[(addr - ADC_JDR1) / 4] = value;
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "Injection ADC is not implemented, the registers are " \
+ "included for compatibility\n", __func__);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps stm32f2xx_adc_ops = {
+ .read = stm32f2xx_adc_read,
+ .write = stm32f2xx_adc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stm32f2xx_adc = {
+ .name = TYPE_STM32F2XX_ADC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(adc_sr, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_cr1, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_cr2, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_smpr1, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_smpr2, STM32F2XXADCState),
+ VMSTATE_UINT32_ARRAY(adc_jofr, STM32F2XXADCState, 4),
+ VMSTATE_UINT32(adc_htr, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_ltr, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_sqr1, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_sqr2, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_sqr3, STM32F2XXADCState),
+ VMSTATE_UINT32(adc_jsqr, STM32F2XXADCState),
+ VMSTATE_UINT32_ARRAY(adc_jdr, STM32F2XXADCState, 4),
+ VMSTATE_UINT32(adc_dr, STM32F2XXADCState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stm32f2xx_adc_init(Object *obj)
+{
+ STM32F2XXADCState *s = STM32F2XX_ADC(obj);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
+ TYPE_STM32F2XX_ADC, 0xFF);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = stm32f2xx_adc_reset;
+ dc->vmsd = &vmstate_stm32f2xx_adc;
+}
+
+static const TypeInfo stm32f2xx_adc_info = {
+ .name = TYPE_STM32F2XX_ADC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F2XXADCState),
+ .instance_init = stm32f2xx_adc_init,
+ .class_init = stm32f2xx_adc_class_init,
+};
+
+static void stm32f2xx_adc_register_types(void)
+{
+ type_register_static(&stm32f2xx_adc_info);
+}
+
+type_init(stm32f2xx_adc_register_types)
diff --git a/include/hw/adc/stm32f2xx_adc.h b/include/hw/adc/stm32f2xx_adc.h
new file mode 100644
index 0000000..a72f734
--- /dev/null
+++ b/include/hw/adc/stm32f2xx_adc.h
@@ -0,0 +1,87 @@
+/*
+ * STM32F2XX ADC
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_ADC_H
+#define HW_STM32F2XX_ADC_H
+
+#define ADC_SR 0x00
+#define ADC_CR1 0x04
+#define ADC_CR2 0x08
+#define ADC_SMPR1 0x0C
+#define ADC_SMPR2 0x10
+#define ADC_JOFR1 0x14
+#define ADC_JOFR2 0x18
+#define ADC_JOFR3 0x1C
+#define ADC_JOFR4 0x20
+#define ADC_HTR 0x24
+#define ADC_LTR 0x28
+#define ADC_SQR1 0x2C
+#define ADC_SQR2 0x30
+#define ADC_SQR3 0x34
+#define ADC_JSQR 0x38
+#define ADC_JDR1 0x3C
+#define ADC_JDR2 0x40
+#define ADC_JDR3 0x44
+#define ADC_JDR4 0x48
+#define ADC_DR 0x4C
+
+#define ADC_CR2_ADON 0x01
+#define ADC_CR2_CONT 0x02
+#define ADC_CR2_ALIGN 0x800
+#define ADC_CR2_SWSTART 0x40000000
+
+#define ADC_CR1_RES 0x3000000
+
+#define ADC_COMMON_ADDRESS 0x100
+
+#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
+#define STM32F2XX_ADC(obj) \
+ OBJECT_CHECK(STM32F2XXADCState, (obj), TYPE_STM32F2XX_ADC)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t adc_sr;
+ uint32_t adc_cr1;
+ uint32_t adc_cr2;
+ uint32_t adc_smpr1;
+ uint32_t adc_smpr2;
+ uint32_t adc_jofr[4];
+ uint32_t adc_htr;
+ uint32_t adc_ltr;
+ uint32_t adc_sqr1;
+ uint32_t adc_sqr2;
+ uint32_t adc_sqr3;
+ uint32_t adc_jsqr;
+ uint32_t adc_jdr[4];
+ uint32_t adc_dr;
+
+ qemu_irq irq;
+} STM32F2XXADCState;
+
+#endif /* HW_STM32F2XX_ADC_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 04/27] STM32F2xx: Add the SPI device
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 03/27] STM32F2xx: Add the ADC device Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 05/27] irq: Add a new irq device that allows the ORing of lines Peter Maydell
` (24 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
Add the STM32F2xx SPI device.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
hw/ssi/Makefile.objs | 1 +
hw/ssi/stm32f2xx_spi.c | 225 ++++++++++++++++++++++++++++++++++++++++
include/hw/ssi/stm32f2xx_spi.h | 72 +++++++++++++
4 files changed, 299 insertions(+)
create mode 100644 hw/ssi/stm32f2xx_spi.c
create mode 100644 include/hw/ssi/stm32f2xx_spi.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 3379b55..6de3e16 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -87,6 +87,7 @@ CONFIG_STM32F2XX_TIMER=y
CONFIG_STM32F2XX_USART=y
CONFIG_STM32F2XX_SYSCFG=y
CONFIG_STM32F2XX_ADC=y
+CONFIG_STM32F2XX_SPI=y
CONFIG_STM32F205_SOC=y
CONFIG_VERSATILE_PCI=y
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index c79a8dc..487add2 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_SSI) += ssi.o
common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
+common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
obj-$(CONFIG_OMAP) += omap_spi.o
obj-$(CONFIG_IMX) += imx_spi.o
diff --git a/hw/ssi/stm32f2xx_spi.c b/hw/ssi/stm32f2xx_spi.c
new file mode 100644
index 0000000..26a1b4d
--- /dev/null
+++ b/hw/ssi/stm32f2xx_spi.c
@@ -0,0 +1,225 @@
+/*
+ * STM32F405 SPI
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "hw/ssi/stm32f2xx_spi.h"
+
+#ifndef STM_SPI_ERR_DEBUG
+#define STM_SPI_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (STM_SPI_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_spi_reset(DeviceState *dev)
+{
+ STM32F2XXSPIState *s = STM32F2XX_SPI(dev);
+
+ s->spi_cr1 = 0x00000000;
+ s->spi_cr2 = 0x00000000;
+ s->spi_sr = 0x0000000A;
+ s->spi_dr = 0x0000000C;
+ s->spi_crcpr = 0x00000007;
+ s->spi_rxcrcr = 0x00000000;
+ s->spi_txcrcr = 0x00000000;
+ s->spi_i2scfgr = 0x00000000;
+ s->spi_i2spr = 0x00000002;
+}
+
+static void stm32f2xx_spi_transfer(STM32F2XXSPIState *s)
+{
+ DB_PRINT("Data to send: 0x%x\n", s->spi_dr);
+
+ s->spi_dr = ssi_transfer(s->ssi, s->spi_dr);
+ s->spi_sr |= STM_SPI_SR_RXNE;
+
+ DB_PRINT("Data received: 0x%x\n", s->spi_dr);
+}
+
+static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32F2XXSPIState *s = opaque;
+
+ DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
+
+ switch (addr) {
+ case STM_SPI_CR1:
+ return s->spi_cr1;
+ case STM_SPI_CR2:
+ qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n",
+ __func__);
+ return s->spi_cr2;
+ case STM_SPI_SR:
+ return s->spi_sr;
+ case STM_SPI_DR:
+ stm32f2xx_spi_transfer(s);
+ s->spi_sr &= ~STM_SPI_SR_RXNE;
+ return s->spi_dr;
+ case STM_SPI_CRCPR:
+ qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+ "are included for compatibility\n", __func__);
+ return s->spi_crcpr;
+ case STM_SPI_RXCRCR:
+ qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+ "are included for compatibility\n", __func__);
+ return s->spi_rxcrcr;
+ case STM_SPI_TXCRCR:
+ qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+ "are included for compatibility\n", __func__);
+ return s->spi_txcrcr;
+ case STM_SPI_I2SCFGR:
+ qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+ "are included for compatibility\n", __func__);
+ return s->spi_i2scfgr;
+ case STM_SPI_I2SPR:
+ qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+ "are included for compatibility\n", __func__);
+ return s->spi_i2spr;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ }
+
+ return 0;
+}
+
+static void stm32f2xx_spi_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32F2XXSPIState *s = opaque;
+ uint32_t value = val64;
+
+ DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value);
+
+ switch (addr) {
+ case STM_SPI_CR1:
+ s->spi_cr1 = value;
+ return;
+ case STM_SPI_CR2:
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "Interrupts and DMA are not implemented\n", __func__);
+ s->spi_cr2 = value;
+ return;
+ case STM_SPI_SR:
+ /* Read only register, except for clearing the CRCERR bit, which
+ * is not supported
+ */
+ return;
+ case STM_SPI_DR:
+ s->spi_dr = value;
+ stm32f2xx_spi_transfer(s);
+ return;
+ case STM_SPI_CRCPR:
+ qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__);
+ return;
+ case STM_SPI_RXCRCR:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
+ "0x%" HWADDR_PRIx "\n", __func__, addr);
+ return;
+ case STM_SPI_TXCRCR:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
+ "0x%" HWADDR_PRIx "\n", __func__, addr);
+ return;
+ case STM_SPI_I2SCFGR:
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "I2S is not implemented\n", __func__);
+ return;
+ case STM_SPI_I2SPR:
+ qemu_log_mask(LOG_UNIMP, "%s: " \
+ "I2S is not implemented\n", __func__);
+ return;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps stm32f2xx_spi_ops = {
+ .read = stm32f2xx_spi_read,
+ .write = stm32f2xx_spi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stm32f2xx_spi = {
+ .name = TYPE_STM32F2XX_SPI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(spi_cr1, STM32F2XXSPIState),
+ VMSTATE_UINT32(spi_cr2, STM32F2XXSPIState),
+ VMSTATE_UINT32(spi_sr, STM32F2XXSPIState),
+ VMSTATE_UINT32(spi_dr, STM32F2XXSPIState),
+ VMSTATE_UINT32(spi_crcpr, STM32F2XXSPIState),
+ VMSTATE_UINT32(spi_rxcrcr, STM32F2XXSPIState),
+ VMSTATE_UINT32(spi_txcrcr, STM32F2XXSPIState),
+ VMSTATE_UINT32(spi_i2scfgr, STM32F2XXSPIState),
+ VMSTATE_UINT32(spi_i2spr, STM32F2XXSPIState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stm32f2xx_spi_init(Object *obj)
+{
+ STM32F2XXSPIState *s = STM32F2XX_SPI(obj);
+ DeviceState *dev = DEVICE(obj);
+
+ memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s,
+ TYPE_STM32F2XX_SPI, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ s->ssi = ssi_create_bus(dev, "ssi");
+}
+
+static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = stm32f2xx_spi_reset;
+ dc->vmsd = &vmstate_stm32f2xx_spi;
+}
+
+static const TypeInfo stm32f2xx_spi_info = {
+ .name = TYPE_STM32F2XX_SPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32F2XXSPIState),
+ .instance_init = stm32f2xx_spi_init,
+ .class_init = stm32f2xx_spi_class_init,
+};
+
+static void stm32f2xx_spi_register_types(void)
+{
+ type_register_static(&stm32f2xx_spi_info);
+}
+
+type_init(stm32f2xx_spi_register_types)
diff --git a/include/hw/ssi/stm32f2xx_spi.h b/include/hw/ssi/stm32f2xx_spi.h
new file mode 100644
index 0000000..1cd73e4
--- /dev/null
+++ b/include/hw/ssi/stm32f2xx_spi.h
@@ -0,0 +1,72 @@
+/*
+ * STM32F2XX SPI
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_SPI_H
+#define HW_STM32F2XX_SPI_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "hw/ssi/ssi.h"
+
+#define STM_SPI_CR1 0x00
+#define STM_SPI_CR2 0x04
+#define STM_SPI_SR 0x08
+#define STM_SPI_DR 0x0C
+#define STM_SPI_CRCPR 0x10
+#define STM_SPI_RXCRCR 0x14
+#define STM_SPI_TXCRCR 0x18
+#define STM_SPI_I2SCFGR 0x1C
+#define STM_SPI_I2SPR 0x20
+
+#define STM_SPI_CR1_SPE (1 << 6)
+#define STM_SPI_CR1_MSTR (1 << 2)
+
+#define STM_SPI_SR_RXNE 1
+
+#define TYPE_STM32F2XX_SPI "stm32f2xx-spi"
+#define STM32F2XX_SPI(obj) \
+ OBJECT_CHECK(STM32F2XXSPIState, (obj), TYPE_STM32F2XX_SPI)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t spi_cr1;
+ uint32_t spi_cr2;
+ uint32_t spi_sr;
+ uint32_t spi_dr;
+ uint32_t spi_crcpr;
+ uint32_t spi_rxcrcr;
+ uint32_t spi_txcrcr;
+ uint32_t spi_i2scfgr;
+ uint32_t spi_i2spr;
+
+ qemu_irq irq;
+ SSIBus *ssi;
+} STM32F2XXSPIState;
+
+#endif /* HW_STM32F2XX_SPI_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 05/27] irq: Add a new irq device that allows the ORing of lines
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 04/27] STM32F2xx: Add the SPI device Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 06/27] STM32F205: Connect the ADC devices Peter Maydell
` (23 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Message-id: 52e5d361e3b5a0ea8554aca73ee65ae2b586112e.1474742262.git.alistair@alistair23.me
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/core/Makefile.objs | 1 +
hw/core/or-irq.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/or-irq.h | 44 +++++++++++++++++++++
3 files changed, 152 insertions(+)
create mode 100644 hw/core/or-irq.c
create mode 100644 include/hw/or-irq.h
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index cfd4840..b47241b 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -16,4 +16,5 @@ common-obj-$(CONFIG_SOFTMMU) += null-machine.o
common-obj-$(CONFIG_SOFTMMU) += loader.o
common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
common-obj-$(CONFIG_SOFTMMU) += register.o
+common-obj-$(CONFIG_SOFTMMU) += or-irq.o
common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o
diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c
new file mode 100644
index 0000000..1ac090d
--- /dev/null
+++ b/hw/core/or-irq.c
@@ -0,0 +1,107 @@
+/*
+ * QEMU IRQ/GPIO common code.
+ *
+ * Copyright (c) 2016 Alistair Francis <alistair@alistair23.me>.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/or-irq.h"
+
+static void or_irq_handler(void *opaque, int n, int level)
+{
+ qemu_or_irq *s = OR_IRQ(opaque);
+ int or_level = 0;
+ int i;
+
+ s->levels[n] = level;
+
+ for (i = 0; i < s->num_lines; i++) {
+ or_level |= s->levels[i];
+ }
+
+ qemu_set_irq(s->out_irq, or_level);
+}
+
+static void or_irq_reset(DeviceState *dev)
+{
+ qemu_or_irq *s = OR_IRQ(dev);
+ int i;
+
+ for (i = 0; i < MAX_OR_LINES; i++) {
+ s->levels[i] = false;
+ }
+}
+
+static void or_irq_realize(DeviceState *dev, Error **errp)
+{
+ qemu_or_irq *s = OR_IRQ(dev);
+
+ assert(s->num_lines < MAX_OR_LINES);
+
+ qdev_init_gpio_in(dev, or_irq_handler, s->num_lines);
+}
+
+static void or_irq_init(Object *obj)
+{
+ qemu_or_irq *s = OR_IRQ(obj);
+
+ qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1);
+}
+
+static const VMStateDescription vmstate_or_irq = {
+ .name = TYPE_OR_IRQ,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_BOOL_ARRAY(levels, qemu_or_irq, MAX_OR_LINES),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property or_irq_properties[] = {
+ DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void or_irq_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = or_irq_reset;
+ dc->props = or_irq_properties;
+ dc->realize = or_irq_realize;
+ dc->vmsd = &vmstate_or_irq;
+}
+
+static const TypeInfo or_irq_type_info = {
+ .name = TYPE_OR_IRQ,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(qemu_or_irq),
+ .instance_init = or_irq_init,
+ .class_init = or_irq_class_init,
+};
+
+static void or_irq_register_types(void)
+{
+ type_register_static(&or_irq_type_info);
+}
+
+type_init(or_irq_register_types)
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
new file mode 100644
index 0000000..d400a81
--- /dev/null
+++ b/include/hw/or-irq.h
@@ -0,0 +1,44 @@
+/*
+ * QEMU IRQ/GPIO common code.
+ *
+ * Copyright (c) 2016 Alistair Francis <alistair@alistair23.me>.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_OR_IRQ "or-irq"
+
+#define MAX_OR_LINES 16
+
+typedef struct OrIRQState qemu_or_irq;
+
+#define OR_IRQ(obj) OBJECT_CHECK(qemu_or_irq, (obj), TYPE_OR_IRQ)
+
+struct OrIRQState {
+ DeviceState parent_obj;
+
+ qemu_irq out_irq;
+ qemu_irq *in_irqs;
+ bool levels[MAX_OR_LINES];
+ uint16_t num_lines;
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 06/27] STM32F205: Connect the ADC devices
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 05/27] irq: Add a new irq device that allows the ORing of lines Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 07/27] STM32F205: Connect the SPI devices Peter Maydell
` (22 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
Connect the ADC devices to the STM32F205 SoC.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Message-id: 6214eda399da7b47014f6f895be25323d52dbc9e.1474742262.git.alistair@alistair23.me
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stm32f205_soc.c | 35 +++++++++++++++++++++++++++++++++++
include/hw/arm/stm32f205_soc.h | 6 ++++++
2 files changed, 41 insertions(+)
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 5b6fa3b..2feddc3 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -34,9 +34,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
0x40000800, 0x40000C00 };
static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
+ 0x40012200 };
static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+#define ADC_IRQ 18
static void stm32f205_soc_initfn(Object *obj)
{
@@ -57,6 +60,14 @@ static void stm32f205_soc_initfn(Object *obj)
TYPE_STM32F2XX_TIMER);
qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
}
+
+ s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
+
+ for (i = 0; i < STM_NUM_ADCS; i++) {
+ object_initialize(&s->adc[i], sizeof(s->adc[i]),
+ TYPE_STM32F2XX_ADC);
+ qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
+ }
}
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -132,6 +143,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(busdev, 0, timer_addr[i]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
}
+
+ /* ADC 1 to 3 */
+ object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
+ "num-lines", &err);
+ object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
+ qdev_get_gpio_in(nvic, ADC_IRQ));
+
+ for (i = 0; i < STM_NUM_ADCS; i++) {
+ dev = DEVICE(&(s->adc[i]));
+ object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, adc_addr[i]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
+ }
}
static Property stm32f205_soc_properties[] = {
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 779b5da..1adf824 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -28,6 +28,8 @@
#include "hw/misc/stm32f2xx_syscfg.h"
#include "hw/timer/stm32f2xx_timer.h"
#include "hw/char/stm32f2xx_usart.h"
+#include "hw/adc/stm32f2xx_adc.h"
+#include "hw/or-irq.h"
#define TYPE_STM32F205_SOC "stm32f205-soc"
#define STM32F205_SOC(obj) \
@@ -35,6 +37,7 @@
#define STM_NUM_USARTS 6
#define STM_NUM_TIMERS 4
+#define STM_NUM_ADCS 3
#define FLASH_BASE_ADDRESS 0x08000000
#define FLASH_SIZE (1024 * 1024)
@@ -52,6 +55,9 @@ typedef struct STM32F205State {
STM32F2XXSyscfgState syscfg;
STM32F2XXUsartState usart[STM_NUM_USARTS];
STM32F2XXTimerState timer[STM_NUM_TIMERS];
+ STM32F2XXADCState adc[STM_NUM_ADCS];
+
+ qemu_or_irq *adc_irqs;
} STM32F205State;
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 07/27] STM32F205: Connect the SPI devices
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 06/27] STM32F205: Connect the ADC devices Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 08/27] MAINTAINERS: Add Alistair to the maintainers list Peter Maydell
` (21 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
Connect the SPI devices to the STM32F205 SoC.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: d05849120420f8db0d9aa053bd23134c33cd9180.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stm32f205_soc.c | 22 ++++++++++++++++++++++
include/hw/arm/stm32f205_soc.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 2feddc3..38425bd 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -36,10 +36,13 @@ static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
0x40012200 };
+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
+ 0x40003C00 };
static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
#define ADC_IRQ 18
+static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
static void stm32f205_soc_initfn(Object *obj)
{
@@ -68,6 +71,12 @@ static void stm32f205_soc_initfn(Object *obj)
TYPE_STM32F2XX_ADC);
qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
}
+
+ for (i = 0; i < STM_NUM_SPIS; i++) {
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
+ TYPE_STM32F2XX_SPI);
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+ }
}
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -167,6 +176,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
}
+
+ /* SPI 1 and 2 */
+ for (i = 0; i < STM_NUM_SPIS; i++) {
+ dev = DEVICE(&(s->spi[i]));
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, spi_addr[i]);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
+ }
}
static Property stm32f205_soc_properties[] = {
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 1adf824..1332141 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -30,6 +30,7 @@
#include "hw/char/stm32f2xx_usart.h"
#include "hw/adc/stm32f2xx_adc.h"
#include "hw/or-irq.h"
+#include "hw/ssi/stm32f2xx_spi.h"
#define TYPE_STM32F205_SOC "stm32f205-soc"
#define STM32F205_SOC(obj) \
@@ -38,6 +39,7 @@
#define STM_NUM_USARTS 6
#define STM_NUM_TIMERS 4
#define STM_NUM_ADCS 3
+#define STM_NUM_SPIS 3
#define FLASH_BASE_ADDRESS 0x08000000
#define FLASH_SIZE (1024 * 1024)
@@ -56,6 +58,7 @@ typedef struct STM32F205State {
STM32F2XXUsartState usart[STM_NUM_USARTS];
STM32F2XXTimerState timer[STM_NUM_TIMERS];
STM32F2XXADCState adc[STM_NUM_ADCS];
+ STM32F2XXSPIState spi[STM_NUM_SPIS];
qemu_or_irq *adc_irqs;
} STM32F205State;
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 08/27] MAINTAINERS: Add Alistair to the maintainers list
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 07/27] STM32F205: Connect the SPI devices Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 09/27] mainstone: Fix incorrect key mapping for Enter key Peter Maydell
` (20 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair23@gmail.com>
Add Alistair Francis as the maintainer for the Netduino 2
and SMM32F205 SoC.
Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 5a46ccf398b050a41cc3b3d0e94bcff4ce2d85e0.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 63cf21f..88fd674 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -479,6 +479,21 @@ S: Maintained
F: hw/arm/virt-acpi-build.c
F: include/hw/arm/virt-acpi-build.h
+STM32F205
+M: Alistair Francis <alistair@alistair23.me>
+S: Maintained
+F: hw/arm/stm32f205_soc.c
+F: hw/misc/stm32f2xx_syscfg.c
+F: hw/char/stm32f2xx_usart.c
+F: hw/timer/stm32f2xx_timer.c
+F: hw/adc/*
+F: hw/ssi/stm32f2xx_spi.c
+
+Netduino 2
+M: Alistair Francis <alistair@alistair23.me>
+S: Maintained
+F: hw/arm/netduino2.c
+
CRIS Machines
-------------
Axis Dev88
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 09/27] mainstone: Fix incorrect key mapping for Enter key.
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 08/27] MAINTAINERS: Add Alistair to the maintainers list Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 10/27] mainstone: Add mapping for dot, slash and backspace Peter Maydell
` (19 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Vijay Kumar B <vijaykumar@zilogic.com>
According to the manual the (5, 5) corresponds to backspace key, and
not Enter key. Linux kernel maps (5, 4) to the enter key. Fixing it up
to match the mapping in the Linux kernel.
Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com>
Reviewed-by: Deepak S. <deepak@zilogic.com>
Message-id: 1475063033-8176-2-git-send-email-vijaykumar@zilogic.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/mainstone.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index 454acc5..e81b878 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -88,7 +88,7 @@ static const struct keymap map[0xE0] = {
* Matrix position {5,4} and other keys are missing here.
* TODO: Compare with Linux code and test real hardware.
*/
- [0x1c] = {5,5}, /* enter (TODO: might be wrong) */
+ [0x1c] = {5,4}, /* enter */
[0xc8] = {6,0}, /* up */
[0xd0] = {6,1}, /* down */
[0xcb] = {6,2}, /* left */
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 10/27] mainstone: Add mapping for dot, slash and backspace.
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 09/27] mainstone: Fix incorrect key mapping for Enter key Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 11/27] hw/arm: Fix Integrator/CM initialization Peter Maydell
` (18 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Vijay Kumar B <vijaykumar@zilogic.com>
Add missed out mappings. These mappings are from the "Intel PXA27x
Processor Developer's Kit User Guide".
Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com>
Reviewed-by: Deepak S. <deepak@zilogic.com>
Message-id: 1475063033-8176-3-git-send-email-vijaykumar@zilogic.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/mainstone.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index e81b878..f962236 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -73,8 +73,10 @@ static const struct keymap map[0xE0] = {
[0x2f] = {3,3}, /* v */
[0x11] = {3,4}, /* w */
[0x2d] = {3,5}, /* x */
+ [0x34] = {4,0}, /* . */
[0x15] = {4,2}, /* y */
[0x2c] = {4,3}, /* z */
+ [0x35] = {4,4}, /* / */
[0xc7] = {5,0}, /* Home */
[0x2a] = {5,1}, /* shift */
/*
@@ -89,6 +91,7 @@ static const struct keymap map[0xE0] = {
* TODO: Compare with Linux code and test real hardware.
*/
[0x1c] = {5,4}, /* enter */
+ [0x0e] = {5,5}, /* backspace */
[0xc8] = {6,0}, /* up */
[0xd0] = {6,1}, /* down */
[0xcb] = {6,2}, /* left */
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 11/27] hw/arm: Fix Integrator/CM initialization
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 10/27] mainstone: Add mapping for dot, slash and backspace Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 12/27] vmstateify tsc2005 Peter Maydell
` (17 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Jakub Jermar <jakub@jermar.eu>
Initialization of a class instance cannot depend on its own properties
as these are not yet set. Move parts of integratorcm_init() that depend
on the "memsz" property to the newly added integratorcm_realize().
This fixes: https://bugs.launchpad.net/qemu/+bug/1624726
Signed-off-by: Jakub Jermar <jakub@jermar.eu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/integratorcp.c | 35 +++++++++++++++++++++--------------
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 96dc150..039812a 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -252,6 +252,26 @@ static void integratorcm_init(Object *obj)
/* ??? What should the high bits of this value be? */
s->cm_auxosc = 0x0007feff;
s->cm_sdram = 0x00011122;
+ memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
+ s->cm_init = 0x00000112;
+ s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
+ 1000);
+ memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
+ &error_fatal);
+ vmstate_register_ram_global(&s->flash);
+
+ memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
+ "integratorcm", 0x00800000);
+ sysbus_init_mmio(dev, &s->iomem);
+
+ integratorcm_do_remap(s);
+ /* ??? Save/restore. */
+}
+
+static void integratorcm_realize(DeviceState *d, Error **errp)
+{
+ IntegratorCMState *s = INTEGRATOR_CM(d);
+
if (s->memsz >= 256) {
integrator_spd[31] = 64;
s->cm_sdram |= 0x10;
@@ -267,20 +287,6 @@ static void integratorcm_init(Object *obj)
} else {
integrator_spd[31] = 2;
}
- memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
- s->cm_init = 0x00000112;
- s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
- 1000);
- memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
- &error_fatal);
- vmstate_register_ram_global(&s->flash);
-
- memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
- "integratorcm", 0x00800000);
- sysbus_init_mmio(dev, &s->iomem);
-
- integratorcm_do_remap(s);
- /* ??? Save/restore. */
}
/* Integrator/CP hardware emulation. */
@@ -633,6 +639,7 @@ static void core_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->props = core_properties;
+ dc->realize = integratorcm_realize;
}
static const TypeInfo core_info = {
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 12/27] vmstateify tsc2005
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 11/27] hw/arm: Fix Integrator/CM initialization Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 13/27] vmstateify tsc210x Peter Maydell
` (16 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
I've converted the fields in it's main data structure
to fixed size types in ways that look sane.
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 1474977735-10156-2-git-send-email-dgilbert@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/input/tsc2005.c | 190 +++++++++++++++++++++--------------------------------
1 file changed, 75 insertions(+), 115 deletions(-)
diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
index 9b359aa..eb5320a 100644
--- a/hw/input/tsc2005.c
+++ b/hw/input/tsc2005.c
@@ -31,30 +31,31 @@ typedef struct {
QEMUTimer *timer;
uint16_t model;
- int x, y;
- int pressure;
+ int32_t x, y;
+ bool pressure;
- int state, reg, irq, command;
+ uint8_t reg, state;
+ bool irq, command;
uint16_t data, dav;
- int busy;
- int enabled;
- int host_mode;
- int function;
- int nextfunction;
- int precision;
- int nextprecision;
- int filter;
- int pin_func;
- int timing[2];
- int noise;
- int reset;
- int pdst;
- int pnd0;
+ bool busy;
+ bool enabled;
+ bool host_mode;
+ int8_t function;
+ int8_t nextfunction;
+ bool precision;
+ bool nextprecision;
+ uint16_t filter;
+ uint8_t pin_func;
+ uint16_t timing[2];
+ uint8_t noise;
+ bool reset;
+ bool pdst;
+ bool pnd0;
uint16_t temp_thr[2];
uint16_t aux_thr[2];
- int tr[8];
+ int32_t tr[8];
} TSC2005State;
enum {
@@ -149,7 +150,7 @@ static uint16_t tsc2005_read(TSC2005State *s, int reg)
ret = s->dav | (s->reset << 7) | (s->pdst << 2) | 0x0;
s->dav &= ~(mode_regs[TSC_MODE_X_TEST] | mode_regs[TSC_MODE_Y_TEST] |
mode_regs[TSC_MODE_TS_TEST]);
- s->reset = 1;
+ s->reset = true;
return ret;
case 0x8: /* AUX high treshold */
@@ -196,14 +197,14 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
break;
case 0xc: /* CFR0 */
- s->host_mode = data >> 15;
+ s->host_mode = (data >> 15) != 0;
if (s->enabled != !(data & 0x4000)) {
s->enabled = !(data & 0x4000);
fprintf(stderr, "%s: touchscreen sense %sabled\n",
__FUNCTION__, s->enabled ? "en" : "dis");
if (s->busy && !s->enabled)
timer_del(s->timer);
- s->busy &= s->enabled;
+ s->busy = s->busy && s->enabled;
}
s->nextprecision = (data >> 13) & 1;
s->timing[0] = data & 0x1fff;
@@ -229,7 +230,7 @@ static void tsc2005_write(TSC2005State *s, int reg, uint16_t data)
static void tsc2005_pin_update(TSC2005State *s)
{
int64_t expires;
- int pin_state;
+ bool pin_state;
switch (s->pin_func) {
case 0:
@@ -253,7 +254,7 @@ static void tsc2005_pin_update(TSC2005State *s)
case TSC_MODE_XYZ_SCAN:
case TSC_MODE_XY_SCAN:
if (!s->host_mode && s->dav)
- s->enabled = 0;
+ s->enabled = false;
if (!s->pressure)
return;
/* Fall through */
@@ -273,7 +274,7 @@ static void tsc2005_pin_update(TSC2005State *s)
case TSC_MODE_Y_TEST:
case TSC_MODE_TS_TEST:
if (s->dav)
- s->enabled = 0;
+ s->enabled = false;
break;
case TSC_MODE_RESERVED:
@@ -287,7 +288,7 @@ static void tsc2005_pin_update(TSC2005State *s)
if (!s->enabled || s->busy)
return;
- s->busy = 1;
+ s->busy = true;
s->precision = s->nextprecision;
s->function = s->nextfunction;
s->pdst = !s->pnd0; /* Synchronised on internal clock */
@@ -300,17 +301,17 @@ static void tsc2005_reset(TSC2005State *s)
{
s->state = 0;
s->pin_func = 0;
- s->enabled = 0;
- s->busy = 0;
- s->nextprecision = 0;
+ s->enabled = false;
+ s->busy = false;
+ s->nextprecision = false;
s->nextfunction = 0;
s->timing[0] = 0;
s->timing[1] = 0;
- s->irq = 0;
+ s->irq = false;
s->dav = 0;
- s->reset = 0;
- s->pdst = 1;
- s->pnd0 = 0;
+ s->reset = false;
+ s->pdst = true;
+ s->pnd0 = false;
s->function = -1;
s->temp_thr[0] = 0x000;
s->temp_thr[1] = 0xfff;
@@ -340,7 +341,7 @@ static uint8_t tsc2005_txrx_word(void *opaque, uint8_t value)
__FUNCTION__, s->enabled ? "en" : "dis");
if (s->busy && !s->enabled)
timer_del(s->timer);
- s->busy &= s->enabled;
+ s->busy = s->busy && s->enabled;
}
tsc2005_pin_update(s);
}
@@ -407,7 +408,7 @@ static void tsc2005_timer_tick(void *opaque)
if (!s->busy)
return;
- s->busy = 0;
+ s->busy = false;
s->dav |= mode_regs[s->function];
s->function = -1;
tsc2005_pin_update(s);
@@ -434,86 +435,9 @@ static void tsc2005_touchscreen_event(void *opaque,
tsc2005_pin_update(s);
}
-static void tsc2005_save(QEMUFile *f, void *opaque)
+static int tsc2005_post_load(void *opaque, int version_id)
{
TSC2005State *s = (TSC2005State *) opaque;
- int i;
-
- qemu_put_be16(f, s->x);
- qemu_put_be16(f, s->y);
- qemu_put_byte(f, s->pressure);
-
- qemu_put_byte(f, s->state);
- qemu_put_byte(f, s->reg);
- qemu_put_byte(f, s->command);
-
- qemu_put_byte(f, s->irq);
- qemu_put_be16s(f, &s->dav);
- qemu_put_be16s(f, &s->data);
-
- timer_put(f, s->timer);
- qemu_put_byte(f, s->enabled);
- qemu_put_byte(f, s->host_mode);
- qemu_put_byte(f, s->function);
- qemu_put_byte(f, s->nextfunction);
- qemu_put_byte(f, s->precision);
- qemu_put_byte(f, s->nextprecision);
- qemu_put_be16(f, s->filter);
- qemu_put_byte(f, s->pin_func);
- qemu_put_be16(f, s->timing[0]);
- qemu_put_be16(f, s->timing[1]);
- qemu_put_be16s(f, &s->temp_thr[0]);
- qemu_put_be16s(f, &s->temp_thr[1]);
- qemu_put_be16s(f, &s->aux_thr[0]);
- qemu_put_be16s(f, &s->aux_thr[1]);
- qemu_put_be32(f, s->noise);
- qemu_put_byte(f, s->reset);
- qemu_put_byte(f, s->pdst);
- qemu_put_byte(f, s->pnd0);
-
- for (i = 0; i < 8; i ++)
- qemu_put_be32(f, s->tr[i]);
-}
-
-static int tsc2005_load(QEMUFile *f, void *opaque, int version_id)
-{
- TSC2005State *s = (TSC2005State *) opaque;
- int i;
-
- s->x = qemu_get_be16(f);
- s->y = qemu_get_be16(f);
- s->pressure = qemu_get_byte(f);
-
- s->state = qemu_get_byte(f);
- s->reg = qemu_get_byte(f);
- s->command = qemu_get_byte(f);
-
- s->irq = qemu_get_byte(f);
- qemu_get_be16s(f, &s->dav);
- qemu_get_be16s(f, &s->data);
-
- timer_get(f, s->timer);
- s->enabled = qemu_get_byte(f);
- s->host_mode = qemu_get_byte(f);
- s->function = qemu_get_byte(f);
- s->nextfunction = qemu_get_byte(f);
- s->precision = qemu_get_byte(f);
- s->nextprecision = qemu_get_byte(f);
- s->filter = qemu_get_be16(f);
- s->pin_func = qemu_get_byte(f);
- s->timing[0] = qemu_get_be16(f);
- s->timing[1] = qemu_get_be16(f);
- qemu_get_be16s(f, &s->temp_thr[0]);
- qemu_get_be16s(f, &s->temp_thr[1]);
- qemu_get_be16s(f, &s->aux_thr[0]);
- qemu_get_be16s(f, &s->aux_thr[1]);
- s->noise = qemu_get_be32(f);
- s->reset = qemu_get_byte(f);
- s->pdst = qemu_get_byte(f);
- s->pnd0 = qemu_get_byte(f);
-
- for (i = 0; i < 8; i ++)
- s->tr[i] = qemu_get_be32(f);
s->busy = timer_pending(s->timer);
tsc2005_pin_update(s);
@@ -521,6 +445,42 @@ static int tsc2005_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
+static const VMStateDescription vmstate_tsc2005 = {
+ .name = "tsc2005",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .post_load = tsc2005_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_BOOL(pressure, TSC2005State),
+ VMSTATE_BOOL(irq, TSC2005State),
+ VMSTATE_BOOL(command, TSC2005State),
+ VMSTATE_BOOL(enabled, TSC2005State),
+ VMSTATE_BOOL(host_mode, TSC2005State),
+ VMSTATE_BOOL(reset, TSC2005State),
+ VMSTATE_BOOL(pdst, TSC2005State),
+ VMSTATE_BOOL(pnd0, TSC2005State),
+ VMSTATE_BOOL(precision, TSC2005State),
+ VMSTATE_BOOL(nextprecision, TSC2005State),
+ VMSTATE_UINT8(reg, TSC2005State),
+ VMSTATE_UINT8(state, TSC2005State),
+ VMSTATE_UINT16(data, TSC2005State),
+ VMSTATE_UINT16(dav, TSC2005State),
+ VMSTATE_UINT16(filter, TSC2005State),
+ VMSTATE_INT8(nextfunction, TSC2005State),
+ VMSTATE_INT8(function, TSC2005State),
+ VMSTATE_INT32(x, TSC2005State),
+ VMSTATE_INT32(y, TSC2005State),
+ VMSTATE_TIMER_PTR(timer, TSC2005State),
+ VMSTATE_UINT8(pin_func, TSC2005State),
+ VMSTATE_UINT16_ARRAY(timing, TSC2005State, 2),
+ VMSTATE_UINT8(noise, TSC2005State),
+ VMSTATE_UINT16_ARRAY(temp_thr, TSC2005State, 2),
+ VMSTATE_UINT16_ARRAY(aux_thr, TSC2005State, 2),
+ VMSTATE_INT32_ARRAY(tr, TSC2005State, 8),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
void *tsc2005_init(qemu_irq pintdav)
{
TSC2005State *s;
@@ -529,8 +489,8 @@ void *tsc2005_init(qemu_irq pintdav)
g_malloc0(sizeof(TSC2005State));
s->x = 400;
s->y = 240;
- s->pressure = 0;
- s->precision = s->nextprecision = 0;
+ s->pressure = false;
+ s->precision = s->nextprecision = false;
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tsc2005_timer_tick, s);
s->pint = pintdav;
s->model = 0x2005;
@@ -550,7 +510,7 @@ void *tsc2005_init(qemu_irq pintdav)
"QEMU TSC2005-driven Touchscreen");
qemu_register_reset((void *) tsc2005_reset, s);
- register_savevm(NULL, "tsc2005", -1, 0, tsc2005_save, tsc2005_load, s);
+ vmstate_register(NULL, 0, &vmstate_tsc2005, s);
return s;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 13/27] vmstateify tsc210x
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 12/27] vmstateify tsc2005 Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 14/27] hw/arm/virt: add 2.8 machine type Peter Maydell
` (15 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
I'm now saving all 3 of the pll entries; only 2 were saved before.
There are a couple of times that were previously stored as offsets
from 'now' calculated before saving; with vmstate it's easier
to store the 'now' and fix it up on reload.
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 1474977735-10156-3-git-send-email-dgilbert@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/input/tsc210x.c | 227 ++++++++++++++++++++++++-----------------------------
1 file changed, 104 insertions(+), 123 deletions(-)
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
index 93ca374..b068343 100644
--- a/hw/input/tsc210x.c
+++ b/hw/input/tsc210x.c
@@ -47,24 +47,25 @@ typedef struct {
uint8_t out_fifo[16384];
uint16_t model;
- int x, y;
- int pressure;
-
- int state, page, offset, irq;
- uint16_t command, dav;
-
- int busy;
- int enabled;
- int host_mode;
- int function;
- int nextfunction;
- int precision;
- int nextprecision;
- int filter;
- int pin_func;
- int ref;
- int timing;
- int noise;
+ int32_t x, y;
+ bool pressure;
+
+ uint8_t page, offset;
+ uint16_t dav;
+
+ bool state;
+ bool irq;
+ bool command;
+ bool busy;
+ bool enabled;
+ bool host_mode;
+ uint8_t function, nextfunction;
+ uint8_t precision, nextprecision;
+ uint8_t filter;
+ uint8_t pin_func;
+ uint8_t ref;
+ uint8_t timing;
+ uint8_t noise;
uint16_t audio_ctrl1;
uint16_t audio_ctrl2;
@@ -72,7 +73,7 @@ typedef struct {
uint16_t pll[3];
uint16_t volume;
int64_t volume_change;
- int softstep;
+ bool softstep;
uint16_t dac_power;
int64_t powerdown;
uint16_t filter_data[0x14];
@@ -93,6 +94,7 @@ typedef struct {
int mode;
int intr;
} kb;
+ int64_t now; /* Time at migration */
} TSC210xState;
static const int resolution[4] = { 12, 8, 10, 12 };
@@ -154,14 +156,14 @@ static const uint16_t mode_regs[16] = {
static void tsc210x_reset(TSC210xState *s)
{
- s->state = 0;
+ s->state = false;
s->pin_func = 2;
- s->enabled = 0;
- s->busy = 0;
+ s->enabled = false;
+ s->busy = false;
s->nextfunction = 0;
s->ref = 0;
s->timing = 0;
- s->irq = 0;
+ s->irq = false;
s->dav = 0;
s->audio_ctrl1 = 0x0000;
@@ -172,7 +174,7 @@ static void tsc210x_reset(TSC210xState *s)
s->pll[2] = 0x1fff;
s->volume = 0xffff;
s->dac_power = 0x8540;
- s->softstep = 1;
+ s->softstep = true;
s->volume_change = 0;
s->powerdown = 0;
s->filter_data[0x00] = 0x6be3;
@@ -566,7 +568,7 @@ static void tsc2102_control_register_write(
s->enabled = !(value & 0x4000);
if (s->busy && !s->enabled)
timer_del(s->timer);
- s->busy &= s->enabled;
+ s->busy = s->busy && s->enabled;
s->nextfunction = (value >> 10) & 0xf;
s->nextprecision = (value >> 8) & 3;
s->filter = value & 0xff;
@@ -773,7 +775,7 @@ static void tsc2102_audio_register_write(
static void tsc210x_pin_update(TSC210xState *s)
{
int64_t expires;
- int pin_state;
+ bool pin_state;
switch (s->pin_func) {
case 0:
@@ -788,7 +790,7 @@ static void tsc210x_pin_update(TSC210xState *s)
}
if (!s->enabled)
- pin_state = 0;
+ pin_state = false;
if (pin_state != s->irq) {
s->irq = pin_state;
@@ -814,7 +816,7 @@ static void tsc210x_pin_update(TSC210xState *s)
case TSC_MODE_TEMP1:
case TSC_MODE_TEMP2:
if (s->dav)
- s->enabled = 0;
+ s->enabled = false;
break;
case TSC_MODE_AUX_SCAN:
@@ -832,7 +834,7 @@ static void tsc210x_pin_update(TSC210xState *s)
if (!s->enabled || s->busy || s->dav)
return;
- s->busy = 1;
+ s->busy = true;
s->precision = s->nextprecision;
s->function = s->nextfunction;
expires = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
@@ -867,7 +869,7 @@ static uint16_t tsc210x_read(TSC210xState *s)
/* Allow sequential reads. */
s->offset ++;
- s->state = 0;
+ s->state = false;
return ret;
}
@@ -878,10 +880,10 @@ static void tsc210x_write(TSC210xState *s, uint16_t value)
* command and data every second time.
*/
if (!s->state) {
- s->command = value >> 15;
+ s->command = (value >> 15) != 0;
s->page = (value >> 11) & 0x0f;
s->offset = (value >> 5) & 0x3f;
- s->state = 1;
+ s->state = true;
} else {
if (s->command)
fprintf(stderr, "tsc210x_write: SPI overrun!\n");
@@ -901,7 +903,7 @@ static void tsc210x_write(TSC210xState *s, uint16_t value)
}
tsc210x_pin_update(s);
- s->state = 0;
+ s->state = false;
}
}
@@ -933,7 +935,7 @@ static void tsc210x_timer_tick(void *opaque)
if (!s->busy)
return;
- s->busy = 0;
+ s->busy = false;
s->dav |= mode_regs[s->function];
tsc210x_pin_update(s);
qemu_irq_lower(s->davint);
@@ -974,108 +976,34 @@ static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out)
s->i2s_rx_rate = in;
}
-static void tsc210x_save(QEMUFile *f, void *opaque)
+static void tsc210x_pre_save(void *opaque)
{
TSC210xState *s = (TSC210xState *) opaque;
- int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- int i;
-
- qemu_put_be16(f, s->x);
- qemu_put_be16(f, s->y);
- qemu_put_byte(f, s->pressure);
-
- qemu_put_byte(f, s->state);
- qemu_put_byte(f, s->page);
- qemu_put_byte(f, s->offset);
- qemu_put_byte(f, s->command);
-
- qemu_put_byte(f, s->irq);
- qemu_put_be16s(f, &s->dav);
-
- timer_put(f, s->timer);
- qemu_put_byte(f, s->enabled);
- qemu_put_byte(f, s->host_mode);
- qemu_put_byte(f, s->function);
- qemu_put_byte(f, s->nextfunction);
- qemu_put_byte(f, s->precision);
- qemu_put_byte(f, s->nextprecision);
- qemu_put_byte(f, s->filter);
- qemu_put_byte(f, s->pin_func);
- qemu_put_byte(f, s->ref);
- qemu_put_byte(f, s->timing);
- qemu_put_be32(f, s->noise);
-
- qemu_put_be16s(f, &s->audio_ctrl1);
- qemu_put_be16s(f, &s->audio_ctrl2);
- qemu_put_be16s(f, &s->audio_ctrl3);
- qemu_put_be16s(f, &s->pll[0]);
- qemu_put_be16s(f, &s->pll[1]);
- qemu_put_be16s(f, &s->volume);
- qemu_put_sbe64(f, (s->volume_change - now));
- qemu_put_sbe64(f, (s->powerdown - now));
- qemu_put_byte(f, s->softstep);
- qemu_put_be16s(f, &s->dac_power);
-
- for (i = 0; i < 0x14; i ++)
- qemu_put_be16s(f, &s->filter_data[i]);
+ s->now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
-static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
+static int tsc210x_post_load(void *opaque, int version_id)
{
TSC210xState *s = (TSC210xState *) opaque;
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- int i;
-
- s->x = qemu_get_be16(f);
- s->y = qemu_get_be16(f);
- s->pressure = qemu_get_byte(f);
-
- s->state = qemu_get_byte(f);
- s->page = qemu_get_byte(f);
- s->offset = qemu_get_byte(f);
- s->command = qemu_get_byte(f);
- s->irq = qemu_get_byte(f);
- qemu_get_be16s(f, &s->dav);
-
- timer_get(f, s->timer);
- s->enabled = qemu_get_byte(f);
- s->host_mode = qemu_get_byte(f);
- s->function = qemu_get_byte(f);
- if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ if (s->function >= ARRAY_SIZE(mode_regs)) {
return -EINVAL;
}
- s->nextfunction = qemu_get_byte(f);
- if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ if (s->nextfunction >= ARRAY_SIZE(mode_regs)) {
return -EINVAL;
}
- s->precision = qemu_get_byte(f);
- if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ if (s->precision >= ARRAY_SIZE(resolution)) {
return -EINVAL;
}
- s->nextprecision = qemu_get_byte(f);
- if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ if (s->nextprecision >= ARRAY_SIZE(resolution)) {
return -EINVAL;
}
- s->filter = qemu_get_byte(f);
- s->pin_func = qemu_get_byte(f);
- s->ref = qemu_get_byte(f);
- s->timing = qemu_get_byte(f);
- s->noise = qemu_get_be32(f);
-
- qemu_get_be16s(f, &s->audio_ctrl1);
- qemu_get_be16s(f, &s->audio_ctrl2);
- qemu_get_be16s(f, &s->audio_ctrl3);
- qemu_get_be16s(f, &s->pll[0]);
- qemu_get_be16s(f, &s->pll[1]);
- qemu_get_be16s(f, &s->volume);
- s->volume_change = qemu_get_sbe64(f) + now;
- s->powerdown = qemu_get_sbe64(f) + now;
- s->softstep = qemu_get_byte(f);
- qemu_get_be16s(f, &s->dac_power);
-
- for (i = 0; i < 0x14; i ++)
- qemu_get_be16s(f, &s->filter_data[i]);
+
+ s->volume_change -= s->now;
+ s->volume_change += now;
+ s->powerdown -= s->now;
+ s->powerdown += now;
s->busy = timer_pending(s->timer);
qemu_set_irq(s->pint, !s->irq);
@@ -1084,6 +1012,60 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
+static VMStateField vmstatefields_tsc210x[] = {
+ VMSTATE_BOOL(enabled, TSC210xState),
+ VMSTATE_BOOL(host_mode, TSC210xState),
+ VMSTATE_BOOL(irq, TSC210xState),
+ VMSTATE_BOOL(command, TSC210xState),
+ VMSTATE_BOOL(pressure, TSC210xState),
+ VMSTATE_BOOL(softstep, TSC210xState),
+ VMSTATE_BOOL(state, TSC210xState),
+ VMSTATE_UINT16(dav, TSC210xState),
+ VMSTATE_INT32(x, TSC210xState),
+ VMSTATE_INT32(y, TSC210xState),
+ VMSTATE_UINT8(offset, TSC210xState),
+ VMSTATE_UINT8(page, TSC210xState),
+ VMSTATE_UINT8(filter, TSC210xState),
+ VMSTATE_UINT8(pin_func, TSC210xState),
+ VMSTATE_UINT8(ref, TSC210xState),
+ VMSTATE_UINT8(timing, TSC210xState),
+ VMSTATE_UINT8(noise, TSC210xState),
+ VMSTATE_UINT8(function, TSC210xState),
+ VMSTATE_UINT8(nextfunction, TSC210xState),
+ VMSTATE_UINT8(precision, TSC210xState),
+ VMSTATE_UINT8(nextprecision, TSC210xState),
+ VMSTATE_UINT16(audio_ctrl1, TSC210xState),
+ VMSTATE_UINT16(audio_ctrl2, TSC210xState),
+ VMSTATE_UINT16(audio_ctrl3, TSC210xState),
+ VMSTATE_UINT16_ARRAY(pll, TSC210xState, 3),
+ VMSTATE_UINT16(volume, TSC210xState),
+ VMSTATE_UINT16(dac_power, TSC210xState),
+ VMSTATE_INT64(volume_change, TSC210xState),
+ VMSTATE_INT64(powerdown, TSC210xState),
+ VMSTATE_INT64(now, TSC210xState),
+ VMSTATE_UINT16_ARRAY(filter_data, TSC210xState, 0x14),
+ VMSTATE_TIMER_PTR(timer, TSC210xState),
+ VMSTATE_END_OF_LIST()
+};
+
+static const VMStateDescription vmstate_tsc2102 = {
+ .name = "tsc2102",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .pre_save = tsc210x_pre_save,
+ .post_load = tsc210x_post_load,
+ .fields = vmstatefields_tsc210x,
+};
+
+static const VMStateDescription vmstate_tsc2301 = {
+ .name = "tsc2301",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .pre_save = tsc210x_pre_save,
+ .post_load = tsc210x_post_load,
+ .fields = vmstatefields_tsc210x,
+};
+
uWireSlave *tsc2102_init(qemu_irq pint)
{
TSC210xState *s;
@@ -1125,8 +1107,7 @@ uWireSlave *tsc2102_init(qemu_irq pint)
AUD_register_card(s->name, &s->card);
qemu_register_reset((void *) tsc210x_reset, s);
- register_savevm(NULL, s->name, -1, 0,
- tsc210x_save, tsc210x_load, s);
+ vmstate_register(NULL, 0, &vmstate_tsc2102, s);
return &s->chip;
}
@@ -1174,7 +1155,7 @@ uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
AUD_register_card(s->name, &s->card);
qemu_register_reset((void *) tsc210x_reset, s);
- register_savevm(NULL, s->name, -1, 0, tsc210x_save, tsc210x_load, s);
+ vmstate_register(NULL, 0, &vmstate_tsc2301, s);
return &s->chip;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 14/27] hw/arm/virt: add 2.8 machine type
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 13/27] vmstateify tsc210x Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 15/27] hw/intc/arm_gic(v3)_kvm: Initialize gsi routing Peter Maydell
` (14 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Andrew Jones <drjones@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 1474641676-25017-1-git-send-email-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a193b5a..2ead58d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1479,7 +1479,7 @@ static void machvirt_machine_init(void)
}
type_init(machvirt_machine_init);
-static void virt_2_7_instance_init(Object *obj)
+static void virt_2_8_instance_init(Object *obj)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -1512,10 +1512,25 @@ static void virt_2_7_instance_init(Object *obj)
"Valid values are 2, 3 and host", NULL);
}
+static void virt_machine_2_8_options(MachineClass *mc)
+{
+}
+DEFINE_VIRT_MACHINE_AS_LATEST(2, 8)
+
+#define VIRT_COMPAT_2_7 \
+ HW_COMPAT_2_7
+
+static void virt_2_7_instance_init(Object *obj)
+{
+ virt_2_8_instance_init(obj);
+}
+
static void virt_machine_2_7_options(MachineClass *mc)
{
+ virt_machine_2_8_options(mc);
+ SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7);
}
-DEFINE_VIRT_MACHINE_AS_LATEST(2, 7)
+DEFINE_VIRT_MACHINE(2, 7)
#define VIRT_COMPAT_2_6 \
HW_COMPAT_2_6
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 15/27] hw/intc/arm_gic(v3)_kvm: Initialize gsi routing
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 14/27] hw/arm/virt: add 2.8 machine type Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 16/27] hw/intc/arm_gicv3_its: Implement ITS base class Peter Maydell
` (13 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Eric Auger <eric.auger@redhat.com>
Advertise gsi routing and set up irqchip routing entries for
GIC SPIs.
This is not mandated as long as MSI routing is not used
(because the kernel sets a default irqchip routing table).
However once MSI routing gets used (for VIRTIO-PCI vhost for
example), the first call to KVM_SET_GSI_ROUTING overrides the
kernel default irqchip table.
If no routing entry exists for the GSI, any IRQFD signaling for
this GSI will fail.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-2-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic_kvm.c | 12 ++++++++++++
hw/intc/arm_gicv3_kvm.c | 13 +++++++++++++
2 files changed, 25 insertions(+)
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 5593cdb..ae7ac58 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -577,6 +577,18 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
"not support vGICv2 migration");
migrate_add_blocker(s->migration_blocker);
}
+
+ if (kvm_has_gsi_routing()) {
+ /* set up irq routing */
+ kvm_init_irq_routing(kvm_state);
+ for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
+ kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
+ }
+
+ kvm_gsi_routing_allowed = true;
+
+ kvm_irqchip_commit_routes(kvm_state);
+ }
}
static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 711fde3..199a439 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -85,6 +85,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
GICv3State *s = KVM_ARM_GICV3(dev);
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
Error *local_err = NULL;
+ int i;
DPRINTF("kvm_arm_gicv3_realize\n");
@@ -127,6 +128,18 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
*/
error_setg(&s->migration_blocker, "vGICv3 migration is not implemented");
migrate_add_blocker(s->migration_blocker);
+
+ if (kvm_has_gsi_routing()) {
+ /* set up irq routing */
+ kvm_init_irq_routing(kvm_state);
+ for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
+ kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
+ }
+
+ kvm_gsi_routing_allowed = true;
+
+ kvm_irqchip_commit_routes(kvm_state);
+ }
}
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 16/27] hw/intc/arm_gicv3_its: Implement ITS base class
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 15/27] hw/intc/arm_gic(v3)_kvm: Initialize gsi routing Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 17/27] target-arm: move gicv3_class_name from machine to kvm_arm.h Peter Maydell
` (12 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Pavel Fedin <p.fedin@samsung.com>
This is the basic skeleton for both KVM and software-emulated ITS.
Since we already prepare status structure, we also introduce complete
VMState description. But, because we currently have no migratable
implementations, we also set unmigratable flag.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-3-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/Makefile.objs | 1 +
hw/intc/arm_gicv3_its_common.c | 148 +++++++++++++++++++++++++++++++++
include/hw/intc/arm_gicv3_its_common.h | 78 +++++++++++++++++
target-arm/kvm_arm.h | 19 +++++
4 files changed, 246 insertions(+)
create mode 100644 hw/intc/arm_gicv3_its_common.c
create mode 100644 include/hw/intc/arm_gicv3_its_common.h
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 05ec21b..23a39f7 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -16,6 +16,7 @@ common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_dist.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_redist.o
+common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_its_common.o
common-obj-$(CONFIG_OPENPIC) += openpic.o
obj-$(CONFIG_APIC) += apic.o apic_common.o
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
new file mode 100644
index 0000000..9d67c5c
--- /dev/null
+++ b/hw/intc/arm_gicv3_its_common.c
@@ -0,0 +1,148 @@
+/*
+ * ITS base class for a GICv3-based system
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Written by Pavel Fedin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci/msi.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "qemu/log.h"
+
+static void gicv3_its_pre_save(void *opaque)
+{
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
+ GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
+
+ if (c->pre_save) {
+ c->pre_save(s);
+ }
+}
+
+static int gicv3_its_post_load(void *opaque, int version_id)
+{
+ GICv3ITSState *s = (GICv3ITSState *)opaque;
+ GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
+
+ if (c->post_load) {
+ c->post_load(s);
+ }
+ return 0;
+}
+
+static const VMStateDescription vmstate_its = {
+ .name = "arm_gicv3_its",
+ .pre_save = gicv3_its_pre_save,
+ .post_load = gicv3_its_post_load,
+ .unmigratable = true,
+};
+
+static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
+ return MEMTX_ERROR;
+}
+
+static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ if (offset == 0x0040 && ((size == 2) || (size == 4))) {
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
+ GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
+ int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
+
+ if (ret <= 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS: Error sending MSI: %s\n", strerror(-ret));
+ return MEMTX_DECODE_ERROR;
+ }
+
+ return MEMTX_OK;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "ITS write at bad offset 0x%"PRIx64"\n", offset);
+ return MEMTX_DECODE_ERROR;
+ }
+}
+
+static const MemoryRegionOps gicv3_its_trans_ops = {
+ .read_with_attrs = gicv3_its_trans_read,
+ .write_with_attrs = gicv3_its_trans_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(s);
+
+ memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
+ "control", ITS_CONTROL_SIZE);
+ memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
+ &gicv3_its_trans_ops, s,
+ "translation", ITS_TRANS_SIZE);
+
+ /* Our two regions are always adjacent, therefore we now combine them
+ * into a single one in order to make our users' life easier.
+ */
+ memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
+ memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
+ memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
+ &s->iomem_its_translation);
+ sysbus_init_mmio(sbd, &s->iomem_main);
+
+ msi_nonbroken = true;
+}
+
+static void gicv3_its_common_reset(DeviceState *dev)
+{
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+
+ s->ctlr = 0;
+ s->cbaser = 0;
+ s->cwriter = 0;
+ s->creadr = 0;
+ memset(&s->baser, 0, sizeof(s->baser));
+
+ gicv3_its_post_load(s, 0);
+}
+
+static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = gicv3_its_common_reset;
+ dc->vmsd = &vmstate_its;
+}
+
+static const TypeInfo gicv3_its_common_info = {
+ .name = TYPE_ARM_GICV3_ITS_COMMON,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(GICv3ITSState),
+ .class_size = sizeof(GICv3ITSCommonClass),
+ .class_init = gicv3_its_common_class_init,
+ .abstract = true,
+};
+
+static void gicv3_its_common_register_types(void)
+{
+ type_register_static(&gicv3_its_common_info);
+}
+
+type_init(gicv3_its_common_register_types)
diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h
new file mode 100644
index 0000000..1ba1894
--- /dev/null
+++ b/include/hw/intc/arm_gicv3_its_common.h
@@ -0,0 +1,78 @@
+/*
+ * ITS support for ARM GICv3
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Written by Pavel Fedin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_ARM_GICV3_ITS_COMMON_H
+#define QEMU_ARM_GICV3_ITS_COMMON_H
+
+#include "hw/sysbus.h"
+#include "hw/intc/arm_gicv3_common.h"
+
+#define ITS_CONTROL_SIZE 0x10000
+#define ITS_TRANS_SIZE 0x10000
+#define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
+
+struct GICv3ITSState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem_main;
+ MemoryRegion iomem_its_cntrl;
+ MemoryRegion iomem_its_translation;
+
+ GICv3State *gicv3;
+
+ int dev_fd; /* kvm device fd if backed by kvm vgic support */
+ uint64_t gits_translater_gpa;
+ bool translater_gpa_known;
+
+ /* Registers */
+ uint32_t ctlr;
+ uint64_t cbaser;
+ uint64_t cwriter;
+ uint64_t creadr;
+ uint64_t baser[8];
+
+ Error *migration_blocker;
+};
+
+typedef struct GICv3ITSState GICv3ITSState;
+
+void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops);
+
+#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
+#define ARM_GICV3_ITS_COMMON(obj) \
+ OBJECT_CHECK(GICv3ITSState, (obj), TYPE_ARM_GICV3_ITS_COMMON)
+#define ARM_GICV3_ITS_COMMON_CLASS(klass) \
+ OBJECT_CLASS_CHECK(GICv3ITSCommonClass, (klass), TYPE_ARM_GICV3_ITS_COMMON)
+#define ARM_GICV3_ITS_COMMON_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(GICv3ITSCommonClass, (obj), TYPE_ARM_GICV3_ITS_COMMON)
+
+struct GICv3ITSCommonClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+ /*< public >*/
+
+ int (*send_msi)(GICv3ITSState *s, uint32_t data, uint16_t devid);
+ void (*pre_save)(GICv3ITSState *s);
+ void (*post_load)(GICv3ITSState *s);
+};
+
+typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
+
+#endif
diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h
index a419368..544e404 100644
--- a/target-arm/kvm_arm.h
+++ b/target-arm/kvm_arm.h
@@ -255,4 +255,23 @@ struct kvm_guest_debug_arch;
void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
+/**
+ * its_class_name
+ *
+ * Return the ITS class name to use depending on whether KVM acceleration
+ * and KVM CAP_SIGNAL_MSI are supported
+ *
+ * Returns: class name to use or NULL
+ */
+static inline const char *its_class_name(void)
+{
+ if (kvm_irqchip_in_kernel()) {
+ /* KVM implementation requires this capability */
+ return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
+ } else {
+ /* Software emulation is not implemented yet */
+ return NULL;
+ }
+}
+
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 17/27] target-arm: move gicv3_class_name from machine to kvm_arm.h
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 16/27] hw/intc/arm_gicv3_its: Implement ITS base class Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 18/27] kvm-all: Pass requester ID to MSI routing functions Peter Maydell
` (11 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Eric Auger <eric.auger@redhat.com>
Machine.c contains code related to migration. Let's move
gicv3_class_name to kvm_arm.h instead.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-4-git-send-email-eric.auger@redhat.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/kvm_arm.h | 16 +++++++++++++++-
target-arm/machine.c | 15 ---------------
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h
index 544e404..633d088 100644
--- a/target-arm/kvm_arm.h
+++ b/target-arm/kvm_arm.h
@@ -13,6 +13,7 @@
#include "sysemu/kvm.h"
#include "exec/memory.h"
+#include "qemu/error-report.h"
/**
* kvm_arm_vcpu_init:
@@ -223,7 +224,20 @@ static inline const char *gic_class_name(void)
*
* Returns: class name to use
*/
-const char *gicv3_class_name(void);
+static inline const char *gicv3_class_name(void)
+{
+ if (kvm_irqchip_in_kernel()) {
+#ifdef TARGET_AARCH64
+ return "kvm-arm-gicv3";
+#else
+ error_report("KVM GICv3 acceleration is not supported on this "
+ "platform");
+ exit(1);
+#endif
+ } else {
+ return "arm-gicv3";
+ }
+}
/**
* kvm_arm_handle_debug:
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 7a6ca31..d90943b 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -331,18 +331,3 @@ const VMStateDescription vmstate_arm_cpu = {
NULL
}
};
-
-const char *gicv3_class_name(void)
-{
- if (kvm_irqchip_in_kernel()) {
-#ifdef TARGET_AARCH64
- return "kvm-arm-gicv3";
-#else
- error_report("KVM GICv3 acceleration is not supported on this "
- "platform");
- exit(1);
-#endif
- } else {
- return "arm-gicv3";
- }
-}
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 18/27] kvm-all: Pass requester ID to MSI routing functions
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 17/27] target-arm: move gicv3_class_name from machine to kvm_arm.h Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 19/27] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation Peter Maydell
` (10 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Pavel Fedin <p.fedin@samsung.com>
Introduce global kvm_msi_use_devid flag plus associated
kvm_msi_devid_required() macro. Passes the device ID,
if needed, while building the MSI route entry. Device IDs are
required by the ARM GICv3 ITS (IRQ remapping function is based on
this information).
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-5-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/sysemu/kvm.h | 9 +++++++++
kvm-all.c | 9 +++++++++
kvm-stub.c | 1 +
3 files changed, 19 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 3e17ba7..df67cc0 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -53,6 +53,7 @@ extern bool kvm_gsi_direct_mapping;
extern bool kvm_readonly_mem_allowed;
extern bool kvm_direct_msi_allowed;
extern bool kvm_ioeventfd_any_length_allowed;
+extern bool kvm_msi_use_devid;
#if defined CONFIG_KVM || !defined NEED_CPU_H
#define kvm_enabled() (kvm_allowed)
@@ -169,6 +170,13 @@ extern bool kvm_ioeventfd_any_length_allowed;
*/
#define kvm_ioeventfd_any_length_enabled() (kvm_ioeventfd_any_length_allowed)
+/**
+ * kvm_msi_devid_required:
+ * Returns: true if KVM requires a device id to be provided while
+ * defining an MSI routing entry.
+ */
+#define kvm_msi_devid_required() (kvm_msi_use_devid)
+
#else
#define kvm_enabled() (0)
#define kvm_irqchip_in_kernel() (false)
@@ -184,6 +192,7 @@ extern bool kvm_ioeventfd_any_length_allowed;
#define kvm_readonly_mem_enabled() (false)
#define kvm_direct_msi_enabled() (false)
#define kvm_ioeventfd_any_length_enabled() (false)
+#define kvm_msi_devid_required() (false)
#endif
struct kvm_run;
diff --git a/kvm-all.c b/kvm-all.c
index fc2898a..efb5fe3 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -119,6 +119,7 @@ bool kvm_readonly_mem_allowed;
bool kvm_vm_attributes_allowed;
bool kvm_direct_msi_allowed;
bool kvm_ioeventfd_any_length_allowed;
+bool kvm_msi_use_devid;
static const KVMCapabilityInfo kvm_required_capabilites[] = {
KVM_CAP_INFO(USER_MEMORY),
@@ -1275,6 +1276,10 @@ int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev)
kroute.u.msi.address_lo = (uint32_t)msg.address;
kroute.u.msi.address_hi = msg.address >> 32;
kroute.u.msi.data = le32_to_cpu(msg.data);
+ if (kvm_msi_devid_required()) {
+ kroute.flags = KVM_MSI_VALID_DEVID;
+ kroute.u.msi.devid = pci_requester_id(dev);
+ }
if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev)) {
kvm_irqchip_release_virq(s, virq);
return -EINVAL;
@@ -1308,6 +1313,10 @@ int kvm_irqchip_update_msi_route(KVMState *s, int virq, MSIMessage msg,
kroute.u.msi.address_lo = (uint32_t)msg.address;
kroute.u.msi.address_hi = msg.address >> 32;
kroute.u.msi.data = le32_to_cpu(msg.data);
+ if (kvm_msi_devid_required()) {
+ kroute.flags = KVM_MSI_VALID_DEVID;
+ kroute.u.msi.devid = pci_requester_id(dev);
+ }
if (kvm_arch_fixup_msi_route(&kroute, msg.address, msg.data, dev)) {
return -EINVAL;
}
diff --git a/kvm-stub.c b/kvm-stub.c
index 3227127..b1b6b96 100644
--- a/kvm-stub.c
+++ b/kvm-stub.c
@@ -31,6 +31,7 @@ bool kvm_gsi_direct_mapping;
bool kvm_allowed;
bool kvm_readonly_mem_allowed;
bool kvm_ioeventfd_any_length_allowed;
+bool kvm_msi_use_devid;
int kvm_destroy_vcpu(CPUState *cpu)
{
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 19/27] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 18/27] kvm-all: Pass requester ID to MSI routing functions Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 20/27] arm/virt: Add ITS to the virt board Peter Maydell
` (9 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Pavel Fedin <p.fedin@samsung.com>
The ITS control frame is in-kernel emulated while accesses to the
GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
direct MSI injection advertised by the CAP_SIGNAL_MSI capability)
the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
difference with GICv2M. Direct mapping cannot work with ITS since
the content of the MSI data is not the target interrupt ID but an
eventd id.
GSI routing is advertised (kvm_gsi_routing_allowed) as well as
msi/irqfd signaling (kvm_msi_via_irqfd_allowed).
The MSI frame (GITS_TRANSLATER) absolute GPA is computed on first
kvm_its_send_msi() call. It is then passed through KVM_SIGNAL_MSI
ioctl.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-6-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/Makefile.objs | 1 +
hw/intc/arm_gicv3_its_kvm.c | 121 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+)
create mode 100644 hw/intc/arm_gicv3_its_kvm.c
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 23a39f7..9cca280 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -22,6 +22,7 @@ common-obj-$(CONFIG_OPENPIC) += openpic.o
obj-$(CONFIG_APIC) += apic.o apic_common.o
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
+obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
obj-$(CONFIG_GRLIB) += grlib_irqmp.o
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
new file mode 100644
index 0000000..fc246e0
--- /dev/null
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -0,0 +1,121 @@
+/*
+ * KVM-based ITS implementation for a GICv3-based system
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Written by Pavel Fedin <p.fedin@samsung.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/intc/arm_gicv3_its_common.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "kvm_arm.h"
+#include "migration/migration.h"
+
+#define TYPE_KVM_ARM_ITS "arm-its-kvm"
+#define KVM_ARM_ITS(obj) OBJECT_CHECK(GICv3ITSState, (obj), TYPE_KVM_ARM_ITS)
+
+static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
+{
+ struct kvm_msi msi;
+
+ if (unlikely(!s->translater_gpa_known)) {
+ MemoryRegion *mr = &s->iomem_its_translation;
+ MemoryRegionSection mrs;
+
+ mrs = memory_region_find(mr, 0, 1);
+ memory_region_unref(mrs.mr);
+ s->gits_translater_gpa = mrs.offset_within_address_space + 0x40;
+ s->translater_gpa_known = true;
+ }
+
+ msi.address_lo = extract64(s->gits_translater_gpa, 0, 32);
+ msi.address_hi = extract64(s->gits_translater_gpa, 32, 32);
+ msi.data = le32_to_cpu(value);
+ msi.flags = KVM_MSI_VALID_DEVID;
+ msi.devid = devid;
+ memset(msi.pad, 0, sizeof(msi.pad));
+
+ return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
+}
+
+static void kvm_arm_its_realize(DeviceState *dev, Error **errp)
+{
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+
+ s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false);
+ if (s->dev_fd < 0) {
+ error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS");
+ return;
+ }
+
+ /* explicit init of the ITS */
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true);
+
+ /* register the base address */
+ kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
+ KVM_VGIC_ITS_ADDR_TYPE, s->dev_fd);
+
+ gicv3_its_init_mmio(s, NULL);
+
+ /*
+ * Block migration of a KVM GICv3 ITS device: the API for saving and
+ * restoring the state in the kernel is not yet available
+ */
+ error_setg(&s->migration_blocker, "vITS migration is not implemented");
+ migrate_add_blocker(s->migration_blocker);
+
+ kvm_msi_use_devid = true;
+ kvm_gsi_direct_mapping = false;
+ kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
+}
+
+static void kvm_arm_its_init(Object *obj)
+{
+ GICv3ITSState *s = KVM_ARM_ITS(obj);
+
+ object_property_add_link(obj, "parent-gicv3",
+ "kvm-arm-gicv3", (Object **)&s->gicv3,
+ object_property_allow_set_link,
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
+ &error_abort);
+}
+
+static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
+
+ dc->realize = kvm_arm_its_realize;
+ icc->send_msi = kvm_its_send_msi;
+}
+
+static const TypeInfo kvm_arm_its_info = {
+ .name = TYPE_KVM_ARM_ITS,
+ .parent = TYPE_ARM_GICV3_ITS_COMMON,
+ .instance_size = sizeof(GICv3ITSState),
+ .instance_init = kvm_arm_its_init,
+ .class_init = kvm_arm_its_class_init,
+};
+
+static void kvm_arm_its_register_types(void)
+{
+ type_register_static(&kvm_arm_its_info);
+}
+
+type_init(kvm_arm_its_register_types)
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 20/27] arm/virt: Add ITS to the virt board
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 19/27] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 21/27] ACPI: Add GIC Interrupt Translation Service Structure definition Peter Maydell
` (8 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Pavel Fedin <p.fedin@samsung.com>
If supported by the configuration, ITS will be added automatically.
This patch also renames v2m_phandle to msi_phandle because it's now used
by both MSI implementations.
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-7-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 47 +++++++++++++++++++++++++++++++++++++++++------
1 file changed, 41 insertions(+), 6 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 2ead58d..0f6305d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -76,7 +76,7 @@ typedef struct VirtBoardInfo {
int fdt_size;
uint32_t clock_phandle;
uint32_t gic_phandle;
- uint32_t v2m_phandle;
+ uint32_t msi_phandle;
bool using_psci;
} VirtBoardInfo;
@@ -423,9 +423,22 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
}
}
+static void fdt_add_its_gic_node(VirtBoardInfo *vbi)
+{
+ vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
+ qemu_fdt_add_subnode(vbi->fdt, "/intc/its");
+ qemu_fdt_setprop_string(vbi->fdt, "/intc/its", "compatible",
+ "arm,gic-v3-its");
+ qemu_fdt_setprop(vbi->fdt, "/intc/its", "msi-controller", NULL, 0);
+ qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/its", "reg",
+ 2, vbi->memmap[VIRT_GIC_ITS].base,
+ 2, vbi->memmap[VIRT_GIC_ITS].size);
+ qemu_fdt_setprop_cell(vbi->fdt, "/intc/its", "phandle", vbi->msi_phandle);
+}
+
static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi)
{
- vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
+ vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m");
qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible",
"arm,gic-v2m-frame");
@@ -433,7 +446,7 @@ static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi)
qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg",
2, vbi->memmap[VIRT_GIC_V2M].base,
2, vbi->memmap[VIRT_GIC_V2M].size);
- qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle);
+ qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->msi_phandle);
}
static void fdt_add_gic_node(VirtBoardInfo *vbi, int type)
@@ -500,6 +513,26 @@ static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype)
}
}
+static void create_its(VirtBoardInfo *vbi, DeviceState *gicdev)
+{
+ const char *itsclass = its_class_name();
+ DeviceState *dev;
+
+ if (!itsclass) {
+ /* Do nothing if not supported */
+ return;
+ }
+
+ dev = qdev_create(NULL, itsclass);
+
+ object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
+ &error_abort);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_ITS].base);
+
+ fdt_add_its_gic_node(vbi);
+}
+
static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic)
{
int i;
@@ -583,7 +616,9 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure)
fdt_add_gic_node(vbi, type);
- if (type == 2) {
+ if (type == 3) {
+ create_its(vbi, gicdev);
+ } else {
create_v2m(vbi, pic);
}
}
@@ -1025,9 +1060,9 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
nr_pcie_buses - 1);
qemu_fdt_setprop(vbi->fdt, nodename, "dma-coherent", NULL, 0);
- if (vbi->v2m_phandle) {
+ if (vbi->msi_phandle) {
qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent",
- vbi->v2m_phandle);
+ vbi->msi_phandle);
}
qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 21/27] ACPI: Add GIC Interrupt Translation Service Structure definition
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 20/27] arm/virt: Add ITS to the virt board Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 22/27] ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table Peter Maydell
` (7 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Shannon Zhao <shannon.zhao@linaro.org>
ACPI Spec 6.0 introduces GIC Interrupt Translation Service Structure.
Here we add the definition of the Structure.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-8-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/acpi/acpi-defs.h | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 41c1d95..9c1b7cb 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -294,7 +294,8 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
#define ACPI_APIC_GENERIC_MSI_FRAME 13
#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
-#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
+#define ACPI_APIC_GENERIC_TRANSLATOR 15
+#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
/*
* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
@@ -395,6 +396,16 @@ struct AcpiMadtGenericRedistributor {
typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor;
+struct AcpiMadtGenericTranslator {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t translation_id;
+ uint64_t base_address;
+ uint32_t reserved2;
+} QEMU_PACKED;
+
+typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
+
/*
* Generic Timer Description Table (GTDT)
*/
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 22/27] ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 21/27] ACPI: Add GIC Interrupt Translation Service Structure definition Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 23/27] generic-loader: Add a generic loader Peter Maydell
` (6 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Shannon Zhao <shannon.zhao@linaro.org>
If GIC ITS is supported, add description in ACPI MADT table, then guest
could use ITS when booting with ACPI.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-9-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt-acpi-build.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 295ec86..7b39b1d 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -44,6 +44,7 @@
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci.h"
#include "sysemu/numa.h"
+#include "kvm_arm.h"
#define ARM_SPI_BASE 32
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
@@ -546,6 +547,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
}
if (guest_info->gic_version == 3) {
+ AcpiMadtGenericTranslator *gic_its;
AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
sizeof *gicr);
@@ -553,6 +555,16 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtGuestInfo *guest_info)
gicr->length = sizeof(*gicr);
gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
+
+ if (!its_class_name()) {
+ return;
+ }
+
+ gic_its = acpi_data_push(table_data, sizeof *gic_its);
+ gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
+ gic_its->length = sizeof(*gic_its);
+ gic_its->translation_id = 0;
+ gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
} else {
gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 23/27] generic-loader: Add a generic loader
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 22/27] ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 24/27] docs: Add a generic loader explanation document Peter Maydell
` (5 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair.francis@xilinx.com>
Add a generic loader to QEMU which can be used to load images or set
memory values.
Internally inside QEMU this is a device. It is a strange device that
provides no hardware interface but allows QEMU to monkey patch memory
specified when it is created. To be able to do this it has a reset
callback that does the memory operations.
This device allows the user to monkey patch memory. To be able to do
this it needs a backend to manage the datas, the same as other
memory-related devices. In this case as the backend is so trivial we
have merged it with the frontend instead of creating and maintaining a
seperate backend.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-id: 10f2a9dce5e5e11b6c6d959415b0ad6ee22bcba5.1475195078.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 6 ++
hw/core/Makefile.objs | 2 +
hw/core/generic-loader.c | 211 +++++++++++++++++++++++++++++++++++++++
include/hw/core/generic-loader.h | 46 +++++++++
4 files changed, 265 insertions(+)
create mode 100644 hw/core/generic-loader.c
create mode 100644 include/hw/core/generic-loader.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 88fd674..76a0fdb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1029,6 +1029,12 @@ M: Dmitry Fleytman <dmitry@daynix.com>
S: Maintained
F: hw/net/e1000e*
+Generic Loader
+M: Alistair Francis <alistair.francis@xilinx.com>
+S: Maintained
+F: hw/core/generic-loader.c
+F: include/hw/core/generic-loader.h
+
Subsystems
----------
Audio
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index b47241b..a4c94e5 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -18,3 +18,5 @@ common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
common-obj-$(CONFIG_SOFTMMU) += register.o
common-obj-$(CONFIG_SOFTMMU) += or-irq.o
common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o
+
+obj-$(CONFIG_SOFTMMU) += generic-loader.o
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
new file mode 100644
index 0000000..79ab6df
--- /dev/null
+++ b/hw/core/generic-loader.c
@@ -0,0 +1,211 @@
+/*
+ * Generic Loader
+ *
+ * Copyright (C) 2014 Li Guang
+ * Copyright (C) 2016 Xilinx Inc.
+ * Written by Li Guang <lig.fnst@cn.fujitsu.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ */
+
+/*
+ * Internally inside QEMU this is a device. It is a strange device that
+ * provides no hardware interface but allows QEMU to monkey patch memory
+ * specified when it is created. To be able to do this it has a reset
+ * callback that does the memory operations.
+
+ * This device allows the user to monkey patch memory. To be able to do
+ * this it needs a backend to manage the datas, the same as other
+ * memory-related devices. In this case as the backend is so trivial we
+ * have merged it with the frontend instead of creating and maintaining a
+ * seperate backend.
+ */
+
+#include "qemu/osdep.h"
+#include "qom/cpu.h"
+#include "hw/sysbus.h"
+#include "sysemu/dma.h"
+#include "hw/loader.h"
+#include "qapi/error.h"
+#include "hw/core/generic-loader.h"
+
+#define CPU_NONE 0xFFFFFFFF
+
+static void generic_loader_reset(void *opaque)
+{
+ GenericLoaderState *s = GENERIC_LOADER(opaque);
+
+ if (s->set_pc) {
+ CPUClass *cc = CPU_GET_CLASS(s->cpu);
+ cpu_reset(s->cpu);
+ if (cc) {
+ cc->set_pc(s->cpu, s->addr);
+ }
+ }
+
+ if (s->data_len) {
+ assert(s->data_len < sizeof(s->data));
+ dma_memory_write(s->cpu->as, s->addr, &s->data, s->data_len);
+ }
+}
+
+static void generic_loader_realize(DeviceState *dev, Error **errp)
+{
+ GenericLoaderState *s = GENERIC_LOADER(dev);
+ hwaddr entry;
+ int big_endian;
+ int size = 0;
+
+ s->set_pc = false;
+
+ /* Perform some error checking on the user's options */
+ if (s->data || s->data_len || s->data_be) {
+ /* User is loading memory values */
+ if (s->file) {
+ error_setg(errp, "Specifying a file is not supported when loading "
+ "memory values");
+ return;
+ } else if (s->force_raw) {
+ error_setg(errp, "Specifying force-raw is not supported when "
+ "loading memory values");
+ return;
+ } else if (!s->data_len) {
+ /* We cant' check for !data here as a value of 0 is still valid. */
+ error_setg(errp, "Both data and data-len must be specified");
+ return;
+ } else if (s->data_len > 8) {
+ error_setg(errp, "data-len cannot be greater then 8 bytes");
+ return;
+ }
+ } else if (s->file || s->force_raw) {
+ /* User is loading an image */
+ if (s->data || s->data_len || s->data_be) {
+ error_setg(errp, "data can not be specified when loading an "
+ "image");
+ return;
+ }
+ s->set_pc = true;
+ } else if (s->addr) {
+ /* User is setting the PC */
+ if (s->data || s->data_len || s->data_be) {
+ error_setg(errp, "data can not be specified when setting a "
+ "program counter");
+ return;
+ } else if (!s->cpu_num) {
+ error_setg(errp, "cpu_num must be specified when setting a "
+ "program counter");
+ return;
+ }
+ s->set_pc = true;
+ } else {
+ /* Did the user specify anything? */
+ error_setg(errp, "please include valid arguments");
+ return;
+ }
+
+ qemu_register_reset(generic_loader_reset, dev);
+
+ if (s->cpu_num != CPU_NONE) {
+ s->cpu = qemu_get_cpu(s->cpu_num);
+ if (!s->cpu) {
+ error_setg(errp, "Specified boot CPU#%d is nonexistent",
+ s->cpu_num);
+ return;
+ }
+ } else {
+ s->cpu = first_cpu;
+ }
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ big_endian = 1;
+#else
+ big_endian = 0;
+#endif
+
+ if (s->file) {
+ if (!s->force_raw) {
+ size = load_elf_as(s->file, NULL, NULL, &entry, NULL, NULL,
+ big_endian, 0, 0, 0, s->cpu->as);
+
+ if (size < 0) {
+ size = load_uimage_as(s->file, &entry, NULL, NULL, NULL, NULL,
+ s->cpu->as);
+ }
+ }
+
+ if (size < 0 || s->force_raw) {
+ /* Default to the maximum size being the machine's ram size */
+ size = load_image_targphys_as(s->file, s->addr, ram_size,
+ s->cpu->as);
+ } else {
+ s->addr = entry;
+ }
+
+ if (size < 0) {
+ error_setg(errp, "Cannot load specified image %s", s->file);
+ return;
+ }
+ }
+
+ /* Convert the data endiannes */
+ if (s->data_be) {
+ s->data = cpu_to_be64(s->data);
+ } else {
+ s->data = cpu_to_le64(s->data);
+ }
+}
+
+static void generic_loader_unrealize(DeviceState *dev, Error **errp)
+{
+ qemu_unregister_reset(generic_loader_reset, dev);
+}
+
+static Property generic_loader_props[] = {
+ DEFINE_PROP_UINT64("addr", GenericLoaderState, addr, 0),
+ DEFINE_PROP_UINT64("data", GenericLoaderState, data, 0),
+ DEFINE_PROP_UINT8("data-len", GenericLoaderState, data_len, 0),
+ DEFINE_PROP_BOOL("data-be", GenericLoaderState, data_be, false),
+ DEFINE_PROP_UINT32("cpu-num", GenericLoaderState, cpu_num, CPU_NONE),
+ DEFINE_PROP_BOOL("force-raw", GenericLoaderState, force_raw, false),
+ DEFINE_PROP_STRING("file", GenericLoaderState, file),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void generic_loader_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ /* The reset function is not registered here and is instead registered in
+ * the realize function to allow this device to be added via the device_add
+ * command in the QEMU monitor.
+ * TODO: Improve the device_add functionality to allow resets to be
+ * connected
+ */
+ dc->realize = generic_loader_realize;
+ dc->unrealize = generic_loader_unrealize;
+ dc->props = generic_loader_props;
+ dc->desc = "Generic Loader";
+}
+
+static TypeInfo generic_loader_info = {
+ .name = TYPE_GENERIC_LOADER,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(GenericLoaderState),
+ .class_init = generic_loader_class_init,
+};
+
+static void generic_loader_register_type(void)
+{
+ type_register_static(&generic_loader_info);
+}
+
+type_init(generic_loader_register_type)
diff --git a/include/hw/core/generic-loader.h b/include/hw/core/generic-loader.h
new file mode 100644
index 0000000..dd27c42
--- /dev/null
+++ b/include/hw/core/generic-loader.h
@@ -0,0 +1,46 @@
+/*
+ * Generic Loader
+ *
+ * Copyright (C) 2014 Li Guang
+ * Written by Li Guang <lig.fnst@cn.fujitsu.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef GENERIC_LOADER_H
+#define GENERIC_LOADER_H
+
+#include "elf.h"
+
+typedef struct GenericLoaderState {
+ /* <private> */
+ DeviceState parent_obj;
+
+ /* <public> */
+ CPUState *cpu;
+
+ uint64_t addr;
+ uint64_t data;
+ uint8_t data_len;
+ uint32_t cpu_num;
+
+ char *file;
+
+ bool force_raw;
+ bool data_be;
+ bool set_pc;
+} GenericLoaderState;
+
+#define TYPE_GENERIC_LOADER "loader"
+#define GENERIC_LOADER(obj) OBJECT_CHECK(GenericLoaderState, (obj), \
+ TYPE_GENERIC_LOADER)
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 24/27] docs: Add a generic loader explanation document
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 23/27] generic-loader: Add a generic loader Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 25/27] cadence_gem: Fix priority queue out of bounds access Peter Maydell
` (4 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 9d991a2df990cf55e2630410a5a03ea48930af5d.1475195078.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/generic-loader.txt | 84 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 docs/generic-loader.txt
diff --git a/docs/generic-loader.txt b/docs/generic-loader.txt
new file mode 100644
index 0000000..8fcb550
--- /dev/null
+++ b/docs/generic-loader.txt
@@ -0,0 +1,84 @@
+Copyright (c) 2016 Xilinx Inc.
+
+This work is licensed under the terms of the GNU GPL, version 2 or later. See
+the COPYING file in the top-level directory.
+
+
+The 'loader' device allows the user to load multiple images or values into
+QEMU at startup.
+
+Loading Data into Memory Values
+---------------------
+The loader device allows memory values to be set from the command line. This
+can be done by following the syntax below:
+
+ -device loader,addr=<addr>,data=<data>,data-len=<data-len>
+ [,data-be=<data-be>][,cpu-num=<cpu-num>]
+
+ <addr> - The address to store the data in.
+ <data> - The value to be written to the address. The maximum size of
+ the data is 8 bytes.
+ <data-len> - The length of the data in bytes. This argument must be
+ included if the data argument is.
+ <data-be> - Set to true if the data to be stored on the guest should be
+ written as big endian data. The default is to write little
+ endian data.
+ <cpu-num> - The number of the CPU's address space where the data should
+ be loaded. If not specified the address space of the first
+ CPU is used.
+
+All values are parsed using the standard QemuOps parsing. This allows the user
+to specify any values in any format supported. By default the values
+will be parsed as decimal. To use hex values the user should prefix the number
+with a '0x'.
+
+An example of loading value 0x8000000e to address 0xfd1a0104 is:
+ -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4
+
+Setting a CPU's Program Counter
+---------------------
+The loader device allows the CPU's PC to be set from the command line. This
+can be done by following the syntax below:
+
+ -device loader,addr=<addr>,cpu-num=<cpu-num>
+
+ <addr> - The value to use as the CPU's PC.
+ <cpu-num> - The number of the CPU whose PC should be set to the
+ specified value.
+
+All values are parsed using the standard QemuOps parsing. This allows the user
+to specify any values in any format supported. By default the values
+will be parsed as decimal. To use hex values the user should prefix the number
+with a '0x'.
+
+An example of setting CPU 0's PC to 0x8000 is:
+ -device loader,addr=0x8000,cpu-num=0
+
+Loading Files
+---------------------
+The loader device also allows files to be loaded into memory. This can be done
+similarly to setting memory values. The syntax is shown below:
+
+ -device loader,file=<file>[,addr=<addr>][,cpu-num=<cpu-num>][,force-raw=<raw>]
+
+ <file> - A file to be loaded into memory
+ <addr> - The addr in memory that the file should be loaded. This is
+ ignored if you are using an ELF (unless force-raw is true).
+ This is required if you aren't loading an ELF.
+ <cpu-num> - This specifies the CPU that should be used. This is an
+ optional argument and will cause the CPU's PC to be set to
+ where the image is stored or in the case of an ELF file to
+ the value in the header. This option should only be used
+ for the boot image.
+ This will also cause the image to be written to the specified
+ CPU's address space. If not specified, the default is CPU 0.
+ <force-raw> - Forces the file to be treated as a raw image. This can be
+ used to specify the load address of ELF files.
+
+All values are parsed using the standard QemuOps parsing. This allows the user
+to specify any values in any format supported. By default the values
+will be parsed as decimal. To use hex values the user should prefix the number
+with a '0x'.
+
+An example of loading an ELF file which CPU0 will boot is shown below:
+ -device loader,file=./images/boot.elf,cpu-num=0
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 25/27] cadence_gem: Fix priority queue out of bounds access
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 24/27] docs: Add a generic loader explanation document Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 26/27] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit Peter Maydell
` (3 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: Alistair Francis <alistair.francis@xilinx.com>
There was an error with some of the register implementation assuming
there are 16 priority queues supported when the IP only supports 8. This
patch corrects the registers to only support 8 queues.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 33bf2d28326d22875602234b8b15cf56fb678333.1474911607.git.alistair.francis@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/cadence_gem.c | 22 ++++------------------
1 file changed, 4 insertions(+), 18 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 8618e7a..7915732 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -147,25 +147,19 @@
#define GEM_INT_Q1_MASK (0x00000640 / 4)
#define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
-#define GEM_TRANSMIT_Q15_PTR (GEM_TRANSMIT_Q1_PTR + 14)
+#define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
-#define GEM_RECEIVE_Q15_PTR (GEM_RECEIVE_Q1_PTR + 14)
+#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
-#define GEM_INT_Q8_ENABLE (0x00000660 / 4)
-#define GEM_INT_Q15_ENABLE (GEM_INT_Q8_ENABLE + 7)
#define GEM_INT_Q1_DISABLE (0x00000620 / 4)
#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
-#define GEM_INT_Q8_DISABLE (0x00000680 / 4)
-#define GEM_INT_Q15_DISABLE (GEM_INT_Q8_DISABLE + 7)
#define GEM_INT_Q1_MASK (0x00000640 / 4)
#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
-#define GEM_INT_Q8_MASK (0x000006A0 / 4)
-#define GEM_INT_Q15_MASK (GEM_INT_Q8_MASK + 7)
#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
@@ -1372,13 +1366,13 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
case GEM_RXQBASE:
s->rx_desc_addr[0] = val;
break;
- case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q15_PTR:
+ case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
break;
case GEM_TXQBASE:
s->tx_desc_addr[0] = val;
break;
- case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q15_PTR:
+ case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
break;
case GEM_RXSTATUS:
@@ -1392,10 +1386,6 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
gem_update_int_status(s);
break;
- case GEM_INT_Q8_ENABLE ... GEM_INT_Q15_ENABLE:
- s->regs[GEM_INT_Q8_MASK + offset - GEM_INT_Q8_ENABLE] &= ~val;
- gem_update_int_status(s);
- break;
case GEM_IDR:
s->regs[GEM_IMR] |= val;
gem_update_int_status(s);
@@ -1404,10 +1394,6 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
gem_update_int_status(s);
break;
- case GEM_INT_Q8_DISABLE ... GEM_INT_Q15_DISABLE:
- s->regs[GEM_INT_Q8_MASK + offset - GEM_INT_Q8_DISABLE] |= val;
- gem_update_int_status(s);
- break;
case GEM_SPADDR1LO:
case GEM_SPADDR2LO:
case GEM_SPADDR3LO:
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 26/27] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 25/27] cadence_gem: Fix priority queue out of bounds access Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 Peter Maydell
` (2 subsequent siblings)
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Fix the decoding of iss_sf in disas_ld_lit.
The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
is a bit that specifies the width of the register that the
instruction loads to.
If cleared it specifies 32 bits.
If set it specifies 64 bits.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com
[PMM: tweaked phrasing per on-list discussion]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ddf52f5..307e281 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
do_fp_ld(s, rt, tcg_addr, size);
} else {
/* Only unsigned 32bit loads target 32bit registers. */
- bool iss_sf = opc == 0 ? 32 : 64;
+ bool iss_sf = opc != 0;
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,
true, rt, iss_sf, false);
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 26/27] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit Peter Maydell
@ 2016-10-04 12:42 ` Peter Maydell
2016-10-14 6:44 ` Alex Bennée
2016-10-04 13:19 ` [Qemu-devel] [PULL 00/27] target-arm queue no-reply
2016-10-04 13:24 ` Peter Maydell
28 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 12:42 UTC (permalink / raw)
To: qemu-devel
In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking
branch, so the computed new value is written to r15 as a normal
value. The architecture says that in this case, bits [1:0] of
the value written must be ignored if we are in ARM mode (or
bit [0] ignored if in Thumb mode); this is a change from the
ARMv4/v5 specification that behaviour is UNPREDICTABLE.
Use the correct mask on the PC value when doing a non-interworking
store to PC.
A popular library used on RaspberryPi uses this instruction
as part of a trick to determine whether it is running on
ARMv6 or ARMv7, and we were mishandling the sequence.
Fixes bug: https://bugs.launchpad.net/bugs/1625295
Reported-by: <stu.axon@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474380941-4730-1-git-send-email-peter.maydell@linaro.org
---
target-arm/translate.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 693d4bc..8df24bf 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -180,7 +180,12 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
{
if (reg == 15) {
- tcg_gen_andi_i32(var, var, ~1);
+ /* In Thumb mode, we must ignore bit 0.
+ * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0]
+ * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0].
+ * We choose to ignore [1:0] in ARM mode for all architecture versions.
+ */
+ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);
s->is_jmp = DISAS_JUMP;
}
tcg_gen_mov_i32(cpu_R[reg], var);
--
2.7.4
^ permalink raw reply related [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2016-10-04 12:42 ` [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 Peter Maydell
@ 2016-10-04 13:19 ` no-reply
2016-10-04 13:24 ` Peter Maydell
28 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2016-10-04 13:19 UTC (permalink / raw)
To: peter.maydell; +Cc: famz, qemu-devel
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1475584975-25099-1-git-send-email-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1475584975-25099-1-git-send-email-peter.maydell@linaro.org -> patchew/1475584975-25099-1-git-send-email-peter.maydell@linaro.org
- [tag update] patchew/20160930161013.9832-1-rkrcmar@redhat.com -> patchew/20160930161013.9832-1-rkrcmar@redhat.com
Switched to a new branch 'test'
de37b98 target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
4dd068d target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
97e3be7 cadence_gem: Fix priority queue out of bounds access
f4e8f92 docs: Add a generic loader explanation document
c2660d7 generic-loader: Add a generic loader
63a3f35 ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
6f1d2f4 ACPI: Add GIC Interrupt Translation Service Structure definition
68dea69 arm/virt: Add ITS to the virt board
4030908 hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
2d52823 kvm-all: Pass requester ID to MSI routing functions
2ec8320 target-arm: move gicv3_class_name from machine to kvm_arm.h
0525eb4 hw/intc/arm_gicv3_its: Implement ITS base class
bfc5ce8 hw/intc/arm_gic(v3)_kvm: Initialize gsi routing
949e404 hw/arm/virt: add 2.8 machine type
64d15c7 vmstateify tsc210x
935a655 vmstateify tsc2005
8d069b9 hw/arm: Fix Integrator/CM initialization
c2aa9be mainstone: Add mapping for dot, slash and backspace.
d924114 mainstone: Fix incorrect key mapping for Enter key.
ffdc92f MAINTAINERS: Add Alistair to the maintainers list
70b0fee STM32F205: Connect the SPI devices
0d1eee4 STM32F205: Connect the ADC devices
15cbf04 irq: Add a new irq device that allows the ORing of lines
d780156 STM32F2xx: Add the SPI device
19a0f11 STM32F2xx: Add the ADC device
5b4ba91 STM32F2xx: Display PWM duty cycle from timer
f7881a5 STM32F205: Remove the individual device variables
=== OUTPUT BEGIN ===
Checking PATCH 1/27: STM32F205: Remove the individual device variables...
Checking PATCH 2/27: STM32F2xx: Display PWM duty cycle from timer...
Checking PATCH 3/27: STM32F2xx: Add the ADC device...
Checking PATCH 4/27: STM32F2xx: Add the SPI device...
Checking PATCH 5/27: irq: Add a new irq device that allows the ORing of lines...
Checking PATCH 6/27: STM32F205: Connect the ADC devices...
Checking PATCH 7/27: STM32F205: Connect the SPI devices...
Checking PATCH 8/27: MAINTAINERS: Add Alistair to the maintainers list...
Checking PATCH 9/27: mainstone: Fix incorrect key mapping for Enter key....
ERROR: space required after that ',' (ctx:VxV)
#25: FILE: hw/arm/mainstone.c:91:
+ [0x1c] = {5,4}, /* enter */
^
total: 1 errors, 0 warnings, 8 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 10/27: mainstone: Add mapping for dot, slash and backspace....
ERROR: space required after that ',' (ctx:VxV)
#23: FILE: hw/arm/mainstone.c:76:
+ [0x34] = {4,0}, /* . */
^
ERROR: space required after that ',' (ctx:VxV)
#26: FILE: hw/arm/mainstone.c:79:
+ [0x35] = {4,4}, /* / */
^
ERROR: space required after that ',' (ctx:VxV)
#34: FILE: hw/arm/mainstone.c:94:
+ [0x0e] = {5,5}, /* backspace */
^
total: 3 errors, 0 warnings, 17 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 11/27: hw/arm: Fix Integrator/CM initialization...
Checking PATCH 12/27: vmstateify tsc2005...
Checking PATCH 13/27: vmstateify tsc210x...
Checking PATCH 14/27: hw/arm/virt: add 2.8 machine type...
Checking PATCH 15/27: hw/intc/arm_gic(v3)_kvm: Initialize gsi routing...
Checking PATCH 16/27: hw/intc/arm_gicv3_its: Implement ITS base class...
Checking PATCH 17/27: target-arm: move gicv3_class_name from machine to kvm_arm.h...
Checking PATCH 18/27: kvm-all: Pass requester ID to MSI routing functions...
Checking PATCH 19/27: hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation...
Checking PATCH 20/27: arm/virt: Add ITS to the virt board...
Checking PATCH 21/27: ACPI: Add GIC Interrupt Translation Service Structure definition...
Checking PATCH 22/27: ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table...
Checking PATCH 23/27: generic-loader: Add a generic loader...
Checking PATCH 24/27: docs: Add a generic loader explanation document...
Checking PATCH 25/27: cadence_gem: Fix priority queue out of bounds access...
Checking PATCH 26/27: target-arm: A64: Fix decoding of iss_sf in disas_ld_lit...
Checking PATCH 27/27: target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
` (27 preceding siblings ...)
2016-10-04 13:19 ` [Qemu-devel] [PULL 00/27] target-arm queue no-reply
@ 2016-10-04 13:24 ` Peter Maydell
28 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-04 13:24 UTC (permalink / raw)
To: QEMU Developers
On 4 October 2016 at 13:42, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM patch queue, notably including the Netduino 2 updates
> and support for in-kernel ITS with GICv3.
>
> -- PMM
>
> The following changes since commit 1bb47107057c645945971cf4e13eb8b524915b71:
>
> Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2016-10-04 11:28:30 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161004
>
> for you to fetch changes up to 9b6a3ea7a699594162ed3d11e4e04b98568dc5c0:
>
> target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 (2016-10-04 13:28:10 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Netduino 2 improvements (SPI, ADC devices)
> * fix some Mainstone key mappings
> * vmstateify tsc210x, tsc2005
> * virt: add 2.8 machine type
> * virt: support in-kernel GICv3 ITS
> * generic-loader device
> * A64: fix iss_sf decoding in disas_ld_lit
> * correctly handle 'sub pc, pc, 1' for ARMv6
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
2016-10-04 12:42 ` [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 Peter Maydell
@ 2016-10-14 6:44 ` Alex Bennée
2016-10-14 17:35 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Alex Bennée @ 2016-10-14 6:44 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Peter Maydell <peter.maydell@linaro.org> writes:
> In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking
> branch, so the computed new value is written to r15 as a normal
> value. The architecture says that in this case, bits [1:0] of
> the value written must be ignored if we are in ARM mode (or
> bit [0] ignored if in Thumb mode); this is a change from the
> ARMv4/v5 specification that behaviour is UNPREDICTABLE.
> Use the correct mask on the PC value when doing a non-interworking
> store to PC.
>
> A popular library used on RaspberryPi uses this instruction
> as part of a trick to determine whether it is running on
> ARMv6 or ARMv7, and we were mishandling the sequence.
>
> Fixes bug: https://bugs.launchpad.net/bugs/1625295
>
> Reported-by: <stu.axon@gmail.com>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> Message-id: 1474380941-4730-1-git-send-email-peter.maydell@linaro.org
I'm not sure how but this seems to have regressed my ARMv7 test images
(currently Linux 4.7.7). With this change I see the guest spinning in
the vectors table. If I comment out the change it boots.
I'll dig some more but as this affects store_reg are there any cases
when writing to the PC with offset bits would be correct?
> ---
> target-arm/translate.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 693d4bc..8df24bf 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -180,7 +180,12 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
> static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
> {
> if (reg == 15) {
> - tcg_gen_andi_i32(var, var, ~1);
> + /* In Thumb mode, we must ignore bit 0.
> + * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0]
> + * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0].
> + * We choose to ignore [1:0] in ARM mode for all architecture versions.
> + */
> + tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);
> s->is_jmp = DISAS_JUMP;
> }
> tcg_gen_mov_i32(cpu_R[reg], var);
--
Alex Bennée
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
2016-10-14 6:44 ` Alex Bennée
@ 2016-10-14 17:35 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2016-10-14 17:35 UTC (permalink / raw)
To: Alex Bennée; +Cc: QEMU Developers
On 14 October 2016 at 07:44, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
>> In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking
>> branch, so the computed new value is written to r15 as a normal
>> value. The architecture says that in this case, bits [1:0] of
>> the value written must be ignored if we are in ARM mode (or
>> bit [0] ignored if in Thumb mode); this is a change from the
>> ARMv4/v5 specification that behaviour is UNPREDICTABLE.
>> Use the correct mask on the PC value when doing a non-interworking
>> store to PC.
>>
>> A popular library used on RaspberryPi uses this instruction
>> as part of a trick to determine whether it is running on
>> ARMv6 or ARMv7, and we were mishandling the sequence.
>>
>> Fixes bug: https://bugs.launchpad.net/bugs/1625295
>>
>> Reported-by: <stu.axon@gmail.com>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> Message-id: 1474380941-4730-1-git-send-email-peter.maydell@linaro.org
>
> I'm not sure how but this seems to have regressed my ARMv7 test images
> (currently Linux 4.7.7). With this change I see the guest spinning in
> the vectors table. If I comment out the change it boots.
>
> I'll dig some more but as this affects store_reg are there any cases
> when writing to the PC with offset bits would be correct?
Look for the patch I sent earlier that fixes a regression
in returning from exceptions to thumb addresses that are
only 2 aligned. That will probably fix it.
thanks
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (20 preceding siblings ...)
2019-02-15 2:24 ` no-reply
@ 2019-02-15 2:43 ` no-reply
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 2:43 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
79f823dd50 gdbstub: Send a reply to the vKill packet.
54055c690e target/arm: Add missing clear_tail calls
256e4557f2 target/arm: Use vector operations for saturation
dac47f6b64 target/arm: Split out FPSCR.QC to a vector field
dffbd3cd1b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
003ad968a8 target/arm: Split out flags setting from vfp compares
8e2cdb45d1 target/arm: Fix arm_cpu_dump_state vs FPSCR
c6859c1a84 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
6a0a150b2d target/arm: Remove neon min/max helpers
ced3d5e3d9 target/arm: Use tcg integer min/max primitives for neon
0f1a572c84 target/arm: Use vector minmax expanders for aarch32
66e0205bc3 target/arm: Use vector minmax expanders for aarch64
2ce0e8773f target/arm: Rely on optimization within tcg_gen_gvec_or
6bd399ef3d hw/arm/armsse: Fix miswiring of expansion IRQs
ee3a0f2e15 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
f2bd89cfd3 MAINTAINERS: Remove Peter Crosthwaite from various entries
0d2f803513 arm: Allow system registers for KVM guests to be changed by QEMU code
8d7c1af9f3 linux-user/elfload: enable HWCAP_CPUID for AArch64
87d553b62c target/arm: expose remaining CPUID registers as RAZ
2296abadfb target/arm: expose MPIDR_EL1 to userspace
682347fb9e target/arm: expose CPUID registers to userspace
61e1e876ae target/arm: relax permission checks for HWCAP_CPUID registers
a03d01166b target/arm: Restructure disas_fp_int_conv
49c75fb14d target/arm: Force result size into dp after operation
b311548ce5 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
6d9154655f target/arm: Implement HACR_EL2
b6a2f6e7d0 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit b6a2f6e7d009 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 6d9154655f8f (target/arm: Implement HACR_EL2)
3/27 Checking commit b311548ce515 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 49c75fb14d08 (target/arm: Force result size into dp after operation)
5/27 Checking commit a03d01166b02 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 61e1e876ae47 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 682347fb9e39 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 2296abadfb9a (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 87d553b62c30 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 8d7c1af9f3f9 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 0d2f8035130d (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit f2bd89cfd3fb (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit ee3a0f2e1566 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 6bd399ef3d57 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 2ce0e8773f22 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 66e0205bc37e (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 0f1a572c8401 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit ced3d5e3d9eb (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 6a0a150b2da5 (target/arm: Remove neon min/max helpers)
20/27 Checking commit c6859c1a849d (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 8e2cdb45d186 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 003ad968a808 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit dffbd3cd1b4d (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit dac47f6b645f (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 256e4557f2e8 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 54055c690e1f (target/arm: Add missing clear_tail calls)
27/27 Checking commit 79f823dd5021 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (19 preceding siblings ...)
2019-02-15 2:19 ` no-reply
@ 2019-02-15 2:24 ` no-reply
2019-02-15 2:43 ` no-reply
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 2:24 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
6035ee1d0b gdbstub: Send a reply to the vKill packet.
6abc10e3cf target/arm: Add missing clear_tail calls
3b446a483a target/arm: Use vector operations for saturation
5ae122d95f target/arm: Split out FPSCR.QC to a vector field
dcf4734824 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
93f672cd3e target/arm: Split out flags setting from vfp compares
a4923fb2a2 target/arm: Fix arm_cpu_dump_state vs FPSCR
59b60a009c target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
2d72031bc3 target/arm: Remove neon min/max helpers
0dc3071aa6 target/arm: Use tcg integer min/max primitives for neon
12249be0d4 target/arm: Use vector minmax expanders for aarch32
210b86c4d0 target/arm: Use vector minmax expanders for aarch64
ec442a042e target/arm: Rely on optimization within tcg_gen_gvec_or
ec303c3244 hw/arm/armsse: Fix miswiring of expansion IRQs
8a6530ed11 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
375c511d5e MAINTAINERS: Remove Peter Crosthwaite from various entries
2a062aa5d8 arm: Allow system registers for KVM guests to be changed by QEMU code
fde061cf2a linux-user/elfload: enable HWCAP_CPUID for AArch64
345f47dc8b target/arm: expose remaining CPUID registers as RAZ
b96e5b9001 target/arm: expose MPIDR_EL1 to userspace
06c582053e target/arm: expose CPUID registers to userspace
8aeda9f436 target/arm: relax permission checks for HWCAP_CPUID registers
e3ceeef98a target/arm: Restructure disas_fp_int_conv
49958fb0df target/arm: Force result size into dp after operation
fc1287b91f target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
fa29b1076a target/arm: Implement HACR_EL2
95fcc314e3 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 95fcc314e34d (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit fa29b1076a08 (target/arm: Implement HACR_EL2)
3/27 Checking commit fc1287b91f25 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 49958fb0df5d (target/arm: Force result size into dp after operation)
5/27 Checking commit e3ceeef98ab2 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 8aeda9f436db (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 06c582053ec6 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit b96e5b900130 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 345f47dc8bac (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit fde061cf2ae3 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 2a062aa5d85a (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 375c511d5ef0 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 8a6530ed11d6 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit ec303c324426 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit ec442a042e1b (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 210b86c4d0a5 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 12249be0d48f (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 0dc3071aa652 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 2d72031bc357 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 59b60a009c37 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit a4923fb2a25e (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 93f672cd3e36 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit dcf4734824cb (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 5ae122d95fb6 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 3b446a483a40 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 6abc10e3cfa5 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 6035ee1d0be8 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (18 preceding siblings ...)
2019-02-15 2:15 ` no-reply
@ 2019-02-15 2:19 ` no-reply
2019-02-15 2:24 ` no-reply
2019-02-15 2:43 ` no-reply
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 2:19 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
1e820f4 gdbstub: Send a reply to the vKill packet.
4b56c88 target/arm: Add missing clear_tail calls
e143845 target/arm: Use vector operations for saturation
a14a04e target/arm: Split out FPSCR.QC to a vector field
b9fc85b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
29d6aa1 target/arm: Split out flags setting from vfp compares
13dc2aa target/arm: Fix arm_cpu_dump_state vs FPSCR
bc2c229 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
e53cd7d target/arm: Remove neon min/max helpers
bf7d4d0 target/arm: Use tcg integer min/max primitives for neon
c592edc target/arm: Use vector minmax expanders for aarch32
cb8987e target/arm: Use vector minmax expanders for aarch64
f6edfc4 target/arm: Rely on optimization within tcg_gen_gvec_or
45a5069 hw/arm/armsse: Fix miswiring of expansion IRQs
eabbdbb hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
8f90489 MAINTAINERS: Remove Peter Crosthwaite from various entries
43cd666 arm: Allow system registers for KVM guests to be changed by QEMU code
14ff7ec linux-user/elfload: enable HWCAP_CPUID for AArch64
a3ad95f target/arm: expose remaining CPUID registers as RAZ
a72a7f2 target/arm: expose MPIDR_EL1 to userspace
5cff337 target/arm: expose CPUID registers to userspace
56a00d6 target/arm: relax permission checks for HWCAP_CPUID registers
4d6cbb2 target/arm: Restructure disas_fp_int_conv
3a6c815 target/arm: Force result size into dp after operation
58d010b target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
07c4523 target/arm: Implement HACR_EL2
4c11ba7 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 4c11ba7a474f (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 07c45234c380 (target/arm: Implement HACR_EL2)
3/27 Checking commit 58d010bbd1a4 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 3a6c8150ed4a (target/arm: Force result size into dp after operation)
5/27 Checking commit 4d6cbb28c5ba (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 56a00d6429b0 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 5cff3370be15 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit a72a7f23daec (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit a3ad95ffd508 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 14ff7ecc19f0 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 43cd666a9ee0 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 8f9048912404 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit eabbdbb6db70 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 45a5069fad23 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit f6edfc43420c (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit cb8987e56aae (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit c592edc6dd12 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit bf7d4d099b2c (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit e53cd7d0b768 (target/arm: Remove neon min/max helpers)
20/27 Checking commit bc2c229b10ce (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 13dc2aabab5f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 29d6aa1c6b90 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit b9fc85bc9f7a (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit a14a04e6bde9 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit e1438456d444 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 4b56c889a3e1 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 1e820f425d28 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (17 preceding siblings ...)
2019-02-15 1:56 ` no-reply
@ 2019-02-15 2:15 ` no-reply
2019-02-15 2:19 ` no-reply
` (2 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 2:15 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
1e820f425d gdbstub: Send a reply to the vKill packet.
4b56c889a3 target/arm: Add missing clear_tail calls
e1438456d4 target/arm: Use vector operations for saturation
a14a04e6bd target/arm: Split out FPSCR.QC to a vector field
b9fc85bc9f target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
29d6aa1c6b target/arm: Split out flags setting from vfp compares
13dc2aabab target/arm: Fix arm_cpu_dump_state vs FPSCR
bc2c229b10 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
e53cd7d0b7 target/arm: Remove neon min/max helpers
bf7d4d099b target/arm: Use tcg integer min/max primitives for neon
c592edc6dd target/arm: Use vector minmax expanders for aarch32
cb8987e56a target/arm: Use vector minmax expanders for aarch64
f6edfc4342 target/arm: Rely on optimization within tcg_gen_gvec_or
45a5069fad hw/arm/armsse: Fix miswiring of expansion IRQs
eabbdbb6db hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
8f90489124 MAINTAINERS: Remove Peter Crosthwaite from various entries
43cd666a9e arm: Allow system registers for KVM guests to be changed by QEMU code
14ff7ecc19 linux-user/elfload: enable HWCAP_CPUID for AArch64
a3ad95ffd5 target/arm: expose remaining CPUID registers as RAZ
a72a7f23da target/arm: expose MPIDR_EL1 to userspace
5cff3370be target/arm: expose CPUID registers to userspace
56a00d6429 target/arm: relax permission checks for HWCAP_CPUID registers
4d6cbb28c5 target/arm: Restructure disas_fp_int_conv
3a6c8150ed target/arm: Force result size into dp after operation
58d010bbd1 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
07c45234c3 target/arm: Implement HACR_EL2
4c11ba7a47 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 4c11ba7a474f (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 07c45234c380 (target/arm: Implement HACR_EL2)
3/27 Checking commit 58d010bbd1a4 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 3a6c8150ed4a (target/arm: Force result size into dp after operation)
5/27 Checking commit 4d6cbb28c5ba (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 56a00d6429b0 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 5cff3370be15 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit a72a7f23daec (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit a3ad95ffd508 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 14ff7ecc19f0 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 43cd666a9ee0 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 8f9048912404 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit eabbdbb6db70 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 45a5069fad23 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit f6edfc43420c (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit cb8987e56aae (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit c592edc6dd12 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit bf7d4d099b2c (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit e53cd7d0b768 (target/arm: Remove neon min/max helpers)
20/27 Checking commit bc2c229b10ce (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 13dc2aabab5f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 29d6aa1c6b90 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit b9fc85bc9f7a (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit a14a04e6bde9 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit e1438456d444 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 4b56c889a3e1 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 1e820f425d28 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (16 preceding siblings ...)
2019-02-15 1:48 ` no-reply
@ 2019-02-15 1:56 ` no-reply
2019-02-15 2:15 ` no-reply
` (3 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:56 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
11ea4f3150 gdbstub: Send a reply to the vKill packet.
be0c840de4 target/arm: Add missing clear_tail calls
23ca71bf65 target/arm: Use vector operations for saturation
32960e7603 target/arm: Split out FPSCR.QC to a vector field
1145bf059b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
754737362f target/arm: Split out flags setting from vfp compares
9eae8889db target/arm: Fix arm_cpu_dump_state vs FPSCR
0ce5d35ee2 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
02666e516f target/arm: Remove neon min/max helpers
4d27e98f16 target/arm: Use tcg integer min/max primitives for neon
8e31e0c833 target/arm: Use vector minmax expanders for aarch32
be6d1d7c04 target/arm: Use vector minmax expanders for aarch64
9c42a28eca target/arm: Rely on optimization within tcg_gen_gvec_or
df0e032414 hw/arm/armsse: Fix miswiring of expansion IRQs
84a7951b4a hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
514aa8eda1 MAINTAINERS: Remove Peter Crosthwaite from various entries
b9286febf7 arm: Allow system registers for KVM guests to be changed by QEMU code
7f9135d2ce linux-user/elfload: enable HWCAP_CPUID for AArch64
9fd22cfa69 target/arm: expose remaining CPUID registers as RAZ
9c0d85264b target/arm: expose MPIDR_EL1 to userspace
fb5effe844 target/arm: expose CPUID registers to userspace
ebebfe1ea5 target/arm: relax permission checks for HWCAP_CPUID registers
6ba2008b2f target/arm: Restructure disas_fp_int_conv
dfa0134d29 target/arm: Force result size into dp after operation
035fc662c1 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
bd1643769b target/arm: Implement HACR_EL2
5d9278ba69 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 5d9278ba6904 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit bd1643769bf4 (target/arm: Implement HACR_EL2)
3/27 Checking commit 035fc662c10f (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit dfa0134d2938 (target/arm: Force result size into dp after operation)
5/27 Checking commit 6ba2008b2f9f (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit ebebfe1ea53d (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit fb5effe8444a (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 9c0d85264bd2 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 9fd22cfa696b (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 7f9135d2ce3c (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit b9286febf73f (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 514aa8eda196 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 84a7951b4a75 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit df0e032414fb (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 9c42a28eca48 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit be6d1d7c044b (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 8e31e0c83344 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 4d27e98f164d (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 02666e516fbe (target/arm: Remove neon min/max helpers)
20/27 Checking commit 0ce5d35ee28b (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 9eae8889dbe3 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 754737362f1b (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 1145bf059b88 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 32960e760343 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 23ca71bf6538 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit be0c840de44a (target/arm: Add missing clear_tail calls)
27/27 Checking commit 11ea4f315038 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (15 preceding siblings ...)
2019-02-15 1:32 ` no-reply
@ 2019-02-15 1:48 ` no-reply
2019-02-15 1:56 ` no-reply
` (4 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:48 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
73ac529141 gdbstub: Send a reply to the vKill packet.
4b247465c1 target/arm: Add missing clear_tail calls
89be70063e target/arm: Use vector operations for saturation
e77ac93de2 target/arm: Split out FPSCR.QC to a vector field
c22864f292 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
ff918185bd target/arm: Split out flags setting from vfp compares
11f919937a target/arm: Fix arm_cpu_dump_state vs FPSCR
dd99a43005 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
e004fed65e target/arm: Remove neon min/max helpers
8f4545ca63 target/arm: Use tcg integer min/max primitives for neon
ab9ebe5a3d target/arm: Use vector minmax expanders for aarch32
72d6045bf1 target/arm: Use vector minmax expanders for aarch64
a7e7d40b7b target/arm: Rely on optimization within tcg_gen_gvec_or
990b62b71d hw/arm/armsse: Fix miswiring of expansion IRQs
ea4ce7fac8 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
40282cba68 MAINTAINERS: Remove Peter Crosthwaite from various entries
530553605c arm: Allow system registers for KVM guests to be changed by QEMU code
cf4f6b485e linux-user/elfload: enable HWCAP_CPUID for AArch64
c38db4cedc target/arm: expose remaining CPUID registers as RAZ
bc98ce37e8 target/arm: expose MPIDR_EL1 to userspace
5b3cbe3a2c target/arm: expose CPUID registers to userspace
3cbbe863dd target/arm: relax permission checks for HWCAP_CPUID registers
9054387819 target/arm: Restructure disas_fp_int_conv
72c798db01 target/arm: Force result size into dp after operation
9b1c8067b0 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
c2f33f799d target/arm: Implement HACR_EL2
5d803e29a6 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 5d803e29a608 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit c2f33f799db1 (target/arm: Implement HACR_EL2)
3/27 Checking commit 9b1c8067b058 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 72c798db0186 (target/arm: Force result size into dp after operation)
5/27 Checking commit 905438781946 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 3cbbe863ddc4 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 5b3cbe3a2cb1 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit bc98ce37e86a (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit c38db4cedc34 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit cf4f6b485e7d (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 530553605c71 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 40282cba687a (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit ea4ce7fac88a (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 990b62b71dd4 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit a7e7d40b7b98 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 72d6045bf127 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit ab9ebe5a3d40 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 8f4545ca6381 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit e004fed65e8b (target/arm: Remove neon min/max helpers)
20/27 Checking commit dd99a430053c (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 11f919937a85 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit ff918185bd76 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit c22864f2927f (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit e77ac93de248 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 89be70063eac (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 4b247465c1e0 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 73ac529141df (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (14 preceding siblings ...)
2019-02-15 1:28 ` no-reply
@ 2019-02-15 1:32 ` no-reply
2019-02-15 1:48 ` no-reply
` (5 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:32 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
6553235 gdbstub: Send a reply to the vKill packet.
c94c565 target/arm: Add missing clear_tail calls
026b9af target/arm: Use vector operations for saturation
c075e4f target/arm: Split out FPSCR.QC to a vector field
682ec57 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
8e880e0 target/arm: Split out flags setting from vfp compares
87c2a20 target/arm: Fix arm_cpu_dump_state vs FPSCR
0918b54 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
2b68e10 target/arm: Remove neon min/max helpers
6e628b4 target/arm: Use tcg integer min/max primitives for neon
b98c382 target/arm: Use vector minmax expanders for aarch32
b5f8871 target/arm: Use vector minmax expanders for aarch64
bb7653f target/arm: Rely on optimization within tcg_gen_gvec_or
cddac75 hw/arm/armsse: Fix miswiring of expansion IRQs
2a5cd58 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
83f6ca0 MAINTAINERS: Remove Peter Crosthwaite from various entries
f66e7b2 arm: Allow system registers for KVM guests to be changed by QEMU code
8f129e3 linux-user/elfload: enable HWCAP_CPUID for AArch64
82b82f4 target/arm: expose remaining CPUID registers as RAZ
2632f88 target/arm: expose MPIDR_EL1 to userspace
4430a67 target/arm: expose CPUID registers to userspace
1ed25cb target/arm: relax permission checks for HWCAP_CPUID registers
705b021 target/arm: Restructure disas_fp_int_conv
8cb3bd0 target/arm: Force result size into dp after operation
579d84d target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
6544e76 target/arm: Implement HACR_EL2
75e724d target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 75e724d7297a (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 6544e760c431 (target/arm: Implement HACR_EL2)
3/27 Checking commit 579d84d2eaa8 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 8cb3bd05da03 (target/arm: Force result size into dp after operation)
5/27 Checking commit 705b021f0005 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 1ed25cbabab7 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 4430a6761146 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 2632f88ceebd (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 82b82f40c0c9 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 8f129e350d23 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit f66e7b248819 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 83f6ca0a1ebf (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 2a5cd585f1d3 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit cddac7511c9e (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit bb7653f060ac (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit b5f88711f2a2 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit b98c382660f7 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 6e628b4a95f8 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 2b68e10ae9c7 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 0918b540445f (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 87c2a204a651 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 8e880e02c632 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 682ec57ab2cf (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit c075e4f90bb4 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 026b9afc537c (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit c94c5655eef4 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 6553235a7219 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (13 preceding siblings ...)
2019-02-15 1:24 ` no-reply
@ 2019-02-15 1:28 ` no-reply
2019-02-15 1:32 ` no-reply
` (6 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:28 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
6553235a72 gdbstub: Send a reply to the vKill packet.
c94c5655ee target/arm: Add missing clear_tail calls
026b9afc53 target/arm: Use vector operations for saturation
c075e4f90b target/arm: Split out FPSCR.QC to a vector field
682ec57ab2 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
8e880e02c6 target/arm: Split out flags setting from vfp compares
87c2a204a6 target/arm: Fix arm_cpu_dump_state vs FPSCR
0918b54044 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
2b68e10ae9 target/arm: Remove neon min/max helpers
6e628b4a95 target/arm: Use tcg integer min/max primitives for neon
b98c382660 target/arm: Use vector minmax expanders for aarch32
b5f88711f2 target/arm: Use vector minmax expanders for aarch64
bb7653f060 target/arm: Rely on optimization within tcg_gen_gvec_or
cddac7511c hw/arm/armsse: Fix miswiring of expansion IRQs
2a5cd585f1 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
83f6ca0a1e MAINTAINERS: Remove Peter Crosthwaite from various entries
f66e7b2488 arm: Allow system registers for KVM guests to be changed by QEMU code
8f129e350d linux-user/elfload: enable HWCAP_CPUID for AArch64
82b82f40c0 target/arm: expose remaining CPUID registers as RAZ
2632f88cee target/arm: expose MPIDR_EL1 to userspace
4430a67611 target/arm: expose CPUID registers to userspace
1ed25cbaba target/arm: relax permission checks for HWCAP_CPUID registers
705b021f00 target/arm: Restructure disas_fp_int_conv
8cb3bd05da target/arm: Force result size into dp after operation
579d84d2ea target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
6544e760c4 target/arm: Implement HACR_EL2
75e724d729 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 75e724d7297a (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 6544e760c431 (target/arm: Implement HACR_EL2)
3/27 Checking commit 579d84d2eaa8 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 8cb3bd05da03 (target/arm: Force result size into dp after operation)
5/27 Checking commit 705b021f0005 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 1ed25cbabab7 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 4430a6761146 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 2632f88ceebd (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 82b82f40c0c9 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 8f129e350d23 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit f66e7b248819 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 83f6ca0a1ebf (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 2a5cd585f1d3 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit cddac7511c9e (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit bb7653f060ac (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit b5f88711f2a2 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit b98c382660f7 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 6e628b4a95f8 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 2b68e10ae9c7 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 0918b540445f (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 87c2a204a651 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 8e880e02c632 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 682ec57ab2cf (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit c075e4f90bb4 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 026b9afc537c (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit c94c5655eef4 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 6553235a7219 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (12 preceding siblings ...)
2019-02-15 1:20 ` no-reply
@ 2019-02-15 1:24 ` no-reply
2019-02-15 1:28 ` no-reply
` (7 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:24 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190214102816.3393-1-peter.maydell@linaro.org -> patchew/20190214102816.3393-1-peter.maydell@linaro.org
- [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
8fd00e6 gdbstub: Send a reply to the vKill packet.
34aa54e target/arm: Add missing clear_tail calls
3846dbe target/arm: Use vector operations for saturation
781e41b target/arm: Split out FPSCR.QC to a vector field
95ef691 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
d640c73 target/arm: Split out flags setting from vfp compares
a556351 target/arm: Fix arm_cpu_dump_state vs FPSCR
6e9dcb5 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
bd99640 target/arm: Remove neon min/max helpers
5246212 target/arm: Use tcg integer min/max primitives for neon
28d1ed9 target/arm: Use vector minmax expanders for aarch32
f835440 target/arm: Use vector minmax expanders for aarch64
2fc345a target/arm: Rely on optimization within tcg_gen_gvec_or
5aafc65 hw/arm/armsse: Fix miswiring of expansion IRQs
c85153c hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
4ec0189 MAINTAINERS: Remove Peter Crosthwaite from various entries
45ab292 arm: Allow system registers for KVM guests to be changed by QEMU code
3382e5f linux-user/elfload: enable HWCAP_CPUID for AArch64
1d9bc81 target/arm: expose remaining CPUID registers as RAZ
ba7bf1b target/arm: expose MPIDR_EL1 to userspace
9ee0c2a target/arm: expose CPUID registers to userspace
a443302 target/arm: relax permission checks for HWCAP_CPUID registers
f59f8c9 target/arm: Restructure disas_fp_int_conv
e9d6907 target/arm: Force result size into dp after operation
aeaa89a target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7124a83 target/arm: Implement HACR_EL2
8820060 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 88200603a8cb (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7124a830e497 (target/arm: Implement HACR_EL2)
3/27 Checking commit aeaa89ad8291 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit e9d6907528aa (target/arm: Force result size into dp after operation)
5/27 Checking commit f59f8c968ae5 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit a44330292615 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 9ee0c2aab31c (target/arm: expose CPUID registers to userspace)
8/27 Checking commit ba7bf1bc03e1 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 1d9bc813e57b (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 3382e5fb3a55 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 45ab2928675e (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 4ec0189e9352 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit c85153c2d903 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 5aafc658edab (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 2fc345aa780c (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit f8354404a2f8 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 28d1ed93b13a (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 524621238d29 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit bd9964085387 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 6e9dcb58eb81 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit a5563518a586 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit d640c730a965 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 95ef6915a6d0 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 781e41b075a0 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 3846dbef44da (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 34aa54edfa31 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 8fd00e6381cf (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (11 preceding siblings ...)
2019-02-15 1:01 ` no-reply
@ 2019-02-15 1:20 ` no-reply
2019-02-15 1:24 ` no-reply
` (8 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:20 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
8fd00e6381 gdbstub: Send a reply to the vKill packet.
34aa54edfa target/arm: Add missing clear_tail calls
3846dbef44 target/arm: Use vector operations for saturation
781e41b075 target/arm: Split out FPSCR.QC to a vector field
95ef6915a6 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
d640c730a9 target/arm: Split out flags setting from vfp compares
a5563518a5 target/arm: Fix arm_cpu_dump_state vs FPSCR
6e9dcb58eb target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
bd99640853 target/arm: Remove neon min/max helpers
524621238d target/arm: Use tcg integer min/max primitives for neon
28d1ed93b1 target/arm: Use vector minmax expanders for aarch32
f8354404a2 target/arm: Use vector minmax expanders for aarch64
2fc345aa78 target/arm: Rely on optimization within tcg_gen_gvec_or
5aafc658ed hw/arm/armsse: Fix miswiring of expansion IRQs
c85153c2d9 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
4ec0189e93 MAINTAINERS: Remove Peter Crosthwaite from various entries
45ab292867 arm: Allow system registers for KVM guests to be changed by QEMU code
3382e5fb3a linux-user/elfload: enable HWCAP_CPUID for AArch64
1d9bc813e5 target/arm: expose remaining CPUID registers as RAZ
ba7bf1bc03 target/arm: expose MPIDR_EL1 to userspace
9ee0c2aab3 target/arm: expose CPUID registers to userspace
a443302926 target/arm: relax permission checks for HWCAP_CPUID registers
f59f8c968a target/arm: Restructure disas_fp_int_conv
e9d6907528 target/arm: Force result size into dp after operation
aeaa89ad82 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7124a830e4 target/arm: Implement HACR_EL2
88200603a8 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 88200603a8cb (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7124a830e497 (target/arm: Implement HACR_EL2)
3/27 Checking commit aeaa89ad8291 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit e9d6907528aa (target/arm: Force result size into dp after operation)
5/27 Checking commit f59f8c968ae5 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit a44330292615 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 9ee0c2aab31c (target/arm: expose CPUID registers to userspace)
8/27 Checking commit ba7bf1bc03e1 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 1d9bc813e57b (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 3382e5fb3a55 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 45ab2928675e (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 4ec0189e9352 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit c85153c2d903 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 5aafc658edab (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 2fc345aa780c (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit f8354404a2f8 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 28d1ed93b13a (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 524621238d29 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit bd9964085387 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 6e9dcb58eb81 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit a5563518a586 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit d640c730a965 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 95ef6915a6d0 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 781e41b075a0 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 3846dbef44da (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 34aa54edfa31 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 8fd00e6381cf (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (10 preceding siblings ...)
2019-02-15 0:38 ` no-reply
@ 2019-02-15 1:01 ` no-reply
2019-02-15 1:20 ` no-reply
` (9 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 1:01 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
b22c3da64b gdbstub: Send a reply to the vKill packet.
db616b3cea target/arm: Add missing clear_tail calls
240db5cc11 target/arm: Use vector operations for saturation
88a9504b9f target/arm: Split out FPSCR.QC to a vector field
e9d315769a target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
78d9813d1a target/arm: Split out flags setting from vfp compares
7addfd4039 target/arm: Fix arm_cpu_dump_state vs FPSCR
930c986b1b target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
a034668e9b target/arm: Remove neon min/max helpers
bb77972f61 target/arm: Use tcg integer min/max primitives for neon
d4bcca5e91 target/arm: Use vector minmax expanders for aarch32
58c8e77c23 target/arm: Use vector minmax expanders for aarch64
c75e5516d5 target/arm: Rely on optimization within tcg_gen_gvec_or
a3de217232 hw/arm/armsse: Fix miswiring of expansion IRQs
de29583b07 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
8fb1a5bac0 MAINTAINERS: Remove Peter Crosthwaite from various entries
acc80866a5 arm: Allow system registers for KVM guests to be changed by QEMU code
05e851518b linux-user/elfload: enable HWCAP_CPUID for AArch64
1e0293cc26 target/arm: expose remaining CPUID registers as RAZ
0443bd4878 target/arm: expose MPIDR_EL1 to userspace
ad0122bcbf target/arm: expose CPUID registers to userspace
1cc2635c69 target/arm: relax permission checks for HWCAP_CPUID registers
592467aa65 target/arm: Restructure disas_fp_int_conv
af2989a366 target/arm: Force result size into dp after operation
f26458f2fa target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
ee1b241af9 target/arm: Implement HACR_EL2
845bd274c6 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 845bd274c624 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit ee1b241af96d (target/arm: Implement HACR_EL2)
3/27 Checking commit f26458f2fa7e (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit af2989a36697 (target/arm: Force result size into dp after operation)
5/27 Checking commit 592467aa6590 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 1cc2635c6964 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit ad0122bcbfcd (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 0443bd48780a (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 1e0293cc26e0 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 05e851518be8 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit acc80866a588 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 8fb1a5bac0c0 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit de29583b07df (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit a3de21723286 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit c75e5516d5de (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 58c8e77c23c0 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit d4bcca5e9117 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit bb77972f618b (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit a034668e9b5d (target/arm: Remove neon min/max helpers)
20/27 Checking commit 930c986b1b61 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 7addfd403939 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 78d9813d1a48 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit e9d315769a5c (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 88a9504b9f85 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 240db5cc1112 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit db616b3ceae7 (target/arm: Add missing clear_tail calls)
27/27 Checking commit b22c3da64b53 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (9 preceding siblings ...)
2019-02-15 0:34 ` no-reply
@ 2019-02-15 0:38 ` no-reply
2019-02-15 1:01 ` no-reply
` (10 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 0:38 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
f74396d gdbstub: Send a reply to the vKill packet.
52c1857 target/arm: Add missing clear_tail calls
2f1aef9 target/arm: Use vector operations for saturation
80683e5 target/arm: Split out FPSCR.QC to a vector field
5d1d26f target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
06fe487 target/arm: Split out flags setting from vfp compares
d0ce625 target/arm: Fix arm_cpu_dump_state vs FPSCR
f382917 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
21c80ed target/arm: Remove neon min/max helpers
822434e target/arm: Use tcg integer min/max primitives for neon
ec47e8c target/arm: Use vector minmax expanders for aarch32
8e1c96f target/arm: Use vector minmax expanders for aarch64
5ce1275 target/arm: Rely on optimization within tcg_gen_gvec_or
7cf21d5 hw/arm/armsse: Fix miswiring of expansion IRQs
fc4f4fb hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
df4e1ca MAINTAINERS: Remove Peter Crosthwaite from various entries
0818f54 arm: Allow system registers for KVM guests to be changed by QEMU code
29ae44a linux-user/elfload: enable HWCAP_CPUID for AArch64
f5eb2f7 target/arm: expose remaining CPUID registers as RAZ
ac0a143 target/arm: expose MPIDR_EL1 to userspace
0263d9a target/arm: expose CPUID registers to userspace
9b69c06 target/arm: relax permission checks for HWCAP_CPUID registers
d616286 target/arm: Restructure disas_fp_int_conv
385be0d target/arm: Force result size into dp after operation
1cc6b86 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
2d2b73d target/arm: Implement HACR_EL2
86f75dd target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 86f75ddfddfc (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 2d2b73dc4d6c (target/arm: Implement HACR_EL2)
3/27 Checking commit 1cc6b8631d42 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 385be0d0977a (target/arm: Force result size into dp after operation)
5/27 Checking commit d61628698a25 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 9b69c06e28d4 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 0263d9ab2de9 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit ac0a14313eb2 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit f5eb2f7c5740 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 29ae44a5951b (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 0818f544d6cd (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit df4e1ca71de6 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit fc4f4fbe1c98 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 7cf21d564829 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 5ce1275e65ee (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 8e1c96f68344 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit ec47e8c9169b (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 822434eb2677 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 21c80ed9cd6e (target/arm: Remove neon min/max helpers)
20/27 Checking commit f38291710529 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit d0ce62513eae (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 06fe48799dc0 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 5d1d26f9eba9 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 80683e5bc15a (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 2f1aef96ec10 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 52c1857391d8 (target/arm: Add missing clear_tail calls)
27/27 Checking commit f74396d1168a (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (8 preceding siblings ...)
2019-02-15 0:11 ` no-reply
@ 2019-02-15 0:34 ` no-reply
2019-02-15 0:38 ` no-reply
` (11 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 0:34 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
f74396d116 gdbstub: Send a reply to the vKill packet.
52c1857391 target/arm: Add missing clear_tail calls
2f1aef96ec target/arm: Use vector operations for saturation
80683e5bc1 target/arm: Split out FPSCR.QC to a vector field
5d1d26f9eb target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
06fe48799d target/arm: Split out flags setting from vfp compares
d0ce62513e target/arm: Fix arm_cpu_dump_state vs FPSCR
f382917105 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
21c80ed9cd target/arm: Remove neon min/max helpers
822434eb26 target/arm: Use tcg integer min/max primitives for neon
ec47e8c916 target/arm: Use vector minmax expanders for aarch32
8e1c96f683 target/arm: Use vector minmax expanders for aarch64
5ce1275e65 target/arm: Rely on optimization within tcg_gen_gvec_or
7cf21d5648 hw/arm/armsse: Fix miswiring of expansion IRQs
fc4f4fbe1c hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
df4e1ca71d MAINTAINERS: Remove Peter Crosthwaite from various entries
0818f544d6 arm: Allow system registers for KVM guests to be changed by QEMU code
29ae44a595 linux-user/elfload: enable HWCAP_CPUID for AArch64
f5eb2f7c57 target/arm: expose remaining CPUID registers as RAZ
ac0a14313e target/arm: expose MPIDR_EL1 to userspace
0263d9ab2d target/arm: expose CPUID registers to userspace
9b69c06e28 target/arm: relax permission checks for HWCAP_CPUID registers
d61628698a target/arm: Restructure disas_fp_int_conv
385be0d097 target/arm: Force result size into dp after operation
1cc6b8631d target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
2d2b73dc4d target/arm: Implement HACR_EL2
86f75ddfdd target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 86f75ddfddfc (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 2d2b73dc4d6c (target/arm: Implement HACR_EL2)
3/27 Checking commit 1cc6b8631d42 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 385be0d0977a (target/arm: Force result size into dp after operation)
5/27 Checking commit d61628698a25 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 9b69c06e28d4 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 0263d9ab2de9 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit ac0a14313eb2 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit f5eb2f7c5740 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 29ae44a5951b (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 0818f544d6cd (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit df4e1ca71de6 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit fc4f4fbe1c98 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 7cf21d564829 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 5ce1275e65ee (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 8e1c96f68344 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit ec47e8c9169b (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 822434eb2677 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 21c80ed9cd6e (target/arm: Remove neon min/max helpers)
20/27 Checking commit f38291710529 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit d0ce62513eae (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 06fe48799dc0 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 5d1d26f9eba9 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 80683e5bc15a (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 2f1aef96ec10 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 52c1857391d8 (target/arm: Add missing clear_tail calls)
27/27 Checking commit f74396d1168a (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (7 preceding siblings ...)
2019-02-15 0:07 ` no-reply
@ 2019-02-15 0:11 ` no-reply
2019-02-15 0:34 ` no-reply
` (12 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 0:11 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
0d3e41d..0266c73 master -> master
- [tag update] patchew/20190214051440.59167-1-aik@ozlabs.ru -> patchew/20190214051440.59167-1-aik@ozlabs.ru
- [tag update] patchew/20190214154053.15050-1-marcel.apfelbaum@gmail.com -> patchew/20190214154053.15050-1-marcel.apfelbaum@gmail.com
* [new tag] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
* [new tag] patchew/20190214201939.494-1-philmd@redhat.com -> patchew/20190214201939.494-1-philmd@redhat.com
* [new tag] patchew/20190214220453.15858-1-svens@stackframe.org -> patchew/20190214220453.15858-1-svens@stackframe.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
3fb84ac gdbstub: Send a reply to the vKill packet.
1b05bfa target/arm: Add missing clear_tail calls
3306632 target/arm: Use vector operations for saturation
585d823 target/arm: Split out FPSCR.QC to a vector field
0a651b3 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
f1e2193 target/arm: Split out flags setting from vfp compares
cc71f73 target/arm: Fix arm_cpu_dump_state vs FPSCR
e5abdca target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
71ab631 target/arm: Remove neon min/max helpers
d64f047 target/arm: Use tcg integer min/max primitives for neon
565ffb8 target/arm: Use vector minmax expanders for aarch32
f07a332 target/arm: Use vector minmax expanders for aarch64
8566cb4 target/arm: Rely on optimization within tcg_gen_gvec_or
a5516fe hw/arm/armsse: Fix miswiring of expansion IRQs
e7ac553 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
bcc7967 MAINTAINERS: Remove Peter Crosthwaite from various entries
f88d98d arm: Allow system registers for KVM guests to be changed by QEMU code
351c302 linux-user/elfload: enable HWCAP_CPUID for AArch64
5927860 target/arm: expose remaining CPUID registers as RAZ
1629af9 target/arm: expose MPIDR_EL1 to userspace
b9d5d58 target/arm: expose CPUID registers to userspace
44e3fc2 target/arm: relax permission checks for HWCAP_CPUID registers
705c2b3 target/arm: Restructure disas_fp_int_conv
d249dc5 target/arm: Force result size into dp after operation
b7be3ad target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7f06ec4f target/arm: Implement HACR_EL2
8f1fa8a target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 8f1fa8a2d44d (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7f06ec4f82fc (target/arm: Implement HACR_EL2)
3/27 Checking commit b7be3ad1569d (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit d249dc5f667b (target/arm: Force result size into dp after operation)
5/27 Checking commit 705c2b3ae778 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 44e3fc28e6b9 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit b9d5d582d0b8 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 1629af984d31 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 5927860dc734 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 351c302ef060 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit f88d98d2500b (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit bcc7967dcbce (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit e7ac553c2731 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit a5516fece4af (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 8566cb485cc1 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit f07a3327aeb2 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 565ffb817594 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit d64f04762c4e (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 71ab631c3993 (target/arm: Remove neon min/max helpers)
20/27 Checking commit e5abdca84207 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit cc71f739fff8 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit f1e2193373cd (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 0a651b397b27 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 585d8235c31a (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 330663235d62 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 1b05bfa0b021 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 3fb84accb10d (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (6 preceding siblings ...)
2019-02-14 23:39 ` no-reply
@ 2019-02-15 0:07 ` no-reply
2019-02-15 0:11 ` no-reply
` (13 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-15 0:07 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
3fb84accb1 gdbstub: Send a reply to the vKill packet.
1b05bfa0b0 target/arm: Add missing clear_tail calls
330663235d target/arm: Use vector operations for saturation
585d8235c3 target/arm: Split out FPSCR.QC to a vector field
0a651b397b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
f1e2193373 target/arm: Split out flags setting from vfp compares
cc71f739ff target/arm: Fix arm_cpu_dump_state vs FPSCR
e5abdca842 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
71ab631c39 target/arm: Remove neon min/max helpers
d64f04762c target/arm: Use tcg integer min/max primitives for neon
565ffb8175 target/arm: Use vector minmax expanders for aarch32
f07a3327ae target/arm: Use vector minmax expanders for aarch64
8566cb485c target/arm: Rely on optimization within tcg_gen_gvec_or
a5516fece4 hw/arm/armsse: Fix miswiring of expansion IRQs
e7ac553c27 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
bcc7967dcb MAINTAINERS: Remove Peter Crosthwaite from various entries
f88d98d250 arm: Allow system registers for KVM guests to be changed by QEMU code
351c302ef0 linux-user/elfload: enable HWCAP_CPUID for AArch64
5927860dc7 target/arm: expose remaining CPUID registers as RAZ
1629af984d target/arm: expose MPIDR_EL1 to userspace
b9d5d582d0 target/arm: expose CPUID registers to userspace
44e3fc28e6 target/arm: relax permission checks for HWCAP_CPUID registers
705c2b3ae7 target/arm: Restructure disas_fp_int_conv
d249dc5f66 target/arm: Force result size into dp after operation
b7be3ad156 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
7f06ec4f82 target/arm: Implement HACR_EL2
8f1fa8a2d4 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 8f1fa8a2d44d (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 7f06ec4f82fc (target/arm: Implement HACR_EL2)
3/27 Checking commit b7be3ad1569d (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit d249dc5f667b (target/arm: Force result size into dp after operation)
5/27 Checking commit 705c2b3ae778 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 44e3fc28e6b9 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit b9d5d582d0b8 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 1629af984d31 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 5927860dc734 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 351c302ef060 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit f88d98d2500b (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit bcc7967dcbce (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit e7ac553c2731 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit a5516fece4af (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 8566cb485cc1 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit f07a3327aeb2 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 565ffb817594 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit d64f04762c4e (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 71ab631c3993 (target/arm: Remove neon min/max helpers)
20/27 Checking commit e5abdca84207 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit cc71f739fff8 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit f1e2193373cd (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 0a651b397b27 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 585d8235c31a (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 330663235d62 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 1b05bfa0b021 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 3fb84accb10d (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (5 preceding siblings ...)
2019-02-14 22:18 ` no-reply
@ 2019-02-14 23:39 ` no-reply
2019-02-15 0:07 ` no-reply
` (14 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 23:39 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
1fcacb9030 gdbstub: Send a reply to the vKill packet.
facc45d026 target/arm: Add missing clear_tail calls
fe47ae1ac0 target/arm: Use vector operations for saturation
beb3acb4a2 target/arm: Split out FPSCR.QC to a vector field
8187800f5f target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
61090e681c target/arm: Split out flags setting from vfp compares
753b33ef6a target/arm: Fix arm_cpu_dump_state vs FPSCR
a6ac25752e target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
70ae1e5a51 target/arm: Remove neon min/max helpers
aa0575d473 target/arm: Use tcg integer min/max primitives for neon
00d818ea1d target/arm: Use vector minmax expanders for aarch32
7e76c6e511 target/arm: Use vector minmax expanders for aarch64
26a48e84cf target/arm: Rely on optimization within tcg_gen_gvec_or
17db94065e hw/arm/armsse: Fix miswiring of expansion IRQs
f5b0afe7e5 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
dafa19baa4 MAINTAINERS: Remove Peter Crosthwaite from various entries
3e133e44a1 arm: Allow system registers for KVM guests to be changed by QEMU code
f2cfb74b09 linux-user/elfload: enable HWCAP_CPUID for AArch64
ca0002eebc target/arm: expose remaining CPUID registers as RAZ
4b893eb212 target/arm: expose MPIDR_EL1 to userspace
9d5e5704e0 target/arm: expose CPUID registers to userspace
b1a6cabff4 target/arm: relax permission checks for HWCAP_CPUID registers
a252f2d3f9 target/arm: Restructure disas_fp_int_conv
095c71f97a target/arm: Force result size into dp after operation
dbb6c95fc5 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
0319bf2a5a target/arm: Implement HACR_EL2
1e79fd6dec target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 1e79fd6decaa (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 0319bf2a5af5 (target/arm: Implement HACR_EL2)
3/27 Checking commit dbb6c95fc539 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 095c71f97a76 (target/arm: Force result size into dp after operation)
5/27 Checking commit a252f2d3f9f7 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit b1a6cabff49f (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 9d5e5704e04b (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 4b893eb21287 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit ca0002eebc43 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit f2cfb74b0916 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 3e133e44a1b8 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit dafa19baa45b (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit f5b0afe7e5f6 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 17db94065e2f (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 26a48e84cf68 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 7e76c6e5113a (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 00d818ea1d8a (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit aa0575d473a8 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 70ae1e5a51e0 (target/arm: Remove neon min/max helpers)
20/27 Checking commit a6ac25752edc (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 753b33ef6a9f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 61090e681cb1 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 8187800f5f67 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit beb3acb4a272 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit fe47ae1ac0ef (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit facc45d0266a (target/arm: Add missing clear_tail calls)
27/27 Checking commit 1fcacb90300d (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (4 preceding siblings ...)
2019-02-14 21:51 ` no-reply
@ 2019-02-14 22:18 ` no-reply
2019-02-14 23:39 ` no-reply
` (15 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 22:18 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
* [new tag] patchew/20190214220453.15858-1-svens@stackframe.org -> patchew/20190214220453.15858-1-svens@stackframe.org
Switched to a new branch 'test'
107d0c1054 gdbstub: Send a reply to the vKill packet.
1cefa94d4c target/arm: Add missing clear_tail calls
2d7acfba65 target/arm: Use vector operations for saturation
4cacb6d477 target/arm: Split out FPSCR.QC to a vector field
af552d5a9a target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
889e25cedd target/arm: Split out flags setting from vfp compares
08ed30fcbd target/arm: Fix arm_cpu_dump_state vs FPSCR
58c34834b4 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
37ba9384f4 target/arm: Remove neon min/max helpers
3fe3bcd56e target/arm: Use tcg integer min/max primitives for neon
7917081632 target/arm: Use vector minmax expanders for aarch32
7be5894710 target/arm: Use vector minmax expanders for aarch64
3dc77fca6e target/arm: Rely on optimization within tcg_gen_gvec_or
0aa85c83b5 hw/arm/armsse: Fix miswiring of expansion IRQs
a171b85781 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
535a7c3670 MAINTAINERS: Remove Peter Crosthwaite from various entries
824e72655d arm: Allow system registers for KVM guests to be changed by QEMU code
c4582c22e5 linux-user/elfload: enable HWCAP_CPUID for AArch64
835edbcab5 target/arm: expose remaining CPUID registers as RAZ
00813a218f target/arm: expose MPIDR_EL1 to userspace
2fad8a0685 target/arm: expose CPUID registers to userspace
876f185d5f target/arm: relax permission checks for HWCAP_CPUID registers
1a8296d2a7 target/arm: Restructure disas_fp_int_conv
9ef7368140 target/arm: Force result size into dp after operation
e6ffe03733 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
0588209db8 target/arm: Implement HACR_EL2
8be75be4ad target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 8be75be4ad21 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 0588209db891 (target/arm: Implement HACR_EL2)
3/27 Checking commit e6ffe03733b4 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 9ef736814077 (target/arm: Force result size into dp after operation)
5/27 Checking commit 1a8296d2a731 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 876f185d5fde (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 2fad8a068527 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 00813a218f3d (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 835edbcab59c (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit c4582c22e533 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 824e72655d47 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 535a7c36704b (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit a171b857817d (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 0aa85c83b58c (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 3dc77fca6e12 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 7be5894710ec (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 7917081632bd (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 3fe3bcd56e94 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 37ba9384f40b (target/arm: Remove neon min/max helpers)
20/27 Checking commit 58c34834b47f (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 08ed30fcbd5f (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 889e25cedd73 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit af552d5a9a15 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 4cacb6d47706 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 2d7acfba6561 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 1cefa94d4c1d (target/arm: Add missing clear_tail calls)
27/27 Checking commit 107d0c10546a (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (3 preceding siblings ...)
2019-02-14 21:24 ` no-reply
@ 2019-02-14 21:51 ` no-reply
2019-02-14 22:18 ` no-reply
` (16 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 21:51 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
acf570635b gdbstub: Send a reply to the vKill packet.
cfd8f55e95 target/arm: Add missing clear_tail calls
259bb867b8 target/arm: Use vector operations for saturation
6b04328ef7 target/arm: Split out FPSCR.QC to a vector field
de7292c5a8 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
999ec7bd2d target/arm: Split out flags setting from vfp compares
20031f4d81 target/arm: Fix arm_cpu_dump_state vs FPSCR
7f2ccbe2fc target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
3652215042 target/arm: Remove neon min/max helpers
a2f9ae9d00 target/arm: Use tcg integer min/max primitives for neon
2a97616341 target/arm: Use vector minmax expanders for aarch32
0cbd8e1d73 target/arm: Use vector minmax expanders for aarch64
60dbc19c09 target/arm: Rely on optimization within tcg_gen_gvec_or
612e1a64f9 hw/arm/armsse: Fix miswiring of expansion IRQs
79033fb4ff hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
b0353d09d8 MAINTAINERS: Remove Peter Crosthwaite from various entries
1f2b02b2cd arm: Allow system registers for KVM guests to be changed by QEMU code
06a5266ef7 linux-user/elfload: enable HWCAP_CPUID for AArch64
60eef60261 target/arm: expose remaining CPUID registers as RAZ
dfe0bf2269 target/arm: expose MPIDR_EL1 to userspace
027c283aef target/arm: expose CPUID registers to userspace
641715c1a5 target/arm: relax permission checks for HWCAP_CPUID registers
0fce875951 target/arm: Restructure disas_fp_int_conv
743fa18abf target/arm: Force result size into dp after operation
93602e2cd3 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
59084e04e5 target/arm: Implement HACR_EL2
7150f17967 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit 7150f17967aa (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 59084e04e5d6 (target/arm: Implement HACR_EL2)
3/27 Checking commit 93602e2cd3f5 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 743fa18abfb8 (target/arm: Force result size into dp after operation)
5/27 Checking commit 0fce87595153 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 641715c1a53d (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 027c283aef86 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit dfe0bf226921 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 60eef60261b6 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit 06a5266ef754 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 1f2b02b2cd7a (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit b0353d09d85b (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 79033fb4ff44 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 612e1a64f9e9 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 60dbc19c096f (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 0cbd8e1d7369 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 2a976163412b (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit a2f9ae9d00dc (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 3652215042cd (target/arm: Remove neon min/max helpers)
20/27 Checking commit 7f2ccbe2fc14 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 20031f4d81ce (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 999ec7bd2d81 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit de7292c5a8d3 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 6b04328ef702 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 259bb867b8c7 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit cfd8f55e9599 (target/arm: Add missing clear_tail calls)
27/27 Checking commit acf570635b34 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
` (2 preceding siblings ...)
2019-02-14 20:57 ` no-reply
@ 2019-02-14 21:24 ` no-reply
2019-02-14 21:51 ` no-reply
` (17 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 21:24 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
4a5fa28330 gdbstub: Send a reply to the vKill packet.
377a1b0e65 target/arm: Add missing clear_tail calls
f7d3af4abb target/arm: Use vector operations for saturation
df8ca3278b target/arm: Split out FPSCR.QC to a vector field
09d6eda7b5 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
08ed43f236 target/arm: Split out flags setting from vfp compares
13d1fa231c target/arm: Fix arm_cpu_dump_state vs FPSCR
89c3c77cc7 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
9ef6297e49 target/arm: Remove neon min/max helpers
409e13e7c6 target/arm: Use tcg integer min/max primitives for neon
dbcd048d95 target/arm: Use vector minmax expanders for aarch32
35d58be2dc target/arm: Use vector minmax expanders for aarch64
ac2c4a327a target/arm: Rely on optimization within tcg_gen_gvec_or
081212958f hw/arm/armsse: Fix miswiring of expansion IRQs
425d5d76ea hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
1b1ca68043 MAINTAINERS: Remove Peter Crosthwaite from various entries
d313b64e06 arm: Allow system registers for KVM guests to be changed by QEMU code
ad6e481428 linux-user/elfload: enable HWCAP_CPUID for AArch64
ec69944c2a target/arm: expose remaining CPUID registers as RAZ
59b0c47736 target/arm: expose MPIDR_EL1 to userspace
38948116f6 target/arm: expose CPUID registers to userspace
de5c25835f target/arm: relax permission checks for HWCAP_CPUID registers
f2d76c5e1d target/arm: Restructure disas_fp_int_conv
f71a727256 target/arm: Force result size into dp after operation
5a52d23be1 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
b7f2a14413 target/arm: Implement HACR_EL2
eb86b450b4 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit eb86b450b4d2 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit b7f2a1441331 (target/arm: Implement HACR_EL2)
3/27 Checking commit 5a52d23be1a7 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit f71a72725699 (target/arm: Force result size into dp after operation)
5/27 Checking commit f2d76c5e1d0e (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit de5c25835ff7 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 38948116f604 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 59b0c4773654 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit ec69944c2adf (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit ad6e481428ed (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit d313b64e0651 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 1b1ca680431d (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit 425d5d76ea60 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 081212958fd9 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit ac2c4a327a45 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 35d58be2dcb7 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit dbcd048d9559 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 409e13e7c607 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 9ef6297e49d3 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 89c3c77cc712 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 13d1fa231c8e (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 08ed43f236ec (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 09d6eda7b5ab (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit df8ca3278b2c (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit f7d3af4abb72 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 377a1b0e655a (target/arm: Add missing clear_tail calls)
27/27 Checking commit 4a5fa2833065 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
2019-02-14 19:56 ` no-reply
2019-02-14 20:30 ` no-reply
@ 2019-02-14 20:57 ` no-reply
2019-02-14 21:24 ` no-reply
` (18 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 20:57 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
8b28bf8c02 gdbstub: Send a reply to the vKill packet.
35e9a92f59 target/arm: Add missing clear_tail calls
679145406a target/arm: Use vector operations for saturation
a14d6bfaf2 target/arm: Split out FPSCR.QC to a vector field
f8fbccbba5 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
ba0918dc3a target/arm: Split out flags setting from vfp compares
97f0d8db7d target/arm: Fix arm_cpu_dump_state vs FPSCR
fcc5258d65 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
496ebd96d8 target/arm: Remove neon min/max helpers
57606e781d target/arm: Use tcg integer min/max primitives for neon
fb20fb9747 target/arm: Use vector minmax expanders for aarch32
09fe9b2ce9 target/arm: Use vector minmax expanders for aarch64
76ee8fbab5 target/arm: Rely on optimization within tcg_gen_gvec_or
a9bf743839 hw/arm/armsse: Fix miswiring of expansion IRQs
a2989bb924 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
d58f7f8928 MAINTAINERS: Remove Peter Crosthwaite from various entries
0db6bcf0f7 arm: Allow system registers for KVM guests to be changed by QEMU code
cc4082ee0d linux-user/elfload: enable HWCAP_CPUID for AArch64
a317a40397 target/arm: expose remaining CPUID registers as RAZ
50b5ab0dc0 target/arm: expose MPIDR_EL1 to userspace
424e73b993 target/arm: expose CPUID registers to userspace
f8c3d064cd target/arm: relax permission checks for HWCAP_CPUID registers
944dfb207b target/arm: Restructure disas_fp_int_conv
770275cef8 target/arm: Force result size into dp after operation
86975d477f target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
0fad7188ea target/arm: Implement HACR_EL2
df8c887922 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit df8c88792230 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 0fad7188ea17 (target/arm: Implement HACR_EL2)
3/27 Checking commit 86975d477ff0 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 770275cef89b (target/arm: Force result size into dp after operation)
5/27 Checking commit 944dfb207b6b (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit f8c3d064cd92 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit 424e73b99329 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 50b5ab0dc071 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit a317a4039735 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit cc4082ee0d10 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 0db6bcf0f7ac (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit d58f7f89287b (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit a2989bb92474 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit a9bf743839e7 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit 76ee8fbab5cf (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 09fe9b2ce988 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit fb20fb9747a0 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 57606e781d78 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 496ebd96d8f5 (target/arm: Remove neon min/max helpers)
20/27 Checking commit fcc5258d65aa (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 97f0d8db7d84 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit ba0918dc3a40 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit f8fbccbba569 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit a14d6bfaf27b (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 679145406ae5 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 35e9a92f5916 (target/arm: Add missing clear_tail calls)
27/27 Checking commit 8b28bf8c02b6 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
2019-02-14 19:56 ` no-reply
@ 2019-02-14 20:30 ` no-reply
2019-02-14 20:57 ` no-reply
` (19 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 20:30 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
fb39c2e90f gdbstub: Send a reply to the vKill packet.
86563bda9d target/arm: Add missing clear_tail calls
866f1958b4 target/arm: Use vector operations for saturation
7fadd905a7 target/arm: Split out FPSCR.QC to a vector field
3bbf4384f9 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
178fe16ac8 target/arm: Split out flags setting from vfp compares
1fb9548fec target/arm: Fix arm_cpu_dump_state vs FPSCR
c045bbe35f target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
0bfb764ba7 target/arm: Remove neon min/max helpers
4a40d71633 target/arm: Use tcg integer min/max primitives for neon
9eaba50860 target/arm: Use vector minmax expanders for aarch32
e222548533 target/arm: Use vector minmax expanders for aarch64
e77230191f target/arm: Rely on optimization within tcg_gen_gvec_or
3f7cda73b2 hw/arm/armsse: Fix miswiring of expansion IRQs
d93ebe8185 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
cce31aab3d MAINTAINERS: Remove Peter Crosthwaite from various entries
9891e5f6c7 arm: Allow system registers for KVM guests to be changed by QEMU code
ab703f0d5a linux-user/elfload: enable HWCAP_CPUID for AArch64
b4301eab08 target/arm: expose remaining CPUID registers as RAZ
7abf3c8631 target/arm: expose MPIDR_EL1 to userspace
d17bc752d8 target/arm: expose CPUID registers to userspace
721d2c2056 target/arm: relax permission checks for HWCAP_CPUID registers
70d62fd729 target/arm: Restructure disas_fp_int_conv
907d999506 target/arm: Force result size into dp after operation
a20dcecfa6 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
d42d84b7b1 target/arm: Implement HACR_EL2
f1dfc8484b target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit f1dfc8484bc4 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit d42d84b7b110 (target/arm: Implement HACR_EL2)
3/27 Checking commit a20dcecfa649 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit 907d99950666 (target/arm: Force result size into dp after operation)
5/27 Checking commit 70d62fd72937 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 721d2c20567e (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit d17bc752d844 (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 7abf3c863143 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit b4301eab085b (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit ab703f0d5a46 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 9891e5f6c709 (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit cce31aab3d66 (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit d93ebe8185a4 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 3f7cda73b20a (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit e77230191f43 (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit e222548533b0 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 9eaba5086098 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 4a40d7163314 (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 0bfb764ba772 (target/arm: Remove neon min/max helpers)
20/27 Checking commit c045bbe35fd4 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 1fb9548fec41 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 178fe16ac872 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 3bbf4384f995 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 7fadd905a7f3 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit 866f1958b4d7 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit 86563bda9da9 (target/arm: Add missing clear_tail calls)
27/27 Checking commit fb39c2e90f66 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2019-02-14 19:05 Peter Maydell
@ 2019-02-14 19:56 ` no-reply
2019-02-14 20:30 ` no-reply
` (20 subsequent siblings)
21 siblings, 0 replies; 67+ messages in thread
From: no-reply @ 2019-02-14 19:56 UTC (permalink / raw)
To: peter.maydell; +Cc: fam, qemu-devel
Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190214190603.25030-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
0d3e41d5ef..0266c739ab master -> master
* [new tag] patchew/20190214190603.25030-1-peter.maydell@linaro.org -> patchew/20190214190603.25030-1-peter.maydell@linaro.org
Switched to a new branch 'test'
c903d16f69 gdbstub: Send a reply to the vKill packet.
f41dbe7001 target/arm: Add missing clear_tail calls
a3938310ec target/arm: Use vector operations for saturation
9b991d3ba4 target/arm: Split out FPSCR.QC to a vector field
268d1b9f5d target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
f1d08942ee target/arm: Split out flags setting from vfp compares
91e223f0f1 target/arm: Fix arm_cpu_dump_state vs FPSCR
764d782f4d target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
47067fd53b target/arm: Remove neon min/max helpers
05f1c9b528 target/arm: Use tcg integer min/max primitives for neon
1f1543646b target/arm: Use vector minmax expanders for aarch32
06f27fadf8 target/arm: Use vector minmax expanders for aarch64
fc2e976aa2 target/arm: Rely on optimization within tcg_gen_gvec_or
1afa20583c hw/arm/armsse: Fix miswiring of expansion IRQs
fdd25e9b24 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
1827768bd1 MAINTAINERS: Remove Peter Crosthwaite from various entries
991af7236f arm: Allow system registers for KVM guests to be changed by QEMU code
a9636655dd linux-user/elfload: enable HWCAP_CPUID for AArch64
5112145efe target/arm: expose remaining CPUID registers as RAZ
12fd99a4ba target/arm: expose MPIDR_EL1 to userspace
aff8cd32cc target/arm: expose CPUID registers to userspace
1ef1d6626a target/arm: relax permission checks for HWCAP_CPUID registers
ba75efcd06 target/arm: Restructure disas_fp_int_conv
a1f51e1111 target/arm: Force result size into dp after operation
50d5b46b34 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
847bae167b target/arm: Implement HACR_EL2
db698e8bd5 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
=== OUTPUT BEGIN ===
1/27 Checking commit db698e8bd558 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR)
2/27 Checking commit 847bae167b24 (target/arm: Implement HACR_EL2)
3/27 Checking commit 50d5b46b34cb (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be)
4/27 Checking commit a1f51e11115a (target/arm: Force result size into dp after operation)
5/27 Checking commit ba75efcd0632 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 1ef1d6626a73 (target/arm: relax permission checks for HWCAP_CPUID registers)
7/27 Checking commit aff8cd32cc4a (target/arm: expose CPUID registers to userspace)
8/27 Checking commit 12fd99a4baf8 (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 5112145efe84 (target/arm: expose remaining CPUID registers as RAZ)
10/27 Checking commit a9636655dd31 (linux-user/elfload: enable HWCAP_CPUID for AArch64)
11/27 Checking commit 991af7236fdf (arm: Allow system registers for KVM guests to be changed by QEMU code)
12/27 Checking commit 1827768bd11f (MAINTAINERS: Remove Peter Crosthwaite from various entries)
13/27 Checking commit fdd25e9b24c8 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1)
14/27 Checking commit 1afa20583c29 (hw/arm/armsse: Fix miswiring of expansion IRQs)
15/27 Checking commit fc2e976aa28e (target/arm: Rely on optimization within tcg_gen_gvec_or)
16/27 Checking commit 06f27fadf836 (target/arm: Use vector minmax expanders for aarch64)
17/27 Checking commit 1f1543646b22 (target/arm: Use vector minmax expanders for aarch32)
18/27 Checking commit 05f1c9b5283e (target/arm: Use tcg integer min/max primitives for neon)
19/27 Checking commit 47067fd53bc4 (target/arm: Remove neon min/max helpers)
20/27 Checking commit 764d782f4d64 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+ case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+ case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
total: 2 errors, 0 warnings, 16 lines checked
Patch 20/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/27 Checking commit 91e223f0f1af (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit f1d08942ee79 (target/arm: Split out flags setting from vfp compares)
23/27 Checking commit 268d1b9f5d61 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR])
24/27 Checking commit 9b991d3ba404 (target/arm: Split out FPSCR.QC to a vector field)
25/27 Checking commit a3938310ec20 (target/arm: Use vector operations for saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+ TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
^
total: 1 errors, 0 warnings, 438 lines checked
Patch 25/27 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/27 Checking commit f41dbe70013f (target/arm: Add missing clear_tail calls)
27/27 Checking commit c903d16f6993 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190214190603.25030-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2019-02-14 19:05 Peter Maydell
2019-02-14 19:56 ` no-reply
` (21 more replies)
0 siblings, 22 replies; 67+ messages in thread
From: Peter Maydell @ 2019-02-14 19:05 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 0d3e41d5efd638a0c5682f6813b26448c3c51624:
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-02-14 17:42:25 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190214
for you to fetch changes up to 497bc12b1b374ecd62903bf062229bd93f8924af:
gdbstub: Send a reply to the vKill packet. (2019-02-14 18:45:49 +0000)
----------------------------------------------------------------
target-arm queue:
* gdbstub: Send a reply to the vKill packet
* Improve codegen for neon min/max and saturating arithmetic
* Fix a bug in clearing FPSCR exception status bits
* hw/arm/armsse: Fix miswiring of expansion IRQs
* hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
* MAINTAINERS: Remove Peter Crosthwaite from various entries
* arm: Allow system registers for KVM guests to be changed by QEMU code
* linux-user: support HWCAP_CPUID which exposes ID registers to user code
* Fix bug in 128-bit cmpxchg for BE Arm guests
* Implement (no-op) HACR_EL2
* Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
----------------------------------------------------------------
Aaron Lindsay OS (1):
target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
Alex Bennée (5):
target/arm: relax permission checks for HWCAP_CPUID registers
target/arm: expose CPUID registers to userspace
target/arm: expose MPIDR_EL1 to userspace
target/arm: expose remaining CPUID registers as RAZ
linux-user/elfload: enable HWCAP_CPUID for AArch64
Catherine Ho (1):
target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
Peter Maydell (5):
target/arm: Implement HACR_EL2
arm: Allow system registers for KVM guests to be changed by QEMU code
MAINTAINERS: Remove Peter Crosthwaite from various entries
hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
hw/arm/armsse: Fix miswiring of expansion IRQs
Richard Henderson (14):
target/arm: Force result size into dp after operation
target/arm: Restructure disas_fp_int_conv
target/arm: Rely on optimization within tcg_gen_gvec_or
target/arm: Use vector minmax expanders for aarch64
target/arm: Use vector minmax expanders for aarch32
target/arm: Use tcg integer min/max primitives for neon
target/arm: Remove neon min/max helpers
target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
target/arm: Fix arm_cpu_dump_state vs FPSCR
target/arm: Split out flags setting from vfp compares
target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
target/arm: Split out FPSCR.QC to a vector field
target/arm: Use vector operations for saturation
target/arm: Add missing clear_tail calls
Sandra Loosemore (1):
gdbstub: Send a reply to the vKill packet.
target/arm/cpu.h | 50 ++++++++-
target/arm/helper.h | 45 +++++---
target/arm/translate.h | 4 +
gdbstub.c | 1 +
hw/arm/armsse.c | 2 +-
hw/intc/armv7m_nvic.c | 4 +-
linux-user/elfload.c | 1 +
target/arm/helper-a64.c | 4 +-
target/arm/helper.c | 228 ++++++++++++++++++++++++++++++++--------
target/arm/kvm32.c | 20 +---
target/arm/kvm64.c | 2 +
target/arm/machine.c | 2 +-
target/arm/neon_helper.c | 14 +--
target/arm/translate-a64.c | 171 +++++++++++++++---------------
target/arm/translate-sve.c | 6 +-
target/arm/translate.c | 251 ++++++++++++++++++++++++++++++++++-----------
target/arm/vec_helper.c | 134 +++++++++++++++++++++++-
MAINTAINERS | 4 -
18 files changed, 687 insertions(+), 256 deletions(-)
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2017-06-01 17:10 Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2017-06-01 17:10 UTC (permalink / raw)
To: qemu-devel
ARM pullreq; contains some patches that arrived while I
was on holiday, plus the series I sent off before going
away, which got reviewed while I was away.
thanks
-- PMM
The following changes since commit c077a998eb3fcae2d048e3baeb5bc592d30fddde:
Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20170531' into staging (2017-06-01 15:50:40 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170601
for you to fetch changes up to cdc58be430b0bdeaef282e2e70f8135ae531616d:
hw/arm/virt: fdt: generate distance-map when needed (2017-06-01 17:27:07 +0100)
----------------------------------------------------------------
target-arm queue:
* virt: numa: provide ACPI distance info when needed
* aspeed: fix i2c controller bugs
* aspeed: add temperature sensor device
* M profile: support MPU
* gicv3: fix mishandling of BPR1, VBPR1
* load_uboot_image: don't assume a full header read
* libvixl: Correct build failures on NetBSD
----------------------------------------------------------------
Andrew Jones (3):
load_uboot_image: don't assume a full header read
hw/arm/virt-acpi-build: build SLIT when needed
hw/arm/virt: fdt: generate distance-map when needed
Cédric Le Goater (6):
aspeed/i2c: improve command handling
aspeed/i2c: handle LAST command under the RX command
aspeed/i2c: introduce a state machine
aspeed: add some I2C devices to the Aspeed machines
hw/misc: add a TMP42{1,2,3} device model
aspeed: add a temp sensor device on I2C bus 3
Kamil Rytarowski (1):
libvixl: Correct build failures on NetBSD
Michael Davidsaver (4):
armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
armv7m: Implement M profile default memory map
armv7m: Classify faults as MemManage or BusFault
arm: add MPU support to M profile CPUs
Peter Maydell (12):
hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1
hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum
hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
arm: Add support for M profile CPUs having different MMU index semantics
arm: Use different ARMMMUIdx values for M profile
arm: Clean up handling of no-MPU PMSA CPUs
arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
arm: Don't let no-MPU PMSA cores write to SCTLR.M
arm: Remove unnecessary check on cpu->pmsav7_dregion
arm: All M profile cores are PMSA
arm: Implement HFNMIENA support for M profile MPU
Wei Huang (1):
target/arm: clear PMUVER field of AA64DFR0 when vPMU=off
disas/libvixl/Makefile.objs | 3 +
hw/misc/Makefile.objs | 1 +
target/arm/cpu.h | 118 ++++++++++--
target/arm/translate.h | 2 +-
hw/arm/aspeed.c | 36 ++++
hw/arm/virt-acpi-build.c | 4 +
hw/arm/virt.c | 21 +++
hw/core/loader.c | 3 +-
hw/i2c/aspeed_i2c.c | 65 ++++++-
hw/intc/arm_gicv3_cpuif.c | 50 ++++-
hw/intc/armv7m_nvic.c | 104 +++++++++++
hw/misc/tmp421.c | 401 ++++++++++++++++++++++++++++++++++++++++
target/arm/cpu.c | 28 ++-
target/arm/helper.c | 338 ++++++++++++++++++++++-----------
target/arm/machine.c | 7 +-
target/arm/op_helper.c | 3 +-
target/arm/translate-a64.c | 18 +-
target/arm/translate.c | 14 +-
default-configs/arm-softmmu.mak | 1 +
19 files changed, 1060 insertions(+), 157 deletions(-)
create mode 100644 hw/misc/tmp421.c
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2017-02-28 12:41 Peter Maydell
@ 2017-02-28 15:59 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2017-02-28 15:59 UTC (permalink / raw)
To: QEMU Developers
On 28 February 2017 at 12:41, Peter Maydell <peter.maydell@linaro.org> wrote:
> v1->v2 changes: drop the sd card-reparenting patch
> and the 2 raspi2 patches that depend on it.
>
> -- PMM
>
> The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
>
> for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
>
> hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * raspi2: implement RNG module
> * raspi2: implement new SD card controller (but don't wire it up)
> * sdhci: bugfixes for block transfers
> * virt: fix cpu object reference leak
> * Add missing fp_access_check() to aarch64 crypto instructions
> * cputlb: Don't assume do_unassigned_access() never returns
> * virt: Add a user option to disallow ITS instantiation
> * i.MX timers: fix reset handling
> * ARMv7M NVIC: rewrite to fix broken priority handling and masking
> * exynos: Fix proper mapping of CPUs by providing real cluster ID
> * exynos: Fix Linux kernel division by zero for PLLs
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2017-02-28 12:41 Peter Maydell
2017-02-28 15:59 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2017-02-28 12:41 UTC (permalink / raw)
To: qemu-devel
v1->v2 changes: drop the sd card-reparenting patch
and the 2 raspi2 patches that depend on it.
-- PMM
The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
----------------------------------------------------------------
target-arm queue:
* raspi2: implement RNG module
* raspi2: implement new SD card controller (but don't wire it up)
* sdhci: bugfixes for block transfers
* virt: fix cpu object reference leak
* Add missing fp_access_check() to aarch64 crypto instructions
* cputlb: Don't assume do_unassigned_access() never returns
* virt: Add a user option to disallow ITS instantiation
* i.MX timers: fix reset handling
* ARMv7M NVIC: rewrite to fix broken priority handling and masking
* exynos: Fix proper mapping of CPUs by providing real cluster ID
* exynos: Fix Linux kernel division by zero for PLLs
----------------------------------------------------------------
Clement Deschamps (1):
bcm2835_sdhost: add bcm2835 sdhost controller
Eric Auger (1):
hw/arm/virt: Add a user option to disallow ITS instantiation
Igor Mammedov (1):
hw/arm/virt: fix cpu object reference leak
Krzysztof Kozlowski (2):
hw/arm/exynos: Fix Linux kernel division by zero for PLLs
hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
Kurban Mallachiev (1):
ARM i.MX timers: fix reset handling
Marcin Chojnacki (1):
target-arm: Implement BCM2835 hardware RNG
Michael Davidsaver (5):
armv7m: Rewrite NVIC to not use any GIC code
arm: gic: Remove references to NVIC
armv7m: Escalate exceptions to HardFault if necessary
armv7m: Simpler and faster exception start
armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
Nick Reilly (1):
Add missing fp_access_check() to aarch64 crypto instructions
Peter Maydell (10):
bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
cputlb: Don't assume do_unassigned_access() never returns
armv7m: Rename nvic_state to NVICState
armv7m: Implement reading and writing of PRIGROUP
armv7m: Fix condition check for taking exceptions
armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
armv7m: Extract "exception taken" code into functions
armv7m: Check exception return consistency
armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
armv7m: Allow SHCSR writes to change pending and active bits
Prasad J Pandit (4):
sd: sdhci: mask transfer mode register value
sd: sdhci: check transfer mode register in multi block transfer
sd: sdhci: conditionally invoke multi block transfer
sd: sdhci: Remove block count enable check in single block transfers
hw/misc/Makefile.objs | 3 +-
hw/sd/Makefile.objs | 1 +
hw/intc/gic_internal.h | 7 +-
include/hw/arm/bcm2835_peripherals.h | 2 +
include/hw/arm/virt.h | 1 +
include/hw/misc/bcm2835_rng.h | 27 ++
include/hw/sd/bcm2835_sdhost.h | 48 ++
target/arm/cpu.h | 23 +-
cputlb.c | 15 +-
hw/arm/bcm2835_peripherals.c | 15 +
hw/arm/exynos4210.c | 18 +
hw/arm/virt.c | 32 +-
hw/intc/arm_gic.c | 31 +-
hw/intc/arm_gic_common.c | 23 +-
hw/intc/armv7m_nvic.c | 885 ++++++++++++++++++++++++++++-------
hw/misc/bcm2835_rng.c | 149 ++++++
hw/misc/exynos4210_clk.c | 164 +++++++
hw/sd/bcm2835_sdhost.c | 429 +++++++++++++++++
hw/sd/sdhci.c | 25 +-
hw/timer/imx_gpt.c | 33 +-
linux-user/main.c | 1 +
target/arm/cpu.c | 16 +-
target/arm/helper.c | 245 +++++++---
target/arm/translate-a64.c | 12 +
target/arm/translate.c | 8 +-
hw/intc/trace-events | 15 +
26 files changed, 1897 insertions(+), 331 deletions(-)
create mode 100644 include/hw/misc/bcm2835_rng.h
create mode 100644 include/hw/sd/bcm2835_sdhost.h
create mode 100644 hw/misc/bcm2835_rng.c
create mode 100644 hw/misc/exynos4210_clk.c
create mode 100644 hw/sd/bcm2835_sdhost.c
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-10-27 15:57 ` Peter Maydell
@ 2015-10-27 16:00 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-10-27 16:00 UTC (permalink / raw)
To: QEMU Developers; +Cc: Jean-Christophe Dubois
On 27 October 2015 at 15:57, Peter Maydell <peter.maydell@linaro.org> wrote:
> I will squash in the fix:
>
> diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
> index 45cf00d..261608d 100644
> --- a/hw/char/imx_serial.c
> +++ b/hw/char/imx_serial.c
> @@ -318,8 +318,7 @@ static void imx_serial_realize(DeviceState *dev,
> Error **errp)
> qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
> imx_event, s);
> } else {
> - DPRINTF("No char dev for uart at 0x%" HWADDR_PRIx "\n",
> - s->iomem.ram_addr);
> + DPRINTF("No char dev for uart"\n");
> }
> }
...without the stray extra '"', obviously :-)
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-10-27 14:33 Peter Maydell
@ 2015-10-27 15:57 ` Peter Maydell
2015-10-27 16:00 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-10-27 15:57 UTC (permalink / raw)
To: QEMU Developers; +Cc: Jean-Christophe Dubois
On 27 October 2015 at 14:33, Peter Maydell <peter.maydell@linaro.org> wrote:
> Here's the target-arm queue for 2.5.
>
> Edgar's stage 2 patchset has been on list in various forms for
> a while, and in any case the code doesn't kick in unless the
> CPU has the EL2 feature bit set, which nothing in master does.
>
> I'm probably going to start getting a bit stricter about only
> small features or bug fixes now, with a week and a half to hardfreeze.
>
> thanks
> -- PMM
>
> The following changes since commit 7e038b94e74e1c2d1b3598e2e4b0b5c8b79a7278:
>
> Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2015-10-27 10:10:46 +0000)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151027
>
> for you to fetch changes up to e194d166b4bc00fb0ce75f21eed67a9e94a25f65:
>
> target-arm: Add support for S1 + S2 MMU translations (2015-10-27 14:04:19 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * more EL2 preparation: handling for stage 2 translations
> * standardize debug macros in i.MX devices
> * improve error message in a corner case for virt board
> * disable live migration of KVM GIC if the kernel can't handle it
> * add SPSR_(ABT|UND|IRQ|FIQ) registers
> * handle non-executable page-straddling Thumb instructions
> * fix a "no 64-bit EL2" assumption in arm_excp_unmasked()
There's a format string error in the i.MX patches which means
it won't compile on 32-bit systems or OSX:
/home/petmay01/qemu/hw/char/imx_serial.c: In function 'imx_serial_realize':
/home/petmay01/qemu/hw/char/imx_serial.c:321:9: error: format '%llx'
expects argument of type 'long long unsigned int', but argument 5 has
type 'ram_addr_t' [-Werror=format=]
DPRINTF("No char dev for uart at 0x%" HWADDR_PRIx "\n",
^
We could fix this just by fixing the format string (to
"0x" RAM_ADDR_FMT rather than "0x%" HWADDR_PRIx), but this
code is wrong anyway, because it is fishing in the MemoryRegion
struct, which is clearly documented as:
/* All fields are private - violators will be prosecuted */
So we should just drop that.
I will squash in the fix:
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 45cf00d..261608d 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -318,8 +318,7 @@ static void imx_serial_realize(DeviceState *dev,
Error **errp)
qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
imx_event, s);
} else {
- DPRINTF("No char dev for uart at 0x%" HWADDR_PRIx "\n",
- s->iomem.ram_addr);
+ DPRINTF("No char dev for uart"\n");
}
}
and respin.
thanks
-- PMM
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2015-10-27 14:33 Peter Maydell
2015-10-27 15:57 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-10-27 14:33 UTC (permalink / raw)
To: qemu-devel
Here's the target-arm queue for 2.5.
Edgar's stage 2 patchset has been on list in various forms for
a while, and in any case the code doesn't kick in unless the
CPU has the EL2 feature bit set, which nothing in master does.
I'm probably going to start getting a bit stricter about only
small features or bug fixes now, with a week and a half to hardfreeze.
thanks
-- PMM
The following changes since commit 7e038b94e74e1c2d1b3598e2e4b0b5c8b79a7278:
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2015-10-27 10:10:46 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151027
for you to fetch changes up to e194d166b4bc00fb0ce75f21eed67a9e94a25f65:
target-arm: Add support for S1 + S2 MMU translations (2015-10-27 14:04:19 +0000)
----------------------------------------------------------------
target-arm queue:
* more EL2 preparation: handling for stage 2 translations
* standardize debug macros in i.MX devices
* improve error message in a corner case for virt board
* disable live migration of KVM GIC if the kernel can't handle it
* add SPSR_(ABT|UND|IRQ|FIQ) registers
* handle non-executable page-straddling Thumb instructions
* fix a "no 64-bit EL2" assumption in arm_excp_unmasked()
----------------------------------------------------------------
Andrew Jones (1):
hw/arm/virt: don't use a15memmap directly
Edgar E. Iglesias (14):
target-arm: Add HPFAR_EL2
target-arm: lpae: Make t0sz and t1sz signed integers
target-arm: lpae: Move declaration of t0sz and t1sz
target-arm: Add support for AArch32 S2 negative t0sz
target-arm: lpae: Replace tsz with computed inputsize
target-arm: lpae: Rename granule_sz to stride
target-arm: Add computation of starting level for S2 PTW
target-arm: Add support for S2 page-table protection bits
target-arm: Avoid inline for get_phys_addr
target-arm: Add ARMMMUFaultInfo
target-arm: Add S2 translation to 64bit S1 PTWs
target-arm: Add S2 translation to 32bit S1 PTWs
target-arm: Route S2 MMU faults to EL2
target-arm: Add support for S1 + S2 MMU translations
Jean-Christophe Dubois (8):
i.MX: Standardize i.MX serial debug.
i.MX: Standardize i.MX GPIO debug
i.MX: Standardize i.MX I2C debug
i.MX: Standardize i.MX AVIC debug
i.MX: Standardize i.MX CCM debug
i.MX: Standardize i.MX FEC debug
i.MX: Standardize i.MX EPIT debug
i.MX: Standardize i.MX GPT debug
Pavel Fedin (1):
arm_gic_kvm: Disable live migration if not supported
Peter Maydell (2):
target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked()
target-arm/translate.c: Handle non-executable page-straddling Thumb insns
Soren Brinkmann (1):
target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)
hw/arm/virt.c | 25 ++-
hw/char/imx_serial.c | 51 +++--
hw/gpio/imx_gpio.c | 27 +--
hw/i2c/imx_i2c.c | 43 ++---
hw/intc/arm_gic_kvm.c | 22 +--
hw/intc/imx_avic.c | 44 ++---
hw/misc/imx_ccm.c | 34 ++--
hw/net/imx_fec.c | 64 +++----
hw/timer/imx_epit.c | 48 ++---
hw/timer/imx_gpt.c | 56 +++---
include/hw/intc/arm_gic_common.h | 1 +
target-arm/cpu.h | 83 ++++++---
target-arm/helper.c | 388 ++++++++++++++++++++++++++++++++-------
target-arm/internals.h | 40 +++-
target-arm/op_helper.c | 18 +-
target-arm/translate.c | 45 ++++-
16 files changed, 680 insertions(+), 309 deletions(-)
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-09-07 9:43 Peter Maydell
@ 2015-09-07 10:22 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-07 10:22 UTC (permalink / raw)
To: QEMU Developers
On 7 September 2015 at 10:43, Peter Maydell <peter.maydell@linaro.org> wrote:
> Version 2 of this pullreq, with a trivial fix squashed in to delete
> an unused function imx_i2c_direction_is_tx().
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2015-09-07 9:43 Peter Maydell
2015-09-07 10:22 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-09-07 9:43 UTC (permalink / raw)
To: qemu-devel
Version 2 of this pullreq, with a trivial fix squashed in to delete
an unused function imx_i2c_direction_is_tx().
thanks
-- PMM
The following changes since commit b597aa037dbd98014c8dec3d69a5e2240f432533:
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2015-09-04' into staging (2015-09-04 17:37:50 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150907
for you to fetch changes up to 8d45c54d4fd3612bd616afcc5c278394f312927b:
arm/virt: Add full-sized CPU affinity handling (2015-09-07 10:39:31 +0100)
----------------------------------------------------------------
target-arm queue:
* cleanup to use g_new() and friends
* support semihosting in A64
* add SMBIOS support to mach-virt
* remove hw_error() usages
* fix bug in the AArch32:AArch64 register mapping
* add a second PCI memory window in highmem on virt board
* fix bug in arm_excp_unmasked()
* add i.MX31 SoC
* remove restriction on handling affinity values in virt board
----------------------------------------------------------------
Christopher Covington (1):
target-arm: Improve semihosting debug prints
Jean-Christophe Dubois (8):
i.MX: Add SOC support for i.MX31
i.MX: KZM: use standalone i.MX31 SOC support
i.MX: Add I2C controller emulator
i.MX: Add FEC Ethernet Emulator
i.MX: Add SOC support for i.MX25
i.MX: Add the i.MX25 PDK platform
i.MX: Add qtest support for I2C device emulator.
i.MX: Add i2C devices to i.MX31 SOC
Markus Armbruster (1):
arm: Use g_new() & friends where that makes obvious sense
Pavel Fedin (3):
hw/arm/virt: Add high MMIO PCI region, 512G in size
target-arm: Refactor CPU affinity handling
arm/virt: Add full-sized CPU affinity handling
Peter Crosthwaite (2):
arm: cpu: assert() on no-EL2 virt IRQ error condition.
arm: Remove hw_error() usages.
Peter Maydell (8):
target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
gdbstub: Implement gdb_do_syscallv()
target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
include/exec/softmmu-semi.h: Add support for 64-bit values
target-arm/arm-semi.c: Support widening APIs to 64 bits
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
Sergey Sorokin (2):
target-arm: Fix AArch32:AArch64 general-purpose register mapping
target-arm: Fix arm_excp_unmasked() function
Wei Huang (2):
smbios: add smbios 3.0 support
smbios: implement smbios support for mach-virt
default-configs/arm-softmmu.mak | 7 +
gdbstub.c | 14 +-
hw/arm/Makefile.objs | 4 +-
hw/arm/fsl-imx25.c | 273 +++++++++++++++
hw/arm/fsl-imx31.c | 246 ++++++++++++++
hw/arm/imx25_pdk.c | 159 +++++++++
hw/arm/kzm.c | 205 ++++++-----
hw/arm/omap1.c | 30 +-
hw/arm/omap2.c | 15 +-
hw/arm/pxa2xx.c | 11 +-
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/arm/virt-acpi-build.c | 17 +-
hw/arm/virt.c | 126 ++++++-
hw/char/imx_serial.c | 35 --
hw/char/omap_uart.c | 3 +-
hw/display/omap_dss.c | 3 +-
hw/display/omap_lcdc.c | 3 +-
hw/dma/omap_dma.c | 6 +-
hw/gpio/omap_gpio.c | 4 +-
hw/i2c/Makefile.objs | 1 +
hw/i2c/imx_i2c.c | 334 ++++++++++++++++++
hw/i386/pc_piix.c | 3 +-
hw/i386/pc_q35.c | 3 +-
hw/input/stellaris_input.c | 4 +-
hw/misc/omap_clk.c | 2 +-
hw/misc/omap_gpmc.c | 3 +-
hw/misc/omap_sdrc.c | 3 +-
hw/net/Makefile.objs | 1 +
hw/net/imx_fec.c | 709 +++++++++++++++++++++++++++++++++++++++
hw/sd/omap_mmc.c | 6 +-
hw/smbios/smbios.c | 84 +++--
hw/ssi/omap_spi.c | 3 +-
hw/timer/imx_epit.c | 11 -
hw/timer/imx_gpt.c | 11 -
hw/timer/omap_gptimer.c | 3 +-
include/exec/gdbstub.h | 27 ++
include/exec/softmmu-semi.h | 18 +
include/hw/arm/fsl-imx25.h | 234 +++++++++++++
include/hw/arm/fsl-imx31.h | 110 ++++++
include/hw/arm/imx.h | 26 --
include/hw/arm/virt-acpi-build.h | 1 +
include/hw/arm/virt.h | 1 +
include/hw/i2c/imx_i2c.h | 87 +++++
include/hw/net/imx_fec.h | 113 +++++++
include/hw/smbios/smbios.h | 62 +++-
linux-user/main.c | 3 +
qemu-options.hx | 2 +-
target-arm/arm-semi.c | 171 +++++++---
target-arm/cpu-qom.h | 13 +
target-arm/cpu.c | 11 +-
target-arm/cpu.h | 9 +-
target-arm/helper-a64.c | 6 +
target-arm/helper.c | 78 +++--
target-arm/internals.h | 2 +
target-arm/kvm32.c | 3 +-
target-arm/kvm64.c | 3 +-
target-arm/translate-a64.c | 24 +-
tests/Makefile | 3 +
tests/bios-tables-test.c | 6 +-
tests/ds1338-test.c | 78 +++++
tests/libqos/i2c-imx.c | 209 ++++++++++++
tests/libqos/i2c.h | 3 +
63 files changed, 3243 insertions(+), 406 deletions(-)
create mode 100644 hw/arm/fsl-imx25.c
create mode 100644 hw/arm/fsl-imx31.c
create mode 100644 hw/arm/imx25_pdk.c
create mode 100644 hw/i2c/imx_i2c.c
create mode 100644 hw/net/imx_fec.c
create mode 100644 include/hw/arm/fsl-imx25.h
create mode 100644 include/hw/arm/fsl-imx31.h
delete mode 100644 include/hw/arm/imx.h
create mode 100644 include/hw/i2c/imx_i2c.h
create mode 100644 include/hw/net/imx_fec.h
create mode 100644 tests/ds1338-test.c
create mode 100644 tests/libqos/i2c-imx.c
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-09-04 15:05 Peter Maydell
@ 2015-09-07 9:40 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-09-07 9:40 UTC (permalink / raw)
To: QEMU Developers; +Cc: Jean-Christophe Dubois
On 4 September 2015 at 16:05, Peter Maydell <peter.maydell@linaro.org> wrote:
> Another target-arm queue flush. I expect there'll be another
> lot next week...
>
>
> The following changes since commit b041066421e8dcc7d080dfcfd83551c9c9f24ade:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging (2015-09-03 16:17:28 +0100)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150904
>
> for you to fetch changes up to d9fd6f3874a326033a446a6db8cd113bf4015e6a:
>
> arm/virt: Add full-sized CPU affinity handling (2015-09-04 15:49:54 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * cleanup to use g_new() and friends
> * support semihosting in A64
> * add SMBIOS support to mach-virt
> * remove hw_error() usages
> * fix bug in the AArch32:AArch64 register mapping
> * add a second PCI memory window in highmem on virt board
> * fix bug in arm_excp_unmasked()
> * add i.MX31 SoC
> * remove restriction on handling affinity values in virt board
The clang build complains about an unused function in imx_i2c.c.
I'm going to squash in this fix to the offending patch and resend
the pullreq (cover letter).
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
index 2568837..8474872 100644
--- a/hw/i2c/imx_i2c.c
+++ b/hw/i2c/imx_i2c.c
@@ -65,11 +65,6 @@ static inline bool imx_i2c_is_master(IMXI2CState *s)
return s->i2cr & I2CR_MSTA;
}
-static inline bool imx_i2c_direction_is_tx(IMXI2CState *s)
-{
- return s->i2cr & I2CR_MTX;
-}
-
static void imx_i2c_reset(DeviceState *dev)
{
IMXI2CState *s = IMX_I2C(dev);
thanks
-- PMM
^ permalink raw reply related [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2015-09-04 15:05 Peter Maydell
2015-09-07 9:40 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-09-04 15:05 UTC (permalink / raw)
To: qemu-devel
Another target-arm queue flush. I expect there'll be another
lot next week...
The following changes since commit b041066421e8dcc7d080dfcfd83551c9c9f24ade:
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging (2015-09-03 16:17:28 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150904
for you to fetch changes up to d9fd6f3874a326033a446a6db8cd113bf4015e6a:
arm/virt: Add full-sized CPU affinity handling (2015-09-04 15:49:54 +0100)
----------------------------------------------------------------
target-arm queue:
* cleanup to use g_new() and friends
* support semihosting in A64
* add SMBIOS support to mach-virt
* remove hw_error() usages
* fix bug in the AArch32:AArch64 register mapping
* add a second PCI memory window in highmem on virt board
* fix bug in arm_excp_unmasked()
* add i.MX31 SoC
* remove restriction on handling affinity values in virt board
----------------------------------------------------------------
Christopher Covington (1):
target-arm: Improve semihosting debug prints
Jean-Christophe Dubois (8):
i.MX: Add SOC support for i.MX31
i.MX: KZM: use standalone i.MX31 SOC support
i.MX: Add I2C controller emulator
i.MX: Add FEC Ethernet Emulator
i.MX: Add SOC support for i.MX25
i.MX: Add the i.MX25 PDK platform
i.MX: Add qtest support for I2C device emulator.
i.MX: Add i2C devices to i.MX31 SOC
Markus Armbruster (1):
arm: Use g_new() & friends where that makes obvious sense
Pavel Fedin (3):
hw/arm/virt: Add high MMIO PCI region, 512G in size
target-arm: Refactor CPU affinity handling
arm/virt: Add full-sized CPU affinity handling
Peter Crosthwaite (2):
arm: cpu: assert() on no-EL2 virt IRQ error condition.
arm: Remove hw_error() usages.
Peter Maydell (8):
target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
gdbstub: Implement gdb_do_syscallv()
target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
include/exec/softmmu-semi.h: Add support for 64-bit values
target-arm/arm-semi.c: Support widening APIs to 64 bits
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
Sergey Sorokin (2):
target-arm: Fix AArch32:AArch64 general-purpose register mapping
target-arm: Fix arm_excp_unmasked() function
Wei Huang (2):
smbios: add smbios 3.0 support
smbios: implement smbios support for mach-virt
default-configs/arm-softmmu.mak | 7 +
gdbstub.c | 14 +-
hw/arm/Makefile.objs | 4 +-
hw/arm/fsl-imx25.c | 273 +++++++++++++++
hw/arm/fsl-imx31.c | 246 ++++++++++++++
hw/arm/imx25_pdk.c | 159 +++++++++
hw/arm/kzm.c | 205 ++++++-----
hw/arm/omap1.c | 30 +-
hw/arm/omap2.c | 15 +-
hw/arm/pxa2xx.c | 11 +-
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/arm/virt-acpi-build.c | 17 +-
hw/arm/virt.c | 126 ++++++-
hw/char/imx_serial.c | 35 --
hw/char/omap_uart.c | 3 +-
hw/display/omap_dss.c | 3 +-
hw/display/omap_lcdc.c | 3 +-
hw/dma/omap_dma.c | 6 +-
hw/gpio/omap_gpio.c | 4 +-
hw/i2c/Makefile.objs | 1 +
hw/i2c/imx_i2c.c | 339 +++++++++++++++++++
hw/i386/pc_piix.c | 3 +-
hw/i386/pc_q35.c | 3 +-
hw/input/stellaris_input.c | 4 +-
hw/misc/omap_clk.c | 2 +-
hw/misc/omap_gpmc.c | 3 +-
hw/misc/omap_sdrc.c | 3 +-
hw/net/Makefile.objs | 1 +
hw/net/imx_fec.c | 709 +++++++++++++++++++++++++++++++++++++++
hw/sd/omap_mmc.c | 6 +-
hw/smbios/smbios.c | 84 +++--
hw/ssi/omap_spi.c | 3 +-
hw/timer/imx_epit.c | 11 -
hw/timer/imx_gpt.c | 11 -
hw/timer/omap_gptimer.c | 3 +-
include/exec/gdbstub.h | 27 ++
include/exec/softmmu-semi.h | 18 +
include/hw/arm/fsl-imx25.h | 234 +++++++++++++
include/hw/arm/fsl-imx31.h | 110 ++++++
include/hw/arm/imx.h | 26 --
include/hw/arm/virt-acpi-build.h | 1 +
include/hw/arm/virt.h | 1 +
include/hw/i2c/imx_i2c.h | 87 +++++
include/hw/net/imx_fec.h | 113 +++++++
include/hw/smbios/smbios.h | 62 +++-
linux-user/main.c | 3 +
qemu-options.hx | 2 +-
target-arm/arm-semi.c | 171 +++++++---
target-arm/cpu-qom.h | 13 +
target-arm/cpu.c | 11 +-
target-arm/cpu.h | 9 +-
target-arm/helper-a64.c | 6 +
target-arm/helper.c | 78 +++--
target-arm/internals.h | 2 +
target-arm/kvm32.c | 3 +-
target-arm/kvm64.c | 3 +-
target-arm/translate-a64.c | 24 +-
tests/Makefile | 3 +
tests/bios-tables-test.c | 6 +-
tests/ds1338-test.c | 78 +++++
tests/libqos/i2c-imx.c | 209 ++++++++++++
tests/libqos/i2c.h | 3 +
63 files changed, 3248 insertions(+), 406 deletions(-)
create mode 100644 hw/arm/fsl-imx25.c
create mode 100644 hw/arm/fsl-imx31.c
create mode 100644 hw/arm/imx25_pdk.c
create mode 100644 hw/i2c/imx_i2c.c
create mode 100644 hw/net/imx_fec.c
create mode 100644 include/hw/arm/fsl-imx25.h
create mode 100644 include/hw/arm/fsl-imx31.h
delete mode 100644 include/hw/arm/imx.h
create mode 100644 include/hw/i2c/imx_i2c.h
create mode 100644 include/hw/net/imx_fec.h
create mode 100644 tests/ds1338-test.c
create mode 100644 tests/libqos/i2c-imx.c
^ permalink raw reply [flat|nested] 67+ messages in thread
* Re: [Qemu-devel] [PULL 00/27] target-arm queue
2015-08-13 10:44 Peter Maydell
@ 2015-08-13 14:06 ` Peter Maydell
0 siblings, 0 replies; 67+ messages in thread
From: Peter Maydell @ 2015-08-13 14:06 UTC (permalink / raw)
To: QEMU Developers
On 13 August 2015 at 11:44, Peter Maydell <peter.maydell@linaro.org> wrote:
> Flushing the accumulated changes from during the 2.4 freeze...
>
> -- PMM
>
> The following changes since commit ca0e5d8b0d065a95d0f9042f71b2ace45b015596:
>
> Open 2.5 development tree (2015-08-11 23:15:55 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150813
>
> for you to fetch changes up to f7a6785e12d834d05200b0595070db453344b25d:
>
> i.MX: Fix UART driver to work with unitialized "chardev" device (2015-08-13 11:26:22 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * i.MX code cleanup/refactorings
> * i.MX UART fix to work with uninitialized chardev
> * minor GIC code refactorings
> * implement the ARM Secure physical timer
> * implement the ARM Hypervisor timer
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 67+ messages in thread
* [Qemu-devel] [PULL 00/27] target-arm queue
@ 2015-08-13 10:44 Peter Maydell
2015-08-13 14:06 ` Peter Maydell
0 siblings, 1 reply; 67+ messages in thread
From: Peter Maydell @ 2015-08-13 10:44 UTC (permalink / raw)
To: qemu-devel
Flushing the accumulated changes from during the 2.4 freeze...
-- PMM
The following changes since commit ca0e5d8b0d065a95d0f9042f71b2ace45b015596:
Open 2.5 development tree (2015-08-11 23:15:55 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150813
for you to fetch changes up to f7a6785e12d834d05200b0595070db453344b25d:
i.MX: Fix UART driver to work with unitialized "chardev" device (2015-08-13 11:26:22 +0100)
----------------------------------------------------------------
target-arm queue:
* i.MX code cleanup/refactorings
* i.MX UART fix to work with uninitialized chardev
* minor GIC code refactorings
* implement the ARM Secure physical timer
* implement the ARM Hypervisor timer
----------------------------------------------------------------
Edgar E. Iglesias (7):
target-arm: Add CNTVOFF_EL2
target-arm: Add CNTHCTL_EL2
target-arm: Rename and move gt_cnt_reset
target-arm: Pass timeridx as argument to various timer functions
target-arm: Add the Hypervisor timer
hw/arm/virt: Replace magic IRQ constants with macros
hw/arm/virt: Connect the Hypervisor timer
Jean-Christophe Dubois (12):
i.MX: Split UART emulator in a header file and a source file
i.MX: Move serial initialization to init/realize of DeviceClass.
i.MX:Fix Coding style for UART emulator.
i.MX: Split AVIC emulator in a header file and a source file
i.MX: Fix Coding style for AVIC emulator.
i.MX: Split CCM emulator in a header file and a source file
i.MX: Fix Coding style for CCM emulator
i.MX: Split EPIT emulator in a header file and a source file
i.MX: Fix Coding style for EPIT emulator
i.MX: Split GPT emulator in a header file and a source file
i.MX: Fix Coding style for GPT emulator
i.MX: Fix UART driver to work with unitialized "chardev" device
Pavel Fedin (3):
Merge memory_region_init_reservation() into memory_region_init_io()
hw/arm/gic: Kill code duplication
Introduce gic_class_name() instead of repeating condition
Peter Maydell (5):
target-arm: Add debug check for mismatched cpreg resets
target-arm: Add the AArch64 view of the Secure physical timer
target-arm: Add AArch32 banked register access to secure physical timer
hw/arm/virt: Wire up secure timer interrupt
hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts
hw/arm/kzm.c | 5 +-
hw/arm/virt.c | 32 ++--
hw/char/imx_serial.c | 159 +++++------------
hw/cpu/a15mpcore.c | 29 ++--
hw/intc/arm_gic.c | 64 ++-----
hw/intc/arm_gic_common.c | 41 +++++
hw/intc/arm_gic_kvm.c | 28 +--
hw/intc/imx_avic.c | 56 ++----
hw/misc/imx_ccm.c | 81 +--------
hw/timer/imx_epit.c | 64 +------
hw/timer/imx_gpt.c | 85 +--------
include/exec/memory.h | 14 +-
include/hw/arm/imx.h | 12 +-
include/hw/char/imx_serial.h | 102 +++++++++++
include/hw/intc/arm_gic_common.h | 3 +
include/hw/intc/imx_avic.h | 55 ++++++
include/hw/misc/imx_ccm.h | 91 ++++++++++
include/hw/timer/imx_epit.h | 79 +++++++++
include/hw/timer/imx_gpt.h | 107 ++++++++++++
memory.c | 10 +-
target-arm/cpu-qom.h | 2 +
target-arm/cpu.c | 27 +++
target-arm/cpu.h | 9 +-
target-arm/helper.c | 367 +++++++++++++++++++++++++++++++++++----
target-arm/kvm_arm.h | 5 +
25 files changed, 1003 insertions(+), 524 deletions(-)
create mode 100644 include/hw/char/imx_serial.h
create mode 100644 include/hw/intc/imx_avic.h
create mode 100644 include/hw/misc/imx_ccm.h
create mode 100644 include/hw/timer/imx_epit.h
create mode 100644 include/hw/timer/imx_gpt.h
^ permalink raw reply [flat|nested] 67+ messages in thread
end of thread, other threads:[~2019-02-15 2:45 UTC | newest]
Thread overview: 67+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 01/27] STM32F205: Remove the individual device variables Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 02/27] STM32F2xx: Display PWM duty cycle from timer Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 03/27] STM32F2xx: Add the ADC device Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 04/27] STM32F2xx: Add the SPI device Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 05/27] irq: Add a new irq device that allows the ORing of lines Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 06/27] STM32F205: Connect the ADC devices Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 07/27] STM32F205: Connect the SPI devices Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 08/27] MAINTAINERS: Add Alistair to the maintainers list Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 09/27] mainstone: Fix incorrect key mapping for Enter key Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 10/27] mainstone: Add mapping for dot, slash and backspace Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 11/27] hw/arm: Fix Integrator/CM initialization Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 12/27] vmstateify tsc2005 Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 13/27] vmstateify tsc210x Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 14/27] hw/arm/virt: add 2.8 machine type Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 15/27] hw/intc/arm_gic(v3)_kvm: Initialize gsi routing Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 16/27] hw/intc/arm_gicv3_its: Implement ITS base class Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 17/27] target-arm: move gicv3_class_name from machine to kvm_arm.h Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 18/27] kvm-all: Pass requester ID to MSI routing functions Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 19/27] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 20/27] arm/virt: Add ITS to the virt board Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 21/27] ACPI: Add GIC Interrupt Translation Service Structure definition Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 22/27] ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 23/27] generic-loader: Add a generic loader Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 24/27] docs: Add a generic loader explanation document Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 25/27] cadence_gem: Fix priority queue out of bounds access Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 26/27] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 Peter Maydell
2016-10-14 6:44 ` Alex Bennée
2016-10-14 17:35 ` Peter Maydell
2016-10-04 13:19 ` [Qemu-devel] [PULL 00/27] target-arm queue no-reply
2016-10-04 13:24 ` Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2019-02-14 19:05 Peter Maydell
2019-02-14 19:56 ` no-reply
2019-02-14 20:30 ` no-reply
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2019-02-14 21:24 ` no-reply
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2019-02-15 0:07 ` no-reply
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2019-02-15 2:43 ` no-reply
2017-06-01 17:10 Peter Maydell
2017-02-28 12:41 Peter Maydell
2017-02-28 15:59 ` Peter Maydell
2015-10-27 14:33 Peter Maydell
2015-10-27 15:57 ` Peter Maydell
2015-10-27 16:00 ` Peter Maydell
2015-09-07 9:43 Peter Maydell
2015-09-07 10:22 ` Peter Maydell
2015-09-04 15:05 Peter Maydell
2015-09-07 9:40 ` Peter Maydell
2015-08-13 10:44 Peter Maydell
2015-08-13 14:06 ` Peter Maydell
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