* [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines
@ 2020-06-26 23:55 Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 01/12] npcm7xx: Add config symbol Havard Skinnemoen
` (13 more replies)
0 siblings, 14 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
Time for another refresh of this patchset. Sorry it took so long -- I've been
trying to figure out why the Winbond flash model isn't working with
npcm750-evb, and I'm fairly convinced the number of dummy cycles in DIO mode
should be 4, not 1. Unfortunately, I don't see any other machines using Winbond
flash in DIO mode, so it's hard to prove that it's correct. I'm planning to
post a libqos-based test suite separately.
I'm also planning to add the vbootrom to qemu as a submodule, similar to the
other roms, but not in this pathset (let me know if you do want me to include
this in the series).
I also pushed this and the previous two patchsets to my qemu fork on github.
The branches are named npcm7xx-v[1-3].
https://github.com/hskinnemoen/qemu
This patch series models enough of the Nuvoton NPCM730 and NPCM750 SoCs to boot
an OpenBMC image built for quanta-gsj. This includes device models for:
- Global Configuration Registers
- Clock Control
- Timers
- Fuses
- Memory Controller
- Flash Controller
These modules, along with the existing Cortex A9 CPU cores and built-in
peripherals, are integrated into a NPCM730 or NPCM750 SoC, which in turn form
the foundation for the quanta-gsj and npcm750-evb machines, respectively. The
two SoCs are very similar; the only difference is that NPCM730 is missing some
peripherals that NPCM750 has, and which are not considered essential for
datacenter use (e.g. graphics controllers). For more information, see
https://www.nuvoton.com/products/cloud-computing/ibmc/
Both quanta-gsj and npcm750-evb correspond to real boards supported by OpenBMC.
At the end of the series, qemu can boot an OpenBMC image built for one of these
boards with some minor modifications.
The patches in this series were developed by Google and reviewed by Nuvoton. We
will be maintaining the machine and peripheral support together.
The data sheet for these SoCs is not generally available. Please let me know if
more comments are needed to understand the device behavior.
Changes since v2:
- Simplified the MAINTAINERS entry.
- Added link to OpenPOWER jenkins for gsj BMC images.
- Reverted the smpboot change, back to byte swapping.
- Adapted to upstream API changes:
- sysbus_init_child_obj -> object_initialize_child
- object_property_set_bool -> qdev_realize / sysbus_realize
- ssi_create_slave_no_init -> qdev_new
- qdev_init_nofail -> qdev_realize_and_unref
- ssi_auto_connect_slaves removed
- Moved Boot ROM loading from soc to machine init.
- Plumbed power-on-straps property from GCR to the machine init code so it
can be properly initialized. Turns out npcm750 memory init doesn't work
without this. npcm730 is fine either way, though I'm not sure why.
- Reworked the flash init code so it looks more like aspeed (i.e. the flash
device gets added even if there's no drive).
Changes since v1 (requested by reviewers):
- Clarify the source of CLK reset values.
- Made smpboot a constant byte array, eliinated byte swapping.
- NPCM7xxState now stores an array of ARMCPUs, not pointers to ARMCPUs.
- Clarify why EL3 is disabled.
- Introduce NPCM7XX_NUM_IRQ constant.
- Set the number of CPUs according to SoC variant, and disallow command line
overrides (i.e. you can no longer override the number of CPUs with the -smp
parameter). This is trying to follow the spirit of
https://patchwork.kernel.org/patch/11595407/.
- Switch register operations to DEVICE_LITTLE_ENDIAN throughout.
- Machine documentation added (new patch).
Changes since v1 to support flash booting:
- GCR reset value changes to get past memory initialization when booting
from flash (patches 2 and 5):
- INTCR2 now indicates that the DDR controller is initialized.
- INTCR3 is initialized according to DDR memory size. A realize()
method was implemented to achieve this.
- Refactor the machine initialization a bit to make it easier to drop in
machine-specific flash initialization (patch 6).
- Extend the series with additional patches to enable booting from flash:
- Boot ROM (through the -bios option).
- OTP (fuse) controller.
- Memory Controller stub (just enough to skip memory training).
- Flash controller.
- Board-specific flash initialization.
Thanks for reviewing,
Havard
Havard Skinnemoen (12):
npcm7xx: Add config symbol
hw/misc: Add NPCM7xx System Global Control Registers device model
hw/misc: Add NPCM7xx Clock Controller device model
hw/timer: Add NPCM7xx Timer device model
hw/arm: Add NPCM730 and NPCM750 SoC models
hw/arm: Add two NPCM7xx-based machines
hw/arm: Load -bios image as a boot ROM for npcm7xx
hw/nvram: NPCM7xx OTP device model
hw/mem: Stubbed out NPCM7xx Memory Controller model
hw/ssi: NPCM7xx Flash Interface Unit device model
hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
docs/system: Add Nuvoton machine documentation
MAINTAINERS | 8 +
default-configs/arm-softmmu.mak | 1 +
docs/system/arm/nuvoton.rst | 92 ++++++
docs/system/target-arm.rst | 1 +
hw/arm/Kconfig | 9 +
hw/arm/Makefile.objs | 1 +
hw/arm/npcm7xx.c | 429 ++++++++++++++++++++++++++
hw/arm/npcm7xx_boards.c | 188 ++++++++++++
hw/mem/Makefile.objs | 1 +
hw/mem/npcm7xx_mc.c | 83 ++++++
hw/misc/Makefile.objs | 2 +
hw/misc/npcm7xx_clk.c | 216 ++++++++++++++
hw/misc/npcm7xx_gcr.c | 211 +++++++++++++
hw/misc/trace-events | 8 +
hw/nvram/Makefile.objs | 1 +
hw/nvram/npcm7xx_otp.c | 391 ++++++++++++++++++++++++
hw/ssi/Makefile.objs | 1 +
hw/ssi/npcm7xx_fiu.c | 496 +++++++++++++++++++++++++++++++
hw/ssi/trace-events | 9 +
hw/timer/Makefile.objs | 1 +
hw/timer/npcm7xx_timer.c | 437 +++++++++++++++++++++++++++
hw/timer/trace-events | 5 +
include/hw/arm/npcm7xx.h | 106 +++++++
include/hw/mem/npcm7xx_mc.h | 35 +++
include/hw/misc/npcm7xx_clk.h | 65 ++++
include/hw/misc/npcm7xx_gcr.h | 76 +++++
include/hw/nvram/npcm7xx_otp.h | 93 ++++++
include/hw/ssi/npcm7xx_fiu.h | 99 ++++++
include/hw/timer/npcm7xx_timer.h | 95 ++++++
29 files changed, 3160 insertions(+)
create mode 100644 docs/system/arm/nuvoton.rst
create mode 100644 hw/arm/npcm7xx.c
create mode 100644 hw/arm/npcm7xx_boards.c
create mode 100644 hw/mem/npcm7xx_mc.c
create mode 100644 hw/misc/npcm7xx_clk.c
create mode 100644 hw/misc/npcm7xx_gcr.c
create mode 100644 hw/nvram/npcm7xx_otp.c
create mode 100644 hw/ssi/npcm7xx_fiu.c
create mode 100644 hw/timer/npcm7xx_timer.c
create mode 100644 include/hw/arm/npcm7xx.h
create mode 100644 include/hw/mem/npcm7xx_mc.h
create mode 100644 include/hw/misc/npcm7xx_clk.h
create mode 100644 include/hw/misc/npcm7xx_gcr.h
create mode 100644 include/hw/nvram/npcm7xx_otp.h
create mode 100644 include/hw/ssi/npcm7xx_fiu.h
create mode 100644 include/hw/timer/npcm7xx_timer.h
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 01/12] npcm7xx: Add config symbol
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 02/12] hw/misc: Add NPCM7xx System Global Control Registers device model Havard Skinnemoen
` (12 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
Add a config symbol for the NPCM7xx BMC SoC family that subsequent
patches can use in Makefiles.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Acked-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Kconfig | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 8fc09a4a51..9a94ebd0be 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -27,6 +27,7 @@ CONFIG_GUMSTIX=y
CONFIG_SPITZ=y
CONFIG_TOSA=y
CONFIG_Z2=y
+CONFIG_NPCM7XX=y
CONFIG_COLLIE=y
CONFIG_ASPEED_SOC=y
CONFIG_NETDUINO2=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 4a224a6351..a31d0d282f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -354,6 +354,14 @@ config XLNX_VERSAL
select VIRTIO_MMIO
select UNIMP
+config NPCM7XX
+ bool
+ select A9MPCORE
+ select ARM_GIC
+ select PL310 # cache controller
+ select SERIAL
+ select UNIMP
+
config FSL_IMX25
bool
select IMX
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 02/12] hw/misc: Add NPCM7xx System Global Control Registers device model
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 01/12] npcm7xx: Add config symbol Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 03/12] hw/misc: Add NPCM7xx Clock Controller " Havard Skinnemoen
` (11 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
Implement a device model for the System Global Control Registers in the
NPCM730 and NPCM750 BMC SoCs.
This is primarily used to enable SMP boot (the boot ROM spins reading
the SCRPAD register) and DDR memory initialization; other registers are
best effort for now.
The reset values of the MDLR and PWRON registers are determined by the
SoC variant (730 vs 750) and board straps respectively.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
MAINTAINERS | 8 ++
hw/misc/Makefile.objs | 1 +
hw/misc/npcm7xx_gcr.c | 211 ++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 4 +
include/hw/misc/npcm7xx_gcr.h | 76 ++++++++++++
5 files changed, 300 insertions(+)
create mode 100644 hw/misc/npcm7xx_gcr.c
create mode 100644 include/hw/misc/npcm7xx_gcr.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 1b40446c73..f6f19f778b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -723,6 +723,14 @@ S: Odd Fixes
F: hw/arm/musicpal.c
F: docs/system/arm/musicpal.rst
+Nuvoton NPCM7xx
+M: Havard Skinnemoen <hskinnemoen@google.com>
+M: Tyrone Ting <kfting@nuvoton.com>
+L: qemu-arm@nongnu.org
+S: Supported
+F: hw/*/npcm7xx*
+F: include/hw/*/npcm7xx*
+
nSeries
M: Andrzej Zaborowski <balrogg@gmail.com>
M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 5aaca8a039..40a9d1c01e 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -51,6 +51,7 @@ common-obj-$(CONFIG_IMX) += imx_rngc.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o
+common-obj-$(CONFIG_NPCM7XX) += npcm7xx_gcr.o
common-obj-$(CONFIG_OMAP) += omap_clk.o
common-obj-$(CONFIG_OMAP) += omap_gpmc.o
common-obj-$(CONFIG_OMAP) += omap_l4.o
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
new file mode 100644
index 0000000000..af03bf4a01
--- /dev/null
+++ b/hw/misc/npcm7xx_gcr.c
@@ -0,0 +1,211 @@
+/*
+ * Nuvoton NPCM7xx System Global Control Registers.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/misc/npcm7xx_gcr.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
+ [NPCM7XX_GCR_PDID] = 0x04A92750, /* Poleg A1 */
+ [NPCM7XX_GCR_MISCPE] = 0x0000FFFF,
+ [NPCM7XX_GCR_SPSWC] = 0x00000003,
+ [NPCM7XX_GCR_INTCR] = 0x0000035E,
+ [NPCM7XX_GCR_HIFCR] = 0x0000004E,
+ [NPCM7XX_GCR_INTCR2] = (1U << 19), /* DDR initialized */
+ [NPCM7XX_GCR_RESSR] = 0x80000000,
+ [NPCM7XX_GCR_DSCNT] = 0x000000c0,
+ [NPCM7XX_GCR_DAVCLVLR] = 0x5A00F3CF,
+ [NPCM7XX_GCR_SCRPAD] = 0x00000008,
+ [NPCM7XX_GCR_USB1PHYCTL] = 0x034730E4,
+ [NPCM7XX_GCR_USB2PHYCTL] = 0x034730E4,
+};
+
+static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size)
+{
+ uint32_t reg = offset / sizeof(uint32_t);
+ NPCM7xxGCRState *s = opaque;
+
+ if (reg >= NPCM7XX_GCR_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04x out of range\n",
+ __func__, (unsigned int)offset);
+ return 0;
+ }
+
+ trace_npcm7xx_gcr_read(offset, s->regs[reg]);
+
+ return s->regs[reg];
+}
+
+static void npcm7xx_gcr_write(void *opaque, hwaddr offset,
+ uint64_t v, unsigned size)
+{
+ uint32_t reg = offset / sizeof(uint32_t);
+ NPCM7xxGCRState *s = opaque;
+ uint32_t value = v;
+
+ trace_npcm7xx_gcr_write(offset, value);
+
+ if (reg >= NPCM7XX_GCR_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04x out of range\n",
+ __func__, (unsigned int)offset);
+ return;
+ }
+
+ switch (reg) {
+ case NPCM7XX_GCR_PDID:
+ case NPCM7XX_GCR_PWRON:
+ case NPCM7XX_GCR_INTSR:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: register @ 0x%04x is read-only\n",
+ __func__, (unsigned int)offset);
+ return;
+
+ case NPCM7XX_GCR_RESSR:
+ case NPCM7XX_GCR_CP2BST:
+ /* Write 1 to clear */
+ value = s->regs[reg] & ~value;
+ break;
+
+ case NPCM7XX_GCR_RLOCKR1:
+ case NPCM7XX_GCR_MDLR:
+ /* Write 1 to set */
+ value |= s->regs[reg];
+ break;
+ };
+
+ s->regs[reg] = value;
+}
+
+static const struct MemoryRegionOps npcm7xx_gcr_ops = {
+ .read = npcm7xx_gcr_read,
+ .write = npcm7xx_gcr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
+{
+ NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
+
+ QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
+
+ switch (type) {
+ case RESET_TYPE_COLD:
+ memcpy(s->regs, cold_reset_values, sizeof(s->regs));
+ s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron;
+ s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr;
+ s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
+ break;
+ }
+}
+
+static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
+{
+ NPCM7xxGCRState *s = NPCM7XX_GCR(dev);
+ uint64_t dram_size;
+
+ if (!s->dram) {
+ error_setg(errp, "npcm7xx_gcr: 'dram' link not set");
+ return;
+ }
+
+ /* Power-on reset value */
+ s->reset_intcr3 = 0x00001002;
+
+ /*
+ * The GMMAP (Graphics Memory Map) field is used by u-boot to detect the
+ * DRAM size, and is normally initialized by the boot block as part of DRAM
+ * training. However, since we don't have a complete emulation of the
+ * memory controller and try to make it look like it has already been
+ * initialized, the boot block will skip this initialization, and we need
+ * to make sure this field is set correctly up front.
+ *
+ * WARNING: some versions of u-boot only looks at bits 8 and 9, so 2 GiB or
+ * more of DRAM will be interpreted as 128 MiB.
+ *
+ * https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408dbaad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244
+ */
+ dram_size = int128_get64(s->dram->size);
+ if (dram_size >= 2 * GiB) {
+ s->reset_intcr3 |= 4 << 8;
+ } else if (dram_size >= 1 * GiB) {
+ s->reset_intcr3 |= 3 << 8;
+ } else if (dram_size >= 512 * MiB) {
+ s->reset_intcr3 |= 2 << 8;
+ } else if (dram_size >= 256 * MiB) {
+ s->reset_intcr3 |= 1 << 8;
+ } else if (dram_size >= 128 * MiB) {
+ s->reset_intcr3 |= 0 << 8;
+ } else {
+ error_setg(errp,
+ "npcm7xx_gcr: DRAM size %" PRIu64
+ " is too small (need 128 MiB minimum)",
+ dram_size);
+ return;
+ }
+}
+
+static void npcm7xx_gcr_init(Object *obj)
+{
+ NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
+
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
+ TYPE_NPCM7XX_GCR, 4 * KiB);
+ sysbus_init_mmio(&s->parent, &s->iomem);
+}
+
+static Property npcm7xx_gcr_properties[] = {
+ DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState, reset_mdlr, 0),
+ DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState, reset_pwron, 0),
+ DEFINE_PROP_LINK("dram", NPCM7xxGCRState, dram, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM7xx System Global Control Registers";
+ dc->realize = npcm7xx_gcr_realize;
+ rc->phases.enter = npcm7xx_gcr_enter_reset;
+
+ device_class_set_props(dc, npcm7xx_gcr_properties);
+}
+
+static const TypeInfo npcm7xx_gcr_info = {
+ .name = TYPE_NPCM7XX_GCR,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxGCRState),
+ .instance_init = npcm7xx_gcr_init,
+ .class_init = npcm7xx_gcr_class_init,
+};
+
+static void npcm7xx_gcr_register_type(void)
+{
+ type_register_static(&npcm7xx_gcr_info);
+}
+type_init(npcm7xx_gcr_register_type);
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 5561746866..1a20ce659a 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -107,6 +107,10 @@ mos6522_set_sr_int(void) "set sr_int"
mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
+# npcm7xx_gcr.c
+npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+
# stm32f4xx_syscfg
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
new file mode 100644
index 0000000000..a881ac41a3
--- /dev/null
+++ b/include/hw/misc/npcm7xx_gcr.h
@@ -0,0 +1,76 @@
+/*
+ * Nuvoton NPCM7xx System Global Control Registers.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef NPCM7XX_GCR_H
+#define NPCM7XX_GCR_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+enum NPCM7xxGCRRegisters {
+ NPCM7XX_GCR_PDID,
+ NPCM7XX_GCR_PWRON,
+ NPCM7XX_GCR_MFSEL1 = 0x0C / sizeof(uint32_t),
+ NPCM7XX_GCR_MFSEL2,
+ NPCM7XX_GCR_MISCPE,
+ NPCM7XX_GCR_SPSWC = 0x038 / sizeof(uint32_t),
+ NPCM7XX_GCR_INTCR,
+ NPCM7XX_GCR_INTSR,
+ NPCM7XX_GCR_HIFCR = 0x050 / sizeof(uint32_t),
+ NPCM7XX_GCR_INTCR2 = 0x060 / sizeof(uint32_t),
+ NPCM7XX_GCR_MFSEL3,
+ NPCM7XX_GCR_SRCNT,
+ NPCM7XX_GCR_RESSR,
+ NPCM7XX_GCR_RLOCKR1,
+ NPCM7XX_GCR_FLOCKR1,
+ NPCM7XX_GCR_DSCNT,
+ NPCM7XX_GCR_MDLR,
+ NPCM7XX_GCR_SCRPAD3,
+ NPCM7XX_GCR_SCRPAD2,
+ NPCM7XX_GCR_DAVCLVLR = 0x098 / sizeof(uint32_t),
+ NPCM7XX_GCR_INTCR3,
+ NPCM7XX_GCR_VSINTR = 0x0AC / sizeof(uint32_t),
+ NPCM7XX_GCR_MFSEL4,
+ NPCM7XX_GCR_CPBPNTR = 0x0C4 / sizeof(uint32_t),
+ NPCM7XX_GCR_CPCTL = 0x0D0 / sizeof(uint32_t),
+ NPCM7XX_GCR_CP2BST,
+ NPCM7XX_GCR_B2CPNT,
+ NPCM7XX_GCR_CPPCTL,
+ NPCM7XX_GCR_I2CSEGSEL,
+ NPCM7XX_GCR_I2CSEGCTL,
+ NPCM7XX_GCR_VSRCR,
+ NPCM7XX_GCR_MLOCKR,
+ NPCM7XX_GCR_SCRPAD = 0x013C / sizeof(uint32_t),
+ NPCM7XX_GCR_USB1PHYCTL,
+ NPCM7XX_GCR_USB2PHYCTL,
+ NPCM7XX_GCR_NR_REGS,
+};
+
+typedef struct NPCM7xxGCRState {
+ SysBusDevice parent;
+
+ MemoryRegion iomem;
+
+ uint32_t regs[NPCM7XX_GCR_NR_REGS];
+
+ uint32_t reset_pwron;
+ uint32_t reset_mdlr;
+ uint32_t reset_intcr3;
+ MemoryRegion *dram;
+} NPCM7xxGCRState;
+
+#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
+#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
+
+#endif /* NPCM7XX_GCR_H */
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 03/12] hw/misc: Add NPCM7xx Clock Controller device model
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 01/12] npcm7xx: Add config symbol Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 02/12] hw/misc: Add NPCM7xx System Global Control Registers device model Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 04/12] hw/timer: Add NPCM7xx Timer " Havard Skinnemoen
` (10 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
Enough functionality to boot the Linux kernel has been implemented. This
includes:
- Correct power-on reset values so the various clock rates can be
accurately calculated.
- Clock enables stick around when written.
In addition, a best effort attempt to implement SECCNT and CNTR25M was
made even though I don't think the kernel needs them.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/npcm7xx_clk.c | 216 ++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 4 +
include/hw/misc/npcm7xx_clk.h | 65 ++++++++++
4 files changed, 286 insertions(+)
create mode 100644 hw/misc/npcm7xx_clk.c
create mode 100644 include/hw/misc/npcm7xx_clk.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 40a9d1c01e..2e74803005 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -51,6 +51,7 @@ common-obj-$(CONFIG_IMX) += imx_rngc.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o
+common-obj-$(CONFIG_NPCM7XX) += npcm7xx_clk.o
common-obj-$(CONFIG_NPCM7XX) += npcm7xx_gcr.o
common-obj-$(CONFIG_OMAP) += omap_clk.o
common-obj-$(CONFIG_OMAP) += omap_gpmc.o
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
new file mode 100644
index 0000000000..2348683305
--- /dev/null
+++ b/hw/misc/npcm7xx_clk.c
@@ -0,0 +1,216 @@
+/*
+ * Nuvoton NPCM7xx Clock Control Registers.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/misc/npcm7xx_clk.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+#define PLLCON_LOKI BIT(31)
+#define PLLCON_LOKS BIT(30)
+#define PLLCON_PWDEN BIT(12)
+
+/*
+ * These reset values were taken from version 0.91 of the NPCM750R data sheet.
+ *
+ * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
+ * core domain reset, but this reset type is not yet supported by QEMU.
+ */
+static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
+ [NPCM7XX_CLK_CLKEN1] = 0xffffffff,
+ [NPCM7XX_CLK_CLKSEL] = 0x004aaaaa,
+ [NPCM7XX_CLK_CLKDIV1] = 0x5413f855,
+ [NPCM7XX_CLK_PLLCON0] = 0x00222101 | PLLCON_LOKI,
+ [NPCM7XX_CLK_PLLCON1] = 0x00202101 | PLLCON_LOKI,
+ [NPCM7XX_CLK_IPSRST1] = 0x00001000,
+ [NPCM7XX_CLK_IPSRST2] = 0x80000000,
+ [NPCM7XX_CLK_CLKEN2] = 0xffffffff,
+ [NPCM7XX_CLK_CLKDIV2] = 0xaa4f8f9f,
+ [NPCM7XX_CLK_CLKEN3] = 0xffffffff,
+ [NPCM7XX_CLK_IPSRST3] = 0x03000000,
+ [NPCM7XX_CLK_WD0RCR] = 0xffffffff,
+ [NPCM7XX_CLK_WD1RCR] = 0xffffffff,
+ [NPCM7XX_CLK_WD2RCR] = 0xffffffff,
+ [NPCM7XX_CLK_SWRSTC1] = 0x00000003,
+ [NPCM7XX_CLK_PLLCON2] = 0x00c02105 | PLLCON_LOKI,
+ [NPCM7XX_CLK_CORSTC] = 0x04000003,
+ [NPCM7XX_CLK_PLLCONG] = 0x01228606 | PLLCON_LOKI,
+ [NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
+};
+
+static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
+{
+ uint32_t reg = offset / sizeof(uint32_t);
+ NPCM7xxCLKState *s = opaque;
+ int64_t now_ns;
+ uint32_t value = 0;
+
+ if (reg >= NPCM7XX_CLK_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04x out of range\n",
+ __func__, (unsigned int)offset);
+ return 0;
+ }
+
+ switch (reg) {
+ case NPCM7XX_CLK_SWRSTR:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: register @ 0x%04x is write-only\n",
+ __func__, (unsigned int)offset);
+ break;
+
+ case NPCM7XX_CLK_SECCNT:
+ now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ value = (now_ns - s->ref_ns) / NANOSECONDS_PER_SECOND;
+ break;
+
+ case NPCM7XX_CLK_CNTR25M:
+ now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ /*
+ * This register counts 25 MHz cycles, updating every 640 ns. It rolls
+ * over to zero every second.
+ *
+ * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
+ */
+ value = (((now_ns - s->ref_ns) / 640) << 4) % 25000000;
+ break;
+
+ default:
+ value = s->regs[reg];
+ break;
+ };
+
+ trace_npcm7xx_clk_read(offset, value);
+
+ return value;
+}
+
+static void npcm7xx_clk_write(void *opaque, hwaddr offset,
+ uint64_t v, unsigned size)
+{
+ uint32_t reg = offset / sizeof(uint32_t);
+ NPCM7xxCLKState *s = opaque;
+ uint32_t value = v;
+
+ trace_npcm7xx_clk_write(offset, value);
+
+ if (reg >= NPCM7XX_CLK_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%04x out of range\n",
+ __func__, (unsigned int)offset);
+ return;
+ }
+
+ switch (reg) {
+ case NPCM7XX_CLK_SWRSTR:
+ qemu_log_mask(LOG_UNIMP, "%s: SW reset not implemented: 0x%02x\n",
+ __func__, value);
+ value = 0;
+ break;
+
+ case NPCM7XX_CLK_PLLCON0:
+ case NPCM7XX_CLK_PLLCON1:
+ case NPCM7XX_CLK_PLLCON2:
+ case NPCM7XX_CLK_PLLCONG:
+ if (value & PLLCON_PWDEN) {
+ /* Power down -- clear lock and indicate loss of lock */
+ value &= ~PLLCON_LOKI;
+ value |= PLLCON_LOKS;
+ } else {
+ /* Normal mode -- assume always locked */
+ value |= PLLCON_LOKI;
+ /* Keep LOKS unchanged unless cleared by writing 1 */
+ if (value & PLLCON_LOKS) {
+ value &= ~PLLCON_LOKS;
+ } else {
+ value |= (value & PLLCON_LOKS);
+ }
+ }
+ break;
+
+ case NPCM7XX_CLK_CNTR25M:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: register @ 0x%04x is read-only\n",
+ __func__, (unsigned int)offset);
+ return;
+ }
+
+ s->regs[reg] = value;
+}
+
+static const struct MemoryRegionOps npcm7xx_clk_ops = {
+ .read = npcm7xx_clk_read,
+ .write = npcm7xx_clk_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
+{
+ NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
+
+ QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
+
+ switch (type) {
+ case RESET_TYPE_COLD:
+ memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
+ s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ return;
+ }
+
+ /*
+ * A small number of registers need to be reset on a core domain reset,
+ * but no such reset type exists yet.
+ */
+ qemu_log_mask(LOG_UNIMP, "%s: reset type %d not implemented.",
+ __func__, type);
+}
+
+static void npcm7xx_clk_init(Object *obj)
+{
+ NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
+
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
+ TYPE_NPCM7XX_CLK, 4 * KiB);
+ sysbus_init_mmio(&s->parent, &s->iomem);
+}
+
+static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM7xx Clock Control Registers";
+ rc->phases.enter = npcm7xx_clk_enter_reset;
+}
+
+static const TypeInfo npcm7xx_clk_info = {
+ .name = TYPE_NPCM7XX_CLK,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxCLKState),
+ .instance_init = npcm7xx_clk_init,
+ .class_init = npcm7xx_clk_class_init,
+};
+
+static void npcm7xx_clk_register_type(void)
+{
+ type_register_static(&npcm7xx_clk_info);
+}
+type_init(npcm7xx_clk_register_type);
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 1a20ce659a..cdc41fe391 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -107,6 +107,10 @@ mos6522_set_sr_int(void) "set sr_int"
mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
+# npcm7xx_clk.c
+npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+
# npcm7xx_gcr.c
npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
new file mode 100644
index 0000000000..a678b50ede
--- /dev/null
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -0,0 +1,65 @@
+/*
+ * Nuvoton NPCM7xx Clock Control Registers.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef NPCM7XX_CLK_H
+#define NPCM7XX_CLK_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+enum NPCM7xxCLKRegisters {
+ NPCM7XX_CLK_CLKEN1,
+ NPCM7XX_CLK_CLKSEL,
+ NPCM7XX_CLK_CLKDIV1,
+ NPCM7XX_CLK_PLLCON0,
+ NPCM7XX_CLK_PLLCON1,
+ NPCM7XX_CLK_SWRSTR,
+ NPCM7XX_CLK_IPSRST1 = 0x20 / sizeof(uint32_t),
+ NPCM7XX_CLK_IPSRST2,
+ NPCM7XX_CLK_CLKEN2,
+ NPCM7XX_CLK_CLKDIV2,
+ NPCM7XX_CLK_CLKEN3,
+ NPCM7XX_CLK_IPSRST3,
+ NPCM7XX_CLK_WD0RCR,
+ NPCM7XX_CLK_WD1RCR,
+ NPCM7XX_CLK_WD2RCR,
+ NPCM7XX_CLK_SWRSTC1,
+ NPCM7XX_CLK_SWRSTC2,
+ NPCM7XX_CLK_SWRSTC3,
+ NPCM7XX_CLK_SWRSTC4,
+ NPCM7XX_CLK_PLLCON2,
+ NPCM7XX_CLK_CLKDIV3,
+ NPCM7XX_CLK_CORSTC,
+ NPCM7XX_CLK_PLLCONG,
+ NPCM7XX_CLK_AHBCKFI,
+ NPCM7XX_CLK_SECCNT,
+ NPCM7XX_CLK_CNTR25M,
+ NPCM7XX_CLK_NR_REGS,
+};
+
+typedef struct NPCM7xxCLKState {
+ SysBusDevice parent;
+
+ MemoryRegion iomem;
+
+ uint32_t regs[NPCM7XX_CLK_NR_REGS];
+
+ /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
+ int64_t ref_ns;
+} NPCM7xxCLKState;
+
+#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
+#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
+
+#endif /* NPCM7XX_CLK_H */
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 04/12] hw/timer: Add NPCM7xx Timer device model
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (2 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 03/12] hw/misc: Add NPCM7xx Clock Controller " Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models Havard Skinnemoen
` (9 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
The NPCM730 and NPCM750 SoCs have three timer modules each holding five
timers and some shared registers (e.g. interrupt status).
Each timer runs at 25 MHz divided by a prescaler, and counts down from a
configurable initial value to zero. When zero is reached, the interrupt
flag for the timer is set, and the timer is disabled (one-shot mode) or
reloaded from its initial value (periodic mode).
This implementation is sufficient to boot a Linux kernel configured for
NPCM750. Note that the kernel does not seem to actually turn on the
interrupts.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/timer/Makefile.objs | 1 +
hw/timer/npcm7xx_timer.c | 437 +++++++++++++++++++++++++++++++
hw/timer/trace-events | 5 +
include/hw/timer/npcm7xx_timer.h | 95 +++++++
4 files changed, 538 insertions(+)
create mode 100644 hw/timer/npcm7xx_timer.c
create mode 100644 include/hw/timer/npcm7xx_timer.h
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index a39f6ec0c2..84c484dda8 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -14,6 +14,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_NPCM7XX) += npcm7xx_timer.o
common-obj-$(CONFIG_NRF51_SOC) += nrf51_timer.o
common-obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
new file mode 100644
index 0000000000..9aae4b09b9
--- /dev/null
+++ b/hw/timer/npcm7xx_timer.c
@@ -0,0 +1,437 @@
+/*
+ * Nuvoton NPCM7xx Timer Controller
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/timer/npcm7xx_timer.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+/* Register field definitions. */
+#define NPCM7XX_TCSR_CEN BIT(30)
+#define NPCM7XX_TCSR_IE BIT(29)
+#define NPCM7XX_TCSR_PERIODIC BIT(27)
+#define NPCM7XX_TCSR_CRST BIT(26)
+#define NPCM7XX_TCSR_CACT BIT(25)
+#define NPCM7XX_TCSR_RSVD 0x21ffff00
+#define NPCM7XX_TCSR_PRESCALE_START 0
+#define NPCM7XX_TCSR_PRESCALE_LEN 8
+
+/* The reference clock frequency is always 25 MHz. */
+#define NPCM7XX_TIMER_REF_HZ (25000000)
+
+/* Return the value by which to divide the reference clock rate. */
+static uint32_t npcm7xx_timer_prescaler(const NPCM7xxTimer *t)
+{
+ return extract32(t->tcsr, NPCM7XX_TCSR_PRESCALE_START,
+ NPCM7XX_TCSR_PRESCALE_LEN) + 1;
+}
+
+/* Convert a timer cycle count to a time interval in nanoseconds. */
+static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
+{
+ int64_t ns = count;
+
+ ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
+ ns *= npcm7xx_timer_prescaler(t);
+
+ return ns;
+}
+
+/* Convert a time interval in nanoseconds to a timer cycle count. */
+static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
+{
+ int64_t count;
+
+ count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
+ count /= npcm7xx_timer_prescaler(t);
+
+ return count;
+}
+
+/*
+ * Raise the interrupt line if there's a pending interrupt and interrupts are
+ * enabled for this timer. If not, lower it.
+ */
+static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
+{
+ NPCM7xxTimerCtrlState *tc = t->ctrl;
+ /* Find the array index of this timer. */
+ int index = t - tc->timer;
+
+ g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);
+
+ if ((t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index))) {
+ qemu_irq_raise(t->irq);
+ trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, 1);
+ } else {
+ qemu_irq_lower(t->irq);
+ trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, 0);
+ }
+}
+
+/* Start or resume the timer. */
+static void npcm7xx_timer_start(NPCM7xxTimer *t)
+{
+ int64_t now;
+
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ t->expires_ns = now + t->remaining_ns;
+ timer_mod(&t->qtimer, t->expires_ns);
+}
+
+/*
+ * Called when the counter reaches zero. Sets the interrupt flag, and either
+ * restarts or disables the timer.
+ */
+static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
+{
+ NPCM7xxTimerCtrlState *tc = t->ctrl;
+ int index = t - tc->timer;
+
+ g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);
+
+ tc->tisr |= BIT(index);
+
+ if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
+ t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
+ if (t->tcsr & NPCM7XX_TCSR_CEN) {
+ npcm7xx_timer_start(t);
+ }
+ } else {
+ t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
+ }
+
+ npcm7xx_timer_check_interrupt(t);
+}
+
+/* Stop counting. Record the time remaining so we can continue later. */
+static void npcm7xx_timer_pause(NPCM7xxTimer *t)
+{
+ int64_t now;
+
+ timer_del(&t->qtimer);
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ t->remaining_ns = t->expires_ns - now;
+ if (t->remaining_ns <= 0) {
+ npcm7xx_timer_reached_zero(t);
+ }
+}
+
+/*
+ * Restart the timer from its initial value. If the timer was enabled and stays
+ * enabled, adjust the QEMU timer according to the new count. If the timer is
+ * transitioning from disabled to enabled, the caller is expected to start the
+ * timer later.
+ */
+static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
+{
+ t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
+
+ if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
+ npcm7xx_timer_start(t);
+ }
+}
+
+/* Register read and write handlers */
+
+static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
+{
+ uint32_t old_tcsr = t->tcsr;
+
+ if (new_tcsr & NPCM7XX_TCSR_RSVD) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits in 0x%08x ignored\n",
+ __func__, new_tcsr);
+ new_tcsr &= ~NPCM7XX_TCSR_RSVD;
+ }
+ if (new_tcsr & NPCM7XX_TCSR_CACT) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only bits in 0x%08x ignored\n",
+ __func__, new_tcsr);
+ new_tcsr &= ~NPCM7XX_TCSR_CACT;
+ }
+
+ t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr;
+
+ if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) {
+ npcm7xx_timer_check_interrupt(t);
+ }
+ if (new_tcsr & NPCM7XX_TCSR_CRST) {
+ npcm7xx_timer_restart(t, old_tcsr);
+ t->tcsr &= ~NPCM7XX_TCSR_CRST;
+ }
+ if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
+ if (new_tcsr & NPCM7XX_TCSR_CEN) {
+ npcm7xx_timer_start(t);
+ } else {
+ npcm7xx_timer_pause(t);
+ }
+ }
+}
+
+static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr)
+{
+ t->ticr = new_ticr;
+
+ npcm7xx_timer_restart(t, t->tcsr);
+}
+
+static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
+{
+ if (t->tcsr & NPCM7XX_TCSR_CEN) {
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+ return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
+ }
+
+ return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
+}
+
+static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
+{
+ NPCM7xxTimerCtrlState *s = opaque;
+ uint64_t value = 0;
+ hwaddr reg;
+
+ reg = offset / sizeof(uint32_t);
+ switch (reg) {
+ case NPCM7XX_TIMER_TCSR0:
+ value = s->timer[0].tcsr;
+ break;
+ case NPCM7XX_TIMER_TCSR1:
+ value = s->timer[1].tcsr;
+ break;
+ case NPCM7XX_TIMER_TCSR2:
+ value = s->timer[2].tcsr;
+ break;
+ case NPCM7XX_TIMER_TCSR3:
+ value = s->timer[3].tcsr;
+ break;
+ case NPCM7XX_TIMER_TCSR4:
+ value = s->timer[4].tcsr;
+ break;
+
+ case NPCM7XX_TIMER_TICR0:
+ value = s->timer[0].ticr;
+ break;
+ case NPCM7XX_TIMER_TICR1:
+ value = s->timer[1].ticr;
+ break;
+ case NPCM7XX_TIMER_TICR2:
+ value = s->timer[2].ticr;
+ break;
+ case NPCM7XX_TIMER_TICR3:
+ value = s->timer[3].ticr;
+ break;
+ case NPCM7XX_TIMER_TICR4:
+ value = s->timer[4].ticr;
+ break;
+
+ case NPCM7XX_TIMER_TDR0:
+ value = npcm7xx_timer_read_tdr(&s->timer[0]);
+ break;
+ case NPCM7XX_TIMER_TDR1:
+ value = npcm7xx_timer_read_tdr(&s->timer[1]);
+ break;
+ case NPCM7XX_TIMER_TDR2:
+ value = npcm7xx_timer_read_tdr(&s->timer[2]);
+ break;
+ case NPCM7XX_TIMER_TDR3:
+ value = npcm7xx_timer_read_tdr(&s->timer[3]);
+ break;
+ case NPCM7XX_TIMER_TDR4:
+ value = npcm7xx_timer_read_tdr(&s->timer[4]);
+ break;
+
+ case NPCM7XX_TIMER_TISR:
+ value = s->tisr;
+ break;
+
+ case NPCM7XX_TIMER_WTCR:
+ value = s->wtcr;
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid offset 0x%04x\n",
+ __func__, (unsigned int)offset);
+ break;
+ }
+
+ trace_npcm7xx_timer_read(DEVICE(s)->canonical_path, offset, value);
+
+ return value;
+}
+
+static void npcm7xx_timer_write(void *opaque, hwaddr offset,
+ uint64_t v, unsigned size)
+{
+ uint32_t reg = offset / sizeof(uint32_t);
+ NPCM7xxTimerCtrlState *s = opaque;
+ uint32_t value = v;
+
+ trace_npcm7xx_timer_write(DEVICE(s)->canonical_path, offset, value);
+
+ switch (reg) {
+ case NPCM7XX_TIMER_TCSR0:
+ npcm7xx_timer_write_tcsr(&s->timer[0], value);
+ return;
+ case NPCM7XX_TIMER_TCSR1:
+ npcm7xx_timer_write_tcsr(&s->timer[1], value);
+ return;
+ case NPCM7XX_TIMER_TCSR2:
+ npcm7xx_timer_write_tcsr(&s->timer[2], value);
+ return;
+ case NPCM7XX_TIMER_TCSR3:
+ npcm7xx_timer_write_tcsr(&s->timer[3], value);
+ return;
+ case NPCM7XX_TIMER_TCSR4:
+ npcm7xx_timer_write_tcsr(&s->timer[4], value);
+ return;
+
+ case NPCM7XX_TIMER_TICR0:
+ npcm7xx_timer_write_ticr(&s->timer[0], value);
+ return;
+ case NPCM7XX_TIMER_TICR1:
+ npcm7xx_timer_write_ticr(&s->timer[1], value);
+ return;
+ case NPCM7XX_TIMER_TICR2:
+ npcm7xx_timer_write_ticr(&s->timer[2], value);
+ return;
+ case NPCM7XX_TIMER_TICR3:
+ npcm7xx_timer_write_ticr(&s->timer[3], value);
+ return;
+ case NPCM7XX_TIMER_TICR4:
+ npcm7xx_timer_write_ticr(&s->timer[4], value);
+ return;
+
+ case NPCM7XX_TIMER_TDR0:
+ case NPCM7XX_TIMER_TDR1:
+ case NPCM7XX_TIMER_TDR2:
+ case NPCM7XX_TIMER_TDR3:
+ case NPCM7XX_TIMER_TDR4:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: register @ 0x%04x is read-only\n",
+ __func__, (unsigned int)offset);
+ return;
+
+ case NPCM7XX_TIMER_TISR:
+ s->tisr &= ~value;
+ return;
+
+ case NPCM7XX_TIMER_WTCR:
+ qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
+ __func__, value);
+ return;
+ }
+
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid offset 0x%04x\n",
+ __func__, (unsigned int)offset);
+}
+
+static const struct MemoryRegionOps npcm7xx_timer_ops = {
+ .read = npcm7xx_timer_read,
+ .write = npcm7xx_timer_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+/* Called when the QEMU timer expires. */
+static void npcm7xx_timer_expired(void *opaque)
+{
+ NPCM7xxTimer *t = opaque;
+
+ if (t->tcsr & NPCM7XX_TCSR_CEN) {
+ npcm7xx_timer_reached_zero(t);
+ }
+}
+
+static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
+{
+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
+ int i;
+
+ for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
+ NPCM7xxTimer *t = &s->timer[i];
+
+ timer_del(&t->qtimer);
+ t->expires_ns = 0;
+ t->remaining_ns = 0;
+ t->tcsr = 0x00000005;
+ t->ticr = 0x00000000;
+ }
+
+ s->tisr = 0x00000000;
+ s->wtcr = 0x00000400;
+}
+
+static void npcm7xx_timer_hold_reset(Object *obj)
+{
+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
+ int i;
+
+ for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
+ qemu_irq_lower(s->timer[i].irq);
+ }
+}
+
+static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
+{
+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
+ SysBusDevice *sbd = &s->parent;
+ int i;
+
+ for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
+ NPCM7xxTimer *t = &s->timer[i];
+ t->ctrl = s;
+ timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
+ sysbus_init_irq(sbd, &t->irq);
+ }
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
+ TYPE_NPCM7XX_TIMER, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM7xx Timer Controller";
+ dc->realize = npcm7xx_timer_realize;
+ rc->phases.enter = npcm7xx_timer_enter_reset;
+ rc->phases.hold = npcm7xx_timer_hold_reset;
+}
+
+static const TypeInfo npcm7xx_timer_info = {
+ .name = TYPE_NPCM7XX_TIMER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxTimerCtrlState),
+ .class_init = npcm7xx_timer_class_init,
+};
+
+static void npcm7xx_timer_register_type(void)
+{
+ type_register_static(&npcm7xx_timer_info);
+}
+type_init(npcm7xx_timer_register_type);
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
index 866c9f546a..e2434ecf3f 100644
--- a/hw/timer/trace-events
+++ b/hw/timer/trace-events
@@ -66,6 +66,11 @@ cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK A
cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
+# npcm7xx_timer.c
+npcm7xx_timer_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
+npcm7xx_timer_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
+npcm7xx_timer_irq(const char *id, int timer, int state) "%s timer %d state %d"
+
# nrf51_timer.c
nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
new file mode 100644
index 0000000000..d8ed98933d
--- /dev/null
+++ b/include/hw/timer/npcm7xx_timer.h
@@ -0,0 +1,95 @@
+/*
+ * Nuvoton NPCM7xx Timer Controller
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef NPCM7XX_TIMER_H
+#define NPCM7XX_TIMER_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+/* Each Timer Module (TIM) instance holds five 25 MHz timers. */
+#define NPCM7XX_TIMERS_PER_CTRL (5)
+
+/**
+ * enum NPCM7xxTimerRegisters - 32-bit register indices.
+ */
+enum NPCM7xxTimerRegisters {
+ NPCM7XX_TIMER_TCSR0,
+ NPCM7XX_TIMER_TCSR1,
+ NPCM7XX_TIMER_TICR0,
+ NPCM7XX_TIMER_TICR1,
+ NPCM7XX_TIMER_TDR0,
+ NPCM7XX_TIMER_TDR1,
+ NPCM7XX_TIMER_TISR,
+ NPCM7XX_TIMER_WTCR,
+ NPCM7XX_TIMER_TCSR2,
+ NPCM7XX_TIMER_TCSR3,
+ NPCM7XX_TIMER_TICR2,
+ NPCM7XX_TIMER_TICR3,
+ NPCM7XX_TIMER_TDR2,
+ NPCM7XX_TIMER_TDR3,
+ NPCM7XX_TIMER_TCSR4 = 0x0040 / sizeof(uint32_t),
+ NPCM7XX_TIMER_TICR4 = 0x0048 / sizeof(uint32_t),
+ NPCM7XX_TIMER_TDR4 = 0x0050 / sizeof(uint32_t),
+ NPCM7XX_TIMER_NR_REGS,
+};
+
+typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
+
+/**
+ * struct NPCM7xxTimer - Individual timer state.
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * @qtimer: QEMU timer that notifies us on expiration.
+ * @expires_ns: Absolute virtual expiration time.
+ * @remaining_ns: Remaining time until expiration if timer is paused.
+ * @tcsr: The Timer Control and Status Register.
+ * @ticr: The Timer Initial Count Register.
+ */
+typedef struct NPCM7xxTimer {
+ NPCM7xxTimerCtrlState *ctrl;
+
+ qemu_irq irq;
+ QEMUTimer qtimer;
+ int64_t expires_ns;
+ int64_t remaining_ns;
+
+ uint32_t tcsr;
+ uint32_t ticr;
+} NPCM7xxTimer;
+
+/**
+ * struct NPCM7xxTimerCtrlState - Timer Module device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @tisr: The Timer Interrupt Status Register.
+ * @wtcr: The Watchdog Timer Control Register.
+ * @timer: The five individual timers managed by this module.
+ */
+struct NPCM7xxTimerCtrlState {
+ SysBusDevice parent;
+
+ MemoryRegion iomem;
+
+ uint32_t tisr;
+ uint32_t wtcr;
+
+ NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
+};
+
+#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
+#define NPCM7XX_TIMER(obj) \
+ OBJECT_CHECK(NPCM7xxTimerCtrlState, (obj), TYPE_NPCM7XX_TIMER)
+
+#endif /* NPCM7XX_TIMER_H */
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (3 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 04/12] hw/timer: Add NPCM7xx Timer " Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-07-03 13:32 ` Philippe Mathieu-Daudé
2020-06-26 23:55 ` [PATCH v3 06/12] hw/arm: Add two NPCM7xx-based machines Havard Skinnemoen
` (8 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
The Nuvoton NPCM7xx SoC family are used to implement Baseboard
Management Controllers in servers. While the family includes four SoCs,
this patch implements limited support for two of them: NPCM730 (targeted
for Data Center applications) and NPCM750 (targeted for Enterprise
applications).
This patch includes little more than the bare minimum needed to boot a
Linux kernel built with NPCM7xx support in direct-kernel mode:
- Two Cortex-A9 CPU cores with built-in periperhals.
- Global Configuration Registers.
- Clock Management.
- 3 Timer Modules with 5 timers each.
- 4 serial ports.
The chips themselves have a lot more features, some of which will be
added to the model at a later stage.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/arm/Makefile.objs | 1 +
hw/arm/npcm7xx.c | 330 +++++++++++++++++++++++++++++++++++++++
include/hw/arm/npcm7xx.h | 80 ++++++++++
3 files changed, 411 insertions(+)
create mode 100644 hw/arm/npcm7xx.c
create mode 100644 include/hw/arm/npcm7xx.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 534a6a119e..13d163a599 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -41,6 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
+obj-$(CONFIG_NPCM7XX) += npcm7xx.o
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
new file mode 100644
index 0000000000..f395fe84b6
--- /dev/null
+++ b/hw/arm/npcm7xx.c
@@ -0,0 +1,330 @@
+/*
+ * Nuvoton NPCM7xx SoC family.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "exec/address-spaces.h"
+#include "hw/arm/npcm7xx.h"
+#include "hw/char/serial.h"
+#include "hw/loader.h"
+#include "hw/misc/unimp.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/units.h"
+#include "sysemu/sysemu.h"
+
+/* The first half of the address space is reserved for DDR4 DRAM. */
+#define NPCM7XX_DRAM_BA (0x00000000)
+#define NPCM7XX_DRAM_SZ (2 * GiB)
+
+/*
+ * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
+ * that aren't handled by any device.
+ */
+#define NPCM7XX_MMIO_BA (0x80000000)
+#define NPCM7XX_MMIO_SZ (0x7FFD0000)
+
+/* Core system modules. */
+#define NPCM7XX_L2C_BA (0xF03FC000)
+#define NPCM7XX_CPUP_BA (0xF03FE000)
+#define NPCM7XX_GCR_BA (0xF0800000)
+#define NPCM7XX_CLK_BA (0xF0801000)
+
+/* Memory blocks at the end of the address space */
+#define NPCM7XX_RAM2_BA (0xFFFD0000)
+#define NPCM7XX_RAM2_SZ (128 * KiB)
+#define NPCM7XX_ROM_BA (0xFFFF0000)
+#define NPCM7XX_ROM_SZ (64 * KiB)
+
+/*
+ * Interrupt lines going into the GIC. This does not include internal Cortex-A9
+ * interrupts.
+ */
+enum NPCM7xxInterrupt {
+ NPCM7XX_UART0_IRQ = 2,
+ NPCM7XX_UART1_IRQ,
+ NPCM7XX_UART2_IRQ,
+ NPCM7XX_UART3_IRQ,
+ NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
+ NPCM7XX_TIMER1_IRQ,
+ NPCM7XX_TIMER2_IRQ,
+ NPCM7XX_TIMER3_IRQ,
+ NPCM7XX_TIMER4_IRQ,
+ NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
+ NPCM7XX_TIMER6_IRQ,
+ NPCM7XX_TIMER7_IRQ,
+ NPCM7XX_TIMER8_IRQ,
+ NPCM7XX_TIMER9_IRQ,
+ NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
+ NPCM7XX_TIMER11_IRQ,
+ NPCM7XX_TIMER12_IRQ,
+ NPCM7XX_TIMER13_IRQ,
+ NPCM7XX_TIMER14_IRQ,
+};
+
+/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
+#define NPCM7XX_NUM_IRQ (160)
+
+/* Register base address for each Timer Module */
+static const hwaddr npcm7xx_tim_addr[] = {
+ 0xF0008000,
+ 0xF0009000,
+ 0xF000A000,
+};
+
+/* Register base address for each 16550 UART */
+static const hwaddr npcm7xx_uart_addr[] = {
+ 0xF0001000,
+ 0xF0002000,
+ 0xF0003000,
+ 0xF0004000,
+};
+
+void npcm7xx_write_secondary_boot(ARMCPU *cpu, const struct arm_boot_info *info)
+{
+ /*
+ * The default smpboot stub halts the secondary CPU with a 'wfi'
+ * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
+ * does not send an IPI to wake it up, so the second CPU fails to boot. So
+ * we need to provide our own smpboot stub that can not use 'wfi', it has
+ * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
+ */
+ uint32_t smpboot[] = {
+ 0xe59f2018, /* ldr r2, bootreg_addr */
+ 0xe3a00000, /* mov r0, #0 */
+ 0xe5820000, /* str r0, [r2] */
+ 0xe320f002, /* wfe */
+ 0xe5921000, /* ldr r1, [r2] */
+ 0xe1110001, /* tst r1, r1 */
+ 0x0afffffb, /* beq <wfe> */
+ 0xe12fff11, /* bx r1 */
+ NPCM7XX_SMP_BOOTREG_ADDR,
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
+ smpboot[i] = tswap32(smpboot[i]);
+ }
+
+ rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
+ NPCM7XX_SMP_LOADER_START);
+}
+
+static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
+{
+ return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
+}
+
+static void npcm7xx_init(Object *obj)
+{
+ NPCM7xxState *s = NPCM7XX(obj);
+ int i;
+
+ for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
+ object_initialize_child(obj, "cpu[*]", &s->cpu[i],
+ ARM_CPU_TYPE_NAME("cortex-a9"));
+ }
+
+ object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+ object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
+ object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
+ "power-on-straps");
+ object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
+
+ for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
+ object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
+ }
+}
+
+static void npcm7xx_realize(DeviceState *dev, Error **errp)
+{
+ NPCM7xxState *s = NPCM7XX(dev);
+ NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
+ Error *err = NULL;
+ int i;
+
+ /* I/O space -- unimplemented unless overridden below. */
+ create_unimplemented_device("npcm7xx.io", NPCM7XX_MMIO_BA, NPCM7XX_MMIO_SZ);
+
+ /* CPUs */
+ for (i = 0; i < nc->num_cpus; i++) {
+ object_property_set_int(OBJECT(&s->cpu[i]),
+ arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
+ "mp-affinity", &error_abort);
+ object_property_set_int(OBJECT(&s->cpu[i]), NPCM7XX_GIC_CPU_IF_ADDR,
+ "reset-cbar", &error_abort);
+ object_property_set_bool(OBJECT(&s->cpu[i]), true,
+ "reset-hivecs", &error_abort);
+
+ /* Disable security extensions. */
+ if (object_property_find(OBJECT(&s->cpu[i]), "has_el3", NULL)) {
+ object_property_set_bool(OBJECT(&s->cpu[i]), false, "has_el3",
+ &error_abort);
+ }
+
+ qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ }
+
+ /* A9MPCORE peripherals */
+ object_property_set_int(OBJECT(&s->a9mpcore), nc->num_cpus, "num-cpu",
+ &error_abort);
+ object_property_set_int(OBJECT(&s->a9mpcore), NPCM7XX_NUM_IRQ, "num-irq",
+ &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err);
+ if (err) {
+ error_propagate(errp, err);
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
+
+ for (i = 0; i < nc->num_cpus; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
+ qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
+ qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
+ }
+
+ /* L2 cache controller */
+ sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
+
+ /* System Global Control Registers (GCR) */
+ object_property_set_int(OBJECT(&s->gcr), nc->disabled_modules,
+ "disabled-modules", &err);
+ object_property_set_link(OBJECT(&s->gcr), OBJECT(s->dram), "dram", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_realize(SYS_BUS_DEVICE(&s->gcr), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
+
+ /* Clock Control Registers (CLK) */
+ sysbus_realize(SYS_BUS_DEVICE(&s->clk), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
+
+ /* Timer Modules (TIM) */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
+ for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
+ int first_irq;
+ int j;
+
+ sysbus_realize(sbd, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
+
+ first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
+ for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
+ qemu_irq irq = npcm7xx_irq(s, first_irq + j);
+ sysbus_connect_irq(sbd, j, irq);
+ }
+ }
+
+ /* UART0..3 (16550 compatible) */
+ for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
+ serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
+ npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
+ serial_hd(i), DEVICE_LITTLE_ENDIAN);
+ }
+
+ /* RAM2 (SRAM) */
+ memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
+ NPCM7XX_RAM2_SZ, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
+
+ /* Internal ROM */
+ memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
+
+ /* External DDR4 SDRAM */
+ memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, s->dram);
+}
+
+static Property npcm7xx_properties[] = {
+ DEFINE_PROP_LINK("dram", NPCM7xxState, dram, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = npcm7xx_realize;
+ dc->user_creatable = false;
+ device_class_set_props(dc, npcm7xx_properties);
+}
+
+static void npcm730_class_init(ObjectClass *oc, void *data)
+{
+ NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
+
+ /* NPCM730 is optimized for data center use, so no graphics, etc. */
+ nc->disabled_modules = 0x00300395;
+ nc->num_cpus = 2;
+}
+
+static void npcm750_class_init(ObjectClass *oc, void *data)
+{
+ NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
+
+ /* NPCM750 has 2 cores and a full set of peripherals */
+ nc->disabled_modules = 0x00000000;
+ nc->num_cpus = 2;
+}
+
+static const TypeInfo npcm7xx_soc_types[] = {
+ {
+ .name = TYPE_NPCM7XX,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(NPCM7xxState),
+ .instance_init = npcm7xx_init,
+ .class_size = sizeof(NPCM7xxClass),
+ .class_init = npcm7xx_class_init,
+ .abstract = true,
+ }, {
+ .name = TYPE_NPCM730,
+ .parent = TYPE_NPCM7XX,
+ .class_init = npcm730_class_init,
+ }, {
+ .name = TYPE_NPCM750,
+ .parent = TYPE_NPCM7XX,
+ .class_init = npcm750_class_init,
+ },
+};
+
+DEFINE_TYPES(npcm7xx_soc_types);
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
new file mode 100644
index 0000000000..38b8c33729
--- /dev/null
+++ b/include/hw/arm/npcm7xx.h
@@ -0,0 +1,80 @@
+/*
+ * Nuvoton NPCM7xx SoC family.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef NPCM7XX_H
+#define NPCM7XX_H
+
+#include "hw/boards.h"
+#include "hw/cpu/a9mpcore.h"
+#include "hw/misc/npcm7xx_clk.h"
+#include "hw/misc/npcm7xx_gcr.h"
+#include "hw/timer/npcm7xx_timer.h"
+#include "target/arm/cpu.h"
+
+#define NPCM7XX_MAX_NUM_CPUS (2)
+
+/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
+#define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */
+#define NPCM7XX_SMP_LOADER_START (0xFFFF0000) /* Boot ROM */
+#define NPCM7XX_SMP_BOOTREG_ADDR (0xF080013C) /* GCR.SCRPAD */
+#define NPCM7XX_GIC_CPU_IF_ADDR (0xF03FE100) /* GIC within A9 */
+
+typedef struct NPCM7xxState {
+ DeviceState parent;
+
+ ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS];
+ A9MPPrivState a9mpcore;
+
+ MemoryRegion sram;
+ MemoryRegion irom;
+ MemoryRegion *dram;
+
+ NPCM7xxGCRState gcr;
+ NPCM7xxCLKState clk;
+ NPCM7xxTimerCtrlState tim[3];
+} NPCM7xxState;
+
+#define TYPE_NPCM7XX "npcm7xx"
+#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
+
+#define TYPE_NPCM730 "npcm730"
+#define TYPE_NPCM750 "npcm750"
+
+typedef struct NPCM7xxClass {
+ DeviceClass parent;
+
+ /* Bitmask of modules that are permanently disabled on this chip. */
+ uint32_t disabled_modules;
+ /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
+ uint32_t num_cpus;
+} NPCM7xxClass;
+
+#define NPCM7XX_CLASS(klass) \
+ OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
+#define NPCM7XX_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
+
+/**
+ * npcm7xx_write_secondary_boot - Write stub for booting secondary CPU.
+ * @cpu: The CPU to be booted.
+ * @info: Boot info structure for the board.
+ *
+ * This will write a short code stub to the internal ROM that will keep the
+ * secondary CPU spinning until the primary CPU writes an address to the SCRPAD
+ * register in the GCR, after which the secondary CPU will jump there.
+ */
+extern void npcm7xx_write_secondary_boot(ARMCPU *cpu,
+ const struct arm_boot_info *info);
+
+#endif /* NPCM7XX_H */
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 06/12] hw/arm: Add two NPCM7xx-based machines
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (4 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 07/12] hw/arm: Load -bios image as a boot ROM for npcm7xx Havard Skinnemoen
` (7 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
This adds two new machines, both supported by OpenBMC:
- npcm750-evb: Nuvoton NPCM750 Evaluation Board.
- quanta-gsj: A board with a NPCM730 chip.
They rely on the NPCM7xx SoC device to do the heavy lifting. They are
almost completely identical at the moment, apart from the SoC type,
which currently only changes the reset contents of one register
(GCR.MDLR), but they might grow apart a bit more as more functionality
is added.
Both machines can boot the Linux kernel into /bin/sh.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/arm/Makefile.objs | 2 +-
hw/arm/npcm7xx_boards.c | 147 +++++++++++++++++++++++++++++++++++++++
include/hw/arm/npcm7xx.h | 19 +++++
3 files changed, 167 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm7xx_boards.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 13d163a599..c333548ce1 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -41,7 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
-obj-$(CONFIG_NPCM7XX) += npcm7xx.o
+obj-$(CONFIG_NPCM7XX) += npcm7xx.o npcm7xx_boards.o
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
new file mode 100644
index 0000000000..c82d9e018b
--- /dev/null
+++ b/hw/arm/npcm7xx_boards.c
@@ -0,0 +1,147 @@
+/*
+ * Machine definitions for boards featuring an NPCM7xx SoC.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/arm/boot.h"
+#include "hw/arm/npcm7xx.h"
+#include "hw/core/cpu.h"
+#include "qapi/error.h"
+#include "qemu/units.h"
+
+#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
+#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
+
+static struct arm_boot_info npcm7xx_binfo = {
+ .loader_start = NPCM7XX_LOADER_START,
+ .smp_loader_start = NPCM7XX_SMP_LOADER_START,
+ .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR,
+ .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR,
+ .write_secondary_boot = npcm7xx_write_secondary_boot,
+ .board_id = -1,
+};
+
+static void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
+{
+ NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc);
+
+ npcm7xx_binfo.ram_size = machine->ram_size;
+ npcm7xx_binfo.nb_cpus = sc->num_cpus;
+
+ arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
+}
+
+static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
+ uint32_t hw_straps)
+{
+ NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
+ NPCM7xxState *soc;
+
+ soc = NPCM7XX(object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
+ &error_abort, NULL));
+ object_property_set_link(OBJECT(soc), OBJECT(machine->ram), "dram",
+ &error_abort);
+ object_property_set_uint(OBJECT(soc), hw_straps, "power-on-straps",
+ &error_abort);
+ qdev_realize(DEVICE(soc), NULL, &error_abort);
+
+ return soc;
+}
+
+static void npcm750_evb_init(MachineState *machine)
+{
+ NPCM7xxState *soc;
+
+ soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
+
+ npcm7xx_load_kernel(machine, soc);
+}
+
+static void quanta_gsj_init(MachineState *machine)
+{
+ NPCM7xxState *soc;
+
+ soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
+
+ npcm7xx_load_kernel(machine, soc);
+}
+
+static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
+{
+ NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
+ MachineClass *mc = MACHINE_CLASS(nmc);
+
+ nmc->soc_type = type;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
+}
+
+static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->no_floppy = 1;
+ mc->no_cdrom = 1;
+ mc->no_parallel = 1;
+ mc->default_ram_id = "ram";
+}
+
+/*
+ * Schematics:
+ * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
+ */
+static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
+{
+ NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ npcm7xx_set_soc_type(nmc, TYPE_NPCM750);
+
+ mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)";
+ mc->init = npcm750_evb_init;
+ mc->default_ram_size = 512 * MiB;
+};
+
+static void gsj_machine_class_init(ObjectClass *oc, void *data)
+{
+ NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
+
+ mc->desc = "Quanta GSJ (Cortex A9)";
+ mc->init = quanta_gsj_init;
+ mc->default_ram_size = 512 * MiB;
+};
+
+static const TypeInfo npcm7xx_machine_types[] = {
+ {
+ .name = TYPE_NPCM7XX_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(NPCM7xxMachine),
+ .class_size = sizeof(NPCM7xxMachineClass),
+ .class_init = npcm7xx_machine_class_init,
+ .abstract = true,
+ }, {
+ .name = MACHINE_TYPE_NAME("npcm750-evb"),
+ .parent = TYPE_NPCM7XX_MACHINE,
+ .class_init = npcm750_evb_machine_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("quanta-gsj"),
+ .parent = TYPE_NPCM7XX_MACHINE,
+ .class_init = gsj_machine_class_init,
+ },
+};
+
+DEFINE_TYPES(npcm7xx_machine_types)
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 38b8c33729..a241af0b8c 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -30,6 +30,25 @@
#define NPCM7XX_SMP_BOOTREG_ADDR (0xF080013C) /* GCR.SCRPAD */
#define NPCM7XX_GIC_CPU_IF_ADDR (0xF03FE100) /* GIC within A9 */
+typedef struct NPCM7xxMachine {
+ MachineState parent;
+} NPCM7xxMachine;
+
+#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
+#define NPCM7XX_MACHINE(obj) \
+ OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
+
+typedef struct NPCM7xxMachineClass {
+ MachineClass parent;
+
+ const char *soc_type;
+} NPCM7xxMachineClass;
+
+#define NPCM7XX_MACHINE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE)
+#define NPCM7XX_MACHINE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
+
typedef struct NPCM7xxState {
DeviceState parent;
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 07/12] hw/arm: Load -bios image as a boot ROM for npcm7xx
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (5 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 06/12] hw/arm: Add two NPCM7xx-based machines Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model Havard Skinnemoen
` (6 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
If a -bios option is specified on the command line, load the image into
the internal ROM memory region, which contains the first instructions
run by the CPU after reset.
A minimal Apache-2.0-licensed boot ROM can be found at
https://github.com/google/vbootrom
It is by no means feature complete, but it is enough to launch the
Nuvoton bootblock[1] from offset 0 in the flash, which in turn will
launch u-boot and finally the Linux kernel.
[1] https://github.com/Nuvoton-Israel/bootblock
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/arm/npcm7xx_boards.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index c82d9e018b..ca33262a59 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -18,8 +18,11 @@
#include "hw/arm/boot.h"
#include "hw/arm/npcm7xx.h"
#include "hw/core/cpu.h"
+#include "hw/loader.h"
#include "qapi/error.h"
+#include "qemu-common.h"
#include "qemu/units.h"
+#include "sysemu/sysemu.h"
#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
@@ -33,6 +36,25 @@ static struct arm_boot_info npcm7xx_binfo = {
.board_id = -1,
};
+static void npcm7xx_load_bootrom(NPCM7xxState *soc)
+{
+ if (bios_name) {
+ g_autofree char *filename = NULL;
+ int ret;
+
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (!filename) {
+ error_report("Could not find ROM image '%s'", bios_name);
+ exit(1);
+ }
+ ret = load_image_mr(filename, &soc->irom);
+ if (ret < 0) {
+ error_report("Failed to load ROM image '%s'", filename);
+ exit(1);
+ }
+ }
+}
+
static void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
{
NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc);
@@ -65,7 +87,7 @@ static void npcm750_evb_init(MachineState *machine)
NPCM7xxState *soc;
soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
-
+ npcm7xx_load_bootrom(soc);
npcm7xx_load_kernel(machine, soc);
}
@@ -74,7 +96,7 @@ static void quanta_gsj_init(MachineState *machine)
NPCM7xxState *soc;
soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
-
+ npcm7xx_load_bootrom(soc);
npcm7xx_load_kernel(machine, soc);
}
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (6 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 07/12] hw/arm: Load -bios image as a boot ROM for npcm7xx Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-07-03 13:46 ` Philippe Mathieu-Daudé
2020-06-26 23:55 ` [PATCH v3 09/12] hw/mem: Stubbed out NPCM7xx Memory Controller model Havard Skinnemoen
` (5 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen,
Avi Fishman
This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.
Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/arm/npcm7xx.c | 32 +++
hw/nvram/Makefile.objs | 1 +
hw/nvram/npcm7xx_otp.c | 391 +++++++++++++++++++++++++++++++++
include/hw/arm/npcm7xx.h | 3 +
include/hw/nvram/npcm7xx_otp.h | 93 ++++++++
5 files changed, 520 insertions(+)
create mode 100644 hw/nvram/npcm7xx_otp.c
create mode 100644 include/hw/nvram/npcm7xx_otp.h
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index f395fe84b6..825910a4bf 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -36,6 +36,10 @@
#define NPCM7XX_MMIO_BA (0x80000000)
#define NPCM7XX_MMIO_SZ (0x7FFD0000)
+/* OTP key storage and fuse strap array */
+#define NPCM7XX_OTP1_BA (0xF0189000)
+#define NPCM7XX_OTP2_BA (0xF018A000)
+
/* Core system modules. */
#define NPCM7XX_L2C_BA (0xF03FC000)
#define NPCM7XX_CPUP_BA (0xF03FE000)
@@ -122,6 +126,15 @@ void npcm7xx_write_secondary_boot(ARMCPU *cpu, const struct arm_boot_info *info)
NPCM7XX_SMP_LOADER_START);
}
+static void npcm7xx_init_fuses(NPCM7xxState *s)
+{
+ NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
+ uint32_t value;
+
+ value = tswap32(nc->disabled_modules);
+ npcm7xx_otp_array_write(&s->fuse_array, &value, 64, sizeof(value));
+}
+
static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
{
return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -142,6 +155,10 @@ static void npcm7xx_init(Object *obj)
object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
"power-on-straps");
object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
+ object_initialize_child(obj, "otp1", &s->key_storage,
+ TYPE_NPCM7XX_KEY_STORAGE);
+ object_initialize_child(obj, "otp2", &s->fuse_array,
+ TYPE_NPCM7XX_FUSE_ARRAY);
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -225,6 +242,21 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
+ /* OTP key storage and fuse strap array */
+ sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
+ sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
+ npcm7xx_init_fuses(s);
+
/* Timer Modules (TIM) */
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs
index f3ad921382..0270f0bbf7 100644
--- a/hw/nvram/Makefile.objs
+++ b/hw/nvram/Makefile.objs
@@ -4,5 +4,6 @@ common-obj-$(CONFIG_AT24C) += eeprom_at24c.o
common-obj-y += fw_cfg.o
common-obj-$(CONFIG_CHRP_NVRAM) += chrp_nvram.o
common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o
+common-obj-$(CONFIG_NPCM7XX) += npcm7xx_otp.o
common-obj-$(CONFIG_NRF51_SOC) += nrf51_nvm.o
obj-$(CONFIG_PSERIES) += spapr_nvram.o
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
new file mode 100644
index 0000000000..71fc728a2d
--- /dev/null
+++ b/hw/nvram/npcm7xx_otp.c
@@ -0,0 +1,391 @@
+/*
+ * Nuvoton NPCM7xx OTP (Fuse Array) Interface
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/nvram/npcm7xx_otp.h"
+#include "qapi/error.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+/* Each module has 4 KiB of register space. Only a fraction of it is used. */
+#define NPCM7XX_OTP_REGS_SIZE (4 * KiB)
+
+/* Register field definitions. */
+#define FST_RIEN BIT(2)
+#define FST_RDST BIT(1)
+#define FST_RDY BIT(0)
+#define FST_RO_MASK (FST_RDST | FST_RDY)
+
+#define FADDR_BYTEADDR(rv) extract32((rv), 0, 10)
+#define FADDR_BITPOS(rv) extract32((rv), 10, 3)
+
+#define FDATA_CLEAR 0x00000001
+
+#define FCFG_FDIS BIT(31)
+#define FCFG_FCFGLK_MASK 0x00ff0000
+
+#define FCTL_PROG_CMD1 0x00000001
+#define FCTL_PROG_CMD2 0xbf79e5d0
+#define FCTL_READ_CMD 0x00000002
+
+static uint8_t ecc_encode_nibble(uint8_t n)
+{
+ uint8_t result = n;
+
+ result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4;
+ result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5;
+ result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6;
+ result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7;
+
+ return result;
+}
+
+void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
+ unsigned int offset, unsigned int len)
+{
+ const uint8_t *src = data;
+ uint8_t *dst = s->array + offset;
+
+ while (len-- > 0) {
+ uint8_t c = *src++;
+
+ *dst++ = ecc_encode_nibble(extract8(c, 0, 4));
+ *dst++ = ecc_encode_nibble(extract8(c, 4, 4));
+ }
+}
+
+/* Common register read handler for both OTP classes. */
+static uint64_t npcm7xx_otp_read(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg)
+{
+ uint32_t value = 0;
+
+ switch (reg) {
+ case NPCM7XX_OTP_FST:
+ case NPCM7XX_OTP_FADDR:
+ case NPCM7XX_OTP_FDATA:
+ case NPCM7XX_OTP_FCFG:
+ value = s->regs[reg];
+ break;
+
+ case NPCM7XX_OTP_FCTL:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: read from write-only FCTL register\n",
+ DEVICE(s)->canonical_path);
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read from invalid offset 0x%zx\n",
+ DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
+ break;
+ }
+
+ return value;
+}
+
+/* Read a byte from the OTP array into the data register. */
+static void npcm7xx_otp_read_array(NPCM7xxOTPState *s)
+{
+ uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
+
+ s->regs[NPCM7XX_OTP_FDATA] = s->array[FADDR_BYTEADDR(faddr)];
+ s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
+}
+
+/* Program a byte from the data register into the OTP array. */
+static void npcm7xx_otp_program_array(NPCM7xxOTPState *s)
+{
+ uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
+
+ /* Bits can only go 0->1, never 1->0. */
+ s->array[FADDR_BYTEADDR(faddr)] |= (1U << FADDR_BITPOS(faddr));
+ s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
+}
+
+/* Compute the next value of the FCFG register. */
+static uint32_t npcm7xx_otp_compute_fcfg(uint32_t cur_value, uint32_t new_value)
+{
+ uint32_t lock_mask;
+ uint32_t value;
+
+ /*
+ * FCFGLK holds sticky bits 16..23, indicating which bits in FPRGLK (8..15)
+ * and FRDLK (0..7) that are read-only.
+ */
+ lock_mask = (cur_value & FCFG_FCFGLK_MASK) >> 8;
+ lock_mask |= lock_mask >> 8;
+ /* FDIS and FCFGLK bits are sticky (write 1 to set; can't clear). */
+ value = cur_value & (FCFG_FDIS | FCFG_FCFGLK_MASK);
+ /* Preserve read-only bits in FPRGLK and FRDLK */
+ value |= cur_value & lock_mask;
+ /* Set all bits that aren't read-only. */
+ value |= new_value & ~lock_mask;
+
+ return value;
+}
+
+/* Common register write handler for both OTP classes. */
+static void npcm7xx_otp_write(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg,
+ uint32_t value)
+{
+ switch (reg) {
+ case NPCM7XX_OTP_FST:
+ /* RDST is cleared by writing 1 to it. */
+ if (value & FST_RDST) {
+ s->regs[NPCM7XX_OTP_FST] &= ~FST_RDST;
+ }
+ /* Preserve read-only and write-one-to-clear bits */
+ value =
+ (value & ~FST_RO_MASK) | (s->regs[NPCM7XX_OTP_FST] & FST_RO_MASK);
+ break;
+
+ case NPCM7XX_OTP_FADDR:
+ break;
+
+ case NPCM7XX_OTP_FDATA:
+ /*
+ * This register is cleared by writing a magic value to it; no other
+ * values can be written.
+ */
+ if (value == FDATA_CLEAR) {
+ value = 0;
+ } else {
+ value = s->regs[NPCM7XX_OTP_FDATA];
+ }
+ break;
+
+ case NPCM7XX_OTP_FCFG:
+ value = npcm7xx_otp_compute_fcfg(s->regs[NPCM7XX_OTP_FCFG], value);
+ break;
+
+ case NPCM7XX_OTP_FCTL:
+ switch (value) {
+ case FCTL_READ_CMD:
+ npcm7xx_otp_read_array(s);
+ break;
+
+ case FCTL_PROG_CMD1:
+ /*
+ * Programming requires writing two separate magic values to this
+ * register; this is the first one. Just store it so it can be
+ * verified later when the second magic value is received.
+ */
+ break;
+
+ case FCTL_PROG_CMD2:
+ /*
+ * Only initiate programming if we received the first half of the
+ * command immediately before this one.
+ */
+ if (s->regs[NPCM7XX_OTP_FCTL] == FCTL_PROG_CMD1) {
+ npcm7xx_otp_program_array(s);
+ }
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: unrecognized FCNTL value 0x%" PRIx32 "\n",
+ DEVICE(s)->canonical_path, value);
+ break;
+ }
+ if (value != FCTL_PROG_CMD1) {
+ value = 0;
+ }
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to invalid offset 0x%zx\n",
+ DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
+ return;
+ }
+
+ s->regs[reg] = value;
+}
+
+/* Register read handler specific to the fuse array OTP module. */
+static uint64_t npcm7xx_fuse_array_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
+ NPCM7xxOTPState *s = opaque;
+ uint32_t value;
+
+ /*
+ * Only the Fuse Strap register needs special handling; all other registers
+ * work the same way for both kinds of OTP modules.
+ */
+ if (reg != NPCM7XX_OTP_FUSTRAP) {
+ value = npcm7xx_otp_read(s, reg);
+ } else {
+ /* FUSTRAP is stored as three copies in the OTP array. */
+ uint32_t fustrap[3];
+
+ memcpy(fustrap, &s->array[0], sizeof(fustrap));
+
+ /* Determine value by a majority vote on each bit. */
+ value = (fustrap[0] & fustrap[1]) | (fustrap[0] & fustrap[2]) |
+ (fustrap[1] & fustrap[2]);
+ }
+
+ return value;
+}
+
+/* Register write handler specific to the fuse array OTP module. */
+static void npcm7xx_fuse_array_write(void *opaque, hwaddr addr, uint64_t v,
+ unsigned int size)
+{
+ NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
+ NPCM7xxOTPState *s = opaque;
+
+ /*
+ * The Fuse Strap register is read-only. Other registers are handled by
+ * common code.
+ */
+ if (reg != NPCM7XX_OTP_FUSTRAP) {
+ npcm7xx_otp_write(s, reg, v);
+ }
+}
+
+static const MemoryRegionOps npcm7xx_fuse_array_ops = {
+ .read = npcm7xx_fuse_array_read,
+ .write = npcm7xx_fuse_array_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+/* Register read handler specific to the key storage OTP module. */
+static uint64_t npcm7xx_key_storage_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
+ NPCM7xxOTPState *s = opaque;
+
+ /*
+ * Only the Fuse Key Index register needs special handling; all other
+ * registers work the same way for both kinds of OTP modules.
+ */
+ if (reg != NPCM7XX_OTP_FKEYIND) {
+ return npcm7xx_otp_read(s, reg);
+ }
+
+ qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
+
+ return s->regs[NPCM7XX_OTP_FKEYIND];
+}
+
+/* Register write handler specific to the key storage OTP module. */
+static void npcm7xx_key_storage_write(void *opaque, hwaddr addr, uint64_t v,
+ unsigned int size)
+{
+ NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
+ NPCM7xxOTPState *s = opaque;
+
+ /*
+ * Only the Fuse Key Index register needs special handling; all other
+ * registers work the same way for both kinds of OTP modules.
+ */
+ if (reg != NPCM7XX_OTP_FKEYIND) {
+ npcm7xx_otp_write(s, reg, v);
+ return;
+ }
+
+ qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
+
+ s->regs[NPCM7XX_OTP_FKEYIND] = v;
+}
+
+static const MemoryRegionOps npcm7xx_key_storage_ops = {
+ .read = npcm7xx_key_storage_read,
+ .write = npcm7xx_key_storage_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void npcm7xx_otp_enter_reset(Object *obj, ResetType type)
+{
+ NPCM7xxOTPState *s = NPCM7XX_OTP(obj);
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ s->regs[NPCM7XX_OTP_FST] = 0x00000001;
+ s->regs[NPCM7XX_OTP_FCFG] = 0x20000000;
+}
+
+static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
+{
+ NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
+ NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
+ SysBusDevice *sbd = &s->parent;
+
+ s->array = g_malloc0(NPCM7XX_OTP_ARRAY_BYTES);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
+ NPCM7XX_OTP_REGS_SIZE);
+ sysbus_init_mmio(sbd, &s->mmio);
+}
+
+static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = npcm7xx_otp_realize;
+ rc->phases.enter = npcm7xx_otp_enter_reset;
+}
+
+static void npcm7xx_key_storage_class_init(ObjectClass *klass, void *data)
+{
+ NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
+
+ oc->mmio_ops = &npcm7xx_key_storage_ops;
+}
+
+static void npcm7xx_fuse_array_class_init(ObjectClass *klass, void *data)
+{
+ NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
+
+ oc->mmio_ops = &npcm7xx_fuse_array_ops;
+}
+
+static const TypeInfo npcm7xx_otp_types[] = {
+ {
+ .name = TYPE_NPCM7XX_OTP,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxOTPState),
+ .class_init = npcm7xx_otp_class_init,
+ .abstract = true,
+ },
+ {
+ .name = TYPE_NPCM7XX_KEY_STORAGE,
+ .parent = TYPE_NPCM7XX_OTP,
+ .class_init = npcm7xx_key_storage_class_init,
+ },
+ {
+ .name = TYPE_NPCM7XX_FUSE_ARRAY,
+ .parent = TYPE_NPCM7XX_OTP,
+ .class_init = npcm7xx_fuse_array_class_init,
+ },
+};
+DEFINE_TYPES(npcm7xx_otp_types);
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index a241af0b8c..360cd965a7 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -19,6 +19,7 @@
#include "hw/cpu/a9mpcore.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/misc/npcm7xx_gcr.h"
+#include "hw/nvram/npcm7xx_otp.h"
#include "hw/timer/npcm7xx_timer.h"
#include "target/arm/cpu.h"
@@ -62,6 +63,8 @@ typedef struct NPCM7xxState {
NPCM7xxGCRState gcr;
NPCM7xxCLKState clk;
NPCM7xxTimerCtrlState tim[3];
+ NPCM7xxOTPState key_storage;
+ NPCM7xxOTPState fuse_array;
} NPCM7xxState;
#define TYPE_NPCM7XX "npcm7xx"
diff --git a/include/hw/nvram/npcm7xx_otp.h b/include/hw/nvram/npcm7xx_otp.h
new file mode 100644
index 0000000000..1127c48fef
--- /dev/null
+++ b/include/hw/nvram/npcm7xx_otp.h
@@ -0,0 +1,93 @@
+/*
+ * Nuvoton NPCM7xx OTP (Fuse Array) Interface
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef NPCM7XX_OTP_H
+#define NPCM7XX_OTP_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+/* Each OTP module holds 8192 bits of one-time programmable storage */
+#define NPCM7XX_OTP_ARRAY_BITS (8192)
+#define NPCM7XX_OTP_ARRAY_BYTES (NPCM7XX_OTP_ARRAY_BITS / 8)
+
+/**
+ * enum NPCM7xxOTPRegister - 32-bit register indices.
+ */
+typedef enum NPCM7xxOTPRegister {
+ NPCM7XX_OTP_FST,
+ NPCM7XX_OTP_FADDR,
+ NPCM7XX_OTP_FDATA,
+ NPCM7XX_OTP_FCFG,
+ /* Offset 0x10 is FKEYIND in OTP1, FUSTRAP in OTP2 */
+ NPCM7XX_OTP_FKEYIND = 0x0010 / sizeof(uint32_t),
+ NPCM7XX_OTP_FUSTRAP = 0x0010 / sizeof(uint32_t),
+ NPCM7XX_OTP_FCTL,
+ NPCM7XX_OTP_NR_REGS,
+} NPCM7xxOTPRegister;
+
+/**
+ * struct NPCM7xxOTPState - Device state for one OTP module.
+ * @parent: System bus device.
+ * @mmio: Memory region through which registers are accessed.
+ * @regs: Register contents.
+ * @array: OTP storage array.
+ */
+typedef struct NPCM7xxOTPState {
+ SysBusDevice parent;
+
+ MemoryRegion mmio;
+ uint32_t regs[NPCM7XX_OTP_NR_REGS];
+ uint8_t *array;
+} NPCM7xxOTPState;
+
+#define TYPE_NPCM7XX_OTP "npcm7xx-otp"
+#define NPCM7XX_OTP(obj) OBJECT_CHECK(NPCM7xxOTPState, (obj), TYPE_NPCM7XX_OTP)
+
+#define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
+#define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
+
+/**
+ * struct NPCM7xxOTPClass - OTP module class.
+ * @parent: System bus device class.
+ * @mmio_ops: MMIO register operations for this type of module.
+ *
+ * The two OTP modules (key-storage and fuse-array) have slightly different
+ * behavior, so we give them different MMIO register operations.
+ */
+typedef struct NPCM7xxOTPClass {
+ SysBusDeviceClass parent;
+
+ const MemoryRegionOps *mmio_ops;
+} NPCM7xxOTPClass;
+
+#define NPCM7XX_OTP_CLASS(klass) \
+ OBJECT_CLASS_CHECK(NPCM7xxOTPClass, (klass), TYPE_NPCM7XX_OTP)
+#define NPCM7XX_OTP_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(NPCM7xxOTPClass, (obj), TYPE_NPCM7XX_OTP)
+
+/**
+ * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
+ * @s: OTP module.
+ * @data: Data to be encoded and written.
+ * @offset: Offset of first byte to be written in the OTP array.
+ * @len: Number of bytes before ECC encoding.
+ *
+ * Each nibble of data is encoded into a byte, so the number of bytes written
+ * to the array will be @len * 2.
+ */
+extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
+ unsigned int offset, unsigned int len);
+
+#endif /* NPCM7XX_OTP_H */
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 09/12] hw/mem: Stubbed out NPCM7xx Memory Controller model
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (7 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 10/12] hw/ssi: NPCM7xx Flash Interface Unit device model Havard Skinnemoen
` (4 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
This just implements the bare minimum to cause the boot block to skip
memory initialization.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/arm/npcm7xx.c | 10 +++++
hw/mem/Makefile.objs | 1 +
hw/mem/npcm7xx_mc.c | 83 +++++++++++++++++++++++++++++++++++++
include/hw/arm/npcm7xx.h | 2 +
include/hw/mem/npcm7xx_mc.h | 35 ++++++++++++++++
5 files changed, 131 insertions(+)
create mode 100644 hw/mem/npcm7xx_mc.c
create mode 100644 include/hw/mem/npcm7xx_mc.h
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 825910a4bf..4ab7fdd405 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -45,6 +45,7 @@
#define NPCM7XX_CPUP_BA (0xF03FE000)
#define NPCM7XX_GCR_BA (0xF0800000)
#define NPCM7XX_CLK_BA (0xF0801000)
+#define NPCM7XX_MC_BA (0xF0824000)
/* Memory blocks at the end of the address space */
#define NPCM7XX_RAM2_BA (0xFFFD0000)
@@ -159,6 +160,7 @@ static void npcm7xx_init(Object *obj)
TYPE_NPCM7XX_KEY_STORAGE);
object_initialize_child(obj, "otp2", &s->fuse_array,
TYPE_NPCM7XX_FUSE_ARRAY);
+ object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -257,6 +259,14 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
npcm7xx_init_fuses(s);
+ /* Fake Memory Controller (MC) */
+ sysbus_realize(SYS_BUS_DEVICE(&s->mc), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
+
/* Timer Modules (TIM) */
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
diff --git a/hw/mem/Makefile.objs b/hw/mem/Makefile.objs
index 56345befd0..9a33ef7b35 100644
--- a/hw/mem/Makefile.objs
+++ b/hw/mem/Makefile.objs
@@ -1,3 +1,4 @@
common-obj-$(CONFIG_DIMM) += pc-dimm.o
common-obj-y += memory-device.o
+common-obj-$(CONFIG_NPCM7XX) += npcm7xx_mc.o
common-obj-$(CONFIG_NVDIMM) += nvdimm.o
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
new file mode 100644
index 0000000000..03a7fb53dc
--- /dev/null
+++ b/hw/mem/npcm7xx_mc.c
@@ -0,0 +1,83 @@
+/*
+ * Nuvoton NPCM7xx Memory Controller stub
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/mem/npcm7xx_mc.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#define NPCM7XX_MC_REGS_SIZE (4 * KiB)
+
+static uint64_t npcm7xx_mc_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ /*
+ * If bits 8..11 @ offset 0 are not zero, the boot block thinks the memory
+ * controller has already been initialized and will skip DDR training.
+ */
+ if (addr == 0) {
+ return 0x100;
+ }
+
+ qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
+
+ return 0;
+}
+
+static void npcm7xx_mc_write(void *opaque, hwaddr addr, uint64_t v,
+ unsigned int size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
+}
+
+static const MemoryRegionOps npcm7xx_mc_ops = {
+ .read = npcm7xx_mc_read,
+ .write = npcm7xx_mc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
+{
+ NPCM7xxMCState *s = NPCM7XX_MC(dev);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
+ NPCM7XX_MC_REGS_SIZE);
+ sysbus_init_mmio(&s->parent, &s->mmio);
+}
+
+static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM7xx Memory Controller stub";
+ dc->realize = npcm7xx_mc_realize;
+}
+
+static const TypeInfo npcm7xx_mc_types[] = {
+ {
+ .name = TYPE_NPCM7XX_MC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxMCState),
+ .class_init = npcm7xx_mc_class_init,
+ },
+};
+DEFINE_TYPES(npcm7xx_mc_types);
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 360cd965a7..8f49f7015c 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -17,6 +17,7 @@
#include "hw/boards.h"
#include "hw/cpu/a9mpcore.h"
+#include "hw/mem/npcm7xx_mc.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/misc/npcm7xx_gcr.h"
#include "hw/nvram/npcm7xx_otp.h"
@@ -65,6 +66,7 @@ typedef struct NPCM7xxState {
NPCM7xxTimerCtrlState tim[3];
NPCM7xxOTPState key_storage;
NPCM7xxOTPState fuse_array;
+ NPCM7xxMCState mc;
} NPCM7xxState;
#define TYPE_NPCM7XX "npcm7xx"
diff --git a/include/hw/mem/npcm7xx_mc.h b/include/hw/mem/npcm7xx_mc.h
new file mode 100644
index 0000000000..8781f5c979
--- /dev/null
+++ b/include/hw/mem/npcm7xx_mc.h
@@ -0,0 +1,35 @@
+/*
+ * Nuvoton NPCM7xx Memory Controller stub
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef NPCM7XX_MC_H
+#define NPCM7XX_MC_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+/**
+ * struct NPCM7xxMCState - Device state for the memory controller.
+ * @parent: System bus device.
+ * @mmio: Memory region through which registers are accessed.
+ */
+typedef struct NPCM7xxMCState {
+ SysBusDevice parent;
+
+ MemoryRegion mmio;
+} NPCM7xxMCState;
+
+#define TYPE_NPCM7XX_MC "npcm7xx-mc"
+#define NPCM7XX_MC(obj) OBJECT_CHECK(NPCM7xxMCState, (obj), TYPE_NPCM7XX_MC)
+
+#endif /* NPCM7XX_MC_H */
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 10/12] hw/ssi: NPCM7xx Flash Interface Unit device model
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (8 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 09/12] hw/mem: Stubbed out NPCM7xx Memory Controller model Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 11/12] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj Havard Skinnemoen
` (3 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
This implements a device model for the NPCM7xx SPI flash controller.
Direct reads and writes, and user-mode transactions have been tested in
various modes. Protection features are not implemented yet.
All the FIU instances are available in the SoC's address space,
regardless of whether or not they're connected to actual flash chips.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/arm/Kconfig | 1 +
hw/arm/npcm7xx.c | 57 ++++
hw/ssi/Makefile.objs | 1 +
hw/ssi/npcm7xx_fiu.c | 496 +++++++++++++++++++++++++++++++++++
hw/ssi/trace-events | 9 +
include/hw/arm/npcm7xx.h | 2 +
include/hw/ssi/npcm7xx_fiu.h | 99 +++++++
7 files changed, 665 insertions(+)
create mode 100644 hw/ssi/npcm7xx_fiu.c
create mode 100644 include/hw/ssi/npcm7xx_fiu.h
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index a31d0d282f..8d0ef0593b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -360,6 +360,7 @@ config NPCM7XX
select ARM_GIC
select PL310 # cache controller
select SERIAL
+ select SSI
select UNIMP
config FSL_IMX25
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 4ab7fdd405..e437d370d6 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -97,6 +97,37 @@ static const hwaddr npcm7xx_uart_addr[] = {
0xF0004000,
};
+static const hwaddr npcm7xx_fiu0_flash_addr[] = {
+ 0x80000000,
+ 0x88000000,
+};
+
+static const hwaddr npcm7xx_fiu3_flash_addr[] = {
+ 0xa0000000,
+ 0xa8000000,
+ 0xb0000000,
+ 0xb8000000,
+};
+
+static const struct {
+ const char *name;
+ hwaddr regs_addr;
+ int cs_count;
+ const hwaddr *flash_addr;
+} npcm7xx_fiu[] = {
+ {
+ .name = "fiu0",
+ .regs_addr = 0xfb000000,
+ .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
+ .flash_addr = npcm7xx_fiu0_flash_addr,
+ }, {
+ .name = "fiu3",
+ .regs_addr = 0xc0000000,
+ .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
+ .flash_addr = npcm7xx_fiu3_flash_addr,
+ },
+};
+
void npcm7xx_write_secondary_boot(ARMCPU *cpu, const struct arm_boot_info *info)
{
/*
@@ -165,6 +196,12 @@ static void npcm7xx_init(Object *obj)
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
}
+
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
+ for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
+ object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
+ TYPE_NPCM7XX_FIU);
+ }
}
static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -295,6 +332,26 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
serial_hd(i), DEVICE_LITTLE_ENDIAN);
}
+ /* Flash Interface Unit (FIU) */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
+ for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
+ int j;
+
+ object_property_set_int(OBJECT(sbd), npcm7xx_fiu[i].cs_count,
+ "cs-count", &error_abort);
+ sysbus_realize(sbd, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
+ for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
+ sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
+ }
+ }
+
/* RAM2 (SRAM) */
memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
NPCM7XX_RAM2_SZ, &err);
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index 07a85f1967..cab48e72c9 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -5,6 +5,7 @@ common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
common-obj-$(CONFIG_MSF2) += mss-spi.o
+common-obj-$(CONFIG_NPCM7XX) += npcm7xx_fiu.o
common-obj-$(CONFIG_OMAP) += omap_spi.o
common-obj-$(CONFIG_IMX) += imx_spi.o
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
new file mode 100644
index 0000000000..3f0b82a181
--- /dev/null
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -0,0 +1,496 @@
+/*
+ * Nuvoton NPCM7xx Flash Interface Unit (FIU)
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/ssi/npcm7xx_fiu.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+/* Up to 128 MiB of flash may be accessed directly as memory. */
+#define NPCM7XX_FIU_FLASH_WINDOW_SIZE (128 * MiB)
+
+/* Each module has 4 KiB of register space. Only a fraction of it is used. */
+#define NPCM7XX_FIU_CTRL_REGS_SIZE (4 * KiB)
+
+/* FIU_{DRD,DWR,UMA,PTR}_CFG cannot be written when this bit is set. */
+#define NPCM7XX_FIU_CFG_LCK BIT(31)
+
+/* Direct Read configuration register fields. */
+#define FIU_DRD_CFG_ADDSIZ(rv) extract32(rv, 16, 2)
+#define FIU_ADDSIZ_3BYTES 0
+#define FIU_ADDSIZ_4BYTES 1
+#define FIU_DRD_CFG_DBW(rv) extract32(rv, 12, 2)
+#define FIU_DRD_CFG_ACCTYPE(rv) extract32(rv, 8, 2)
+#define FIU_DRD_CFG_RDCMD(rv) extract32(rv, 0, 8)
+
+/* Direct Write configuration register fields. */
+#define FIU_DWR_CFG_ADDSIZ(rv) extract32(rv, 16, 2)
+#define FIU_DWR_CFG_WRCMD(rv) extract32(rv, 0, 8)
+
+/* User-Mode Access register fields. */
+
+/* Command Mode Lock and the bits protected by it. */
+#define FIU_UMA_CFG_CMMLCK BIT(30)
+#define FIU_UMA_CFG_CMMLCK_MASK 0x00000403
+
+#define FIU_UMA_CFG_RDATSIZ(rv) extract32(rv, 24, 5)
+#define FIU_UMA_CFG_DBSIZ(rv) extract32(rv, 21, 3)
+#define FIU_UMA_CFG_WDATSIZ(rv) extract32(rv, 16, 5)
+#define FIU_UMA_CFG_ADDSIZ(rv) extract32(rv, 11, 3)
+#define FIU_UMA_CFG_CMDSIZ(rv) extract32(rv, 10, 1)
+#define FIU_UMA_CFG_DBPCK(rv) extract32(rv, 6, 2)
+
+#define FIU_UMA_CTS_RDYIE BIT(25)
+#define FIU_UMA_CTS_RDYST BIT(24)
+#define FIU_UMA_CTS_SW_CS BIT(16)
+#define FIU_UMA_CTS_DEV_NUM(rv) extract32(rv, 8, 2)
+#define FIU_UMA_CTS_EXEC_DONE BIT(0)
+
+/* Direct flash memory read handler. */
+static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ NPCM7xxFIUFlash *f = opaque;
+ NPCM7xxFIUState *fiu = f->fiu;
+ int cs_id = f - fiu->flash;
+ uint64_t value = 0;
+ uint32_t drd_cfg;
+ int dummy_cycles;
+ int i;
+
+ drd_cfg = fiu->regs[NPCM7XX_FIU_DRD_CFG];
+
+ qemu_irq_lower(fiu->cs_lines[cs_id]);
+ ssi_transfer(fiu->spi, FIU_DRD_CFG_RDCMD(drd_cfg));
+
+ switch (FIU_DRD_CFG_ADDSIZ(drd_cfg)) {
+ case FIU_ADDSIZ_4BYTES:
+ ssi_transfer(fiu->spi, extract32(addr, 24, 8));
+ /* fall through */
+ case FIU_ADDSIZ_3BYTES:
+ ssi_transfer(fiu->spi, extract32(addr, 16, 8));
+ ssi_transfer(fiu->spi, extract32(addr, 8, 8));
+ ssi_transfer(fiu->spi, extract32(addr, 0, 8));
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
+ DEVICE(fiu)->canonical_path, FIU_DRD_CFG_ADDSIZ(drd_cfg));
+ break;
+ }
+
+ /* Flash chip model expects one transfer per dummy bit, not byte */
+ dummy_cycles =
+ (FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg);
+ for (i = 0; i < dummy_cycles; i++) {
+ ssi_transfer(fiu->spi, 0);
+ }
+
+ for (i = 0; i < size; i++) {
+ value |= ssi_transfer(fiu->spi, 0) << (8 * i);
+ }
+
+ qemu_irq_raise(fiu->cs_lines[cs_id]);
+
+ trace_npcm7xx_fiu_flash_read(DEVICE(fiu)->canonical_path, cs_id, addr, size,
+ value);
+
+ return value;
+}
+
+/* Direct flash memory write handler. */
+static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
+ unsigned int size)
+{
+ NPCM7xxFIUFlash *f = opaque;
+ NPCM7xxFIUState *fiu = f->fiu;
+ int cs_id = f - fiu->flash;
+ uint32_t dwr_cfg;
+ int i;
+
+ trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
+ size, v);
+
+ dwr_cfg = fiu->regs[NPCM7XX_FIU_DWR_CFG];
+
+ qemu_irq_lower(fiu->cs_lines[cs_id]);
+ ssi_transfer(fiu->spi, FIU_DWR_CFG_WRCMD(dwr_cfg));
+
+ switch (FIU_DWR_CFG_ADDSIZ(dwr_cfg)) {
+ case FIU_ADDSIZ_4BYTES:
+ ssi_transfer(fiu->spi, extract32(addr, 24, 8));
+ /* fall through */
+ case FIU_ADDSIZ_3BYTES:
+ ssi_transfer(fiu->spi, extract32(addr, 16, 8));
+ ssi_transfer(fiu->spi, extract32(addr, 8, 8));
+ ssi_transfer(fiu->spi, extract32(addr, 0, 8));
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
+ DEVICE(fiu)->canonical_path, FIU_DWR_CFG_ADDSIZ(dwr_cfg));
+ break;
+ }
+
+ for (i = 0; i < size; i++) {
+ ssi_transfer(fiu->spi, v & 0xff);
+ v >>= 8;
+ }
+
+ qemu_irq_raise(fiu->cs_lines[cs_id]);
+}
+
+static const MemoryRegionOps npcm7xx_fiu_flash_ops = {
+ .read = npcm7xx_fiu_flash_read,
+ .write = npcm7xx_fiu_flash_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ .unaligned = true,
+ },
+};
+
+/* Control register read handler. */
+static uint64_t npcm7xx_fiu_ctrl_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ hwaddr reg = addr / sizeof(uint32_t);
+ NPCM7xxFIUState *s = opaque;
+ uint32_t value;
+
+ if (reg < NPCM7XX_FIO_NR_REGS) {
+ value = s->regs[reg];
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: read from invalid offset 0x%" PRIx64 "\n",
+ DEVICE(s)->canonical_path, addr);
+ value = 0;
+ }
+
+ trace_npcm7xx_fiu_ctrl_read(DEVICE(s)->canonical_path, addr, value);
+
+ return value;
+}
+
+/* Send the specified number of address bytes from the UMA address register. */
+static void send_address(SSIBus *spi, unsigned int addsiz, uint32_t addr)
+{
+ /* All cases fall through */
+ switch (addsiz) {
+ case 4:
+ ssi_transfer(spi, extract32(addr, 24, 8));
+ case 3:
+ ssi_transfer(spi, extract32(addr, 16, 8));
+ case 2:
+ ssi_transfer(spi, extract32(addr, 8, 8));
+ case 1:
+ ssi_transfer(spi, extract32(addr, 0, 8));
+ case 0:
+ break;
+ }
+}
+
+/* Send the number of dummy bits specified in the UMA config register. */
+static void send_dummy_bits(SSIBus *spi, uint32_t uma_cfg, uint32_t uma_cmd)
+{
+ unsigned int bits_per_clock = 1U << FIU_UMA_CFG_DBPCK(uma_cfg);
+ unsigned int i;
+
+ for (i = 0; i < FIU_UMA_CFG_DBSIZ(uma_cfg); i++) {
+ /* Use bytes 0 and 1 first, then keep repeating byte 2 */
+ unsigned int field = (i < 2) ? ((i + 1) * 8) : 24;
+ unsigned int j;
+
+ for (j = 0; j < 8; j += bits_per_clock) {
+ ssi_transfer(spi, extract32(uma_cmd, field + j, bits_per_clock));
+ }
+ }
+}
+
+/* Assert the chip select specified in the UMA Control/Status Register. */
+static void npcm7xx_fiu_select(NPCM7xxFIUState *s)
+{
+ int cs_id;
+
+ cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]);
+ if (cs_id < s->cs_count) {
+ qemu_irq_lower(s->cs_lines[cs_id]);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: UMA to CS%d; this module has only %d chip selects",
+ DEVICE(s)->canonical_path, cs_id, s->cs_count);
+ cs_id = -1;
+ }
+
+ s->active_cs = cs_id;
+}
+
+/* Deassert the currently active chip select. */
+static void npcm7xx_fiu_deselect(NPCM7xxFIUState *s)
+{
+ if (s->active_cs < 0) {
+ return;
+ }
+
+ qemu_irq_raise(s->cs_lines[s->active_cs]);
+ s->active_cs = -1;
+}
+
+/* Perform a User-Mode Access transaction. */
+static void npcm7xx_fiu_uma_transaction(NPCM7xxFIUState *s)
+{
+ uint32_t uma_cts = s->regs[NPCM7XX_FIU_UMA_CTS];
+ uint32_t uma_cfg;
+ unsigned int i;
+
+ /* SW_CS means the CS is already forced low, so don't touch it. */
+ if (uma_cts & FIU_UMA_CTS_SW_CS) {
+ npcm7xx_fiu_select(s);
+ }
+
+ /* Send command, if present. */
+ uma_cfg = s->regs[NPCM7XX_FIU_UMA_CFG];
+ if (FIU_UMA_CFG_CMDSIZ(uma_cfg) > 0) {
+ ssi_transfer(s->spi, extract32(s->regs[NPCM7XX_FIU_UMA_CMD], 0, 8));
+ }
+
+ /* Send address, if present. */
+ send_address(s->spi, FIU_UMA_CFG_ADDSIZ(uma_cfg),
+ s->regs[NPCM7XX_FIU_UMA_ADDR]);
+
+ /* Write data, if present. */
+ for (i = 0; i < FIU_UMA_CFG_WDATSIZ(uma_cfg); i++) {
+ unsigned int reg =
+ (i < 16) ? (NPCM7XX_FIU_UMA_DW0 + i / 4) : NPCM7XX_FIU_UMA_DW3;
+ unsigned int field = (i % 4) * 8;
+
+ ssi_transfer(s->spi, extract32(s->regs[reg], field, 8));
+ }
+
+ /* Send aummy bits, if present. */
+ send_dummy_bits(s->spi, uma_cfg, s->regs[NPCM7XX_FIU_UMA_CMD]);
+
+ /* Read data, if present. */
+ for (i = 0; i < FIU_UMA_CFG_RDATSIZ(uma_cfg); i++) {
+ unsigned int reg = NPCM7XX_FIU_UMA_DR0 + i / 4;
+ unsigned int field = (i % 4) * 8;
+ uint8_t c;
+
+ c = ssi_transfer(s->spi, 0);
+ if (reg <= NPCM7XX_FIU_UMA_DR3) {
+ s->regs[reg] = deposit32(s->regs[reg], field, 8, c);
+ }
+ }
+
+ /* Again, don't touch CS if the user is forcing it low. */
+ if (uma_cts & FIU_UMA_CTS_SW_CS) {
+ npcm7xx_fiu_deselect(s);
+ }
+
+ /* RDYST means a command has completed since it was cleared. */
+ s->regs[NPCM7XX_FIU_UMA_CTS] |= FIU_UMA_CTS_RDYST;
+ /* EXEC_DONE means Execute Command / Not Done, so clear it here. */
+ s->regs[NPCM7XX_FIU_UMA_CTS] &= ~FIU_UMA_CTS_EXEC_DONE;
+}
+
+/* Control register write handler. */
+static void npcm7xx_fiu_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
+ unsigned int size)
+{
+ hwaddr reg = addr / sizeof(uint32_t);
+ NPCM7xxFIUState *s = opaque;
+ uint32_t value = v;
+
+ trace_npcm7xx_fiu_ctrl_write(DEVICE(s)->canonical_path, addr, value);
+
+ switch (reg) {
+ case NPCM7XX_FIU_UMA_CFG:
+ if (s->regs[reg] & FIU_UMA_CFG_CMMLCK) {
+ value &= ~FIU_UMA_CFG_CMMLCK_MASK;
+ value |= (s->regs[reg] & FIU_UMA_CFG_CMMLCK_MASK);
+ }
+ /* fall through */
+ case NPCM7XX_FIU_DRD_CFG:
+ case NPCM7XX_FIU_DWR_CFG:
+ if (s->regs[reg] & NPCM7XX_FIU_CFG_LCK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to locked register @ 0x%" PRIx64 "\n",
+ DEVICE(s)->canonical_path, addr);
+ return;
+ }
+ s->regs[reg] = value;
+ break;
+
+ case NPCM7XX_FIU_UMA_CTS:
+ if (value & FIU_UMA_CTS_RDYST) {
+ value &= ~FIU_UMA_CTS_RDYST;
+ } else {
+ value |= s->regs[reg] & FIU_UMA_CTS_RDYST;
+ }
+ if ((s->regs[reg] ^ value) & FIU_UMA_CTS_SW_CS) {
+ if (value & FIU_UMA_CTS_SW_CS) {
+ /*
+ * Don't drop CS if there's a transfer in progress, or we're
+ * about to start one.
+ */
+ if (!((value | s->regs[reg]) & FIU_UMA_CTS_EXEC_DONE)) {
+ npcm7xx_fiu_deselect(s);
+ }
+ } else {
+ npcm7xx_fiu_select(s);
+ }
+ }
+ s->regs[reg] = value | (s->regs[reg] & FIU_UMA_CTS_EXEC_DONE);
+ if (value & FIU_UMA_CTS_EXEC_DONE) {
+ npcm7xx_fiu_uma_transaction(s);
+ }
+ break;
+
+ case NPCM7XX_FIU_UMA_DR0 ... NPCM7XX_FIU_UMA_DR3:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to read-only register @ 0x%" PRIx64 "\n",
+ DEVICE(s)->canonical_path, addr);
+ return;
+
+ case NPCM7XX_FIU_PRT_CFG:
+ case NPCM7XX_FIU_PRT_CMD0 ... NPCM7XX_FIU_PRT_CMD9:
+ qemu_log_mask(LOG_UNIMP, "%s: PRT is not implemented\n", __func__);
+ break;
+
+ case NPCM7XX_FIU_UMA_CMD:
+ case NPCM7XX_FIU_UMA_ADDR:
+ case NPCM7XX_FIU_UMA_DW0 ... NPCM7XX_FIU_UMA_DW3:
+ case NPCM7XX_FIU_CFG:
+ s->regs[reg] = value;
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to invalid offset 0x%" PRIx64 "\n",
+ DEVICE(s)->canonical_path, addr);
+ return;
+ }
+}
+
+static const MemoryRegionOps npcm7xx_fiu_ctrl_ops = {
+ .read = npcm7xx_fiu_ctrl_read,
+ .write = npcm7xx_fiu_ctrl_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void npcm7xx_fiu_enter_reset(Object *obj, ResetType type)
+{
+ NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
+
+ trace_npcm7xx_fiu_enter_reset(DEVICE(obj)->canonical_path, type);
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ s->regs[NPCM7XX_FIU_DRD_CFG] = 0x0300100b;
+ s->regs[NPCM7XX_FIU_DWR_CFG] = 0x03000002;
+ s->regs[NPCM7XX_FIU_UMA_CFG] = 0x00000400;
+ s->regs[NPCM7XX_FIU_UMA_CTS] = 0x00010000;
+ s->regs[NPCM7XX_FIU_UMA_CMD] = 0x0000000b;
+ s->regs[NPCM7XX_FIU_PRT_CFG] = 0x00000400;
+ s->regs[NPCM7XX_FIU_CFG] = 0x0000000b;
+}
+
+static void npcm7xx_fiu_hold_reset(Object *obj)
+{
+ NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
+ int i;
+
+ trace_npcm7xx_fiu_hold_reset(DEVICE(obj)->canonical_path);
+
+ for (i = 0; i < s->cs_count; i++) {
+ qemu_irq_raise(s->cs_lines[i]);
+ }
+}
+
+static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
+{
+ NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
+ SysBusDevice *sbd = &s->parent;
+ int i;
+
+ if (s->cs_count <= 0) {
+ error_setg(errp, "%s: %d chip selects specified, need at least one",
+ dev->canonical_path, s->cs_count);
+ return;
+ }
+
+ s->spi = ssi_create_bus(dev, "spi");
+ s->cs_lines = g_new0(qemu_irq, s->cs_count);
+ s->flash = g_new0(NPCM7xxFIUFlash, s->cs_count);
+
+ /*
+ * Register the control registers region first. It may be followed by one
+ * or more direct flash access regions.
+ */
+ memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_fiu_ctrl_ops, s, "ctrl",
+ NPCM7XX_FIU_CTRL_REGS_SIZE);
+ sysbus_init_mmio(sbd, &s->mmio);
+
+ for (i = 0; i < s->cs_count; i++) {
+ NPCM7xxFIUFlash *flash = &s->flash[i];
+ sysbus_init_irq(sbd, &s->cs_lines[i]);
+ flash->fiu = s;
+ memory_region_init_io(&flash->direct_access, OBJECT(s),
+ &npcm7xx_fiu_flash_ops, &s->flash[i], "flash",
+ NPCM7XX_FIU_FLASH_WINDOW_SIZE);
+ sysbus_init_mmio(sbd, &flash->direct_access);
+ }
+}
+
+static Property npcm7xx_fiu_properties[] = {
+ DEFINE_PROP_INT32("cs-count", NPCM7xxFIUState, cs_count, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_fiu_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM7xx Flash Interface Unit";
+ dc->realize = npcm7xx_fiu_realize;
+ rc->phases.enter = npcm7xx_fiu_enter_reset;
+ rc->phases.hold = npcm7xx_fiu_hold_reset;
+ device_class_set_props(dc, npcm7xx_fiu_properties);
+}
+
+static const TypeInfo npcm7xx_fiu_types[] = {
+ {
+ .name = TYPE_NPCM7XX_FIU,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxFIUState),
+ .class_init = npcm7xx_fiu_class_init,
+ },
+};
+DEFINE_TYPES(npcm7xx_fiu_types);
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index 0ea498de91..8024253c1f 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -9,3 +9,12 @@ aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%08x size:0x%08x"
aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
+
+# npcm7xx_fiu.c
+
+npcm7xx_fiu_enter_reset(const char *id, int reset_type) "%s reset type: %d"
+npcm7xx_fiu_hold_reset(const char *id) "%s"
+npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08x"
+npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08x"
+npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
+npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 8f49f7015c..e357f4bf59 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -22,6 +22,7 @@
#include "hw/misc/npcm7xx_gcr.h"
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/timer/npcm7xx_timer.h"
+#include "hw/ssi/npcm7xx_fiu.h"
#include "target/arm/cpu.h"
#define NPCM7XX_MAX_NUM_CPUS (2)
@@ -67,6 +68,7 @@ typedef struct NPCM7xxState {
NPCM7xxOTPState key_storage;
NPCM7xxOTPState fuse_array;
NPCM7xxMCState mc;
+ NPCM7xxFIUState fiu[2];
} NPCM7xxState;
#define TYPE_NPCM7XX "npcm7xx"
diff --git a/include/hw/ssi/npcm7xx_fiu.h b/include/hw/ssi/npcm7xx_fiu.h
new file mode 100644
index 0000000000..88bfd4ba8e
--- /dev/null
+++ b/include/hw/ssi/npcm7xx_fiu.h
@@ -0,0 +1,99 @@
+/*
+ * Nuvoton NPCM7xx Flash Interface Unit (FIU)
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef NPCM7XX_FIU_H
+#define NPCM7XX_FIU_H
+
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+
+/**
+ * enum NPCM7xxFIURegister - 32-bit FIU register indices.
+ */
+enum NPCM7xxFIURegister {
+ NPCM7XX_FIU_DRD_CFG,
+ NPCM7XX_FIU_DWR_CFG,
+ NPCM7XX_FIU_UMA_CFG,
+ NPCM7XX_FIU_UMA_CTS,
+ NPCM7XX_FIU_UMA_CMD,
+ NPCM7XX_FIU_UMA_ADDR,
+ NPCM7XX_FIU_PRT_CFG,
+ NPCM7XX_FIU_UMA_DW0 = 0x0020 / sizeof(uint32_t),
+ NPCM7XX_FIU_UMA_DW1,
+ NPCM7XX_FIU_UMA_DW2,
+ NPCM7XX_FIU_UMA_DW3,
+ NPCM7XX_FIU_UMA_DR0,
+ NPCM7XX_FIU_UMA_DR1,
+ NPCM7XX_FIU_UMA_DR2,
+ NPCM7XX_FIU_UMA_DR3,
+ NPCM7XX_FIU_PRT_CMD0,
+ NPCM7XX_FIU_PRT_CMD1,
+ NPCM7XX_FIU_PRT_CMD2,
+ NPCM7XX_FIU_PRT_CMD3,
+ NPCM7XX_FIU_PRT_CMD4,
+ NPCM7XX_FIU_PRT_CMD5,
+ NPCM7XX_FIU_PRT_CMD6,
+ NPCM7XX_FIU_PRT_CMD7,
+ NPCM7XX_FIU_PRT_CMD8,
+ NPCM7XX_FIU_PRT_CMD9,
+ NPCM7XX_FIU_CFG = 0x78 / sizeof(uint32_t),
+ NPCM7XX_FIO_NR_REGS,
+};
+
+typedef struct NPCM7xxFIUState NPCM7xxFIUState;
+
+/**
+ * struct NPCM7xxFIUFlash - Per-chipselect flash controller state.
+ * @direct_access: Memory region for direct flash access.
+ * @fiu: Pointer to flash controller shared state.
+ */
+typedef struct NPCM7xxFIUFlash {
+ MemoryRegion direct_access;
+ NPCM7xxFIUState *fiu;
+} NPCM7xxFIUFlash;
+
+/**
+ * NPCM7xxFIUState - Device state for one Flash Interface Unit.
+ * @parent: System bus device.
+ * @mmio: Memory region for register access.
+ * @cs_count: Number of flash chips that may be connected to this module.
+ * @active_cs: Currently active chip select, or -1 if no chip is selected.
+ * @cs_lines: GPIO lines that may be wired to flash chips.
+ * @flash: Array of @cs_count per-flash-chip state objects.
+ * @spi: The SPI bus mastered by this controller.
+ * @regs: Register contents.
+ *
+ * Each FIU has a shared bank of registers, and controls up to four chip
+ * selects. Each chip select has a dedicated memory region which may be used to
+ * read and write the flash connected to that chip select as if it were memory.
+ */
+struct NPCM7xxFIUState {
+ SysBusDevice parent;
+
+ MemoryRegion mmio;
+
+ int32_t cs_count;
+ int32_t active_cs;
+ qemu_irq *cs_lines;
+ NPCM7xxFIUFlash *flash;
+
+ SSIBus *spi;
+
+ uint32_t regs[NPCM7XX_FIO_NR_REGS];
+};
+
+#define TYPE_NPCM7XX_FIU "npcm7xx-fiu"
+#define NPCM7XX_FIU(obj) OBJECT_CHECK(NPCM7xxFIUState, (obj), TYPE_NPCM7XX_FIU)
+
+#endif /* NPCM7XX_FIU_H */
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 11/12] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (9 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 10/12] hw/ssi: NPCM7xx Flash Interface Unit device model Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 12/12] docs/system: Add Nuvoton machine documentation Havard Skinnemoen
` (2 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
This allows these NPCM7xx-based boards to boot from a flash image, e.g.
one built with OpenBMC. For example like this:
IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc
qemu-system-arm -machine quanta-gsj -nographic \
-bios ~/qemu/bootrom/npcm7xx_bootrom.bin \
-drive file=${IMAGE},if=mtd,bus=0,unit=0,format=raw,snapshot=on
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
hw/arm/npcm7xx_boards.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index ca33262a59..12bf5a216f 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -19,6 +19,7 @@
#include "hw/arm/npcm7xx.h"
#include "hw/core/cpu.h"
#include "hw/loader.h"
+#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/units.h"
@@ -65,6 +66,21 @@ static void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
}
+static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
+ const char *flash_type, DriveInfo *dinfo) {
+ DeviceState *flash;
+ qemu_irq flash_cs;
+
+ flash = qdev_new(flash_type);
+ if (dinfo) {
+ qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
+ }
+ qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
+
+ flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
+ sysbus_connect_irq(SYS_BUS_DEVICE(fiu), cs_no, flash_cs);
+}
+
static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
uint32_t hw_straps)
{
@@ -88,6 +104,7 @@ static void npcm750_evb_init(MachineState *machine)
soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
npcm7xx_load_bootrom(soc);
+ npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
npcm7xx_load_kernel(machine, soc);
}
@@ -97,6 +114,8 @@ static void quanta_gsj_init(MachineState *machine)
soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
npcm7xx_load_bootrom(soc);
+ npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
+ drive_get(IF_MTD, 0, 0));
npcm7xx_load_kernel(machine, soc);
}
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 12/12] docs/system: Add Nuvoton machine documentation
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (10 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 11/12] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj Havard Skinnemoen
@ 2020-06-26 23:55 ` Havard Skinnemoen
2020-07-03 16:35 ` Philippe Mathieu-Daudé
2020-06-27 0:15 ` [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines no-reply
2020-07-03 12:27 ` Peter Maydell
13 siblings, 1 reply; 30+ messages in thread
From: Havard Skinnemoen @ 2020-06-26 23:55 UTC (permalink / raw)
To: peter.maydell, clg, joel
Cc: qemu-arm, qemu-devel, Avi.Fishman, kfting, Havard Skinnemoen
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
docs/system/arm/nuvoton.rst | 92 +++++++++++++++++++++++++++++++++++++
docs/system/target-arm.rst | 1 +
2 files changed, 93 insertions(+)
create mode 100644 docs/system/arm/nuvoton.rst
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
new file mode 100644
index 0000000000..7384662d58
--- /dev/null
+++ b/docs/system/arm/nuvoton.rst
@@ -0,0 +1,92 @@
+Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
+=====================================================
+
+The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
+designed to be used as Baseboard Management Controllers (BMCs) in various
+servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an
+assortment of peripherals targeted for either Enterprise or Data Center /
+Hyperscale applications. The former is a superset of the latter, so NPCM750 has
+all the peripherals of NPCM730 and more.
+
+.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
+
+The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise
+segment. The following machines are based on this chip :
+
+- ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
+
+The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and
+Hyperscale applications. The following machines are based on this chip :
+
+- ``quanta-gsj`` Quanta GSJ server BMC
+
+There are also two more SoCs, NPCM710 and NPCM705, which are single-core
+variants of NPCM750 and NPCM730, respectively. These are currently not
+supported by QEMU.
+
+Supported devices
+-----------------
+
+ * SMP (Dual Core Cortex-A9)
+ * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer
+ and Watchdog.
+ * SRAM, ROM and DRAM mappings
+ * System Global Control Registers (GCR)
+ * Clock and reset controller (CLK)
+ * Timer controller (TIM)
+ * Serial ports (16550-based)
+ * DDR4 memory controller (dummy interface indicating memory training is done)
+ * OTP controllers (no protection features)
+ * Flash Interface Unit (FIU; no protection features)
+
+Missing devices
+---------------
+
+ * GPIO controller
+ * LPC/eSPI host-to-BMC interface, including
+
+ * Keyboard and mouse controller interface (KBCI)
+ * Keyboard Controller Style (KCS) channels
+ * BIOS POST code FIFO
+ * System Wake-up Control (SWC)
+ * Shared memory (SHM)
+ * eSPI slave interface
+
+ * Ethernet controllers (GMAC and EMC)
+ * USB host (USBH)
+ * USB device (USBD)
+ * SMBus controller (SMBF)
+ * Peripheral SPI controller (PSPI)
+ * Analog to Digital Converter (ADC)
+ * SD/MMC host
+ * Random Number Generator (RNG)
+ * PECI interface
+ * Pulse Width Modulation (PWM)
+ * Tachometer
+ * PCI and PCIe root complex and bridges
+ * VDM and MCTP support
+ * Serial I/O expansion
+ * LPC/eSPI host
+ * Coprocessor
+ * Graphics
+ * Video capture
+ * Encoding compression engine
+ * Security features
+
+Boot options
+------------
+
+The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
+a kernel using the ``-kernel`` option. OpenBMC images for `quanta-gsj` and
+possibly others can be downloaded from the OpenPOWER jenkins :
+
+ https://openpower.xyz/
+
+Booting a full firmware image requires a Boot ROM specified via the ``-bios``
+option to QEMU. The firmware image should be attached as an MTD drive. Example :
+
+.. code-block:: bash
+
+ $ qemu-system-arm -machine quanta-gsj -nographic \
+ -bios npcm7xx_bootrom.bin \
+ -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index 1bd477a293..38a9daa9b9 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -84,6 +84,7 @@ undocumented; you can get a complete list by running
arm/aspeed
arm/musicpal
arm/nseries
+ arm/nuvoton
arm/orangepi
arm/palm
arm/xscale
--
2.27.0.212.ge8ba1cc988-goog
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (11 preceding siblings ...)
2020-06-26 23:55 ` [PATCH v3 12/12] docs/system: Add Nuvoton machine documentation Havard Skinnemoen
@ 2020-06-27 0:15 ` no-reply
2020-07-03 12:27 ` Peter Maydell
13 siblings, 0 replies; 30+ messages in thread
From: no-reply @ 2020-06-27 0:15 UTC (permalink / raw)
To: hskinnemoen
Cc: peter.maydell, qemu-devel, joel, kfting, qemu-arm, clg,
hskinnemoen, Avi.Fishman
Patchew URL: https://patchew.org/QEMU/20200626235519.591734-1-hskinnemoen@google.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#! /bin/bash
export ARCH=x86_64
make docker-image-fedora V=1 NETWORK=1
time make docker-test-mingw@fedora J=14 NETWORK=1
=== TEST SCRIPT END ===
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=a230e4bd116749a0878a758b497ee67e', '-u', '1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-vg6aufvv/src/docker-src.2020-06-26-20.09.42.21707:/var/tmp/qemu:z,ro', 'qemu:fedora', '/var/tmp/qemu/run', 'test-mingw']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=a230e4bd116749a0878a758b497ee67e
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-vg6aufvv/src'
make: *** [docker-run-test-mingw@fedora] Error 2
real 5m38.662s
user 0m9.129s
The full log is available at
http://patchew.org/logs/20200626235519.591734-1-hskinnemoen@google.com/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
` (12 preceding siblings ...)
2020-06-27 0:15 ` [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines no-reply
@ 2020-07-03 12:27 ` Peter Maydell
2020-07-03 13:35 ` Philippe Mathieu-Daudé
2020-07-03 20:41 ` Havard Skinnemoen
13 siblings, 2 replies; 30+ messages in thread
From: Peter Maydell @ 2020-07-03 12:27 UTC (permalink / raw)
To: Havard Skinnemoen
Cc: QEMU Developers, Joel Stanley, CS20 KFTing, qemu-arm,
Cédric Le Goater, IS20 Avi Fishman
On Sat, 27 Jun 2020 at 00:55, Havard Skinnemoen <hskinnemoen@google.com> wrote:
>
> Time for another refresh of this patchset. Sorry it took so long -- I've been
> trying to figure out why the Winbond flash model isn't working with
> npcm750-evb, and I'm fairly convinced the number of dummy cycles in DIO mode
> should be 4, not 1. Unfortunately, I don't see any other machines using Winbond
> flash in DIO mode, so it's hard to prove that it's correct. I'm planning to
> post a libqos-based test suite separately.
>
> I'm also planning to add the vbootrom to qemu as a submodule, similar to the
> other roms, but not in this pathset (let me know if you do want me to include
> this in the series).
Hi; it looks like codewise this patchset is ready to go in
and it's all been reviewed. I see however that all the
new files are GPL-v2-only. We usually prefer GPL-v2-or-later
for new code: is it possible to use that license instead ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models
2020-06-26 23:55 ` [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models Havard Skinnemoen
@ 2020-07-03 13:32 ` Philippe Mathieu-Daudé
2020-07-03 20:56 ` Havard Skinnemoen
0 siblings, 1 reply; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-03 13:32 UTC (permalink / raw)
To: Havard Skinnemoen, peter.maydell, clg, joel
Cc: kfting, qemu-arm, qemu-devel, Avi.Fishman
On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> The Nuvoton NPCM7xx SoC family are used to implement Baseboard
> Management Controllers in servers. While the family includes four SoCs,
> this patch implements limited support for two of them: NPCM730 (targeted
> for Data Center applications) and NPCM750 (targeted for Enterprise
> applications).
>
> This patch includes little more than the bare minimum needed to boot a
> Linux kernel built with NPCM7xx support in direct-kernel mode:
>
> - Two Cortex-A9 CPU cores with built-in periperhals.
> - Global Configuration Registers.
> - Clock Management.
> - 3 Timer Modules with 5 timers each.
> - 4 serial ports.
>
> The chips themselves have a lot more features, some of which will be
> added to the model at a later stage.
>
> Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
> ---
> hw/arm/Makefile.objs | 1 +
> hw/arm/npcm7xx.c | 330 +++++++++++++++++++++++++++++++++++++++
> include/hw/arm/npcm7xx.h | 80 ++++++++++
> 3 files changed, 411 insertions(+)
> create mode 100644 hw/arm/npcm7xx.c
> create mode 100644 include/hw/arm/npcm7xx.h
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 534a6a119e..13d163a599 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -41,6 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
> obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
> obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
> obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
> +obj-$(CONFIG_NPCM7XX) += npcm7xx.o
> obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
> obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o
> diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
> new file mode 100644
> index 0000000000..f395fe84b6
> --- /dev/null
> +++ b/hw/arm/npcm7xx.c
> @@ -0,0 +1,330 @@
> +/*
> + * Nuvoton NPCM7xx SoC family.
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "exec/address-spaces.h"
> +#include "hw/arm/npcm7xx.h"
> +#include "hw/char/serial.h"
> +#include "hw/loader.h"
> +#include "hw/misc/unimp.h"
> +#include "hw/qdev-properties.h"
> +#include "qapi/error.h"
> +#include "qemu/units.h"
> +#include "sysemu/sysemu.h"
> +
> +/* The first half of the address space is reserved for DDR4 DRAM. */
> +#define NPCM7XX_DRAM_BA (0x00000000)
> +#define NPCM7XX_DRAM_SZ (2 * GiB)
> +
> +/*
> + * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
> + * that aren't handled by any device.
> + */
> +#define NPCM7XX_MMIO_BA (0x80000000)
> +#define NPCM7XX_MMIO_SZ (0x7FFD0000)
Could be 0x80000000 since UNIMP_DEVICE is created with low
priority.
> +
> +/* Core system modules. */
> +#define NPCM7XX_L2C_BA (0xF03FC000)
> +#define NPCM7XX_CPUP_BA (0xF03FE000)
> +#define NPCM7XX_GCR_BA (0xF0800000)
> +#define NPCM7XX_CLK_BA (0xF0801000)
> +
> +/* Memory blocks at the end of the address space */
> +#define NPCM7XX_RAM2_BA (0xFFFD0000)
> +#define NPCM7XX_RAM2_SZ (128 * KiB)
> +#define NPCM7XX_ROM_BA (0xFFFF0000)
> +#define NPCM7XX_ROM_SZ (64 * KiB)
> +
> +/*
> + * Interrupt lines going into the GIC. This does not include internal Cortex-A9
> + * interrupts.
> + */
> +enum NPCM7xxInterrupt {
> + NPCM7XX_UART0_IRQ = 2,
> + NPCM7XX_UART1_IRQ,
> + NPCM7XX_UART2_IRQ,
> + NPCM7XX_UART3_IRQ,
> + NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
> + NPCM7XX_TIMER1_IRQ,
> + NPCM7XX_TIMER2_IRQ,
> + NPCM7XX_TIMER3_IRQ,
> + NPCM7XX_TIMER4_IRQ,
> + NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
> + NPCM7XX_TIMER6_IRQ,
> + NPCM7XX_TIMER7_IRQ,
> + NPCM7XX_TIMER8_IRQ,
> + NPCM7XX_TIMER9_IRQ,
> + NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
> + NPCM7XX_TIMER11_IRQ,
> + NPCM7XX_TIMER12_IRQ,
> + NPCM7XX_TIMER13_IRQ,
> + NPCM7XX_TIMER14_IRQ,
> +};
> +
> +/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
> +#define NPCM7XX_NUM_IRQ (160)
> +
> +/* Register base address for each Timer Module */
> +static const hwaddr npcm7xx_tim_addr[] = {
> + 0xF0008000,
> + 0xF0009000,
> + 0xF000A000,
> +};
> +
> +/* Register base address for each 16550 UART */
> +static const hwaddr npcm7xx_uart_addr[] = {
> + 0xF0001000,
> + 0xF0002000,
> + 0xF0003000,
> + 0xF0004000,
> +};
> +
> +void npcm7xx_write_secondary_boot(ARMCPU *cpu, const struct arm_boot_info *info)
> +{
> + /*
> + * The default smpboot stub halts the secondary CPU with a 'wfi'
> + * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
> + * does not send an IPI to wake it up, so the second CPU fails to boot. So
> + * we need to provide our own smpboot stub that can not use 'wfi', it has
> + * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
> + */
> + uint32_t smpboot[] = {
> + 0xe59f2018, /* ldr r2, bootreg_addr */
> + 0xe3a00000, /* mov r0, #0 */
> + 0xe5820000, /* str r0, [r2] */
> + 0xe320f002, /* wfe */
> + 0xe5921000, /* ldr r1, [r2] */
> + 0xe1110001, /* tst r1, r1 */
> + 0x0afffffb, /* beq <wfe> */
> + 0xe12fff11, /* bx r1 */
> + NPCM7XX_SMP_BOOTREG_ADDR,
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
> + smpboot[i] = tswap32(smpboot[i]);
> + }
> +
> + rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
> + NPCM7XX_SMP_LOADER_START);
> +}
> +
> +static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
> +{
> + return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
> +}
> +
> +static void npcm7xx_init(Object *obj)
> +{
> + NPCM7xxState *s = NPCM7XX(obj);
> + int i;
> +
> + for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
> + object_initialize_child(obj, "cpu[*]", &s->cpu[i],
> + ARM_CPU_TYPE_NAME("cortex-a9"));
> + }
> +
> + object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
> + object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
> + object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
> + "power-on-straps");
> + object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
> +
> + for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
> + object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
> + }
> +}
> +
> +static void npcm7xx_realize(DeviceState *dev, Error **errp)
> +{
> + NPCM7xxState *s = NPCM7XX(dev);
> + NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
> + Error *err = NULL;
> + int i;
> +
> + /* I/O space -- unimplemented unless overridden below. */
> + create_unimplemented_device("npcm7xx.io", NPCM7XX_MMIO_BA, NPCM7XX_MMIO_SZ);
Note by doing that you won't get transaction failures when accessing
unassigned regions. This not incorrect, but a bit overkill (this covers
almost 2GiB...).
> +
> + /* CPUs */
> + for (i = 0; i < nc->num_cpus; i++) {
> + object_property_set_int(OBJECT(&s->cpu[i]),
> + arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
> + "mp-affinity", &error_abort);
> + object_property_set_int(OBJECT(&s->cpu[i]), NPCM7XX_GIC_CPU_IF_ADDR,
> + "reset-cbar", &error_abort);
> + object_property_set_bool(OBJECT(&s->cpu[i]), true,
> + "reset-hivecs", &error_abort);
> +
> + /* Disable security extensions. */
> + if (object_property_find(OBJECT(&s->cpu[i]), "has_el3", NULL)) {
> + object_property_set_bool(OBJECT(&s->cpu[i]), false, "has_el3",
> + &error_abort);
> + }
> +
> + qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + }
> +
> + /* A9MPCORE peripherals */
> + object_property_set_int(OBJECT(&s->a9mpcore), nc->num_cpus, "num-cpu",
> + &error_abort);
> + object_property_set_int(OBJECT(&s->a9mpcore), NPCM7XX_NUM_IRQ, "num-irq",
> + &error_abort);
> + sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err);
> + if (err) {
> + error_propagate(errp, err);
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
> +
> + for (i = 0; i < nc->num_cpus; i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
> + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
> + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
> + }
> +
> + /* L2 cache controller */
> + sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
> +
> + /* System Global Control Registers (GCR) */
> + object_property_set_int(OBJECT(&s->gcr), nc->disabled_modules,
> + "disabled-modules", &err);
> + object_property_set_link(OBJECT(&s->gcr), OBJECT(s->dram), "dram", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_realize(SYS_BUS_DEVICE(&s->gcr), &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
> +
> + /* Clock Control Registers (CLK) */
> + sysbus_realize(SYS_BUS_DEVICE(&s->clk), &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
> +
> + /* Timer Modules (TIM) */
> + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
> + for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
> + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
> + int first_irq;
> + int j;
> +
> + sysbus_realize(sbd, &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
> +
> + first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
> + for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
> + qemu_irq irq = npcm7xx_irq(s, first_irq + j);
> + sysbus_connect_irq(sbd, j, irq);
> + }
> + }
> +
> + /* UART0..3 (16550 compatible) */
> + for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
> + serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
> + npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
> + serial_hd(i), DEVICE_LITTLE_ENDIAN);
> + }
> +
> + /* RAM2 (SRAM) */
> + memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
> + NPCM7XX_RAM2_SZ, &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
> +
> + /* Internal ROM */
> + memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
> +
> + /* External DDR4 SDRAM */
> + memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, s->dram);
> +}
> +
> +static Property npcm7xx_properties[] = {
> + DEFINE_PROP_LINK("dram", NPCM7xxState, dram, TYPE_MEMORY_REGION,
> + MemoryRegion *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void npcm7xx_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = npcm7xx_realize;
> + dc->user_creatable = false;
> + device_class_set_props(dc, npcm7xx_properties);
> +}
> +
> +static void npcm730_class_init(ObjectClass *oc, void *data)
> +{
> + NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
> +
> + /* NPCM730 is optimized for data center use, so no graphics, etc. */
> + nc->disabled_modules = 0x00300395;
> + nc->num_cpus = 2;
> +}
> +
> +static void npcm750_class_init(ObjectClass *oc, void *data)
> +{
> + NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
> +
> + /* NPCM750 has 2 cores and a full set of peripherals */
> + nc->disabled_modules = 0x00000000;
> + nc->num_cpus = 2;
> +}
> +
> +static const TypeInfo npcm7xx_soc_types[] = {
> + {
> + .name = TYPE_NPCM7XX,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(NPCM7xxState),
> + .instance_init = npcm7xx_init,
> + .class_size = sizeof(NPCM7xxClass),
> + .class_init = npcm7xx_class_init,
> + .abstract = true,
> + }, {
> + .name = TYPE_NPCM730,
> + .parent = TYPE_NPCM7XX,
> + .class_init = npcm730_class_init,
> + }, {
> + .name = TYPE_NPCM750,
> + .parent = TYPE_NPCM7XX,
> + .class_init = npcm750_class_init,
> + },
> +};
> +
> +DEFINE_TYPES(npcm7xx_soc_types);
> diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
> new file mode 100644
> index 0000000000..38b8c33729
> --- /dev/null
> +++ b/include/hw/arm/npcm7xx.h
> @@ -0,0 +1,80 @@
> +/*
> + * Nuvoton NPCM7xx SoC family.
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#ifndef NPCM7XX_H
> +#define NPCM7XX_H
> +
> +#include "hw/boards.h"
> +#include "hw/cpu/a9mpcore.h"
> +#include "hw/misc/npcm7xx_clk.h"
> +#include "hw/misc/npcm7xx_gcr.h"
> +#include "hw/timer/npcm7xx_timer.h"
> +#include "target/arm/cpu.h"
> +
> +#define NPCM7XX_MAX_NUM_CPUS (2)
> +
> +/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
> +#define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */
> +#define NPCM7XX_SMP_LOADER_START (0xFFFF0000) /* Boot ROM */
> +#define NPCM7XX_SMP_BOOTREG_ADDR (0xF080013C) /* GCR.SCRPAD */
> +#define NPCM7XX_GIC_CPU_IF_ADDR (0xF03FE100) /* GIC within A9 */
> +
> +typedef struct NPCM7xxState {
> + DeviceState parent;
> +
> + ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS];
> + A9MPPrivState a9mpcore;
> +
> + MemoryRegion sram;
> + MemoryRegion irom;
> + MemoryRegion *dram;
> +
> + NPCM7xxGCRState gcr;
> + NPCM7xxCLKState clk;
> + NPCM7xxTimerCtrlState tim[3];
> +} NPCM7xxState;
> +
> +#define TYPE_NPCM7XX "npcm7xx"
> +#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
> +
> +#define TYPE_NPCM730 "npcm730"
> +#define TYPE_NPCM750 "npcm750"
> +
> +typedef struct NPCM7xxClass {
> + DeviceClass parent;
> +
> + /* Bitmask of modules that are permanently disabled on this chip. */
> + uint32_t disabled_modules;
> + /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
> + uint32_t num_cpus;
> +} NPCM7xxClass;
> +
> +#define NPCM7XX_CLASS(klass) \
> + OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
> +#define NPCM7XX_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
> +
> +/**
> + * npcm7xx_write_secondary_boot - Write stub for booting secondary CPU.
> + * @cpu: The CPU to be booted.
> + * @info: Boot info structure for the board.
> + *
> + * This will write a short code stub to the internal ROM that will keep the
> + * secondary CPU spinning until the primary CPU writes an address to the SCRPAD
> + * register in the GCR, after which the secondary CPU will jump there.
> + */
> +extern void npcm7xx_write_secondary_boot(ARMCPU *cpu,
> + const struct arm_boot_info *info);
> +
> +#endif /* NPCM7XX_H */
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines
2020-07-03 12:27 ` Peter Maydell
@ 2020-07-03 13:35 ` Philippe Mathieu-Daudé
2020-07-03 21:15 ` Havard Skinnemoen
2020-07-03 20:41 ` Havard Skinnemoen
1 sibling, 1 reply; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-03 13:35 UTC (permalink / raw)
To: Peter Maydell, Havard Skinnemoen, Markus Armbruster
Cc: QEMU Developers, Joel Stanley, CS20 KFTing, qemu-arm,
Cédric Le Goater, IS20 Avi Fishman
On 7/3/20 2:27 PM, Peter Maydell wrote:
> On Sat, 27 Jun 2020 at 00:55, Havard Skinnemoen <hskinnemoen@google.com> wrote:
>>
>> Time for another refresh of this patchset. Sorry it took so long -- I've been
>> trying to figure out why the Winbond flash model isn't working with
>> npcm750-evb, and I'm fairly convinced the number of dummy cycles in DIO mode
>> should be 4, not 1. Unfortunately, I don't see any other machines using Winbond
>> flash in DIO mode, so it's hard to prove that it's correct. I'm planning to
>> post a libqos-based test suite separately.
>>
>> I'm also planning to add the vbootrom to qemu as a submodule, similar to the
>> other roms, but not in this pathset (let me know if you do want me to include
>> this in the series).
>
> Hi; it looks like codewise this patchset is ready to go in
> and it's all been reviewed. I see however that all the
> new files are GPL-v2-only. We usually prefer GPL-v2-or-later
> for new code: is it possible to use that license instead ?
This series has been posted before Markus qdev & error cleanups.
Maybe some newer error patterns should be used now instead?
Phil.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model
2020-06-26 23:55 ` [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model Havard Skinnemoen
@ 2020-07-03 13:46 ` Philippe Mathieu-Daudé
2020-07-03 21:07 ` Havard Skinnemoen
0 siblings, 1 reply; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-03 13:46 UTC (permalink / raw)
To: Havard Skinnemoen, peter.maydell, clg, joel
Cc: kfting, qemu-arm, qemu-devel, Avi.Fishman
On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> This supports reading and writing OTP fuses and keys. Only fuse reading
> has been tested. Protection is not implemented.
>
> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
> ---
> hw/arm/npcm7xx.c | 32 +++
> hw/nvram/Makefile.objs | 1 +
> hw/nvram/npcm7xx_otp.c | 391 +++++++++++++++++++++++++++++++++
> include/hw/arm/npcm7xx.h | 3 +
> include/hw/nvram/npcm7xx_otp.h | 93 ++++++++
> 5 files changed, 520 insertions(+)
> create mode 100644 hw/nvram/npcm7xx_otp.c
> create mode 100644 include/hw/nvram/npcm7xx_otp.h
>
> diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
> index f395fe84b6..825910a4bf 100644
> --- a/hw/arm/npcm7xx.c
> +++ b/hw/arm/npcm7xx.c
> @@ -36,6 +36,10 @@
> #define NPCM7XX_MMIO_BA (0x80000000)
> #define NPCM7XX_MMIO_SZ (0x7FFD0000)
>
> +/* OTP key storage and fuse strap array */
> +#define NPCM7XX_OTP1_BA (0xF0189000)
> +#define NPCM7XX_OTP2_BA (0xF018A000)
> +
> /* Core system modules. */
> #define NPCM7XX_L2C_BA (0xF03FC000)
> #define NPCM7XX_CPUP_BA (0xF03FE000)
> @@ -122,6 +126,15 @@ void npcm7xx_write_secondary_boot(ARMCPU *cpu, const struct arm_boot_info *info)
> NPCM7XX_SMP_LOADER_START);
> }
>
> +static void npcm7xx_init_fuses(NPCM7xxState *s)
> +{
> + NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
> + uint32_t value;
> +
> + value = tswap32(nc->disabled_modules);
> + npcm7xx_otp_array_write(&s->fuse_array, &value, 64, sizeof(value));
> +}
> +
> static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
> {
> return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
> @@ -142,6 +155,10 @@ static void npcm7xx_init(Object *obj)
> object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
> "power-on-straps");
> object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
> + object_initialize_child(obj, "otp1", &s->key_storage,
> + TYPE_NPCM7XX_KEY_STORAGE);
> + object_initialize_child(obj, "otp2", &s->fuse_array,
> + TYPE_NPCM7XX_FUSE_ARRAY);
>
> for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
> object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
> @@ -225,6 +242,21 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
> }
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
>
> + /* OTP key storage and fuse strap array */
> + sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
> + sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
> + npcm7xx_init_fuses(s);
> +
> /* Timer Modules (TIM) */
> QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
> for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
> diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs
> index f3ad921382..0270f0bbf7 100644
> --- a/hw/nvram/Makefile.objs
> +++ b/hw/nvram/Makefile.objs
> @@ -4,5 +4,6 @@ common-obj-$(CONFIG_AT24C) += eeprom_at24c.o
> common-obj-y += fw_cfg.o
> common-obj-$(CONFIG_CHRP_NVRAM) += chrp_nvram.o
> common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o
> +common-obj-$(CONFIG_NPCM7XX) += npcm7xx_otp.o
> common-obj-$(CONFIG_NRF51_SOC) += nrf51_nvm.o
> obj-$(CONFIG_PSERIES) += spapr_nvram.o
> diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
> new file mode 100644
> index 0000000000..71fc728a2d
> --- /dev/null
> +++ b/hw/nvram/npcm7xx_otp.c
> @@ -0,0 +1,391 @@
> +/*
> + * Nuvoton NPCM7xx OTP (Fuse Array) Interface
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "hw/nvram/npcm7xx_otp.h"
> +#include "qapi/error.h"
> +#include "qemu/bitops.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "qemu/units.h"
> +
> +/* Each module has 4 KiB of register space. Only a fraction of it is used. */
> +#define NPCM7XX_OTP_REGS_SIZE (4 * KiB)
> +
> +/* Register field definitions. */
> +#define FST_RIEN BIT(2)
> +#define FST_RDST BIT(1)
> +#define FST_RDY BIT(0)
> +#define FST_RO_MASK (FST_RDST | FST_RDY)
> +
> +#define FADDR_BYTEADDR(rv) extract32((rv), 0, 10)
> +#define FADDR_BITPOS(rv) extract32((rv), 10, 3)
> +
> +#define FDATA_CLEAR 0x00000001
> +
> +#define FCFG_FDIS BIT(31)
> +#define FCFG_FCFGLK_MASK 0x00ff0000
> +
> +#define FCTL_PROG_CMD1 0x00000001
> +#define FCTL_PROG_CMD2 0xbf79e5d0
> +#define FCTL_READ_CMD 0x00000002
> +
> +static uint8_t ecc_encode_nibble(uint8_t n)
> +{
> + uint8_t result = n;
> +
> + result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4;
> + result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5;
> + result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6;
> + result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7;
> +
> + return result;
> +}
> +
> +void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
> + unsigned int offset, unsigned int len)
> +{
> + const uint8_t *src = data;
> + uint8_t *dst = s->array + offset;
> +
> + while (len-- > 0) {
> + uint8_t c = *src++;
> +
> + *dst++ = ecc_encode_nibble(extract8(c, 0, 4));
> + *dst++ = ecc_encode_nibble(extract8(c, 4, 4));
> + }
> +}
> +
> +/* Common register read handler for both OTP classes. */
> +static uint64_t npcm7xx_otp_read(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg)
> +{
> + uint32_t value = 0;
> +
> + switch (reg) {
> + case NPCM7XX_OTP_FST:
> + case NPCM7XX_OTP_FADDR:
> + case NPCM7XX_OTP_FDATA:
> + case NPCM7XX_OTP_FCFG:
> + value = s->regs[reg];
> + break;
> +
> + case NPCM7XX_OTP_FCTL:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: read from write-only FCTL register\n",
> + DEVICE(s)->canonical_path);
> + break;
> +
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: read from invalid offset 0x%zx\n",
> + DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
> + break;
> + }
> +
> + return value;
> +}
> +
> +/* Read a byte from the OTP array into the data register. */
> +static void npcm7xx_otp_read_array(NPCM7xxOTPState *s)
> +{
> + uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
> +
> + s->regs[NPCM7XX_OTP_FDATA] = s->array[FADDR_BYTEADDR(faddr)];
> + s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
> +}
> +
> +/* Program a byte from the data register into the OTP array. */
> +static void npcm7xx_otp_program_array(NPCM7xxOTPState *s)
> +{
> + uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
> +
> + /* Bits can only go 0->1, never 1->0. */
> + s->array[FADDR_BYTEADDR(faddr)] |= (1U << FADDR_BITPOS(faddr));
> + s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
> +}
> +
> +/* Compute the next value of the FCFG register. */
> +static uint32_t npcm7xx_otp_compute_fcfg(uint32_t cur_value, uint32_t new_value)
> +{
> + uint32_t lock_mask;
> + uint32_t value;
> +
> + /*
> + * FCFGLK holds sticky bits 16..23, indicating which bits in FPRGLK (8..15)
> + * and FRDLK (0..7) that are read-only.
> + */
> + lock_mask = (cur_value & FCFG_FCFGLK_MASK) >> 8;
> + lock_mask |= lock_mask >> 8;
> + /* FDIS and FCFGLK bits are sticky (write 1 to set; can't clear). */
> + value = cur_value & (FCFG_FDIS | FCFG_FCFGLK_MASK);
> + /* Preserve read-only bits in FPRGLK and FRDLK */
> + value |= cur_value & lock_mask;
> + /* Set all bits that aren't read-only. */
> + value |= new_value & ~lock_mask;
> +
> + return value;
> +}
> +
> +/* Common register write handler for both OTP classes. */
> +static void npcm7xx_otp_write(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg,
> + uint32_t value)
> +{
> + switch (reg) {
> + case NPCM7XX_OTP_FST:
> + /* RDST is cleared by writing 1 to it. */
> + if (value & FST_RDST) {
> + s->regs[NPCM7XX_OTP_FST] &= ~FST_RDST;
> + }
> + /* Preserve read-only and write-one-to-clear bits */
> + value =
> + (value & ~FST_RO_MASK) | (s->regs[NPCM7XX_OTP_FST] & FST_RO_MASK);
> + break;
> +
> + case NPCM7XX_OTP_FADDR:
> + break;
> +
> + case NPCM7XX_OTP_FDATA:
> + /*
> + * This register is cleared by writing a magic value to it; no other
> + * values can be written.
> + */
> + if (value == FDATA_CLEAR) {
> + value = 0;
> + } else {
> + value = s->regs[NPCM7XX_OTP_FDATA];
> + }
> + break;
> +
> + case NPCM7XX_OTP_FCFG:
> + value = npcm7xx_otp_compute_fcfg(s->regs[NPCM7XX_OTP_FCFG], value);
> + break;
> +
> + case NPCM7XX_OTP_FCTL:
> + switch (value) {
> + case FCTL_READ_CMD:
> + npcm7xx_otp_read_array(s);
> + break;
> +
> + case FCTL_PROG_CMD1:
> + /*
> + * Programming requires writing two separate magic values to this
> + * register; this is the first one. Just store it so it can be
> + * verified later when the second magic value is received.
> + */
> + break;
> +
> + case FCTL_PROG_CMD2:
> + /*
> + * Only initiate programming if we received the first half of the
> + * command immediately before this one.
> + */
> + if (s->regs[NPCM7XX_OTP_FCTL] == FCTL_PROG_CMD1) {
> + npcm7xx_otp_program_array(s);
> + }
> + break;
> +
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: unrecognized FCNTL value 0x%" PRIx32 "\n",
> + DEVICE(s)->canonical_path, value);
> + break;
> + }
> + if (value != FCTL_PROG_CMD1) {
> + value = 0;
> + }
> + break;
> +
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: write to invalid offset 0x%zx\n",
> + DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
> + return;
> + }
> +
> + s->regs[reg] = value;
> +}
> +
> +/* Register read handler specific to the fuse array OTP module. */
> +static uint64_t npcm7xx_fuse_array_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
> + NPCM7xxOTPState *s = opaque;
> + uint32_t value;
> +
> + /*
> + * Only the Fuse Strap register needs special handling; all other registers
> + * work the same way for both kinds of OTP modules.
> + */
> + if (reg != NPCM7XX_OTP_FUSTRAP) {
> + value = npcm7xx_otp_read(s, reg);
> + } else {
> + /* FUSTRAP is stored as three copies in the OTP array. */
> + uint32_t fustrap[3];
> +
> + memcpy(fustrap, &s->array[0], sizeof(fustrap));
> +
> + /* Determine value by a majority vote on each bit. */
> + value = (fustrap[0] & fustrap[1]) | (fustrap[0] & fustrap[2]) |
> + (fustrap[1] & fustrap[2]);
> + }
> +
> + return value;
> +}
> +
> +/* Register write handler specific to the fuse array OTP module. */
> +static void npcm7xx_fuse_array_write(void *opaque, hwaddr addr, uint64_t v,
> + unsigned int size)
> +{
> + NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
> + NPCM7xxOTPState *s = opaque;
> +
> + /*
> + * The Fuse Strap register is read-only. Other registers are handled by
> + * common code.
> + */
> + if (reg != NPCM7XX_OTP_FUSTRAP) {
> + npcm7xx_otp_write(s, reg, v);
> + }
> +}
> +
> +static const MemoryRegionOps npcm7xx_fuse_array_ops = {
> + .read = npcm7xx_fuse_array_read,
> + .write = npcm7xx_fuse_array_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + .unaligned = false,
> + },
> +};
> +
> +/* Register read handler specific to the key storage OTP module. */
> +static uint64_t npcm7xx_key_storage_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
> + NPCM7xxOTPState *s = opaque;
> +
> + /*
> + * Only the Fuse Key Index register needs special handling; all other
> + * registers work the same way for both kinds of OTP modules.
> + */
> + if (reg != NPCM7XX_OTP_FKEYIND) {
> + return npcm7xx_otp_read(s, reg);
> + }
> +
> + qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
> +
> + return s->regs[NPCM7XX_OTP_FKEYIND];
> +}
> +
> +/* Register write handler specific to the key storage OTP module. */
> +static void npcm7xx_key_storage_write(void *opaque, hwaddr addr, uint64_t v,
> + unsigned int size)
> +{
> + NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
> + NPCM7xxOTPState *s = opaque;
> +
> + /*
> + * Only the Fuse Key Index register needs special handling; all other
> + * registers work the same way for both kinds of OTP modules.
> + */
> + if (reg != NPCM7XX_OTP_FKEYIND) {
> + npcm7xx_otp_write(s, reg, v);
> + return;
> + }
> +
> + qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
> +
> + s->regs[NPCM7XX_OTP_FKEYIND] = v;
> +}
> +
> +static const MemoryRegionOps npcm7xx_key_storage_ops = {
> + .read = npcm7xx_key_storage_read,
> + .write = npcm7xx_key_storage_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + .unaligned = false,
> + },
> +};
> +
> +static void npcm7xx_otp_enter_reset(Object *obj, ResetType type)
> +{
> + NPCM7xxOTPState *s = NPCM7XX_OTP(obj);
> +
> + memset(s->regs, 0, sizeof(s->regs));
> +
> + s->regs[NPCM7XX_OTP_FST] = 0x00000001;
> + s->regs[NPCM7XX_OTP_FCFG] = 0x20000000;
> +}
> +
> +static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
> +{
> + NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
> + NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
> + SysBusDevice *sbd = &s->parent;
> +
> + s->array = g_malloc0(NPCM7XX_OTP_ARRAY_BYTES);
The possibility to reuse persistent OTP seems important.
This can be added later of course.
See simple example in hw/nvram/eeprom_at24c.c which use
a BlockBackend so the OTP content is not lost after reset
or migration.
> +
> + memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
> + NPCM7XX_OTP_REGS_SIZE);
> + sysbus_init_mmio(sbd, &s->mmio);
> +}
> +
> +static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
> +{
> + ResettableClass *rc = RESETTABLE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
Missing migration vmstate for NPCM7xxOTPState::regs[].
> + dc->realize = npcm7xx_otp_realize;
> + rc->phases.enter = npcm7xx_otp_enter_reset;
> +}
> +
> +static void npcm7xx_key_storage_class_init(ObjectClass *klass, void *data)
> +{
> + NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
> +
> + oc->mmio_ops = &npcm7xx_key_storage_ops;
> +}
> +
> +static void npcm7xx_fuse_array_class_init(ObjectClass *klass, void *data)
> +{
> + NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
> +
> + oc->mmio_ops = &npcm7xx_fuse_array_ops;
> +}
> +
> +static const TypeInfo npcm7xx_otp_types[] = {
> + {
> + .name = TYPE_NPCM7XX_OTP,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(NPCM7xxOTPState),
> + .class_init = npcm7xx_otp_class_init,
> + .abstract = true,
> + },
> + {
> + .name = TYPE_NPCM7XX_KEY_STORAGE,
> + .parent = TYPE_NPCM7XX_OTP,
> + .class_init = npcm7xx_key_storage_class_init,
> + },
> + {
> + .name = TYPE_NPCM7XX_FUSE_ARRAY,
> + .parent = TYPE_NPCM7XX_OTP,
> + .class_init = npcm7xx_fuse_array_class_init,
> + },
> +};
> +DEFINE_TYPES(npcm7xx_otp_types);
> diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
> index a241af0b8c..360cd965a7 100644
> --- a/include/hw/arm/npcm7xx.h
> +++ b/include/hw/arm/npcm7xx.h
> @@ -19,6 +19,7 @@
> #include "hw/cpu/a9mpcore.h"
> #include "hw/misc/npcm7xx_clk.h"
> #include "hw/misc/npcm7xx_gcr.h"
> +#include "hw/nvram/npcm7xx_otp.h"
> #include "hw/timer/npcm7xx_timer.h"
> #include "target/arm/cpu.h"
>
> @@ -62,6 +63,8 @@ typedef struct NPCM7xxState {
> NPCM7xxGCRState gcr;
> NPCM7xxCLKState clk;
> NPCM7xxTimerCtrlState tim[3];
> + NPCM7xxOTPState key_storage;
> + NPCM7xxOTPState fuse_array;
> } NPCM7xxState;
>
> #define TYPE_NPCM7XX "npcm7xx"
> diff --git a/include/hw/nvram/npcm7xx_otp.h b/include/hw/nvram/npcm7xx_otp.h
> new file mode 100644
> index 0000000000..1127c48fef
> --- /dev/null
> +++ b/include/hw/nvram/npcm7xx_otp.h
> @@ -0,0 +1,93 @@
> +/*
> + * Nuvoton NPCM7xx OTP (Fuse Array) Interface
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#ifndef NPCM7XX_OTP_H
> +#define NPCM7XX_OTP_H
> +
> +#include "exec/memory.h"
> +#include "hw/sysbus.h"
> +
> +/* Each OTP module holds 8192 bits of one-time programmable storage */
> +#define NPCM7XX_OTP_ARRAY_BITS (8192)
> +#define NPCM7XX_OTP_ARRAY_BYTES (NPCM7XX_OTP_ARRAY_BITS / 8)
> +
> +/**
> + * enum NPCM7xxOTPRegister - 32-bit register indices.
> + */
> +typedef enum NPCM7xxOTPRegister {
> + NPCM7XX_OTP_FST,
> + NPCM7XX_OTP_FADDR,
> + NPCM7XX_OTP_FDATA,
> + NPCM7XX_OTP_FCFG,
> + /* Offset 0x10 is FKEYIND in OTP1, FUSTRAP in OTP2 */
> + NPCM7XX_OTP_FKEYIND = 0x0010 / sizeof(uint32_t),
> + NPCM7XX_OTP_FUSTRAP = 0x0010 / sizeof(uint32_t),
> + NPCM7XX_OTP_FCTL,
> + NPCM7XX_OTP_NR_REGS,
> +} NPCM7xxOTPRegister;
> +
> +/**
> + * struct NPCM7xxOTPState - Device state for one OTP module.
> + * @parent: System bus device.
> + * @mmio: Memory region through which registers are accessed.
> + * @regs: Register contents.
> + * @array: OTP storage array.
> + */
> +typedef struct NPCM7xxOTPState {
> + SysBusDevice parent;
> +
> + MemoryRegion mmio;
> + uint32_t regs[NPCM7XX_OTP_NR_REGS];
> + uint8_t *array;
> +} NPCM7xxOTPState;
> +
> +#define TYPE_NPCM7XX_OTP "npcm7xx-otp"
> +#define NPCM7XX_OTP(obj) OBJECT_CHECK(NPCM7xxOTPState, (obj), TYPE_NPCM7XX_OTP)
> +
> +#define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
> +#define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
> +
> +/**
> + * struct NPCM7xxOTPClass - OTP module class.
> + * @parent: System bus device class.
> + * @mmio_ops: MMIO register operations for this type of module.
> + *
> + * The two OTP modules (key-storage and fuse-array) have slightly different
> + * behavior, so we give them different MMIO register operations.
> + */
> +typedef struct NPCM7xxOTPClass {
> + SysBusDeviceClass parent;
> +
> + const MemoryRegionOps *mmio_ops;
> +} NPCM7xxOTPClass;
> +
> +#define NPCM7XX_OTP_CLASS(klass) \
> + OBJECT_CLASS_CHECK(NPCM7xxOTPClass, (klass), TYPE_NPCM7XX_OTP)
> +#define NPCM7XX_OTP_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(NPCM7xxOTPClass, (obj), TYPE_NPCM7XX_OTP)
> +
> +/**
> + * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
> + * @s: OTP module.
> + * @data: Data to be encoded and written.
> + * @offset: Offset of first byte to be written in the OTP array.
> + * @len: Number of bytes before ECC encoding.
> + *
> + * Each nibble of data is encoded into a byte, so the number of bytes written
> + * to the array will be @len * 2.
> + */
> +extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
> + unsigned int offset, unsigned int len);
> +
> +#endif /* NPCM7XX_OTP_H */
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 12/12] docs/system: Add Nuvoton machine documentation
2020-06-26 23:55 ` [PATCH v3 12/12] docs/system: Add Nuvoton machine documentation Havard Skinnemoen
@ 2020-07-03 16:35 ` Philippe Mathieu-Daudé
2020-07-03 21:02 ` Havard Skinnemoen
0 siblings, 1 reply; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-03 16:35 UTC (permalink / raw)
To: Havard Skinnemoen, peter.maydell, clg, joel
Cc: kfting, qemu-arm, qemu-devel, Avi.Fishman
On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
> ---
[...]
> +Boot options
> +------------
> +
> +The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
> +a kernel using the ``-kernel`` option. OpenBMC images for `quanta-gsj` and
> +possibly others can be downloaded from the OpenPOWER jenkins :
> +
> + https://openpower.xyz/
I can only see the build log, not the u-boot/kernel binaries.
Can you point me to an example please?
> +
> +Booting a full firmware image requires a Boot ROM specified via the ``-bios``
> +option to QEMU. The firmware image should be attached as an MTD drive. Example :
> +
> +.. code-block:: bash
> +
> + $ qemu-system-arm -machine quanta-gsj -nographic \
> + -bios npcm7xx_bootrom.bin \
> + -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw
> diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
> index 1bd477a293..38a9daa9b9 100644
> --- a/docs/system/target-arm.rst
> +++ b/docs/system/target-arm.rst
> @@ -84,6 +84,7 @@ undocumented; you can get a complete list by running
> arm/aspeed
> arm/musicpal
> arm/nseries
> + arm/nuvoton
> arm/orangepi
> arm/palm
> arm/xscale
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines
2020-07-03 12:27 ` Peter Maydell
2020-07-03 13:35 ` Philippe Mathieu-Daudé
@ 2020-07-03 20:41 ` Havard Skinnemoen
1 sibling, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-07-03 20:41 UTC (permalink / raw)
To: Peter Maydell
Cc: Cédric Le Goater, Joel Stanley, qemu-arm, QEMU Developers,
IS20 Avi Fishman, CS20 KFTing
[-- Attachment #1: Type: text/plain, Size: 1306 bytes --]
On Fri, Jul 3, 2020 at 5:27 AM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Sat, 27 Jun 2020 at 00:55, Havard Skinnemoen <hskinnemoen@google.com>
> wrote:
> >
> > Time for another refresh of this patchset. Sorry it took so long -- I've
> been
> > trying to figure out why the Winbond flash model isn't working with
> > npcm750-evb, and I'm fairly convinced the number of dummy cycles in DIO
> mode
> > should be 4, not 1. Unfortunately, I don't see any other machines using
> Winbond
> > flash in DIO mode, so it's hard to prove that it's correct. I'm planning
> to
> > post a libqos-based test suite separately.
> >
> > I'm also planning to add the vbootrom to qemu as a submodule, similar to
> the
> > other roms, but not in this pathset (let me know if you do want me to
> include
> > this in the series).
>
> Hi; it looks like codewise this patchset is ready to go in
> and it's all been reviewed. I see however that all the
> new files are GPL-v2-only. We usually prefer GPL-v2-or-later
> for new code: is it possible to use that license instead ?
>
I sent an e-mail to our licensing team to see if there are any issues with
doing that. I don't expect a response until next week though, since this is
a long weekend.
I'll send out a v4 with updated headers if they approve.
Thanks,
Havard
[-- Attachment #2: Type: text/html, Size: 1846 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models
2020-07-03 13:32 ` Philippe Mathieu-Daudé
@ 2020-07-03 20:56 ` Havard Skinnemoen
2020-07-03 22:27 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 30+ messages in thread
From: Havard Skinnemoen @ 2020-07-03 20:56 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Cédric Le Goater, Joel Stanley, qemu-arm,
QEMU Developers, IS20 Avi Fishman, CS20 KFTing
On Fri, Jul 3, 2020 at 6:32 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> > +/*
> > + * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
> > + * that aren't handled by any device.
> > + */
> > +#define NPCM7XX_MMIO_BA (0x80000000)
> > +#define NPCM7XX_MMIO_SZ (0x7FFD0000)
>
> Could be 0x80000000 since UNIMP_DEVICE is created with low
> priority.
Good point, I'll do that.
> > + /* I/O space -- unimplemented unless overridden below. */
> > + create_unimplemented_device("npcm7xx.io", NPCM7XX_MMIO_BA, NPCM7XX_MMIO_SZ);
>
> Note by doing that you won't get transaction failures when accessing
> unassigned regions. This not incorrect, but a bit overkill (this covers
> almost 2GiB...).
A lot of that 2GiB space is used by six 128 MiB flash memory
apertures. But there are some holes that probably should generate
transaction failures instead of a default response.
Would it be OK if I send a patch to tighten up the unimplemented space
once a few more of the peripherals have been implemented?
Havard
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 12/12] docs/system: Add Nuvoton machine documentation
2020-07-03 16:35 ` Philippe Mathieu-Daudé
@ 2020-07-03 21:02 ` Havard Skinnemoen
0 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-07-03 21:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Cédric Le Goater, Joel Stanley, qemu-arm,
QEMU Developers, IS20 Avi Fishman, CS20 KFTing
On Fri, Jul 3, 2020 at 9:35 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> > +The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
> > +a kernel using the ``-kernel`` option. OpenBMC images for `quanta-gsj` and
> > +possibly others can be downloaded from the OpenPOWER jenkins :
> > +
> > + https://openpower.xyz/
>
> I can only see the build log, not the u-boot/kernel binaries.
> Can you point me to an example please?
This looks like the artifacts from the last successful gsj build:
https://openpower.xyz/job/run-meta-ci/distro=ubuntu,label=builder,target=gsj/lastSuccessfulBuild/artifact/openbmc/build/tmp/deploy/images/gsj/
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model
2020-07-03 13:46 ` Philippe Mathieu-Daudé
@ 2020-07-03 21:07 ` Havard Skinnemoen
2020-07-03 21:19 ` Havard Skinnemoen
2020-07-03 22:24 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-07-03 21:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Cédric Le Goater, Joel Stanley, qemu-arm,
QEMU Developers, IS20 Avi Fishman, CS20 KFTing
On Fri, Jul 3, 2020 at 6:46 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> > +static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
> > +{
> > + NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
> > + NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
> > + SysBusDevice *sbd = &s->parent;
> > +
> > + s->array = g_malloc0(NPCM7XX_OTP_ARRAY_BYTES);
>
> The possibility to reuse persistent OTP seems important.
> This can be added later of course.
Agree, it's an important part of the behavior of the module. But it's
not essential to be able to boot a BMC firmware image, so I left it
out initially.
> See simple example in hw/nvram/eeprom_at24c.c which use
> a BlockBackend so the OTP content is not lost after reset
> or migration.
I'll take a look at that, thanks!
> > +
> > + memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
> > + NPCM7XX_OTP_REGS_SIZE);
> > + sysbus_init_mmio(sbd, &s->mmio);
> > +}
> > +
> > +static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
> > +{
> > + ResettableClass *rc = RESETTABLE_CLASS(klass);
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
>
> Missing migration vmstate for NPCM7xxOTPState::regs[].
Ah, you're right. This is probably true for most of the peripherals in
this series. I'll see if I can get it sorted out for the next
iteration.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines
2020-07-03 13:35 ` Philippe Mathieu-Daudé
@ 2020-07-03 21:15 ` Havard Skinnemoen
2020-07-03 22:33 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 30+ messages in thread
From: Havard Skinnemoen @ 2020-07-03 21:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Markus Armbruster, QEMU Developers, Joel Stanley,
CS20 KFTing, qemu-arm, Cédric Le Goater, IS20 Avi Fishman
On Fri, Jul 3, 2020 at 6:35 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 7/3/20 2:27 PM, Peter Maydell wrote:
> > On Sat, 27 Jun 2020 at 00:55, Havard Skinnemoen <hskinnemoen@google.com> wrote:
> >>
> >> Time for another refresh of this patchset. Sorry it took so long -- I've been
> >> trying to figure out why the Winbond flash model isn't working with
> >> npcm750-evb, and I'm fairly convinced the number of dummy cycles in DIO mode
> >> should be 4, not 1. Unfortunately, I don't see any other machines using Winbond
> >> flash in DIO mode, so it's hard to prove that it's correct. I'm planning to
> >> post a libqos-based test suite separately.
> >>
> >> I'm also planning to add the vbootrom to qemu as a submodule, similar to the
> >> other roms, but not in this pathset (let me know if you do want me to include
> >> this in the series).
> >
> > Hi; it looks like codewise this patchset is ready to go in
> > and it's all been reviewed. I see however that all the
> > new files are GPL-v2-only. We usually prefer GPL-v2-or-later
> > for new code: is it possible to use that license instead ?
>
> This series has been posted before Markus qdev & error cleanups.
> Maybe some newer error patterns should be used now instead?
I'm not sure if I understand exactly what you're referring to, but
I'll do 'git log origin/master --author=armbru@redhat.com' to see if I
can apply any similar fixes or cleanups to this series.
Havard
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model
2020-07-03 21:07 ` Havard Skinnemoen
@ 2020-07-03 21:19 ` Havard Skinnemoen
2020-07-03 21:34 ` Philippe Mathieu-Daudé
2020-07-03 22:24 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 30+ messages in thread
From: Havard Skinnemoen @ 2020-07-03 21:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Cédric Le Goater, Joel Stanley, qemu-arm,
QEMU Developers, IS20 Avi Fishman, CS20 KFTing
On Fri, Jul 3, 2020 at 2:07 PM Havard Skinnemoen <hskinnemoen@google.com> wrote:
>
> On Fri, Jul 3, 2020 at 6:46 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >
> > On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> > > +static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
> > > +{
> > > + NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
> > > + NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
> > > + SysBusDevice *sbd = &s->parent;
> > > +
> > > + s->array = g_malloc0(NPCM7XX_OTP_ARRAY_BYTES);
> >
> > The possibility to reuse persistent OTP seems important.
> > This can be added later of course.
>
> Agree, it's an important part of the behavior of the module. But it's
> not essential to be able to boot a BMC firmware image, so I left it
> out initially.
>
> > See simple example in hw/nvram/eeprom_at24c.c which use
> > a BlockBackend so the OTP content is not lost after reset
> > or migration.
>
> I'll take a look at that, thanks!
>
> > > +
> > > + memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
> > > + NPCM7XX_OTP_REGS_SIZE);
> > > + sysbus_init_mmio(sbd, &s->mmio);
> > > +}
> > > +
> > > +static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
> > > +{
> > > + ResettableClass *rc = RESETTABLE_CLASS(klass);
> > > + DeviceClass *dc = DEVICE_CLASS(klass);
> > > +
> >
> > Missing migration vmstate for NPCM7xxOTPState::regs[].
>
> Ah, you're right. This is probably true for most of the peripherals in
> this series. I'll see if I can get it sorted out for the next
> iteration.
Btw, do you have any advice on how to test device migration? I'm not
planning to do actual migration of BMCs in the near future, so I'm not
sure if I'd notice if I get it wrong.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model
2020-07-03 21:19 ` Havard Skinnemoen
@ 2020-07-03 21:34 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-03 21:34 UTC (permalink / raw)
To: Havard Skinnemoen
Cc: Peter Maydell, QEMU Developers, Joel Stanley, CS20 KFTing,
qemu-arm, Cédric Le Goater, IS20 Avi Fishman
On Fri, Jul 3, 2020 at 11:19 PM Havard Skinnemoen
<hskinnemoen@google.com> wrote:
>
> On Fri, Jul 3, 2020 at 2:07 PM Havard Skinnemoen <hskinnemoen@google.com> wrote:
> >
> > On Fri, Jul 3, 2020 at 6:46 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> > >
> > > On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> > > > +static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
> > > > +{
> > > > + NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
> > > > + NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
> > > > + SysBusDevice *sbd = &s->parent;
> > > > +
> > > > + s->array = g_malloc0(NPCM7XX_OTP_ARRAY_BYTES);
> > >
> > > The possibility to reuse persistent OTP seems important.
> > > This can be added later of course.
> >
> > Agree, it's an important part of the behavior of the module. But it's
> > not essential to be able to boot a BMC firmware image, so I left it
> > out initially.
> >
> > > See simple example in hw/nvram/eeprom_at24c.c which use
> > > a BlockBackend so the OTP content is not lost after reset
> > > or migration.
> >
> > I'll take a look at that, thanks!
> >
> > > > +
> > > > + memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
> > > > + NPCM7XX_OTP_REGS_SIZE);
> > > > + sysbus_init_mmio(sbd, &s->mmio);
> > > > +}
> > > > +
> > > > +static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
> > > > +{
> > > > + ResettableClass *rc = RESETTABLE_CLASS(klass);
> > > > + DeviceClass *dc = DEVICE_CLASS(klass);
> > > > +
> > >
> > > Missing migration vmstate for NPCM7xxOTPState::regs[].
> >
> > Ah, you're right. This is probably true for most of the peripherals in
> > this series. I'll see if I can get it sorted out for the next
> > iteration.
>
> Btw, do you have any advice on how to test device migration? I'm not
> planning to do actual migration of BMCs in the near future, so I'm not
> sure if I'd notice if I get it wrong.
Peter Maydell described it very simply here:
https://translatedcode.wordpress.com/category/debugging-tricks/
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model
2020-07-03 21:07 ` Havard Skinnemoen
2020-07-03 21:19 ` Havard Skinnemoen
@ 2020-07-03 22:24 ` Philippe Mathieu-Daudé
2020-07-04 0:50 ` Havard Skinnemoen
1 sibling, 1 reply; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-03 22:24 UTC (permalink / raw)
To: Havard Skinnemoen
Cc: Peter Maydell, QEMU Developers, Joel Stanley, CS20 KFTing,
qemu-arm, Cédric Le Goater, IS20 Avi Fishman
On 7/3/20 11:07 PM, Havard Skinnemoen wrote:
> On Fri, Jul 3, 2020 at 6:46 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
>>> +static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
>>> +{
>>> + NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
>>> + NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
>>> + SysBusDevice *sbd = &s->parent;
>>> +
>>> + s->array = g_malloc0(NPCM7XX_OTP_ARRAY_BYTES);
>>
>> The possibility to reuse persistent OTP seems important.
>> This can be added later of course.
>
> Agree, it's an important part of the behavior of the module. But it's
> not essential to be able to boot a BMC firmware image, so I left it
> out initially.
This is not a problem until someone else try to use it. And OTP/NVRAM
are devices currently in hype. Meanwhile we have another technical debt.
I am just giving generic review comments.
What bugs me particularly is the OTP content zeroed at reset without
any warning. Maybe you can add something like:
qemu_log_mask(LOG_UNIMP,
"Persistence not supported, OTP content erased!\n");
in npcm7xx_otp_enter_reset().
>
>> See simple example in hw/nvram/eeprom_at24c.c which use
>> a BlockBackend so the OTP content is not lost after reset
>> or migration.
>
> I'll take a look at that, thanks!
>
>>> +
>>> + memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
>>> + NPCM7XX_OTP_REGS_SIZE);
>>> + sysbus_init_mmio(sbd, &s->mmio);
>>> +}
>>> +
>>> +static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
>>> +{
>>> + ResettableClass *rc = RESETTABLE_CLASS(klass);
>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>> +
>>
>> Missing migration vmstate for NPCM7xxOTPState::regs[].
>
> Ah, you're right. This is probably true for most of the peripherals in
> this series. I'll see if I can get it sorted out for the next
> iteration.
IIUC Peter is ready to queue your series on Monday if you fix the
license, but he usually doesn't accept devices without vmstate via
his tree, you got lucky ;) See:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg643089.html
Adding the vmstate is not a hard task. If you need to respin,
I strongly recommend you to consider adding them.
Excellent work btw :)
Regards,
Phil.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models
2020-07-03 20:56 ` Havard Skinnemoen
@ 2020-07-03 22:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-03 22:27 UTC (permalink / raw)
To: Havard Skinnemoen
Cc: Peter Maydell, QEMU Developers, Joel Stanley, CS20 KFTing,
qemu-arm, Cédric Le Goater, IS20 Avi Fishman
On 7/3/20 10:56 PM, Havard Skinnemoen wrote:
> On Fri, Jul 3, 2020 at 6:32 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
>>> +/*
>>> + * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
>>> + * that aren't handled by any device.
>>> + */
>>> +#define NPCM7XX_MMIO_BA (0x80000000)
>>> +#define NPCM7XX_MMIO_SZ (0x7FFD0000)
>>
>> Could be 0x80000000 since UNIMP_DEVICE is created with low
>> priority.
>
> Good point, I'll do that.
>
>>> + /* I/O space -- unimplemented unless overridden below. */
>>> + create_unimplemented_device("npcm7xx.io", NPCM7XX_MMIO_BA, NPCM7XX_MMIO_SZ);
>>
>> Note by doing that you won't get transaction failures when accessing
>> unassigned regions. This not incorrect, but a bit overkill (this covers
>> almost 2GiB...).
>
> A lot of that 2GiB space is used by six 128 MiB flash memory
> apertures. But there are some holes that probably should generate
> transaction failures instead of a default response.
See commit 529fc5fd3e ("hw/arm: Add the STM32F4xx SoC") for the
recommended verbose way.
>
> Would it be OK if I send a patch to tighten up the unimplemented space
> once a few more of the peripherals have been implemented?
Fine by me, this is not a blocker. Joel reviewed your patch anyway,
I trust him :)
Regards,
Phil.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines
2020-07-03 21:15 ` Havard Skinnemoen
@ 2020-07-03 22:33 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 30+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-03 22:33 UTC (permalink / raw)
To: Havard Skinnemoen
Cc: Peter Maydell, IS20 Avi Fishman, Markus Armbruster,
QEMU Developers, CS20 KFTing, qemu-arm, Joel Stanley,
Cédric Le Goater
On 7/3/20 11:15 PM, Havard Skinnemoen wrote:
> On Fri, Jul 3, 2020 at 6:35 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>>
>> On 7/3/20 2:27 PM, Peter Maydell wrote:
>>> On Sat, 27 Jun 2020 at 00:55, Havard Skinnemoen <hskinnemoen@google.com> wrote:
>>>>
>>>> Time for another refresh of this patchset. Sorry it took so long -- I've been
>>>> trying to figure out why the Winbond flash model isn't working with
>>>> npcm750-evb, and I'm fairly convinced the number of dummy cycles in DIO mode
>>>> should be 4, not 1. Unfortunately, I don't see any other machines using Winbond
>>>> flash in DIO mode, so it's hard to prove that it's correct. I'm planning to
>>>> post a libqos-based test suite separately.
>>>>
>>>> I'm also planning to add the vbootrom to qemu as a submodule, similar to the
>>>> other roms, but not in this pathset (let me know if you do want me to include
>>>> this in the series).
>>>
>>> Hi; it looks like codewise this patchset is ready to go in
>>> and it's all been reviewed. I see however that all the
>>> new files are GPL-v2-only. We usually prefer GPL-v2-or-later
>>> for new code: is it possible to use that license instead ?
>>
>> This series has been posted before Markus qdev & error cleanups.
>> Maybe some newer error patterns should be used now instead?
>
> I'm not sure if I understand exactly what you're referring to, but
> I'll do 'git log origin/master --author=armbru@redhat.com' to see if I
> can apply any similar fixes or cleanups to this series.
Sorry this was a quick comment for Peter, that he might get conflicts
when applying.
See Markus "Fix realize error API violations" commits:
7cd1c981eb, b40181942e & 3e9a88c372, and commit 123327d14
"Clean up roundabout error propagation".
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model
2020-07-03 22:24 ` Philippe Mathieu-Daudé
@ 2020-07-04 0:50 ` Havard Skinnemoen
0 siblings, 0 replies; 30+ messages in thread
From: Havard Skinnemoen @ 2020-07-04 0:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Cédric Le Goater, Joel Stanley, qemu-arm,
QEMU Developers, IS20 Avi Fishman, CS20 KFTing
On Fri, Jul 3, 2020 at 3:24 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 7/3/20 11:07 PM, Havard Skinnemoen wrote:
> > On Fri, Jul 3, 2020 at 6:46 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >>
> >> On 6/27/20 1:55 AM, Havard Skinnemoen wrote:
> >>> +static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
> >>> +{
> >>> + NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
> >>> + NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
> >>> + SysBusDevice *sbd = &s->parent;
> >>> +
> >>> + s->array = g_malloc0(NPCM7XX_OTP_ARRAY_BYTES);
> >>
> >> The possibility to reuse persistent OTP seems important.
> >> This can be added later of course.
> >
> > Agree, it's an important part of the behavior of the module. But it's
> > not essential to be able to boot a BMC firmware image, so I left it
> > out initially.
>
> This is not a problem until someone else try to use it. And OTP/NVRAM
> are devices currently in hype. Meanwhile we have another technical debt.
> I am just giving generic review comments.
>
> What bugs me particularly is the OTP content zeroed at reset without
> any warning. Maybe you can add something like:
>
> qemu_log_mask(LOG_UNIMP,
> "Persistence not supported, OTP content erased!\n");
>
> in npcm7xx_otp_enter_reset().
Ah, but it only zeroes the registers. The OTP array is only zeroed in realize().
But I see your point about persistence. I will work on that.
One possible complication is that real boards are expected to be
programmed a certain way, so some reasonable defaults need to be
loaded when the user doesn't specify an image (and perhaps also if the
user specifies an "uninitialized" image, if there's any way to detect
that). Would it make sense to add pc-bios blobs that can be loaded by
default, and used as a starting point or backing file for users that
need persistent OTP arrays? Or maybe just OR the factory-programmed
bits into the user-provided image, since that would match the OTP
nature of those bits.
> >
> >> See simple example in hw/nvram/eeprom_at24c.c which use
> >> a BlockBackend so the OTP content is not lost after reset
> >> or migration.
> >
> > I'll take a look at that, thanks!
> >
> >>> +
> >>> + memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
> >>> + NPCM7XX_OTP_REGS_SIZE);
> >>> + sysbus_init_mmio(sbd, &s->mmio);
> >>> +}
> >>> +
> >>> +static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
> >>> +{
> >>> + ResettableClass *rc = RESETTABLE_CLASS(klass);
> >>> + DeviceClass *dc = DEVICE_CLASS(klass);
> >>> +
> >>
> >> Missing migration vmstate for NPCM7xxOTPState::regs[].
> >
> > Ah, you're right. This is probably true for most of the peripherals in
> > this series. I'll see if I can get it sorted out for the next
> > iteration.
>
> IIUC Peter is ready to queue your series on Monday if you fix the
> license, but he usually doesn't accept devices without vmstate via
> his tree, you got lucky ;) See:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg643089.html
>
> Adding the vmstate is not a hard task. If you need to respin,
> I strongly recommend you to consider adding them.
Yeah, I'll add vmstate for v4. Thanks for the blog link, that looks
like what I need.
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2020-07-04 0:51 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-26 23:55 [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 01/12] npcm7xx: Add config symbol Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 02/12] hw/misc: Add NPCM7xx System Global Control Registers device model Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 03/12] hw/misc: Add NPCM7xx Clock Controller " Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 04/12] hw/timer: Add NPCM7xx Timer " Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models Havard Skinnemoen
2020-07-03 13:32 ` Philippe Mathieu-Daudé
2020-07-03 20:56 ` Havard Skinnemoen
2020-07-03 22:27 ` Philippe Mathieu-Daudé
2020-06-26 23:55 ` [PATCH v3 06/12] hw/arm: Add two NPCM7xx-based machines Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 07/12] hw/arm: Load -bios image as a boot ROM for npcm7xx Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 08/12] hw/nvram: NPCM7xx OTP device model Havard Skinnemoen
2020-07-03 13:46 ` Philippe Mathieu-Daudé
2020-07-03 21:07 ` Havard Skinnemoen
2020-07-03 21:19 ` Havard Skinnemoen
2020-07-03 21:34 ` Philippe Mathieu-Daudé
2020-07-03 22:24 ` Philippe Mathieu-Daudé
2020-07-04 0:50 ` Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 09/12] hw/mem: Stubbed out NPCM7xx Memory Controller model Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 10/12] hw/ssi: NPCM7xx Flash Interface Unit device model Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 11/12] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj Havard Skinnemoen
2020-06-26 23:55 ` [PATCH v3 12/12] docs/system: Add Nuvoton machine documentation Havard Skinnemoen
2020-07-03 16:35 ` Philippe Mathieu-Daudé
2020-07-03 21:02 ` Havard Skinnemoen
2020-06-27 0:15 ` [PATCH v3 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines no-reply
2020-07-03 12:27 ` Peter Maydell
2020-07-03 13:35 ` Philippe Mathieu-Daudé
2020-07-03 21:15 ` Havard Skinnemoen
2020-07-03 22:33 ` Philippe Mathieu-Daudé
2020-07-03 20:41 ` Havard Skinnemoen
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