From: Daniel Palmer <daniel@0x0f.com> To: Romain Perier <romain.perier@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, DTML <devicetree@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 5/5] ARM: dts: mstar: Switch to compatible "mstar,ssd20xd-timer" on ssd20xd Date: Sat, 27 Nov 2021 11:34:07 +0900 [thread overview] Message-ID: <CAFr9PXmVkcxFUAg-Z11hu5vqXJm7b8=DGJ_hnwkONhnEW_GdGw@mail.gmail.com> (raw) In-Reply-To: <20211126202144.72936-7-romain.perier@gmail.com> Hi Romain, On Sat, 27 Nov 2021 at 05:22, Romain Perier <romain.perier@gmail.com> wrote: > > This defines the real oscillators as input of timer1 and timer2 and > switch to "mstar,ssd20xd-timer". > > Signed-off-by: Romain Perier <romain.perier@gmail.com> > --- > .../arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi > index 6f067da61ba3..6ff1f02e00a0 100644 > --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi > +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi > @@ -6,6 +6,14 @@ > > #include "mstar-infinity2m.dtsi" > > +/ { > + xtal_timer: timer_xtal { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <432000000>; > + }; > +}; mm I think xtal is a bit confusing here. This isn't an external crystal but a fixed clock because we can't find where the clock is coming from yet. So maybe this should be s/xtal/clk/ or something? Maybe a comment about why we need this like "A header in the vendor kernel says the timers clk comes from XIU clock but we don't know what/where XIU clock is yet". > &gpio { > compatible = "sstar,ssd20xd-gpio"; > status = "okay"; > @@ -15,3 +23,13 @@ &smpctrl { > compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; > status = "okay"; > }; > + > +&timer1 { > + compatible = "mstar,ssd20xd-timer"; > + clocks = <&xtal_timer>; > +}; I think we should do this for timer0 too. As the below hunk in the driver will change the clock divider (For others reading this: The boot ROM in the chip sets a divider for timer0 to get something ~12MHz to stay compatible with their u-boot that expects 12MHz)) and timer0 will have the right clock rate instead of the roughly 12MHz but not really 12MHz frequency it has from boot and we don't need to rely on the divider value for timer0 being correct on boot. + if (of_device_is_compatible(np, "mstar,ssd20xd-timer")) { + to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER; + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); + writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE); + } + Cheers, Daniel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Palmer <daniel@0x0f.com> To: Romain Perier <romain.perier@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, DTML <devicetree@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 5/5] ARM: dts: mstar: Switch to compatible "mstar,ssd20xd-timer" on ssd20xd Date: Sat, 27 Nov 2021 11:34:07 +0900 [thread overview] Message-ID: <CAFr9PXmVkcxFUAg-Z11hu5vqXJm7b8=DGJ_hnwkONhnEW_GdGw@mail.gmail.com> (raw) In-Reply-To: <20211126202144.72936-7-romain.perier@gmail.com> Hi Romain, On Sat, 27 Nov 2021 at 05:22, Romain Perier <romain.perier@gmail.com> wrote: > > This defines the real oscillators as input of timer1 and timer2 and > switch to "mstar,ssd20xd-timer". > > Signed-off-by: Romain Perier <romain.perier@gmail.com> > --- > .../arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi > index 6f067da61ba3..6ff1f02e00a0 100644 > --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi > +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi > @@ -6,6 +6,14 @@ > > #include "mstar-infinity2m.dtsi" > > +/ { > + xtal_timer: timer_xtal { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <432000000>; > + }; > +}; mm I think xtal is a bit confusing here. This isn't an external crystal but a fixed clock because we can't find where the clock is coming from yet. So maybe this should be s/xtal/clk/ or something? Maybe a comment about why we need this like "A header in the vendor kernel says the timers clk comes from XIU clock but we don't know what/where XIU clock is yet". > &gpio { > compatible = "sstar,ssd20xd-gpio"; > status = "okay"; > @@ -15,3 +23,13 @@ &smpctrl { > compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; > status = "okay"; > }; > + > +&timer1 { > + compatible = "mstar,ssd20xd-timer"; > + clocks = <&xtal_timer>; > +}; I think we should do this for timer0 too. As the below hunk in the driver will change the clock divider (For others reading this: The boot ROM in the chip sets a divider for timer0 to get something ~12MHz to stay compatible with their u-boot that expects 12MHz)) and timer0 will have the right clock rate instead of the roughly 12MHz but not really 12MHz frequency it has from boot and we don't need to rely on the divider value for timer0 being correct on boot. + if (of_device_is_compatible(np, "mstar,ssd20xd-timer")) { + to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER; + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); + writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE); + } + Cheers, Daniel
next prev parent reply other threads:[~2021-11-27 2:39 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-26 20:21 [PATCH 0/5] Add timers for Mstar SoCs Romain Perier 2021-11-26 20:21 ` Romain Perier 2021-11-26 20:21 ` [PATCH 1/5] clocksource: Add MStar MSC313e timer support Romain Perier 2021-11-26 20:21 ` Romain Perier 2021-11-29 17:02 ` Daniel Lezcano 2021-11-29 17:02 ` Daniel Lezcano [not found] ` <CABgxDo+W3vg_dDTphkOLxRPzKER891CxTJnPPVuryj9YQOg1EQ@mail.gmail.com> 2021-11-30 14:39 ` Daniel Lezcano 2021-11-30 14:39 ` Daniel Lezcano 2021-11-26 20:21 ` [PATCH 2/4] ARM: dts: mstar: Remove unused rtc_xtal Romain Perier 2021-11-26 20:21 ` Romain Perier 2021-11-27 1:22 ` Daniel Palmer 2021-11-27 1:22 ` Daniel Palmer 2021-11-26 20:21 ` [PATCH 2/5] clocksource: msc313e: Add support for ssd20xd-based platforms Romain Perier 2021-11-26 20:21 ` Romain Perier 2021-11-26 20:21 ` [PATCH 3/5] dt-bindings: timer: Add Mstar MSC313e timer devicetree bindings documentation Romain Perier 2021-11-26 20:21 ` Romain Perier 2021-11-27 2:23 ` Daniel Palmer 2021-11-27 2:23 ` Daniel Palmer 2021-12-02 0:11 ` Rob Herring 2021-12-02 0:11 ` Rob Herring 2021-11-26 20:21 ` [PATCH 4/5] ARM: dts: mstar: Add timers device nodes Romain Perier 2021-11-26 20:21 ` Romain Perier 2021-11-26 20:21 ` [PATCH 5/5] ARM: dts: mstar: Switch to compatible "mstar,ssd20xd-timer" on ssd20xd Romain Perier 2021-11-26 20:21 ` [PATCH 5/5] ARM: dts: mstar: Switch to compatible "mstar, ssd20xd-timer" " Romain Perier 2021-11-27 2:34 ` Daniel Palmer [this message] 2021-11-27 2:34 ` [PATCH 5/5] ARM: dts: mstar: Switch to compatible "mstar,ssd20xd-timer" " Daniel Palmer 2021-11-28 13:17 ` Daniel Palmer 2021-11-28 13:17 ` Daniel Palmer [not found] ` <CABgxDo+pF0RKK+HL+MVv5s0pn1T9a9Mqp6uPEkT0YPEH9kvQqw@mail.gmail.com> 2021-12-12 16:44 ` Daniel Palmer 2021-12-12 16:44 ` Daniel Palmer
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