From: Jim Wilson <jimw@sifive.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Jim Wilson <jimw@sifive.com> Subject: [Qemu-devel] [PATCH 0/5 v2] RISC-V: Add gdb xml files and gdbstub support. Date: Fri, 28 Dec 2018 14:05:57 -0800 [thread overview] Message-ID: <CAFyWVaai=5K7j8w+Abpk9jxGyKuo4v9w2BgmDbY=_29+Q++Jyw@mail.gmail.com> (raw) This is the second version of the patch set. I haven't gotten any bug reports for the patches in the several weeks that they have been available, and no review yet, so the only significant difference from the first version is that I ran them through checkpatch to fix style issues, and I sent them to the right mailing list this time. With these patches, I can run system qemu with -s -S, connect to it with gdb, and then print any integer, FP, or CSR register. This support is currently broken. The first two patches in the series are just dropping in xml files from gdb unchanged, with configure support to point at them. The next two patches are the inconvenient stuff. The gdb CSR files are in documentation order not numerical order, so I need an array to map the gdb numbers to the actual hardware numbers. The gdb files should probably be improved, but I don't know when that will happen. That is the third patch. The fourth patch is to disable all of the illegal instruction checks when accessing CSRs from the debugger, as it needs to be able to access them without traps. The last patch adds the gdbstub support to use the new xml files which is pretty simple, though there is an unanswered question in there about what to do with the FP registers. Should we try to configure them based on the target? Right now I just always enable them which is the simple solution. I'm not sure if enabling them based on the target will even work with gdb or not. Jim
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From: Jim Wilson <jimw@sifive.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Jim Wilson <jimw@sifive.com> Subject: [Qemu-riscv] [PATCH 0/5 v2] RISC-V: Add gdb xml files and gdbstub support. Date: Fri, 28 Dec 2018 14:05:57 -0800 [thread overview] Message-ID: <CAFyWVaai=5K7j8w+Abpk9jxGyKuo4v9w2BgmDbY=_29+Q++Jyw@mail.gmail.com> (raw) This is the second version of the patch set. I haven't gotten any bug reports for the patches in the several weeks that they have been available, and no review yet, so the only significant difference from the first version is that I ran them through checkpatch to fix style issues, and I sent them to the right mailing list this time. With these patches, I can run system qemu with -s -S, connect to it with gdb, and then print any integer, FP, or CSR register. This support is currently broken. The first two patches in the series are just dropping in xml files from gdb unchanged, with configure support to point at them. The next two patches are the inconvenient stuff. The gdb CSR files are in documentation order not numerical order, so I need an array to map the gdb numbers to the actual hardware numbers. The gdb files should probably be improved, but I don't know when that will happen. That is the third patch. The fourth patch is to disable all of the illegal instruction checks when accessing CSRs from the debugger, as it needs to be able to access them without traps. The last patch adds the gdbstub support to use the new xml files which is pretty simple, though there is an unanswered question in there about what to do with the FP registers. Should we try to configure them based on the target? Right now I just always enable them which is the simple solution. I'm not sure if enabling them based on the target will even work with gdb or not. Jim
next reply other threads:[~2018-12-28 22:20 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-28 22:05 Jim Wilson [this message] 2018-12-28 22:05 ` [Qemu-riscv] [PATCH 0/5 v2] RISC-V: Add gdb xml files and gdbstub support Jim Wilson 2018-12-28 22:07 ` [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files Jim Wilson 2018-12-28 22:07 ` [Qemu-riscv] " Jim Wilson 2018-12-29 22:20 ` [Qemu-devel] " Richard Henderson 2018-12-29 22:20 ` [Qemu-riscv] " Richard Henderson 2018-12-30 19:56 ` Jim Wilson 2018-12-30 19:56 ` [Qemu-riscv] " Jim Wilson 2019-01-22 21:53 ` Alistair Francis 2019-01-22 21:53 ` [Qemu-riscv] " Alistair Francis 2018-12-28 22:08 ` [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit " Jim Wilson 2018-12-28 22:08 ` [Qemu-riscv] " Jim Wilson 2019-01-22 21:53 ` [Qemu-devel] " Alistair Francis 2019-01-22 21:53 ` [Qemu-riscv] " Alistair Francis 2018-12-28 22:09 ` [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers Jim Wilson 2018-12-28 22:09 ` [Qemu-riscv] " Jim Wilson 2018-12-29 22:23 ` [Qemu-devel] " Richard Henderson 2018-12-29 22:23 ` [Qemu-riscv] " Richard Henderson 2018-12-30 19:22 ` Jim Wilson 2018-12-30 19:22 ` [Qemu-riscv] " Jim Wilson 2019-01-22 21:45 ` Alistair Francis 2019-01-22 21:45 ` [Qemu-riscv] " Alistair Francis 2019-01-29 3:00 ` Jim Wilson 2019-01-29 3:00 ` [Qemu-riscv] " Jim Wilson 2018-12-28 22:10 ` [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs Jim Wilson 2018-12-28 22:10 ` [Qemu-riscv] " Jim Wilson 2018-12-29 22:25 ` [Qemu-devel] " Richard Henderson 2018-12-29 22:25 ` [Qemu-riscv] " Richard Henderson 2019-01-22 21:46 ` Alistair Francis 2019-01-22 21:46 ` [Qemu-riscv] " Alistair Francis 2018-12-28 22:11 ` [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files Jim Wilson 2018-12-28 22:11 ` [Qemu-riscv] " Jim Wilson 2019-01-22 21:52 ` [Qemu-devel] " Alistair Francis 2019-01-22 21:52 ` [Qemu-riscv] " Alistair Francis 2019-01-29 3:11 ` Jim Wilson 2019-01-29 3:11 ` [Qemu-riscv] " Jim Wilson 2019-01-29 23:21 ` Palmer Dabbelt 2019-01-29 23:21 ` [Qemu-riscv] " Palmer Dabbelt
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