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From: Jim Wilson <jimw@sifive.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	qemu-riscv@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
Date: Mon, 28 Jan 2019 19:11:58 -0800	[thread overview]
Message-ID: <CAFyWVaYACGYvUe2ehYiT0hjJR4bUc44ZG5niEdT7mJOMXxGVpg@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKMT7F_ziNjbdTU08ph33DnSkKyt+dSMSVXLVZffSvBu-w@mail.gmail.com>

On Tue, Jan 22, 2019 at 1:52 PM Alistair Francis <alistair23@gmail.com> wrote:
> You can get env and then check for floating point support:
>
> CPURISCVState *env = &cs->env;
> if (env->misa_mask & RVF) {
> ...

I needed this which wasn't hard to figure out.
    RISCVCPU *cpu = RISCV_CPU(cs);
    CPURISCVState *env = &cpu->env;
    if (env->misa & RVF) {

The tricky bit was figuring out how to test it, because I wasn't sure
if making registers conditional would actually work.  I figured out
that using -machine sifive_e gives me a target with no fpu, and
playing with that a bit I get the expected result, which is that the
FP regs don't print anymore.  The FP related CSRs still do, but that
would require gdb fixes I think, because gdb knows that they are both
FP regs and CSR, and tries to print them both ways.  That leads to a
more general problem of figuring out exactly which CSRs a particular
target implements, which is a bigger problem than I have time to fix
at the moment, and should be handled as a separate problem.

Since my patch set is now a month old, I'll rebase onto current master
and post a version 3 patch set.

Jim

WARNING: multiple messages have this Message-ID (diff)
From: Jim Wilson <jimw@sifive.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	qemu-riscv@nongnu.org
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
Date: Mon, 28 Jan 2019 19:11:58 -0800	[thread overview]
Message-ID: <CAFyWVaYACGYvUe2ehYiT0hjJR4bUc44ZG5niEdT7mJOMXxGVpg@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKMT7F_ziNjbdTU08ph33DnSkKyt+dSMSVXLVZffSvBu-w@mail.gmail.com>

On Tue, Jan 22, 2019 at 1:52 PM Alistair Francis <alistair23@gmail.com> wrote:
> You can get env and then check for floating point support:
>
> CPURISCVState *env = &cs->env;
> if (env->misa_mask & RVF) {
> ...

I needed this which wasn't hard to figure out.
    RISCVCPU *cpu = RISCV_CPU(cs);
    CPURISCVState *env = &cpu->env;
    if (env->misa & RVF) {

The tricky bit was figuring out how to test it, because I wasn't sure
if making registers conditional would actually work.  I figured out
that using -machine sifive_e gives me a target with no fpu, and
playing with that a bit I get the expected result, which is that the
FP regs don't print anymore.  The FP related CSRs still do, but that
would require gdb fixes I think, because gdb knows that they are both
FP regs and CSR, and tries to print them both ways.  That leads to a
more general problem of figuring out exactly which CSRs a particular
target implements, which is a bigger problem than I have time to fix
at the moment, and should be handled as a separate problem.

Since my patch set is now a month old, I'll rebase onto current master
and post a version 3 patch set.

Jim


  reply	other threads:[~2019-01-29  3:14 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-28 22:05 [Qemu-devel] [PATCH 0/5 v2] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
2018-12-28 22:05 ` [Qemu-riscv] " Jim Wilson
2018-12-28 22:07 ` [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files Jim Wilson
2018-12-28 22:07   ` [Qemu-riscv] " Jim Wilson
2018-12-29 22:20   ` [Qemu-devel] " Richard Henderson
2018-12-29 22:20     ` [Qemu-riscv] " Richard Henderson
2018-12-30 19:56     ` Jim Wilson
2018-12-30 19:56       ` [Qemu-riscv] " Jim Wilson
2019-01-22 21:53   ` Alistair Francis
2019-01-22 21:53     ` [Qemu-riscv] " Alistair Francis
2018-12-28 22:08 ` [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit " Jim Wilson
2018-12-28 22:08   ` [Qemu-riscv] " Jim Wilson
2019-01-22 21:53   ` [Qemu-devel] " Alistair Francis
2019-01-22 21:53     ` [Qemu-riscv] " Alistair Francis
2018-12-28 22:09 ` [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers Jim Wilson
2018-12-28 22:09   ` [Qemu-riscv] " Jim Wilson
2018-12-29 22:23   ` [Qemu-devel] " Richard Henderson
2018-12-29 22:23     ` [Qemu-riscv] " Richard Henderson
2018-12-30 19:22     ` Jim Wilson
2018-12-30 19:22       ` [Qemu-riscv] " Jim Wilson
2019-01-22 21:45       ` Alistair Francis
2019-01-22 21:45         ` [Qemu-riscv] " Alistair Francis
2019-01-29  3:00         ` Jim Wilson
2019-01-29  3:00           ` [Qemu-riscv] " Jim Wilson
2018-12-28 22:10 ` [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs Jim Wilson
2018-12-28 22:10   ` [Qemu-riscv] " Jim Wilson
2018-12-29 22:25   ` [Qemu-devel] " Richard Henderson
2018-12-29 22:25     ` [Qemu-riscv] " Richard Henderson
2019-01-22 21:46   ` Alistair Francis
2019-01-22 21:46     ` [Qemu-riscv] " Alistair Francis
2018-12-28 22:11 ` [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files Jim Wilson
2018-12-28 22:11   ` [Qemu-riscv] " Jim Wilson
2019-01-22 21:52   ` [Qemu-devel] " Alistair Francis
2019-01-22 21:52     ` [Qemu-riscv] " Alistair Francis
2019-01-29  3:11     ` Jim Wilson [this message]
2019-01-29  3:11       ` Jim Wilson
2019-01-29 23:21       ` Palmer Dabbelt
2019-01-29 23:21         ` [Qemu-riscv] " Palmer Dabbelt

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