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From: Saravana Kannan <saravanak@google.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>,
	Atish Patra <atishp@atishpatra.org>,
	Andrew Jones <ajones@ventanamicro.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v6 03/14] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized
Date: Wed, 19 Jul 2023 15:14:51 -0700	[thread overview]
Message-ID: <CAGETcx9zAF2ipO0s-6-zjyvn1JWt7OUS9G=cQ6OwyOPuqh-pBA@mail.gmail.com> (raw)
In-Reply-To: <20230719113542.2293295-4-apatel@ventanamicro.com>

On Wed, Jul 19, 2023 at 4:36 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The RISC-V INTC local interrupts are per-HART (or per-CPU) so
> we create INTC IRQ domain only for the INTC node belonging to
> the boot HART. This means only the boot HART INTC node will be
> marked as initialized and other INTC nodes won't be marked which
> results downstream interrupt controllers (such as IMSIC and APLIC
> direct-mode) not being probed due to missing device suppliers.
>
> To address this issue, we mark all INTC node for which we don't
> create IRQ domain as initialized.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  drivers/irqchip/irq-riscv-intc.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index 65f4a2afb381..4e2704bc25fb 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -155,8 +155,16 @@ static int __init riscv_intc_init(struct device_node *node,
>          * for each INTC DT node. We only need to do INTC initialization
>          * for the INTC DT node belonging to boot CPU (or boot HART).
>          */
> -       if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
> +       if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) {
> +               /*
> +                * The INTC nodes of each CPU are suppliers for downstream
> +                * interrupt controllers (such as IMSIC and APLIC direct-mode)
> +                * so we should mark an INTC node as initialized if we are
> +                * not creating IRQ domain for it.
> +                */

I'm a bit confused by this. If those non-boot CPUs INTC doesn't have
an IRQ domain, why are the downstream interrupt controllers listing
these non-boot CPU INTCs as an upstream interrupt controller?

This is more of a question of the existing behavior that this patch,
but this patch highlights the existing oddity.

-Saravana

> +               fwnode_dev_initialized(of_fwnode_handle(node), true);
>                 return 0;
> +       }
>
>         return riscv_intc_init_common(of_node_to_fwnode(node));
>  }
> --
> 2.34.1
>

WARNING: multiple messages have this Message-ID (diff)
From: Saravana Kannan <saravanak@google.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
	Marc Zyngier <maz@kernel.org>, Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Frank Rowand <frowand.list@gmail.com>,
	linux-riscv@lists.infradead.org,
	Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH v6 03/14] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized
Date: Wed, 19 Jul 2023 15:14:51 -0700	[thread overview]
Message-ID: <CAGETcx9zAF2ipO0s-6-zjyvn1JWt7OUS9G=cQ6OwyOPuqh-pBA@mail.gmail.com> (raw)
In-Reply-To: <20230719113542.2293295-4-apatel@ventanamicro.com>

On Wed, Jul 19, 2023 at 4:36 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The RISC-V INTC local interrupts are per-HART (or per-CPU) so
> we create INTC IRQ domain only for the INTC node belonging to
> the boot HART. This means only the boot HART INTC node will be
> marked as initialized and other INTC nodes won't be marked which
> results downstream interrupt controllers (such as IMSIC and APLIC
> direct-mode) not being probed due to missing device suppliers.
>
> To address this issue, we mark all INTC node for which we don't
> create IRQ domain as initialized.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  drivers/irqchip/irq-riscv-intc.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index 65f4a2afb381..4e2704bc25fb 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -155,8 +155,16 @@ static int __init riscv_intc_init(struct device_node *node,
>          * for each INTC DT node. We only need to do INTC initialization
>          * for the INTC DT node belonging to boot CPU (or boot HART).
>          */
> -       if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
> +       if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) {
> +               /*
> +                * The INTC nodes of each CPU are suppliers for downstream
> +                * interrupt controllers (such as IMSIC and APLIC direct-mode)
> +                * so we should mark an INTC node as initialized if we are
> +                * not creating IRQ domain for it.
> +                */

I'm a bit confused by this. If those non-boot CPUs INTC doesn't have
an IRQ domain, why are the downstream interrupt controllers listing
these non-boot CPU INTCs as an upstream interrupt controller?

This is more of a question of the existing behavior that this patch,
but this patch highlights the existing oddity.

-Saravana

> +               fwnode_dev_initialized(of_fwnode_handle(node), true);
>                 return 0;
> +       }
>
>         return riscv_intc_init_common(of_node_to_fwnode(node));
>  }
> --
> 2.34.1
>

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  reply	other threads:[~2023-07-19 22:15 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-19 11:35 [PATCH v6 00/14] Linux RISC-V AIA Support Anup Patel
2023-07-19 11:35 ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 01/14] RISC-V: Add riscv_get_intc_hartid() function Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 02/14] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 22:25   ` Saravana Kannan
2023-07-19 22:25     ` Saravana Kannan
2023-07-20  5:21     ` Anup Patel
2023-07-20  5:21       ` Anup Patel
2023-07-19 22:37   ` Rob Herring
2023-07-19 22:37     ` Rob Herring
2023-07-20 11:55     ` Anup Patel
2023-07-20 11:55       ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 03/14] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 22:14   ` Saravana Kannan [this message]
2023-07-19 22:14     ` Saravana Kannan
2023-07-20  5:21     ` Anup Patel
2023-07-20  5:21       ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 04/14] irqchip/sifive-plic: Use platform driver probing for PLIC Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-27  8:41   ` Sunil V L
2023-07-27  8:41     ` Sunil V L
2023-08-02 12:25     ` Anup Patel
2023-08-02 12:25       ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 05/14] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 06/14] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 07/14] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 08/14] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 09/14] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 10/14] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 11/14] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 12/14] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 13/14] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-07-19 11:35   ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 14/14] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2023-07-19 11:35   ` Anup Patel

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