From: "Björn Töpel" <bjorn.topel@gmail.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@sifive.com>,
davidlee@sifive.com, Daniel Borkmann <daniel@iogearbox.net>,
Netdev <netdev@vger.kernel.org>
Subject: Re: [RFC PATCH 1/3] riscv: set HAVE_EFFICIENT_UNALIGNED_ACCESS
Date: Tue, 15 Jan 2019 17:06:47 +0100 [thread overview]
Message-ID: <CAJ+HfNigethi_fK-Cv5CskH9B7b+9Go1_qSVsGhvXnX1kbxykw@mail.gmail.com> (raw)
In-Reply-To: <20190115153931.GF26443@infradead.org>
Den tis 15 jan. 2019 kl 16:39 skrev Christoph Hellwig <hch@infradead.org>:
>
> Hmm, while the RISC-V spec requires misaligned load/store support,
> who says they are efficient? Maybe add a little comment that says
> on which cpus they are efficient.
Good point! :-) I need to check how other architectures does this.
Enabling it for *all* RV64 is probably not correct.
WARNING: multiple messages have this Message-ID (diff)
From: "Björn Töpel" <bjorn.topel@gmail.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: Netdev <netdev@vger.kernel.org>,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@sifive.com>,
Daniel Borkmann <daniel@iogearbox.net>,
davidlee@sifive.com
Subject: Re: [RFC PATCH 1/3] riscv: set HAVE_EFFICIENT_UNALIGNED_ACCESS
Date: Tue, 15 Jan 2019 17:06:47 +0100 [thread overview]
Message-ID: <CAJ+HfNigethi_fK-Cv5CskH9B7b+9Go1_qSVsGhvXnX1kbxykw@mail.gmail.com> (raw)
In-Reply-To: <20190115153931.GF26443@infradead.org>
Den tis 15 jan. 2019 kl 16:39 skrev Christoph Hellwig <hch@infradead.org>:
>
> Hmm, while the RISC-V spec requires misaligned load/store support,
> who says they are efficient? Maybe add a little comment that says
> on which cpus they are efficient.
Good point! :-) I need to check how other architectures does this.
Enabling it for *all* RV64 is probably not correct.
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next prev parent reply other threads:[~2019-01-15 16:07 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-15 8:35 [RFC PATCH 0/3] RV64G eBPF JIT Björn Töpel
2019-01-15 8:35 ` Björn Töpel
2019-01-15 8:35 ` Björn Töpel
2019-01-15 8:35 ` [RFC PATCH 1/3] riscv: set HAVE_EFFICIENT_UNALIGNED_ACCESS Björn Töpel
2019-01-15 8:35 ` Björn Töpel
2019-01-15 15:39 ` Christoph Hellwig
2019-01-15 15:39 ` Christoph Hellwig
2019-01-15 16:06 ` Björn Töpel [this message]
2019-01-15 16:06 ` Björn Töpel
2019-01-25 20:21 ` Palmer Dabbelt
2019-01-25 20:21 ` Palmer Dabbelt
2019-01-26 1:33 ` Jim Wilson
2019-01-26 1:33 ` Jim Wilson
2019-01-29 2:43 ` Palmer Dabbelt
2019-01-29 2:43 ` Palmer Dabbelt
2019-01-15 8:35 ` [RFC PATCH 2/3] riscv: add build infra for JIT compiler Björn Töpel
2019-01-15 8:35 ` Björn Töpel
2019-01-15 15:43 ` Christoph Hellwig
2019-01-15 15:43 ` Christoph Hellwig
2019-01-15 16:09 ` Björn Töpel
2019-01-15 16:09 ` Björn Töpel
2019-01-15 8:35 ` [RFC PATCH 3/3] bpf, riscv: added eBPF JIT for RV64G Björn Töpel
2019-01-15 8:35 ` Björn Töpel
2019-01-15 8:35 ` Björn Töpel
2019-01-15 23:49 ` Daniel Borkmann
2019-01-15 23:49 ` Daniel Borkmann
2019-01-16 7:23 ` Björn Töpel
2019-01-16 7:23 ` Björn Töpel
2019-01-16 15:41 ` Daniel Borkmann
2019-01-16 15:41 ` Daniel Borkmann
2019-01-16 19:06 ` Björn Töpel
2019-01-16 19:06 ` Björn Töpel
2019-01-15 15:40 ` [RFC PATCH 0/3] RV64G eBPF JIT Christoph Hellwig
2019-01-15 15:40 ` Christoph Hellwig
2019-01-15 16:03 ` Björn Töpel
2019-01-15 16:03 ` Björn Töpel
2019-01-25 19:02 ` Palmer Dabbelt
2019-01-25 19:02 ` Palmer Dabbelt
2019-01-25 19:54 ` Paul Walmsley
2019-01-25 19:54 ` Paul Walmsley
2019-01-27 12:28 ` Björn Töpel
2019-01-27 12:28 ` Björn Töpel
2019-01-30 2:02 ` Palmer Dabbelt
2019-01-30 2:02 ` Palmer Dabbelt
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