All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mike Leach <mike.leach@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Coresight ML <coresight@lists.linaro.org>,
	Anshuman.Khandual@arm.com,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Leo Yan <leo.yan@linaro.org>
Subject: Re: [PATCH 06/19] coresight: etm4x: Always read the registers on the host CPU
Date: Fri, 18 Sep 2020 16:34:28 +0100	[thread overview]
Message-ID: <CAJ9a7VgvWcnuineewEcDJv3cNuxomQTe0t4r=o4TmFjGsmM2wQ@mail.gmail.com> (raw)
In-Reply-To: <20200911084119.1080694-7-suzuki.poulose@arm.com>

Reviewed-by: Mike Leach <mike.leach@linaro.org>


On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> As we are about to add support for sysreg access to ETM4.4+ components,
> make sure that we read the registers only on the host CPU.
>
> Cc: Mike Leach <mike.leach@linaro.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 23 ++++++++-----------
>  1 file changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index a588cd6de01c..57fc8dad2e92 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -2341,23 +2341,20 @@ static u32 etmv4_cross_read(const struct device *dev, u32 offset)
>         return reg.data;
>  }
>
> -#define coresight_etm4x_reg(name, offset)                      \
> -       coresight_simple_reg32(struct etmv4_drvdata, name, offset)
> -
>  #define coresight_etm4x_cross_read(name, offset)                       \
>         coresight_simple_func(struct etmv4_drvdata, etmv4_cross_read,   \
>                               name, offset)
>
> -coresight_etm4x_reg(trcpdcr, TRCPDCR);
> -coresight_etm4x_reg(trcpdsr, TRCPDSR);
> -coresight_etm4x_reg(trclsr, TRCLSR);
> -coresight_etm4x_reg(trcauthstatus, TRCAUTHSTATUS);
> -coresight_etm4x_reg(trcdevid, TRCDEVID);
> -coresight_etm4x_reg(trcdevtype, TRCDEVTYPE);
> -coresight_etm4x_reg(trcpidr0, TRCPIDR0);
> -coresight_etm4x_reg(trcpidr1, TRCPIDR1);
> -coresight_etm4x_reg(trcpidr2, TRCPIDR2);
> -coresight_etm4x_reg(trcpidr3, TRCPIDR3);
> +coresight_etm4x_cross_read(trcpdcr, TRCPDCR);
> +coresight_etm4x_cross_read(trcpdsr, TRCPDSR);
> +coresight_etm4x_cross_read(trclsr, TRCLSR);
> +coresight_etm4x_cross_read(trcauthstatus, TRCAUTHSTATUS);
> +coresight_etm4x_cross_read(trcdevid, TRCDEVID);
> +coresight_etm4x_cross_read(trcdevtype, TRCDEVTYPE);
> +coresight_etm4x_cross_read(trcpidr0, TRCPIDR0);
> +coresight_etm4x_cross_read(trcpidr1, TRCPIDR1);
> +coresight_etm4x_cross_read(trcpidr2, TRCPIDR2);
> +coresight_etm4x_cross_read(trcpidr3, TRCPIDR3);
>  coresight_etm4x_cross_read(trcoslsr, TRCOSLSR);
>  coresight_etm4x_cross_read(trcconfig, TRCCONFIGR);
>  coresight_etm4x_cross_read(trctraceid, TRCTRACEIDR);
> --
> 2.24.1
>


--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-09-18 15:37 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-11  8:41 [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 01/19] coresight: Introduce device access abstraction Suzuki K Poulose
2020-09-18 15:33   ` Mike Leach
2020-09-11  8:41 ` [PATCH 02/19] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 03/19] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 04/19] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 05/19] coresight: Use device access layer for Software lock/unlock operations Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-18 15:52     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 06/19] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach [this message]
2020-09-11  8:41 ` [PATCH 07/19] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 08/19] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 09/19] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-22 10:20     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 11/19] coresight: etm4x: Check for OS and Software Lock Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:44     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:55     ` Suzuki K Poulose
2020-09-22 12:47       ` Mike Leach
2020-09-30 10:32         ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 13/19] coresight: etm4x: Clean up " Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 14/19] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:18     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 16/19] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 17/19] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-11  8:41 ` [PATCH 18/19] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-23 11:52     ` Suzuki K Poulose
2020-09-23 16:55       ` Mike Leach
2020-09-11  8:41 ` [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units Suzuki K Poulose
2020-09-11  8:41   ` Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-18 15:35     ` Mike Leach
2020-09-24  9:48     ` Suzuki K Poulose
2020-09-24  9:48       ` Suzuki K Poulose
2020-09-24 10:08       ` Mike Leach
2020-09-24 10:08         ` Mike Leach
2020-09-18 15:33 ` [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Mike Leach
2020-09-25  9:55   ` Suzuki K Poulose
2020-09-29 16:42     ` Mike Leach

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAJ9a7VgvWcnuineewEcDJv3cNuxomQTe0t4r=o4TmFjGsmM2wQ@mail.gmail.com' \
    --to=mike.leach@linaro.org \
    --cc=Anshuman.Khandual@arm.com \
    --cc=coresight@lists.linaro.org \
    --cc=leo.yan@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=mathieu.poirier@linaro.org \
    --cc=suzuki.poulose@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.