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From: Mike Leach <mike.leach@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Coresight ML <coresight@lists.linaro.org>,
	Anshuman.Khandual@arm.com,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Leo Yan <leo.yan@linaro.org>
Subject: Re: [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields
Date: Fri, 18 Sep 2020 16:34:50 +0100	[thread overview]
Message-ID: <CAJ9a7VjMFbY1q_MnBsFNuVesxPiWQoHcGtZADneJuqBk02bbyw@mail.gmail.com> (raw)
In-Reply-To: <20200911084119.1080694-11-suzuki.poulose@arm.com>

Hi Suzuki,

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> Define the fields of the DEVARCH register for identifying
> a component as an ETMv4.x unit. Going forward, we use the
> DEVARCH register for the component identification, rather
> than the TRCIDR3.
>

TRCIDR1? - but either way, we are not using this for component ID. For
the AMBA path component ID is made using CID + PID + optionally if in
the table UCI - which includes DEVARCH.
TRCIDR1 is simply used to get the architecture version so we can be
sure the driver supports it, and can adjust behaviour for version
dependent elements.

> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x.c |  4 ++--
>  drivers/hwtracing/coresight/coresight-etm4x.h | 18 ++++++++++++++++++
>  2 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 40f8113191e0..34b27c26591b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -1598,8 +1598,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
>  static struct amba_cs_uci_id uci_id_etm4[] = {
>         {
>                 /*  ETMv4 UCI data */
> -               .devarch        = 0x47704a13,
> -               .devarch_mask   = 0xfff0ffff,
> +               .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
> +               .devarch_mask   = ETM_DEVARCH_ID_MASK,
>                 .devtype        = 0x00000013,

Perhaps a good time to change this to a #define constant too.
I assume that if the system access is going to use the coresight
architected registers for ID - it should use the same set as the AMBA
path - i.e. DEVARCH + DEVTYPE.

>         }
>  };
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 4044676d2385..29ffad6a5279 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -497,6 +497,24 @@
>                                          ETM_MODE_EXCL_KERN | \
>                                          ETM_MODE_EXCL_USER)
>
> +#define ETM_DEVARCH_ARCHITECT_MASK             GENMASK(31, 21)
> +#define ETM_DEVARCH_ARCHITECT_ARM              ((0x4 << 28) | (0b0111011 << 21))
> +#define ETM_DEVARCH_PRESENT                    BIT(20)
> +#define ETM_DEVARCH_REVISION_MASK              GENMASK(19, 16)
> +#define ETM_DEVARCH_REVISION_SHIFT             16
> +#define ETM_DEVARCH_ARCHID_MASK                        GENMASK(15, 0)
> +#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT      12
> +#define ETM_DEVARCH_ARCHID_ARCH_VER(x)         \
> +       (((x) & 0xfUL) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
> +#define ETM_DEVARCH_ARCHID_ARCH_PART(x)                ((x) & 0xfffUL)
> +#define ETM_DEVARCH_ARCHID_ETMv4               \
> +       (ETM_DEVARCH_ARCHID_ARCH_VER(4) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
> +
> +#define ETM_DEVARCH_ID_MASK                                            \
> +       (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
> +#define ETM_DEVARCH_ETMv4x_ARCH                                                \
> +       (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4 | ETM_DEVARCH_PRESENT)
> +
>  #define TRCSTATR_IDLE_BIT              0
>  #define TRCSTATR_PMSTABLE_BIT          1
>  #define ETM_DEFAULT_ADDR_COMP          0
> --
> 2.24.1
>

Regards


Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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  reply	other threads:[~2020-09-18 15:40 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-11  8:41 [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 01/19] coresight: Introduce device access abstraction Suzuki K Poulose
2020-09-18 15:33   ` Mike Leach
2020-09-11  8:41 ` [PATCH 02/19] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 03/19] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 04/19] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 05/19] coresight: Use device access layer for Software lock/unlock operations Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-18 15:52     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 06/19] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 07/19] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 08/19] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 09/19] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach [this message]
2020-09-22 10:20     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 11/19] coresight: etm4x: Check for OS and Software Lock Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:44     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:55     ` Suzuki K Poulose
2020-09-22 12:47       ` Mike Leach
2020-09-30 10:32         ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 13/19] coresight: etm4x: Clean up " Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 14/19] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:18     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 16/19] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 17/19] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-11  8:41 ` [PATCH 18/19] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-23 11:52     ` Suzuki K Poulose
2020-09-23 16:55       ` Mike Leach
2020-09-11  8:41 ` [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units Suzuki K Poulose
2020-09-11  8:41   ` Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-18 15:35     ` Mike Leach
2020-09-24  9:48     ` Suzuki K Poulose
2020-09-24  9:48       ` Suzuki K Poulose
2020-09-24 10:08       ` Mike Leach
2020-09-24 10:08         ` Mike Leach
2020-09-18 15:33 ` [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Mike Leach
2020-09-25  9:55   ` Suzuki K Poulose
2020-09-29 16:42     ` Mike Leach

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