From: Mike Leach <mike.leach@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Coresight ML <coresight@lists.linaro.org>,
Anshuman.Khandual@arm.com,
Mathieu Poirier <mathieu.poirier@linaro.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Leo Yan <leo.yan@linaro.org>
Subject: Re: [PATCH 05/19] coresight: Use device access layer for Software lock/unlock operations
Date: Fri, 18 Sep 2020 16:34:22 +0100 [thread overview]
Message-ID: <CAJ9a7ViTqruyTg608WhaH0a+c22evvjUrYyzfBn82ZyCtkNULg@mail.gmail.com> (raw)
In-Reply-To: <20200911084119.1080694-6-suzuki.poulose@arm.com>
Hi Suzuki,
On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> Convert CS_LOCK/UNLOCK operations to use the device access layer.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-catu.c | 12 +++--
> .../hwtracing/coresight/coresight-cpu-debug.c | 22 +++++++--
> .../hwtracing/coresight/coresight-cti-sysfs.c | 5 +-
> drivers/hwtracing/coresight/coresight-cti.c | 16 ++++---
> drivers/hwtracing/coresight/coresight-etb10.c | 19 ++++----
> .../coresight/coresight-etm3x-sysfs.c | 10 ++--
> drivers/hwtracing/coresight/coresight-etm3x.c | 26 +++++++----
> drivers/hwtracing/coresight/coresight-etm4x.c | 27 +++++++----
> .../hwtracing/coresight/coresight-funnel.c | 15 +++---
> drivers/hwtracing/coresight/coresight-priv.h | 9 ++--
> .../coresight/coresight-replicator.c | 16 ++++---
> drivers/hwtracing/coresight/coresight-stm.c | 46 ++++++++++++-------
> .../hwtracing/coresight/coresight-tmc-etf.c | 28 +++++++----
> .../hwtracing/coresight/coresight-tmc-etr.c | 16 ++++---
> drivers/hwtracing/coresight/coresight-tpiu.c | 9 ++--
> drivers/hwtracing/coresight/coresight.c | 8 ++--
> 16 files changed, 179 insertions(+), 105 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c
> index df2f45457e2b..9e96cda2f924 100644
> --- a/drivers/hwtracing/coresight/coresight-catu.c
> +++ b/drivers/hwtracing/coresight/coresight-catu.c
> @@ -456,10 +456,12 @@ static int catu_enable(struct coresight_device *csdev, void *data)
> {
> int rc;
> struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);
> + struct csdev_access *csa = &csdev->access;
>
> - CS_UNLOCK(catu_drvdata->base);
> + CS_UNLOCK(csa);
> rc = catu_enable_hw(catu_drvdata, data);
> - CS_LOCK(catu_drvdata->base);
> + CS_LOCK(csa);
> +
> return rc;
> }
>
> @@ -484,10 +486,12 @@ static int catu_disable(struct coresight_device *csdev, void *__unused)
> {
> int rc;
> struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);
> + struct csdev_access *csa = &csdev->access;
>
> - CS_UNLOCK(catu_drvdata->base);
> + CS_UNLOCK(csa);
> rc = catu_disable_hw(catu_drvdata);
> - CS_LOCK(catu_drvdata->base);
> + CS_LOCK(csa);
> +
> return rc;
> }
>
> diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
> index 96544b348c27..5d5619284866 100644
> --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c
> +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
> @@ -108,6 +108,20 @@ static bool debug_enable;
> module_param_named(enable, debug_enable, bool, 0600);
> MODULE_PARM_DESC(enable, "Control to enable coresight CPU debug functionality");
>
> +static inline void coresight_debug_lock(struct debug_drvdata *drvdata)
> +{
> + struct csdev_access dummy = CSDEV_ACCESS_IOMEM(drvdata->base);
> +
> + CS_LOCK(&dummy);
> +}
> +
> +static void coresight_debug_unlock(struct debug_drvdata *drvdata)
> +{
> + struct csdev_access dummy = CSDEV_ACCESS_IOMEM(drvdata->base);
> +
> + CS_UNLOCK(&dummy);
> +}
> +
Perhaps it's just me, but whenever I see "dummy" in code, I
immediately think this is stubbed out and doing nothing.
> static void debug_os_unlock(struct debug_drvdata *drvdata)
> {
> /* Unlocks the debug registers */
> @@ -191,7 +205,7 @@ static void debug_read_regs(struct debug_drvdata *drvdata)
> {
> u32 save_edprcr;
>
> - CS_UNLOCK(drvdata->base);
> + coresight_debug_unlock(drvdata);
>
> /* Unlock os lock */
> debug_os_unlock(drvdata);
> @@ -238,7 +252,7 @@ static void debug_read_regs(struct debug_drvdata *drvdata)
> /* Restore EDPRCR register */
> writel_relaxed(save_edprcr, drvdata->base + EDPRCR);
>
> - CS_LOCK(drvdata->base);
> + coresight_debug_lock(drvdata);
> }
>
> #ifdef CONFIG_64BIT
> @@ -326,13 +340,13 @@ static void debug_init_arch_data(void *info)
> u32 mode, pcsr_offset;
> u32 eddevid, eddevid1;
>
> - CS_UNLOCK(drvdata->base);
> + coresight_debug_unlock(drvdata);
>
> /* Read device info */
> eddevid = readl_relaxed(drvdata->base + EDDEVID);
> eddevid1 = readl_relaxed(drvdata->base + EDDEVID1);
>
> - CS_LOCK(drvdata->base);
> + coresight_debug_lock(drvdata);
>
> /* Parse implementation feature */
> mode = eddevid & EDDEVID_PCSAMPLE_MODE;
> diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> index 392757f3a019..2208b5191042 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> @@ -220,14 +220,15 @@ static ssize_t cti_reg32_show(struct device *dev, char *buf,
> u32 val = 0;
> struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct cti_config *config = &drvdata->config;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> spin_lock(&drvdata->spinlock);
> if ((reg_offset >= 0) && cti_active(config)) {
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
> val = readl_relaxed(drvdata->base + reg_offset);
> if (pcached_val)
> *pcached_val = val;
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> } else if (pcached_val) {
> val = *pcached_val;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c
> index e07e15593dd8..f921a9eeba81 100644
> --- a/drivers/hwtracing/coresight/coresight-cti.c
> +++ b/drivers/hwtracing/coresight/coresight-cti.c
> @@ -60,10 +60,11 @@ DEFINE_CORESIGHT_DEVLIST(cti_sys_devs, "cti_sys");
> /* write set of regs to hardware - call with spinlock claimed */
> void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
> {
> + struct csdev_access *csa = &drvdata->csdev->access;
> struct cti_config *config = &drvdata->config;
> int i;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> /* disable CTI before writing registers */
> writel_relaxed(0, drvdata->base + CTICONTROL);
> @@ -83,7 +84,7 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
> /* re-enable CTI */
> writel_relaxed(1, drvdata->base + CTICONTROL);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> /* write regs to hardware and enable */
> @@ -155,6 +156,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata)
> struct cti_config *config = &drvdata->config;
> struct device *dev = &drvdata->csdev->dev;
> struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &csdev->access;
>
> spin_lock(&drvdata->spinlock);
>
> @@ -166,14 +168,14 @@ static int cti_disable_hw(struct cti_drvdata *drvdata)
> if (!config->hw_enabled || !config->hw_powered)
> goto cti_not_disabled;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> /* disable CTI */
> writel_relaxed(0, drvdata->base + CTICONTROL);
> config->hw_enabled = false;
>
> coresight_disclaim_device_unlocked(csdev);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> spin_unlock(&drvdata->spinlock);
> pm_runtime_put(dev);
> return 0;
> @@ -186,9 +188,11 @@ static int cti_disable_hw(struct cti_drvdata *drvdata)
>
> void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
> writel_relaxed(value, drvdata->base + offset);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> void cti_write_intack(struct device *dev, u32 ackval)
> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
> index 5b0d1c1a0442..b41cd73585cc 100644
> --- a/drivers/hwtracing/coresight/coresight-etb10.c
> +++ b/drivers/hwtracing/coresight/coresight-etb10.c
> @@ -106,8 +106,9 @@ static void __etb_enable_hw(struct etb_drvdata *drvdata)
> {
> int i;
> u32 depth;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> depth = drvdata->buffer_depth;
> /* reset write RAM pointer address */
> @@ -127,7 +128,7 @@ static void __etb_enable_hw(struct etb_drvdata *drvdata)
> /* ETB trace capture enable */
> writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static int etb_enable_hw(struct etb_drvdata *drvdata)
> @@ -253,7 +254,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata)
> struct device *dev = &drvdata->csdev->dev;
> struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
> /* stop formatter when a stop has completed */
> @@ -276,7 +277,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata)
> "timeout while waiting for Formatter to Stop\n");
> }
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void etb_dump_hw(struct etb_drvdata *drvdata)
> @@ -288,8 +289,9 @@ static void etb_dump_hw(struct etb_drvdata *drvdata)
> u32 read_ptr, write_ptr;
> u32 frame_off, frame_endoff;
> struct device *dev = &drvdata->csdev->dev;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
> write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
> @@ -337,7 +339,7 @@ static void etb_dump_hw(struct etb_drvdata *drvdata)
>
> writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void etb_disable_hw(struct etb_drvdata *drvdata)
> @@ -435,6 +437,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev,
> unsigned long offset, to_read = 0, flags;
> struct cs_buffers *buf = sink_config;
> struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> if (!buf)
> return 0;
> @@ -448,7 +451,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev,
> goto out;
>
> __etb_disable_hw(drvdata);
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> /* unit is in words, not bytes */
> read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
> @@ -563,7 +566,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev,
> handle->head += to_read;
>
> __etb_enable_hw(drvdata);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> out:
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> index e8c7649f123e..3e379b3fcdfd 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> @@ -47,14 +47,15 @@ static ssize_t etmsr_show(struct device *dev,
> {
> unsigned long flags, val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> pm_runtime_get_sync(dev->parent);
> spin_lock_irqsave(&drvdata->spinlock, flags);
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> val = etm_readl(drvdata, ETMSR);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> pm_runtime_put(dev->parent);
>
> @@ -939,6 +940,7 @@ static ssize_t seq_curr_state_show(struct device *dev,
> unsigned long val, flags;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct etm_config *config = &drvdata->config;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> if (!local_read(&drvdata->mode)) {
> val = config->seq_curr_state;
> @@ -948,9 +950,9 @@ static ssize_t seq_curr_state_show(struct device *dev,
> pm_runtime_get_sync(dev->parent);
> spin_lock_irqsave(&drvdata->spinlock, flags);
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
> val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> pm_runtime_put(dev->parent);
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
> index a7c791f15da7..debb4dc15527 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x.c
> @@ -361,8 +361,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> u32 etmcr;
> struct etm_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> rc = coresight_claim_device_unlocked(csdev);
> if (rc)
> @@ -424,7 +425,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> etm_clr_prog(drvdata);
>
> done:
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n",
> drvdata->cpu, rc);
> @@ -457,10 +458,12 @@ int etm_get_trace_id(struct etm_drvdata *drvdata)
> unsigned long flags;
> int trace_id = -1;
> struct device *etm_dev;
> + struct csdev_access *csa;
>
> if (!drvdata)
> goto out;
>
> + csa = &drvdata->csdev->access;
> etm_dev = drvdata->csdev->dev.parent;
> if (!local_read(&drvdata->mode))
> return drvdata->traceid;
> @@ -469,9 +472,9 @@ int etm_get_trace_id(struct etm_drvdata *drvdata)
>
> spin_lock_irqsave(&drvdata->spinlock, flags);
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
> trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> pm_runtime_put(etm_dev);
> @@ -570,8 +573,9 @@ static void etm_disable_hw(void *info)
> struct etm_drvdata *drvdata = info;
> struct etm_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
> etm_set_prog(drvdata);
>
> /* Read back sequencer and counters for post trace analysis */
> @@ -583,7 +587,7 @@ static void etm_disable_hw(void *info)
> etm_set_pwrdwn(drvdata);
> coresight_disclaim_device_unlocked(csdev);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> dev_dbg(&drvdata->csdev->dev,
> "cpu: %d disable smp call done\n", drvdata->cpu);
> @@ -592,11 +596,12 @@ static void etm_disable_hw(void *info)
> static void etm_disable_perf(struct coresight_device *csdev)
> {
> struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
> return;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> /* Setting the prog bit disables tracing immediately */
> etm_set_prog(drvdata);
> @@ -608,7 +613,7 @@ static void etm_disable_perf(struct coresight_device *csdev)
> etm_set_pwrdwn(drvdata);
> coresight_disclaim_device_unlocked(csdev);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void etm_disable_sysfs(struct coresight_device *csdev)
> @@ -739,11 +744,12 @@ static void etm_init_arch_data(void *info)
> u32 etmidr;
> u32 etmccr;
> struct etm_drvdata *drvdata = info;
> + struct csdev_access csa = CSDEV_ACCESS_IOMEM(drvdata->base);
>
> /* Make sure all registers are accessible */
> etm_os_unlock(drvdata);
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(&csa);
>
> /* First dummy read */
> (void)etm_readl(drvdata, ETMPDSR);
> @@ -776,7 +782,7 @@ static void etm_init_arch_data(void *info)
>
> etm_set_pwrdwn(drvdata);
> etm_clr_pwrup(drvdata);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(&csa);
> }
>
> static void etm_init_trace_id(struct etm_drvdata *drvdata)
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 5b81d6f12027..40d242d14ffa 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -111,7 +111,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> struct device *etm_dev = &csdev->dev;
> struct csdev_access *csa = &csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> etm4_os_unlock(drvdata);
>
> @@ -222,7 +222,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> isb();
>
> done:
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
> drvdata->cpu, rc);
> @@ -479,7 +479,7 @@ static void etm4_disable_hw(void *info)
> struct csdev_access *csa = &csdev->access;
> int i;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> if (!drvdata->skip_power_up) {
> /* power can be removed from the trace unit now */
> @@ -521,7 +521,7 @@ static void etm4_disable_hw(void *info)
>
> coresight_disclaim_device_unlocked(csdev);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> dev_dbg(&drvdata->csdev->dev,
> "cpu: %d disable smp call done\n", drvdata->cpu);
> @@ -626,11 +626,12 @@ static void etm4_init_arch_data(void *info)
> u32 etmidr5;
> struct etmv4_drvdata *drvdata = info;
> int i;
> + struct csdev_access csa = CSDEV_ACCESS_IOMEM(drvdata->base);
>
> /* Make sure all registers are accessible */
> etm4_os_unlock(drvdata);
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(&csa);
>
> /* find all capabilities of the tracing unit */
> etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
> @@ -784,7 +785,7 @@ static void etm4_init_arch_data(void *info)
> drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
> /* NUMCNTR, bits[30:28] number of counters available for tracing */
> drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(&csa);
> }
>
> /* Set ELx trace filter access in the TRCVICTLR register */
> @@ -1165,7 +1166,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> dsb(sy);
> isb();
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> /* Lock the OS lock to disable trace and external debugger access */
> etm4_os_lock(drvdata);
> @@ -1273,7 +1274,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> drvdata->base + TRCPDCR);
>
> out:
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> return ret;
> }
>
> @@ -1281,8 +1282,14 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> {
> int i;
> struct etmv4_save_state *state = drvdata->save_state;
> + struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa;
> +
> + if (WARN_ON(!csdev))
> + return;
>
> - CS_UNLOCK(drvdata->base);
> + csa = &csdev->access;
> + CS_UNLOCK(csa);
>
> writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
>
> @@ -1374,7 +1381,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>
> /* Unlock the OS lock to re-enable trace and external debug access */
> etm4_os_unlock(drvdata);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
> diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
> index b3f98ce51a68..5b74dd0d0652 100644
> --- a/drivers/hwtracing/coresight/coresight-funnel.c
> +++ b/drivers/hwtracing/coresight/coresight-funnel.c
> @@ -53,8 +53,9 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port)
> u32 functl;
> int rc = 0;
> struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL);
> /* Claim the device only when we enable the first slave */
> @@ -70,7 +71,7 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port)
> writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL);
> writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL);
> done:
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> return rc;
> }
>
> @@ -103,8 +104,9 @@ static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata,
> {
> u32 functl;
> struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL);
> functl &= ~(1 << inport);
> @@ -114,7 +116,7 @@ static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata,
> if (!(functl & FUNNEL_ENSx_MASK))
> coresight_disclaim_device_unlocked(csdev);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void funnel_disable(struct coresight_device *csdev, int inport,
> @@ -174,10 +176,11 @@ static DEVICE_ATTR_RW(priority);
> static u32 get_funnel_ctrl_hw(struct funnel_drvdata *drvdata)
> {
> u32 functl;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
> functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> return functl;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> index f2dc625ea585..a87ce11a0ea6 100644
> --- a/drivers/hwtracing/coresight/coresight-priv.h
> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> @@ -108,19 +108,20 @@ static inline void coresight_insert_barrier_packet(void *buf)
> }
>
>
> -static inline void CS_LOCK(void __iomem *addr)
> +static inline void CS_LOCK(struct csdev_access *csa)
> {
> do {
> /* Wait for things to settle */
> mb();
> - writel_relaxed(0x0, addr + CORESIGHT_LAR);
> + csdev_access_relaxed_write32(csa, 0x0, CORESIGHT_LAR);
> } while (0);
> }
>
> -static inline void CS_UNLOCK(void __iomem *addr)
> +static inline void CS_UNLOCK(struct csdev_access *csa)
> {
> do {
> - writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
> + csdev_access_relaxed_write32(csa, CORESIGHT_UNLOCK,
> + CORESIGHT_LAR);
> /* Make sure everyone has seen this */
> mb();
> } while (0);
> diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
> index b8361bb808f1..b9b40822f3aa 100644
> --- a/drivers/hwtracing/coresight/coresight-replicator.c
> +++ b/drivers/hwtracing/coresight/coresight-replicator.c
> @@ -46,12 +46,12 @@ struct replicator_drvdata {
> static void dynamic_replicator_reset(struct replicator_drvdata *drvdata)
> {
> struct coresight_device *csdev = drvdata->csdev;
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &csdev->access;
>
> if (WARN_ON(!csdev))
> return;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> if (!coresight_claim_device_unlocked(csdev)) {
> writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
> @@ -59,7 +59,7 @@ static void dynamic_replicator_reset(struct replicator_drvdata *drvdata)
> coresight_disclaim_device_unlocked(csdev);
> }
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> /*
> @@ -77,8 +77,9 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata,
> int rc = 0;
> u32 id0val, id1val;
> struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> id0val = readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0);
> id1val = readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1);
> @@ -113,7 +114,7 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata,
> writel_relaxed(id1val, drvdata->base + REPLICATOR_IDFILTER1);
> }
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> return rc;
> }
> @@ -148,6 +149,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata,
> {
> u32 reg;
> struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &csdev->access;
>
> switch (outport) {
> case 0:
> @@ -161,7 +163,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata,
> return;
> }
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> /* disable the flow of ATB data through port */
> writel_relaxed(0xff, drvdata->base + reg);
> @@ -169,7 +171,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata,
> if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
> (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))
> coresight_disclaim_device_unlocked(csdev);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void replicator_disable(struct coresight_device *csdev, int inport,
> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
> index 9667c5c8f433..ddf90c76284c 100644
> --- a/drivers/hwtracing/coresight/coresight-stm.c
> +++ b/drivers/hwtracing/coresight/coresight-stm.c
> @@ -148,7 +148,9 @@ struct stm_drvdata {
>
> static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
>
> writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
> writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
> @@ -157,29 +159,33 @@ static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
> 0x04, /* Error detection on event tracing */
> drvdata->base + STMHEMCR);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void stm_port_enable_hw(struct stm_drvdata *drvdata)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
> /* ATB trigger enable on direct writes to TRIG locations */
> writel_relaxed(0x10,
> drvdata->base + STMSPTRIGCSR);
> writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
> writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void stm_enable_hw(struct stm_drvdata *drvdata)
> {
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> if (drvdata->stmheer)
> stm_hwevent_enable_hw(drvdata);
>
> stm_port_enable_hw(drvdata);
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> /* 4096 byte between synchronisation packets */
> writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
> @@ -188,7 +194,7 @@ static void stm_enable_hw(struct stm_drvdata *drvdata)
> 0x01), /* global STM enable */
> drvdata->base + STMTCSR);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static int stm_enable(struct coresight_device *csdev,
> @@ -218,36 +224,41 @@ static int stm_enable(struct coresight_device *csdev,
>
> static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
>
> writel_relaxed(0x0, drvdata->base + STMHEMCR);
> writel_relaxed(0x0, drvdata->base + STMHEER);
> writel_relaxed(0x0, drvdata->base + STMHETER);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void stm_port_disable_hw(struct stm_drvdata *drvdata)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
>
> writel_relaxed(0x0, drvdata->base + STMSPER);
> writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void stm_disable_hw(struct stm_drvdata *drvdata)
> {
> u32 val;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> val = readl_relaxed(drvdata->base + STMTCSR);
> val &= ~0x1; /* clear global STM enable [0] */
> writel_relaxed(val, drvdata->base + STMTCSR);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> stm_port_disable_hw(drvdata);
> if (drvdata->stmheer)
> @@ -538,6 +549,8 @@ static ssize_t port_select_store(struct device *dev,
> const char *buf, size_t size)
> {
> struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> unsigned long val, stmsper;
> int ret = 0;
>
> @@ -549,13 +562,13 @@ static ssize_t port_select_store(struct device *dev,
> drvdata->stmspscr = val;
>
> if (local_read(&drvdata->mode)) {
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
> /* Process as per ARM's TRM recommendation */
> stmsper = readl_relaxed(drvdata->base + STMSPER);
> writel_relaxed(0x0, drvdata->base + STMSPER);
> writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
> writel_relaxed(stmsper, drvdata->base + STMSPER);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
> spin_unlock(&drvdata->spinlock);
>
> @@ -585,6 +598,7 @@ static ssize_t port_enable_store(struct device *dev,
> const char *buf, size_t size)
> {
> struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct csdev_access *csa = &drvdata->csdev->access;
> unsigned long val;
> int ret = 0;
>
> @@ -596,9 +610,9 @@ static ssize_t port_enable_store(struct device *dev,
> drvdata->stmsper = val;
>
> if (local_read(&drvdata->mode)) {
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
> writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
> spin_unlock(&drvdata->spinlock);
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index 610a494efbbc..05f65bd08cb1 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -18,7 +18,9 @@ static int tmc_set_etf_buffer(struct coresight_device *csdev,
>
> static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
>
> /* Wait for TMCSReady bit to be set */
> tmc_wait_for_tmcready(drvdata);
> @@ -32,7 +34,7 @@ static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
> writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
> tmc_enable_hw(drvdata);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
> @@ -71,7 +73,9 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
>
> static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
>
> tmc_flush_and_stop(drvdata);
> /*
> @@ -82,7 +86,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> tmc_etb_dump_hw(drvdata);
> tmc_disable_hw(drvdata);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> @@ -93,7 +97,9 @@ static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
>
> static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
>
> /* Wait for TMCSReady bit to be set */
> tmc_wait_for_tmcready(drvdata);
> @@ -104,7 +110,7 @@ static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
> writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
> tmc_enable_hw(drvdata);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
> @@ -121,13 +127,14 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
> static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
> {
> struct coresight_device *csdev = drvdata->csdev;
> + struct csdev_access *csa = &csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> tmc_flush_and_stop(drvdata);
> tmc_disable_hw(drvdata);
> coresight_disclaim_device_unlocked(csdev);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> /*
> @@ -452,6 +459,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
> unsigned long offset, to_read = 0, flags;
> struct cs_buffers *buf = sink_config;
> struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + struct csdev_access *csa = &csdev->access;
>
> if (!buf)
> return 0;
> @@ -466,7 +474,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
> if (atomic_read(csdev->refcnt) != 1)
> goto out;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> tmc_flush_and_stop(drvdata);
>
> @@ -551,7 +559,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
> if (buf->snapshot)
> handle->head += to_read;
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> out:
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 1aae2405041d..d33b93deefcb 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -952,8 +952,9 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> {
> u32 axictl, sts;
> struct etr_buf *etr_buf = drvdata->etr_buf;
> + struct csdev_access *csa = &drvdata->csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> /* Wait for TMCSReady bit to be set */
> tmc_wait_for_tmcready(drvdata);
> @@ -995,7 +996,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
> tmc_enable_hw(drvdata);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> }
>
> static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
> @@ -1094,7 +1095,9 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)
>
> static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> {
> - CS_UNLOCK(drvdata->base);
> + struct csdev_access *csa = &drvdata->csdev->access;
> +
> + CS_UNLOCK(csa);
>
> tmc_flush_and_stop(drvdata);
> /*
> @@ -1106,7 +1109,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
>
> tmc_disable_hw(drvdata);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
>
> }
>
> @@ -1482,6 +1485,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
> struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> struct etr_perf_buffer *etr_perf = config;
> struct etr_buf *etr_buf = etr_perf->etr_buf;
> + struct csdev_access *csa = &csdev->access;
>
> spin_lock_irqsave(&drvdata->spinlock, flags);
>
> @@ -1497,12 +1501,12 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
> goto out;
> }
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(csa);
>
> tmc_flush_and_stop(drvdata);
> tmc_sync_etr_buf(drvdata);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(csa);
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
>
> lost = etr_buf->full;
> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
> index 7dd8300cf6be..dd38be482c21 100644
> --- a/drivers/hwtracing/coresight/coresight-tpiu.c
> +++ b/drivers/hwtracing/coresight/coresight-tpiu.c
> @@ -62,11 +62,11 @@ struct tpiu_drvdata {
>
> static void tpiu_enable_hw(struct csdev_access *csa)
> {
> - CS_UNLOCK(csa->base);
> + CS_UNLOCK(csa);
>
> /* TODO: fill this up */
>
> - CS_LOCK(csa->base);
> + CS_LOCK(csa);
> }
>
> static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused)
> @@ -79,7 +79,8 @@ static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused)
>
> static void tpiu_disable_hw(struct csdev_access *csa)
> {
> - CS_UNLOCK(csa->base);
> +
> + CS_UNLOCK(csa);
>
> /* Clear formatter and stop on flush */
> csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR);
> @@ -90,7 +91,7 @@ static void tpiu_disable_hw(struct csdev_access *csa)
> /* Wait for formatter to stop */
> coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
>
> - CS_LOCK(csa->base);
> + CS_LOCK(csa);
> }
>
> static int tpiu_disable(struct coresight_device *csdev)
> diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
> index 7545a22769c4..64353ee0a2bc 100644
> --- a/drivers/hwtracing/coresight/coresight.c
> +++ b/drivers/hwtracing/coresight/coresight.c
> @@ -192,9 +192,9 @@ int coresight_claim_device(struct coresight_device *csdev)
> if (WARN_ON(!csdev))
> return -EINVAL;
>
> - CS_UNLOCK(csdev->access.base);
> + CS_UNLOCK(&csdev->access);
> rc = coresight_claim_device_unlocked(csdev);
> - CS_LOCK(csdev->access.base);
> + CS_LOCK(&csdev->access);
>
> return rc;
> }
> @@ -225,9 +225,9 @@ void coresight_disclaim_device(struct coresight_device *csdev)
> if (WARN_ON(!csdev))
> return;
>
> - CS_UNLOCK(csdev->access.base);
> + CS_UNLOCK(&csdev->access);
> coresight_disclaim_device_unlocked(csdev);
> - CS_LOCK(csdev->access.base);
> + CS_LOCK(&csdev->access);
> }
>
> /* enable or disable an associated CTI device of the supplied CS device */
> --
> 2.24.1
>
Reviewed by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
_______________________________________________
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next prev parent reply other threads:[~2020-09-18 15:38 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-11 8:41 [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 01/19] coresight: Introduce device access abstraction Suzuki K Poulose
2020-09-18 15:33 ` Mike Leach
2020-09-11 8:41 ` [PATCH 02/19] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 03/19] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 04/19] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 05/19] coresight: Use device access layer for Software lock/unlock operations Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach [this message]
2020-09-18 15:52 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 06/19] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 07/19] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 08/19] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 09/19] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-22 10:20 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 11/19] coresight: etm4x: Check for OS and Software Lock Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 10:44 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 10:55 ` Suzuki K Poulose
2020-09-22 12:47 ` Mike Leach
2020-09-30 10:32 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 13/19] coresight: etm4x: Clean up " Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 10:59 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 14/19] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 11:18 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 16/19] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 11:59 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 17/19] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-11 8:41 ` [PATCH 18/19] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-23 11:52 ` Suzuki K Poulose
2020-09-23 16:55 ` Mike Leach
2020-09-11 8:41 ` [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units Suzuki K Poulose
2020-09-11 8:41 ` Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-18 15:35 ` Mike Leach
2020-09-24 9:48 ` Suzuki K Poulose
2020-09-24 9:48 ` Suzuki K Poulose
2020-09-24 10:08 ` Mike Leach
2020-09-24 10:08 ` Mike Leach
2020-09-18 15:33 ` [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Mike Leach
2020-09-25 9:55 ` Suzuki K Poulose
2020-09-29 16:42 ` Mike Leach
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