Re: [PATCH v9 0/6] Add support for H6 PWM

["Clément Péron" <peron.clem@gmail.com>]

Hi Uwe, Thierry,

On Sun, 24 Nov 2019 at 18:29, Clément Péron <peron.clem@gmail.com> wrote:
>
> Hi,
>
> This is a rework of Jernej's previous work[1] taking account all the
> previous remarks.

Is this series ok for you?
FYI the device-tree bindings is merged in sunxi-next.

Thanks,
Clement

>
> Bindings is still strict but probe in the driver are now optionnals.
>
> If someone could confirm that the PWM is not broken, as my board
> doesn't output it.
>
> Thanks,
> Clément
>
> Jernej's cover:
> Allwinner H6 SoC has PWM core which is basically the same as that found
> in A20, it's just depends on additional bus clock and reset line.
>
> This series adds support for it and extends PWM driver functionality in
> a way that it's now possible to bypass whole core and output PWM source
> clock directly as a PWM signal. This functionality is needed by AC200
> chip, which is bundled in same physical package as H6 SoC, to serve as a
> clock source of 24 MHz. AC200 clock input pin is bonded internally to
> the second PWM channel.
>
> I would be grateful if anyone can test this patch series for any kind of
> regression on other SoCs.
>
> [1]: https://patchwork.kernel.org/cover/11061737/
>
> Changes in v9:
>  - print error code in error message
>  - no capital letter to keep coherency
>
> Changes in v8:
>  - Display error return code
>  - split commit
>  - bypass is false if unsupported
>  - return instead of goto
>
> Changes in v7:
>  - Fix indent in Yaml bindings
>
> Changes in v6:
>  - Update git commit log
>  - Distinguish error message
>
> Changes in v5:
>  - Move bypass calculation to pwm_calculate
>  - Split mod_clock fallback from bus_clk probe
>  - Update comment
>  - Move my SoB after acked-by/reviewed-by
>
> Changes in v4:
>  - item description in correct order and add a blank line
>  - use %pe for printing PTR_ERR
>  - don't print error when it's an EPROBE_DEFER
>  - change output clock bypass formula to match PWM policy
>
> Changes in v3:
>  - Documentation update to allow one clock without name
>  - Change reset optional to shared
>  - If reset probe failed return an error
>  - Remove old clock probe
>  - Update bypass enabled formula
>
> Changes in v2:
>  - Remove allOf in Documentation
>  - Add H6 example in Documentation
>  - Change clock name from "pwm" to "mod"
>  - Change reset quirk to optional probe
>  - Change bus_clock quirk to optional probe
>  - Add limitation comment about mod_clk_output
>  - Add quirk for mod_clk_output
>  - Change bypass formula
>
> Clément Péron (2):
>   pwm: sun4i: Prefer "mod" clock to unnamed
>   pwm: sun4i: Always calculate params when applying new parameters
>
> Jernej Skrabec (4):
>   pwm: sun4i: Add an optional probe for reset line
>   pwm: sun4i: Add an optional probe for bus clock
>   pwm: sun4i: Add support to output source clock directly
>   pwm: sun4i: Add support for H6 PWM
>
>  drivers/pwm/pwm-sun4i.c | 187 +++++++++++++++++++++++++++++++++-------
>  1 file changed, 156 insertions(+), 31 deletions(-)
>
> --
> 2.20.1
>