[PATCH 0/3] drm/i915: Trickle feed bits

[PATCH 0/3] drm/i915: Trickle feed bits

[ville.syrjala]

This series tries to get the trickle feed settings corrected for all gen4+.

Note that I've only compile tested the gen4 and vlv bits as I don't have
either type of machine set up at the moment. The g4x patch (well, v1 actually)
was smoke tested on real hardware at some point.

[PATCH v2 1/3] drm/i915: Disable primary plane trickle feed for g4x

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The docs say that the trickle feed disable bit is present (for primary
planes only, not video sprites) on CTG, and that it must be set
for ELK. Just set it for all g4x chipsets.

v2: Do it in init_clock_gating too

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 drivers/gpu/drm/i915/intel_pm.c      | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 684ab64..c8b033a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2041,6 +2041,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 			dspcntr &= ~DISPPLANE_TILED;
 	}
 
+	if (IS_G4X(dev))
+		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+
 	I915_WRITE(reg, dspcntr);
 
 	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a90cf3..cf0f658 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4390,6 +4390,7 @@ static void g4x_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dspclk_gate;
+	int pipe;
 
 	I915_WRITE(RENCLK_GATE_D1, 0);
 	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@@ -4406,6 +4407,14 @@ static void g4x_init_clock_gating(struct drm_device *dev)
 	/* WaDisableRenderCachePipelinedFlush */
 	I915_WRITE(CACHE_MODE_0,
 		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
+
+	for_each_pipe(pipe) {
+		I915_WRITE(DSPCNTR(pipe),
+			   I915_READ(DSPCNTR(pipe)) |
+			   DISPPLANE_TRICKLE_FEED_DISABLE);
+		intel_flush_display_plane(dev_priv, pipe);
+	}
+
 }
 
 static void crestline_init_clock_gating(struct drm_device *dev)
-- 
1.8.1.5

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Re: [PATCH v2 1/3] drm/i915: Disable primary plane trickle feed for g4x

[Ville Syrjälä]

On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The docs say that the trickle feed disable bit is present (for primary
> planes only, not video sprites) on CTG, and that it must be set
> for ELK. Just set it for all g4x chipsets.
> 
> v2: Do it in init_clock_gating too

Actually I just noticed that we don't set up this stuff in
ironlake_init_clock_gating() either. Any opinions whether I should just
kill the per-plane trickle feed stuff from *_init_clock_gating(), or
should I add it to ironlake_init_clock_gating() as well?

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c      | 9 +++++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 684ab64..c8b033a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2041,6 +2041,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>  			dspcntr &= ~DISPPLANE_TILED;
>  	}
>  
> +	if (IS_G4X(dev))
> +		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> +
>  	I915_WRITE(reg, dspcntr);
>  
>  	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8a90cf3..cf0f658 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4390,6 +4390,7 @@ static void g4x_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t dspclk_gate;
> +	int pipe;
>  
>  	I915_WRITE(RENCLK_GATE_D1, 0);
>  	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> @@ -4406,6 +4407,14 @@ static void g4x_init_clock_gating(struct drm_device *dev)
>  	/* WaDisableRenderCachePipelinedFlush */
>  	I915_WRITE(CACHE_MODE_0,
>  		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
> +
> +	for_each_pipe(pipe) {
> +		I915_WRITE(DSPCNTR(pipe),
> +			   I915_READ(DSPCNTR(pipe)) |
> +			   DISPPLANE_TRICKLE_FEED_DISABLE);
> +		intel_flush_display_plane(dev_priv, pipe);
> +	}
> +
>  }
>  
>  static void crestline_init_clock_gating(struct drm_device *dev)
> -- 
> 1.8.1.5

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH v2 1/3] drm/i915: Disable primary plane trickle feed for g4x

[Daniel Vetter]

On Tue, May 21, 2013 at 2:35 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> The docs say that the trickle feed disable bit is present (for primary
>> planes only, not video sprites) on CTG, and that it must be set
>> for ELK. Just set it for all g4x chipsets.
>>
>> v2: Do it in init_clock_gating too
>
> Actually I just noticed that we don't set up this stuff in
> ironlake_init_clock_gating() either. Any opinions whether I should just
> kill the per-plane trickle feed stuff from *_init_clock_gating(), or
> should I add it to ironlake_init_clock_gating() as well?

This is a bit a crazy topic since conceptually it ties into the
wm/pipe-config stuff. And fastboot will make this stuff rather
interesting ... I expect that we'll eventually end up with a
post_modeset_fixup stage to patch up all these little bits&pieces -
fastboot would only call that one if possible.

For now I'm not sure what to do though. Ideas highly welcome ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH v2 1/3] drm/i915: Disable primary plane trickle feed for g4x

[Ville Syrjälä]

On Tue, May 21, 2013 at 02:52:24PM +0200, Daniel Vetter wrote:
> On Tue, May 21, 2013 at 2:35 PM, Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> > On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrjala@linux.intel.com wrote:
> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> The docs say that the trickle feed disable bit is present (for primary
> >> planes only, not video sprites) on CTG, and that it must be set
> >> for ELK. Just set it for all g4x chipsets.
> >>
> >> v2: Do it in init_clock_gating too
> >
> > Actually I just noticed that we don't set up this stuff in
> > ironlake_init_clock_gating() either. Any opinions whether I should just
> > kill the per-plane trickle feed stuff from *_init_clock_gating(), or
> > should I add it to ironlake_init_clock_gating() as well?
> 
> This is a bit a crazy topic since conceptually it ties into the
> wm/pipe-config stuff. And fastboot will make this stuff rather
> interesting ... I expect that we'll eventually end up with a
> post_modeset_fixup stage to patch up all these little bits&pieces -
> fastboot would only call that one if possible.

I'd expect we do at least a set_base w/ fastboot, which would take care
of the per-plane trickle feed bit. But I don't care much either way at
this point. I'll post a quick patch for ironlake_init_clock_gating()
just to keep these things at least somewhat consistent...

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH v2 1/3] drm/i915: Disable primary plane trickle feed for g4x

[Chris Wilson]

On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The docs say that the trickle feed disable bit is present (for primary
> planes only, not video sprites) on CTG, and that it must be set
> for ELK. Just set it for all g4x chipsets.
> 
> v2: Do it in init_clock_gating too
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

The bspec says this bit is ignored on Cantiga, so this should be
harmless there.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[PATCH 2/3] drm/i915: Disable trickle feed via MI_ARB_STATE for gen4

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

According to BSpec, trickle feed should be disabled for BW and
mobile CL. Those constraints seem to match all of our gen4 chipsets.

Trickle feed is disabled via the MI_ARB_STATE register instead of
per plane controls on gen4.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cf0f658..5690b3d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4426,6 +4426,8 @@ static void crestline_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(DSPCLK_GATE_D, 0);
 	I915_WRITE(RAMCLK_GATE_D, 0);
 	I915_WRITE16(DEUC, 0);
+	I915_WRITE(MI_ARB_STATE,
+		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
 }
 
 static void broadwater_init_clock_gating(struct drm_device *dev)
@@ -4438,6 +4440,8 @@ static void broadwater_init_clock_gating(struct drm_device *dev)
 		   I965_ISC_CLOCK_GATE_DISABLE |
 		   I965_FBC_CLOCK_GATE_DISABLE);
 	I915_WRITE(RENCLK_GATE_D2, 0);
+	I915_WRITE(MI_ARB_STATE,
+		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
 }
 
 static void gen3_init_clock_gating(struct drm_device *dev)
-- 
1.8.1.5

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Re: [PATCH 2/3] drm/i915: Disable trickle feed via MI_ARB_STATE for gen4

[Chris Wilson]

On Tue, May 21, 2013 at 03:28:33PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> According to BSpec, trickle feed should be disabled for BW and
> mobile CL. Those constraints seem to match all of our gen4 chipsets.
> 
> Trickle feed is disabled via the MI_ARB_STATE register instead of
> per plane controls on gen4.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Foolish me overlooking this patch earlier.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[PATCH 3/3] drm/i915: Try harder to disable trickle feed on VLV

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The specs are a bit unclear whether the per-plane trickle feed disable
control exists on VLV. There is another trickle feed disable control
in the MI_ARB register.

Based on some quick register dumps from Jani's VLV machine, the per-plane
bits don't actually seem to exist, so I'm guessing we should use the
MI_ARB method instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 8 +-------
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55caedb..942699a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1321,6 +1321,8 @@
 #define FW_BLC_SELF_VLV		(VLV_DISPLAY_BASE + 0x6500)
 #define  FW_CSPWRDWNEN		(1<<15)
 
+#define MI_ARB_VLV		(VLV_DISPLAY_BASE + 0x6504)
+
 /*
  * Palette regs
  */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5690b3d..93d13d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4282,7 +4282,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 static void valleyview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int pipe;
 
 	I915_WRITE(WM3_LP_ILK, 0);
 	I915_WRITE(WM2_LP_ILK, 0);
@@ -4359,12 +4358,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 
 	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
 
-	for_each_pipe(pipe) {
-		I915_WRITE(DSPCNTR(pipe),
-			   I915_READ(DSPCNTR(pipe)) |
-			   DISPPLANE_TRICKLE_FEED_DISABLE);
-		intel_flush_display_plane(dev_priv, pipe);
-	}
+	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
-- 
1.8.1.5

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Re: [PATCH 3/3] drm/i915: Try harder to disable trickle feed on VLV

[Chris Wilson]

On Tue, May 21, 2013 at 03:28:34PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The specs are a bit unclear whether the per-plane trickle feed disable
> control exists on VLV. There is another trickle feed disable control
> in the MI_ARB register.
> 
> Based on some quick register dumps from Jani's VLV machine, the per-plane
> bits don't actually seem to exist, so I'm guessing we should use the
> MI_ARB method instead.

I think neither. I'm guessing this behaviour is covered by 'Note: On
mobile products this bit will be ignored such that Trickle Feed is
always disabled.' in the DSP.CNTR spec. And I don't think MI_ARB_STATE
is applicable as it wasn't used for the display block VLV was based
upon.

Being VPN-less I can't actually dig through the VLV bspec to confirm.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 3/3] drm/i915: Try harder to disable trickle feed on VLV

[Ville Syrjälä]

On Tue, Jun 04, 2013 at 03:19:12PM +0100, Chris Wilson wrote:
> On Tue, May 21, 2013 at 03:28:34PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The specs are a bit unclear whether the per-plane trickle feed disable
> > control exists on VLV. There is another trickle feed disable control
> > in the MI_ARB register.
> > 
> > Based on some quick register dumps from Jani's VLV machine, the per-plane
> > bits don't actually seem to exist, so I'm guessing we should use the
> > MI_ARB method instead.
> 
> I think neither. I'm guessing this behaviour is covered by 'Note: On
> mobile products this bit will be ignored such that Trickle Feed is
> always disabled.' in the DSP.CNTR spec. And I don't think MI_ARB_STATE
> is applicable as it wasn't used for the display block VLV was based
> upon.
> 
> Being VPN-less I can't actually dig through the VLV bspec to confirm.

The register spec has it, and it's even highlighted so it was apparetnly
changed at some point. Also note that the register seems to differ from
MI_ARB_STATE by being the non masked type, so clearly someone felt the
need to edit it for some reason.

The display cluster doc also says that trickle feed is configurable, but
doesn't go into any further details on the subject.

I guess we should confirm on real hardware whether the bit sticks. I
don't remember if I poked Jani to do that since he was a bit busy with
other stuff when I made the patch. Anyways, that could give us a hint
whether the bit really does something.

-- 
Ville Syrjälä
Intel OTC

[PATCH] drm/i915: Disable trickle feed in ironlake_init_clock_gating()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We disable trickle feed in all the (relevant) clock gating functions,
except ironlake_init_clock_gating(). Copy paste the same code there as
well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 93d13d9..4ca214d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3870,6 +3870,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+	int pipe;
 
 	/* Required for FBC */
 	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
@@ -3929,6 +3930,13 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(CACHE_MODE_0,
 		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
 
+	for_each_pipe(pipe) {
+		I915_WRITE(DSPCNTR(pipe),
+			   I915_READ(DSPCNTR(pipe)) |
+			   DISPPLANE_TRICKLE_FEED_DISABLE);
+		intel_flush_display_plane(dev_priv, pipe);
+	}
+
 	ibx_init_clock_gating(dev);
 }
 
-- 
1.8.1.5

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