* [PATCH 1/2] riscv: opentitan: fixup plic stride len
@ 2022-01-10 6:13 Alistair Francis
2022-01-10 6:13 ` [PATCH 2/2] hw: timer: ibex_timer: update/add reg address Alistair Francis
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Alistair Francis @ 2022-01-10 6:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bmeng.cn, palmer, alistair.francis, alistair23, wilfred.mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
The following change was made to rectify incorrectly set stride length
on the PLIC. Where it should be 32bit and not 24bit (0x18). This was
discovered whilst attempting to fix a bug where a timer_interrupt was
not serviced on TockOS-OpenTitan.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
hw/riscv/opentitan.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index c531450b9f..5144845567 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -160,7 +160,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
- qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
2022-01-10 6:13 [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis
@ 2022-01-10 6:13 ` Alistair Francis
2022-01-10 6:16 ` Alistair Francis
2022-01-10 7:40 ` Bin Meng
2022-01-10 6:15 ` Alistair Francis
2022-01-10 7:34 ` Bin Meng
2 siblings, 2 replies; 12+ messages in thread
From: Alistair Francis @ 2022-01-10 6:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bmeng.cn, palmer, alistair.francis, alistair23, wilfred.mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
The following changes:
1. Fixes the incorrectly set CTRL register address. As
per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
The CTRL register is @ 0x04.
This was found when attempting to fixup a bug where a timer_interrupt
was not serviced on TockOS-OpenTitan.
2. Adds ALERT_TEST register as documented on [1], adding repective
switch cases to error handle and later implement functionality.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
hw/timer/ibex_timer.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index 66e1f8e48c..096588ac8a 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -34,7 +34,9 @@
#include "target/riscv/cpu.h"
#include "migration/vmstate.h"
-REG32(CTRL, 0x00)
+REG32(ALERT_TEST, 0x00)
+ FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
+REG32(CTRL, 0x04)
FIELD(CTRL, ACTIVE, 0, 1)
REG32(CFG0, 0x100)
FIELD(CFG0, PRESCALE, 0, 12)
@@ -143,6 +145,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
uint64_t retvalue = 0;
switch (addr >> 2) {
+ case R_ALERT_TEST:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Attempted to read ALERT_TEST, a write only register");
+ break;
case R_CTRL:
retvalue = s->timer_ctrl;
break;
@@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
uint32_t val = val64;
switch (addr >> 2) {
+ case R_ALERT_TEST:
+ qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
+ break;
case R_CTRL:
s->timer_ctrl = val;
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
2022-01-10 6:13 ` [PATCH 2/2] hw: timer: ibex_timer: update/add reg address Alistair Francis
@ 2022-01-10 6:16 ` Alistair Francis
2022-01-10 7:40 ` Bin Meng
1 sibling, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2022-01-10 6:16 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, wilfred.mallawa,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng
On Mon, Jan 10, 2022 at 4:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following changes:
> 1. Fixes the incorrectly set CTRL register address. As
> per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
>
> The CTRL register is @ 0x04.
>
> This was found when attempting to fixup a bug where a timer_interrupt
> was not serviced on TockOS-OpenTitan.
>
> 2. Adds ALERT_TEST register as documented on [1], adding repective
> switch cases to error handle and later implement functionality.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/timer/ibex_timer.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
> index 66e1f8e48c..096588ac8a 100644
> --- a/hw/timer/ibex_timer.c
> +++ b/hw/timer/ibex_timer.c
> @@ -34,7 +34,9 @@
> #include "target/riscv/cpu.h"
> #include "migration/vmstate.h"
>
> -REG32(CTRL, 0x00)
> +REG32(ALERT_TEST, 0x00)
> + FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
> +REG32(CTRL, 0x04)
> FIELD(CTRL, ACTIVE, 0, 1)
> REG32(CFG0, 0x100)
> FIELD(CFG0, PRESCALE, 0, 12)
> @@ -143,6 +145,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
> uint64_t retvalue = 0;
>
> switch (addr >> 2) {
> + case R_ALERT_TEST:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Attempted to read ALERT_TEST, a write only register");
> + break;
> case R_CTRL:
> retvalue = s->timer_ctrl;
> break;
> @@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
> uint32_t val = val64;
>
> switch (addr >> 2) {
> + case R_ALERT_TEST:
> + qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
> + break;
> case R_CTRL:
> s->timer_ctrl = val;
> break;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
@ 2022-01-10 6:16 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2022-01-10 6:16 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Palmer Dabbelt, Alistair Francis, wilfred.mallawa
On Mon, Jan 10, 2022 at 4:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following changes:
> 1. Fixes the incorrectly set CTRL register address. As
> per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
>
> The CTRL register is @ 0x04.
>
> This was found when attempting to fixup a bug where a timer_interrupt
> was not serviced on TockOS-OpenTitan.
>
> 2. Adds ALERT_TEST register as documented on [1], adding repective
> switch cases to error handle and later implement functionality.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/timer/ibex_timer.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
> index 66e1f8e48c..096588ac8a 100644
> --- a/hw/timer/ibex_timer.c
> +++ b/hw/timer/ibex_timer.c
> @@ -34,7 +34,9 @@
> #include "target/riscv/cpu.h"
> #include "migration/vmstate.h"
>
> -REG32(CTRL, 0x00)
> +REG32(ALERT_TEST, 0x00)
> + FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
> +REG32(CTRL, 0x04)
> FIELD(CTRL, ACTIVE, 0, 1)
> REG32(CFG0, 0x100)
> FIELD(CFG0, PRESCALE, 0, 12)
> @@ -143,6 +145,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
> uint64_t retvalue = 0;
>
> switch (addr >> 2) {
> + case R_ALERT_TEST:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "Attempted to read ALERT_TEST, a write only register");
> + break;
> case R_CTRL:
> retvalue = s->timer_ctrl;
> break;
> @@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
> uint32_t val = val64;
>
> switch (addr >> 2) {
> + case R_ALERT_TEST:
> + qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
> + break;
> case R_CTRL:
> s->timer_ctrl = val;
> break;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
2022-01-10 6:13 ` [PATCH 2/2] hw: timer: ibex_timer: update/add reg address Alistair Francis
@ 2022-01-10 7:40 ` Bin Meng
2022-01-10 7:40 ` Bin Meng
1 sibling, 0 replies; 12+ messages in thread
From: Bin Meng @ 2022-01-10 7:40 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, wilfred.mallawa,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Alistair Francis
On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following changes:
> 1. Fixes the incorrectly set CTRL register address. As
> per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
>
> The CTRL register is @ 0x04.
>
> This was found when attempting to fixup a bug where a timer_interrupt
> was not serviced on TockOS-OpenTitan.
>
> 2. Adds ALERT_TEST register as documented on [1], adding repective
> switch cases to error handle and later implement functionality.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
> hw/timer/ibex_timer.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
@ 2022-01-10 7:40 ` Bin Meng
0 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2022-01-10 7:40 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Alistair Francis,
wilfred.mallawa
On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following changes:
> 1. Fixes the incorrectly set CTRL register address. As
> per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
>
> The CTRL register is @ 0x04.
>
> This was found when attempting to fixup a bug where a timer_interrupt
> was not serviced on TockOS-OpenTitan.
>
> 2. Adds ALERT_TEST register as documented on [1], adding repective
> switch cases to error handle and later implement functionality.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
> hw/timer/ibex_timer.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
2022-01-10 6:13 [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis
@ 2022-01-10 6:15 ` Alistair Francis
2022-01-10 6:15 ` Alistair Francis
2022-01-10 7:34 ` Bin Meng
2 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2022-01-10 6:15 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, wilfred.mallawa,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng
On Mon, Jan 10, 2022 at 4:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following change was made to rectify incorrectly set stride length
> on the PLIC. Where it should be 32bit and not 24bit (0x18). This was
> discovered whilst attempting to fix a bug where a timer_interrupt was
> not serviced on TockOS-OpenTitan.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/opentitan.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index c531450b9f..5144845567 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -160,7 +160,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
> qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
> qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
> - qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
> + qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
> qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
> qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
> qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
@ 2022-01-10 6:15 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2022-01-10 6:15 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Palmer Dabbelt, Alistair Francis, wilfred.mallawa
On Mon, Jan 10, 2022 at 4:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following change was made to rectify incorrectly set stride length
> on the PLIC. Where it should be 32bit and not 24bit (0x18). This was
> discovered whilst attempting to fix a bug where a timer_interrupt was
> not serviced on TockOS-OpenTitan.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/opentitan.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index c531450b9f..5144845567 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -160,7 +160,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
> qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
> qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
> - qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
> + qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
> qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
> qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
> qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
2022-01-10 6:13 [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis
@ 2022-01-10 7:34 ` Bin Meng
2022-01-10 6:15 ` Alistair Francis
2022-01-10 7:34 ` Bin Meng
2 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2022-01-10 7:34 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, wilfred.mallawa,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Alistair Francis
On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following change was made to rectify incorrectly set stride length
> on the PLIC. Where it should be 32bit and not 24bit (0x18). This was
PLIC [1]
> discovered whilst attempting to fix a bug where a timer_interrupt was
> not serviced on TockOS-OpenTitan.
>
[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
> hw/riscv/opentitan.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
@ 2022-01-10 7:34 ` Bin Meng
0 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2022-01-10 7:34 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis, Alistair Francis,
wilfred.mallawa
On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following change was made to rectify incorrectly set stride length
> on the PLIC. Where it should be 32bit and not 24bit (0x18). This was
PLIC [1]
> discovered whilst attempting to fix a bug where a timer_interrupt was
> not serviced on TockOS-OpenTitan.
>
[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
> hw/riscv/opentitan.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
2022-01-10 7:34 ` Bin Meng
@ 2022-01-10 23:24 ` Wilfred Mallawa
-1 siblings, 0 replies; 12+ messages in thread
From: Wilfred Mallawa @ 2022-01-10 23:24 UTC (permalink / raw)
To: bmeng.cn, alistair.francis
Cc: palmer, Alistair Francis, qemu-riscv, qemu-devel, alistair23
On Mon, 2022-01-10 at 15:34 +0800, Bin Meng wrote:
> CAUTION: This email originated from outside of Western Digital. Do
> not click on links or open attachments unless you recognize the
> sender and know that the content is safe.
>
>
> On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> >
> > From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> >
> > The following change was made to rectify incorrectly set stride
> > length
> > on the PLIC. Where it should be 32bit and not 24bit (0x18). This
> > was
>
> PLIC [1]
Thanks, will add this in.
>
> > discovered whilst attempting to fix a bug where a timer_interrupt
> > was
> > not serviced on TockOS-OpenTitan.
> >
>
> [1]
> https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/
>
> > Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> > ---
> > hw/riscv/opentitan.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
@ 2022-01-10 23:24 ` Wilfred Mallawa
0 siblings, 0 replies; 12+ messages in thread
From: Wilfred Mallawa @ 2022-01-10 23:24 UTC (permalink / raw)
To: bmeng.cn, alistair.francis
Cc: qemu-riscv, palmer, Alistair Francis, alistair23, qemu-devel
On Mon, 2022-01-10 at 15:34 +0800, Bin Meng wrote:
> CAUTION: This email originated from outside of Western Digital. Do
> not click on links or open attachments unless you recognize the
> sender and know that the content is safe.
>
>
> On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> >
> > From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> >
> > The following change was made to rectify incorrectly set stride
> > length
> > on the PLIC. Where it should be 32bit and not 24bit (0x18). This
> > was
>
> PLIC [1]
Thanks, will add this in.
>
> > discovered whilst attempting to fix a bug where a timer_interrupt
> > was
> > not serviced on TockOS-OpenTitan.
> >
>
> [1]
> https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/
>
> > Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> > ---
> > hw/riscv/opentitan.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-01-11 1:32 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-10 6:13 [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-10 6:13 ` [PATCH 2/2] hw: timer: ibex_timer: update/add reg address Alistair Francis
2022-01-10 6:16 ` Alistair Francis
2022-01-10 6:16 ` Alistair Francis
2022-01-10 7:40 ` Bin Meng
2022-01-10 7:40 ` Bin Meng
2022-01-10 6:15 ` [PATCH 1/2] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-10 6:15 ` Alistair Francis
2022-01-10 7:34 ` Bin Meng
2022-01-10 7:34 ` Bin Meng
2022-01-10 23:24 ` Wilfred Mallawa
2022-01-10 23:24 ` Wilfred Mallawa
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