* [PATCH V2 0/5] Support RISC-V migration
@ 2020-10-10 8:06 ` Yifei Jiang
0 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, richard.henderson,
victor.zhangxiaofeng, wu.wubin, zhang.zhanghailiang, dengkai1,
yinyipeng1, Yifei Jiang
This patches supported RISC-V migration based on tcg accel. And we have
verified related migration features such as snapshot and live migration.
A few weeks ago, we submitted RFC patches about supporting RISC-V migration
based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html.
And we found that tcg accelerated migration can be supported with a few
changes. Most of the devices have already implemented the migration
interface, so, to achieve the tcg accelerated migration, we just need to
add vmstate of both cpu and sifive_plic.
Changes since v1:
1. Add license head to target/riscv/machine.c.
2. Regenerate some state of PMP at post_load hook.
Yifei Jiang (5):
target/riscv: Add basic vmstate description of CPU
target/riscv: Add PMP state description
target/riscv: Add H extension state description
target/riscv: Add V extension state description
target/riscv: Add sifive_plic vmstate
hw/intc/sifive_plic.c | 26 ++++-
hw/intc/sifive_plic.h | 1 +
target/riscv/cpu.c | 7 --
target/riscv/cpu.h | 4 +
target/riscv/machine.c | 203 +++++++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/pmp.c | 29 +++---
target/riscv/pmp.h | 2 +
8 files changed, 255 insertions(+), 20 deletions(-)
create mode 100644 target/riscv/machine.c
--
2.19.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
2020-10-10 8:06 ` Yifei Jiang
@ 2020-10-10 8:06 ` Yifei Jiang
-1 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: zhang.zhanghailiang, sagark, kbastian, victor.zhangxiaofeng,
richard.henderson, Yifei Jiang, Alistair.Francis, yinyipeng1,
palmer, wu.wubin, dengkai1
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/cpu.c | 7 ----
target/riscv/cpu.h | 4 +++
target/riscv/machine.c | 77 ++++++++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
4 files changed, 83 insertions(+), 8 deletions(-)
create mode 100644 target/riscv/machine.c
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f457..bf396e2916 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -496,13 +496,6 @@ static void riscv_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu);
}
-#ifndef CONFIG_USER_ONLY
-static const VMStateDescription vmstate_riscv_cpu = {
- .name = "cpu",
- .unmigratable = 1,
-};
-#endif
-
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de275782e6..8440ea0793 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -311,6 +311,10 @@ extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_riscv_cpu;
+#endif
+
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
new file mode 100644
index 0000000000..af2828a80a
--- /dev/null
+++ b/target/riscv/machine.c
@@ -0,0 +1,77 @@
+/*
+ * RISC-V VMState Description
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/error-report.h"
+#include "sysemu/kvm.h"
+#include "migration/cpu.h"
+
+const VMStateDescription vmstate_riscv_cpu = {
+ .name = "cpu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
+ VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
+ VMSTATE_UINTTL(env.pc, RISCVCPU),
+ VMSTATE_UINTTL(env.load_res, RISCVCPU),
+ VMSTATE_UINTTL(env.load_val, RISCVCPU),
+ VMSTATE_UINTTL(env.frm, RISCVCPU),
+ VMSTATE_UINTTL(env.badaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
+ VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
+ VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
+ VMSTATE_UINTTL(env.misa, RISCVCPU),
+ VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
+ VMSTATE_UINT32(env.features, RISCVCPU),
+ VMSTATE_UINTTL(env.priv, RISCVCPU),
+ VMSTATE_UINTTL(env.virt, RISCVCPU),
+ VMSTATE_UINTTL(env.resetvec, RISCVCPU),
+ VMSTATE_UINTTL(env.mhartid, RISCVCPU),
+ VMSTATE_UINTTL(env.mstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.mip, RISCVCPU),
+ VMSTATE_UINT32(env.miclaim, RISCVCPU),
+ VMSTATE_UINTTL(env.mie, RISCVCPU),
+ VMSTATE_UINTTL(env.mideleg, RISCVCPU),
+ VMSTATE_UINTTL(env.sptbr, RISCVCPU),
+ VMSTATE_UINTTL(env.satp, RISCVCPU),
+ VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.medeleg, RISCVCPU),
+ VMSTATE_UINTTL(env.stvec, RISCVCPU),
+ VMSTATE_UINTTL(env.sepc, RISCVCPU),
+ VMSTATE_UINTTL(env.scause, RISCVCPU),
+ VMSTATE_UINTTL(env.mtvec, RISCVCPU),
+ VMSTATE_UINTTL(env.mepc, RISCVCPU),
+ VMSTATE_UINTTL(env.mcause, RISCVCPU),
+ VMSTATE_UINTTL(env.mtval, RISCVCPU),
+ VMSTATE_UINTTL(env.scounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.sscratch, RISCVCPU),
+ VMSTATE_UINTTL(env.mscratch, RISCVCPU),
+ VMSTATE_UINT64(env.mfromhost, RISCVCPU),
+ VMSTATE_UINT64(env.mtohost, RISCVCPU),
+ VMSTATE_UINT64(env.timecmp, RISCVCPU),
+
+#ifdef TARGET_RISCV32
+ VMSTATE_UINTTL(env.mstatush, RISCVCPU),
+#endif
+ VMSTATE_END_OF_LIST()
+ }
+};
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index abd647fea1..14a5c62dac 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -27,7 +27,8 @@ riscv_ss.add(files(
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
'pmp.c',
- 'monitor.c'
+ 'monitor.c',
+ 'machine.c'
))
target_arch += {'riscv': riscv_ss}
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
@ 2020-10-10 8:06 ` Yifei Jiang
0 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, richard.henderson,
victor.zhangxiaofeng, wu.wubin, zhang.zhanghailiang, dengkai1,
yinyipeng1, Yifei Jiang
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/cpu.c | 7 ----
target/riscv/cpu.h | 4 +++
target/riscv/machine.c | 77 ++++++++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
4 files changed, 83 insertions(+), 8 deletions(-)
create mode 100644 target/riscv/machine.c
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0bbfd7f457..bf396e2916 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -496,13 +496,6 @@ static void riscv_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu);
}
-#ifndef CONFIG_USER_ONLY
-static const VMStateDescription vmstate_riscv_cpu = {
- .name = "cpu",
- .unmigratable = 1,
-};
-#endif
-
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de275782e6..8440ea0793 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -311,6 +311,10 @@ extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_riscv_cpu;
+#endif
+
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
new file mode 100644
index 0000000000..af2828a80a
--- /dev/null
+++ b/target/riscv/machine.c
@@ -0,0 +1,77 @@
+/*
+ * RISC-V VMState Description
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/error-report.h"
+#include "sysemu/kvm.h"
+#include "migration/cpu.h"
+
+const VMStateDescription vmstate_riscv_cpu = {
+ .name = "cpu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
+ VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
+ VMSTATE_UINTTL(env.pc, RISCVCPU),
+ VMSTATE_UINTTL(env.load_res, RISCVCPU),
+ VMSTATE_UINTTL(env.load_val, RISCVCPU),
+ VMSTATE_UINTTL(env.frm, RISCVCPU),
+ VMSTATE_UINTTL(env.badaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
+ VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
+ VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
+ VMSTATE_UINTTL(env.misa, RISCVCPU),
+ VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
+ VMSTATE_UINT32(env.features, RISCVCPU),
+ VMSTATE_UINTTL(env.priv, RISCVCPU),
+ VMSTATE_UINTTL(env.virt, RISCVCPU),
+ VMSTATE_UINTTL(env.resetvec, RISCVCPU),
+ VMSTATE_UINTTL(env.mhartid, RISCVCPU),
+ VMSTATE_UINTTL(env.mstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.mip, RISCVCPU),
+ VMSTATE_UINT32(env.miclaim, RISCVCPU),
+ VMSTATE_UINTTL(env.mie, RISCVCPU),
+ VMSTATE_UINTTL(env.mideleg, RISCVCPU),
+ VMSTATE_UINTTL(env.sptbr, RISCVCPU),
+ VMSTATE_UINTTL(env.satp, RISCVCPU),
+ VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.medeleg, RISCVCPU),
+ VMSTATE_UINTTL(env.stvec, RISCVCPU),
+ VMSTATE_UINTTL(env.sepc, RISCVCPU),
+ VMSTATE_UINTTL(env.scause, RISCVCPU),
+ VMSTATE_UINTTL(env.mtvec, RISCVCPU),
+ VMSTATE_UINTTL(env.mepc, RISCVCPU),
+ VMSTATE_UINTTL(env.mcause, RISCVCPU),
+ VMSTATE_UINTTL(env.mtval, RISCVCPU),
+ VMSTATE_UINTTL(env.scounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.sscratch, RISCVCPU),
+ VMSTATE_UINTTL(env.mscratch, RISCVCPU),
+ VMSTATE_UINT64(env.mfromhost, RISCVCPU),
+ VMSTATE_UINT64(env.mtohost, RISCVCPU),
+ VMSTATE_UINT64(env.timecmp, RISCVCPU),
+
+#ifdef TARGET_RISCV32
+ VMSTATE_UINTTL(env.mstatush, RISCVCPU),
+#endif
+ VMSTATE_END_OF_LIST()
+ }
+};
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index abd647fea1..14a5c62dac 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -27,7 +27,8 @@ riscv_ss.add(files(
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
'pmp.c',
- 'monitor.c'
+ 'monitor.c',
+ 'machine.c'
))
target_arch += {'riscv': riscv_ss}
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
2020-10-10 8:06 ` Yifei Jiang
@ 2020-10-10 13:23 ` Richard Henderson
-1 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-10-10 13:23 UTC (permalink / raw)
To: Yifei Jiang, qemu-devel, qemu-riscv
Cc: zhang.zhanghailiang, sagark, kbastian, victor.zhangxiaofeng,
Alistair.Francis, yinyipeng1, palmer, wu.wubin, dengkai1
On 10/10/20 3:06 AM, Yifei Jiang wrote:
> +++ b/target/riscv/cpu.h
> @@ -311,6 +311,10 @@ extern const char * const riscv_fpr_regnames[];
> extern const char * const riscv_excp_names[];
> extern const char * const riscv_intr_names[];
>
> +#ifndef CONFIG_USER_ONLY
> +extern const VMStateDescription vmstate_riscv_cpu;
> +#endif
> +
This is not part of the public interface to RISCVCPU, so it should go in
internals.h.
Not that there aren't other things in cpu.h that don't belong. No target has
been perfect in differentiating what's interface and what's implementation.
> +
> +#ifdef TARGET_RISCV32
> + VMSTATE_UINTTL(env.mstatush, RISCVCPU),
> +#endif
Would this be a good time to expand mstatus to uint64_t instead of target_ulong
so that it can be saved as one unit and reduce some ifdefs in the code base?
Similarly with some of the other status registers that are two halved for riscv32.
r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
@ 2020-10-10 13:23 ` Richard Henderson
0 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-10-10 13:23 UTC (permalink / raw)
To: Yifei Jiang, qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, victor.zhangxiaofeng,
wu.wubin, zhang.zhanghailiang, dengkai1, yinyipeng1
On 10/10/20 3:06 AM, Yifei Jiang wrote:
> +++ b/target/riscv/cpu.h
> @@ -311,6 +311,10 @@ extern const char * const riscv_fpr_regnames[];
> extern const char * const riscv_excp_names[];
> extern const char * const riscv_intr_names[];
>
> +#ifndef CONFIG_USER_ONLY
> +extern const VMStateDescription vmstate_riscv_cpu;
> +#endif
> +
This is not part of the public interface to RISCVCPU, so it should go in
internals.h.
Not that there aren't other things in cpu.h that don't belong. No target has
been perfect in differentiating what's interface and what's implementation.
> +
> +#ifdef TARGET_RISCV32
> + VMSTATE_UINTTL(env.mstatush, RISCVCPU),
> +#endif
Would this be a good time to expand mstatus to uint64_t instead of target_ulong
so that it can be saved as one unit and reduce some ifdefs in the code base?
Similarly with some of the other status registers that are two halved for riscv32.
r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
2020-10-10 13:23 ` Richard Henderson
@ 2020-10-14 10:21 ` Jiangyifei
-1 siblings, 0 replies; 22+ messages in thread
From: Jiangyifei @ 2020-10-14 10:21 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-riscv
Cc: Zhanghailiang, sagark, kbastian, Zhangxiaofeng (F),
Alistair.Francis, yinyipeng, palmer, Wubin (H), dengkai (A)
> -----Original Message-----
> From: Richard Henderson [mailto:richard.henderson@linaro.org]
> Sent: Saturday, October 10, 2020 9:23 PM
> To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org
> Cc: palmer@dabbelt.com; Alistair.Francis@wdc.com;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Wubin (H) <wu.wubin@huawei.com>;
> Zhanghailiang <zhang.zhanghailiang@huawei.com>; dengkai (A)
> <dengkai1@huawei.com>; yinyipeng <yinyipeng1@huawei.com>
> Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
>
> On 10/10/20 3:06 AM, Yifei Jiang wrote:
> > +++ b/target/riscv/cpu.h
> > @@ -311,6 +311,10 @@ extern const char * const riscv_fpr_regnames[];
> > extern const char * const riscv_excp_names[]; extern const char *
> > const riscv_intr_names[];
> >
> > +#ifndef CONFIG_USER_ONLY
> > +extern const VMStateDescription vmstate_riscv_cpu; #endif
> > +
>
> This is not part of the public interface to RISCVCPU, so it should go in
> internals.h.
>
> Not that there aren't other things in cpu.h that don't belong. No target has
> been perfect in differentiating what's interface and what's implementation.
>
Yes, I think it should go in internals.h, although most architectures declare it in cpu.h.
I would move it to internals.h in the next series.
> > +
> > +#ifdef TARGET_RISCV32
> > + VMSTATE_UINTTL(env.mstatush, RISCVCPU), #endif
>
> Would this be a good time to expand mstatus to uint64_t instead of
> target_ulong so that it can be saved as one unit and reduce some ifdefs in the
> code base?
>
> Similarly with some of the other status registers that are two halved for
> riscv32.
I agree with you that it should be rearranged.
But I hope this series will focus on achieving migration.
Can I send another patch to rearrange it later?
Yifei
>
>
> r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
@ 2020-10-14 10:21 ` Jiangyifei
0 siblings, 0 replies; 22+ messages in thread
From: Jiangyifei @ 2020-10-14 10:21 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, Zhangxiaofeng (F),
Wubin (H), Zhanghailiang, dengkai (A),
yinyipeng
> -----Original Message-----
> From: Richard Henderson [mailto:richard.henderson@linaro.org]
> Sent: Saturday, October 10, 2020 9:23 PM
> To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org
> Cc: palmer@dabbelt.com; Alistair.Francis@wdc.com;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Wubin (H) <wu.wubin@huawei.com>;
> Zhanghailiang <zhang.zhanghailiang@huawei.com>; dengkai (A)
> <dengkai1@huawei.com>; yinyipeng <yinyipeng1@huawei.com>
> Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
>
> On 10/10/20 3:06 AM, Yifei Jiang wrote:
> > +++ b/target/riscv/cpu.h
> > @@ -311,6 +311,10 @@ extern const char * const riscv_fpr_regnames[];
> > extern const char * const riscv_excp_names[]; extern const char *
> > const riscv_intr_names[];
> >
> > +#ifndef CONFIG_USER_ONLY
> > +extern const VMStateDescription vmstate_riscv_cpu; #endif
> > +
>
> This is not part of the public interface to RISCVCPU, so it should go in
> internals.h.
>
> Not that there aren't other things in cpu.h that don't belong. No target has
> been perfect in differentiating what's interface and what's implementation.
>
Yes, I think it should go in internals.h, although most architectures declare it in cpu.h.
I would move it to internals.h in the next series.
> > +
> > +#ifdef TARGET_RISCV32
> > + VMSTATE_UINTTL(env.mstatush, RISCVCPU), #endif
>
> Would this be a good time to expand mstatus to uint64_t instead of
> target_ulong so that it can be saved as one unit and reduce some ifdefs in the
> code base?
>
> Similarly with some of the other status registers that are two halved for
> riscv32.
I agree with you that it should be rearranged.
But I hope this series will focus on achieving migration.
Can I send another patch to rearrange it later?
Yifei
>
>
> r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
2020-10-14 10:21 ` Jiangyifei
@ 2020-10-14 15:45 ` Richard Henderson
-1 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-10-14 15:45 UTC (permalink / raw)
To: Jiangyifei, qemu-devel, qemu-riscv
Cc: Zhanghailiang, sagark, kbastian, Zhangxiaofeng (F),
Alistair.Francis, yinyipeng, palmer, Wubin (H), dengkai (A)
On 10/14/20 3:21 AM, Jiangyifei wrote:
>> Would this be a good time to expand mstatus to uint64_t instead of
>> target_ulong so that it can be saved as one unit and reduce some ifdefs in the
>> code base?
>>
>> Similarly with some of the other status registers that are two halved for
>> riscv32.
>
> I agree with you that it should be rearranged.
> But I hope this series will focus on achieving migration.
> Can I send another patch to rearrange it later?
Well, that changes the bit layout for migration.
While we could bump the version number, it seemed
easier to change the representation first.
r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
@ 2020-10-14 15:45 ` Richard Henderson
0 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-10-14 15:45 UTC (permalink / raw)
To: Jiangyifei, qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, Zhangxiaofeng (F),
Wubin (H), Zhanghailiang, dengkai (A),
yinyipeng
On 10/14/20 3:21 AM, Jiangyifei wrote:
>> Would this be a good time to expand mstatus to uint64_t instead of
>> target_ulong so that it can be saved as one unit and reduce some ifdefs in the
>> code base?
>>
>> Similarly with some of the other status registers that are two halved for
>> riscv32.
>
> I agree with you that it should be rearranged.
> But I hope this series will focus on achieving migration.
> Can I send another patch to rearrange it later?
Well, that changes the bit layout for migration.
While we could bump the version number, it seemed
easier to change the representation first.
r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
2020-10-14 15:45 ` Richard Henderson
@ 2020-10-14 19:12 ` Alistair Francis
-1 siblings, 0 replies; 22+ messages in thread
From: Alistair Francis @ 2020-10-14 19:12 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-riscv, Zhanghailiang, sagark, kbastian, Zhangxiaofeng (F),
qemu-devel, Jiangyifei, yinyipeng, Alistair.Francis, palmer,
Wubin (H), dengkai (A)
On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/14/20 3:21 AM, Jiangyifei wrote:
> >> Would this be a good time to expand mstatus to uint64_t instead of
> >> target_ulong so that it can be saved as one unit and reduce some ifdefs in the
> >> code base?
> >>
> >> Similarly with some of the other status registers that are two halved for
> >> riscv32.
> >
> > I agree with you that it should be rearranged.
> > But I hope this series will focus on achieving migration.
> > Can I send another patch to rearrange it later?
>
> Well, that changes the bit layout for migration.
> While we could bump the version number, it seemed
> easier to change the representation first.
+1 it would be great to consolidate these.
Alistair
>
>
> r~
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
@ 2020-10-14 19:12 ` Alistair Francis
0 siblings, 0 replies; 22+ messages in thread
From: Alistair Francis @ 2020-10-14 19:12 UTC (permalink / raw)
To: Richard Henderson
Cc: Jiangyifei, qemu-devel, qemu-riscv, Zhanghailiang, sagark,
kbastian, Zhangxiaofeng (F),
Alistair.Francis, yinyipeng, palmer, Wubin (H), dengkai (A)
On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/14/20 3:21 AM, Jiangyifei wrote:
> >> Would this be a good time to expand mstatus to uint64_t instead of
> >> target_ulong so that it can be saved as one unit and reduce some ifdefs in the
> >> code base?
> >>
> >> Similarly with some of the other status registers that are two halved for
> >> riscv32.
> >
> > I agree with you that it should be rearranged.
> > But I hope this series will focus on achieving migration.
> > Can I send another patch to rearrange it later?
>
> Well, that changes the bit layout for migration.
> While we could bump the version number, it seemed
> easier to change the representation first.
+1 it would be great to consolidate these.
Alistair
>
>
> r~
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
2020-10-14 19:12 ` Alistair Francis
@ 2020-10-15 2:03 ` Jiangyifei
-1 siblings, 0 replies; 22+ messages in thread
From: Jiangyifei @ 2020-10-15 2:03 UTC (permalink / raw)
To: Alistair Francis, Richard Henderson
Cc: qemu-riscv, Zhanghailiang, sagark, kbastian, Zhangxiaofeng (F),
qemu-devel, Alistair.Francis, yinyipeng, palmer, Wubin (H),
dengkai (A)
> -----Original Message-----
> From: Alistair Francis [mailto:alistair23@gmail.com]
> Sent: Thursday, October 15, 2020 3:12 AM
> To: Richard Henderson <richard.henderson@linaro.org>
> Cc: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org; Zhanghailiang <zhang.zhanghailiang@huawei.com>;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng
> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)
> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
>
> On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > On 10/14/20 3:21 AM, Jiangyifei wrote:
> > >> Would this be a good time to expand mstatus to uint64_t instead of
> > >> target_ulong so that it can be saved as one unit and reduce some
> > >> ifdefs in the code base?
> > >>
> > >> Similarly with some of the other status registers that are two
> > >> halved for riscv32.
> > >
> > > I agree with you that it should be rearranged.
> > > But I hope this series will focus on achieving migration.
> > > Can I send another patch to rearrange it later?
> >
> > Well, that changes the bit layout for migration.
> > While we could bump the version number, it seemed easier to change the
> > representation first.
>
> +1 it would be great to consolidate these.
>
> Alistair
>
OK. I will change this in the next series.
Yifei
> >
> >
> > r~
> >
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
@ 2020-10-15 2:03 ` Jiangyifei
0 siblings, 0 replies; 22+ messages in thread
From: Jiangyifei @ 2020-10-15 2:03 UTC (permalink / raw)
To: Alistair Francis, Richard Henderson
Cc: qemu-devel, qemu-riscv, Zhanghailiang, sagark, kbastian,
Zhangxiaofeng (F), Alistair.Francis, yinyipeng, palmer, Wubin (H),
dengkai (A)
> -----Original Message-----
> From: Alistair Francis [mailto:alistair23@gmail.com]
> Sent: Thursday, October 15, 2020 3:12 AM
> To: Richard Henderson <richard.henderson@linaro.org>
> Cc: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org; Zhanghailiang <zhang.zhanghailiang@huawei.com>;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng
> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)
> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
>
> On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > On 10/14/20 3:21 AM, Jiangyifei wrote:
> > >> Would this be a good time to expand mstatus to uint64_t instead of
> > >> target_ulong so that it can be saved as one unit and reduce some
> > >> ifdefs in the code base?
> > >>
> > >> Similarly with some of the other status registers that are two
> > >> halved for riscv32.
> > >
> > > I agree with you that it should be rearranged.
> > > But I hope this series will focus on achieving migration.
> > > Can I send another patch to rearrange it later?
> >
> > Well, that changes the bit layout for migration.
> > While we could bump the version number, it seemed easier to change the
> > representation first.
>
> +1 it would be great to consolidate these.
>
> Alistair
>
OK. I will change this in the next series.
Yifei
> >
> >
> > r~
> >
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V2 2/5] target/riscv: Add PMP state description
2020-10-10 8:06 ` Yifei Jiang
@ 2020-10-10 8:06 ` Yifei Jiang
-1 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: zhang.zhanghailiang, sagark, kbastian, victor.zhangxiaofeng,
richard.henderson, Yifei Jiang, Alistair.Francis, yinyipeng1,
palmer, wu.wubin, dengkai1
In the case of supporting PMP feature, add PMP state description
to vmstate_riscv_cpu.
'vmstate_pmp_addr' and 'num_rules' could be regenerated by
pmp_update_rule(). But there exists the problem of updating
num_rules repeatedly in pmp_update_rule(). So here extracts
pmp_update_rule_addr() and pmp_update_rule_nums() to update
'vmstate_pmp_addr' and 'num_rules' respectively.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++
target/riscv/pmp.c | 29 ++++++++++++++----------
target/riscv/pmp.h | 2 ++
3 files changed, 70 insertions(+), 11 deletions(-)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index af2828a80a..8fffd2db3f 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -22,6 +22,52 @@
#include "sysemu/kvm.h"
#include "migration/cpu.h"
+static bool pmp_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_feature(env, RISCV_FEATURE_PMP);
+}
+
+static int pmp_post_load(void *opaque, int version_id)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+ int i;
+
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ pmp_update_rule_addr(env, i);
+ }
+ pmp_update_rule_nums(env);
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_pmp_entry = {
+ .name = "cpu/pmp/entry",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(addr_reg, pmp_entry_t),
+ VMSTATE_UINT8(cfg_reg, pmp_entry_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_pmp = {
+ .name = "cpu/pmp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pmp_needed,
+ .post_load = pmp_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
+ 0, vmstate_pmp_entry, pmp_entry_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 1,
@@ -73,5 +119,9 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mstatush, RISCVCPU),
#endif
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * []) {
+ &vmstate_pmp,
+ NULL
}
};
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index c394e867f8..2eda8e1e2f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -136,18 +136,8 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
}
}
-
-/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
- * end address values.
- * This function is called relatively infrequently whereas the check that
- * an address is within a pmp rule is called often, so optimise that one
- */
-static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
+void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
{
- int i;
-
- env->pmp_state.num_rules = 0;
-
uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
target_ulong prev_addr = 0u;
@@ -186,7 +176,13 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
env->pmp_state.addr[pmp_index].sa = sa;
env->pmp_state.addr[pmp_index].ea = ea;
+}
+void pmp_update_rule_nums(CPURISCVState *env)
+{
+ int i;
+
+ env->pmp_state.num_rules = 0;
for (i = 0; i < MAX_RISCV_PMPS; i++) {
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
@@ -196,6 +192,17 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
}
}
+/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
+ * end address values.
+ * This function is called relatively infrequently whereas the check that
+ * an address is within a pmp rule is called often, so optimise that one
+ */
+static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
+{
+ pmp_update_rule_addr(env, pmp_index);
+ pmp_update_rule_nums(env);
+}
+
static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
{
int result = 0;
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 6a8f072871..6c6b4c9bef 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -62,5 +62,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t priv, target_ulong mode);
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
target_ulong *tlb_size);
+void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
+void pmp_update_rule_nums(CPURISCVState *env);
#endif
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH V2 2/5] target/riscv: Add PMP state description
@ 2020-10-10 8:06 ` Yifei Jiang
0 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, richard.henderson,
victor.zhangxiaofeng, wu.wubin, zhang.zhanghailiang, dengkai1,
yinyipeng1, Yifei Jiang
In the case of supporting PMP feature, add PMP state description
to vmstate_riscv_cpu.
'vmstate_pmp_addr' and 'num_rules' could be regenerated by
pmp_update_rule(). But there exists the problem of updating
num_rules repeatedly in pmp_update_rule(). So here extracts
pmp_update_rule_addr() and pmp_update_rule_nums() to update
'vmstate_pmp_addr' and 'num_rules' respectively.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++
target/riscv/pmp.c | 29 ++++++++++++++----------
target/riscv/pmp.h | 2 ++
3 files changed, 70 insertions(+), 11 deletions(-)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index af2828a80a..8fffd2db3f 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -22,6 +22,52 @@
#include "sysemu/kvm.h"
#include "migration/cpu.h"
+static bool pmp_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_feature(env, RISCV_FEATURE_PMP);
+}
+
+static int pmp_post_load(void *opaque, int version_id)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+ int i;
+
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ pmp_update_rule_addr(env, i);
+ }
+ pmp_update_rule_nums(env);
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_pmp_entry = {
+ .name = "cpu/pmp/entry",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(addr_reg, pmp_entry_t),
+ VMSTATE_UINT8(cfg_reg, pmp_entry_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_pmp = {
+ .name = "cpu/pmp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pmp_needed,
+ .post_load = pmp_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
+ 0, vmstate_pmp_entry, pmp_entry_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 1,
@@ -73,5 +119,9 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mstatush, RISCVCPU),
#endif
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * []) {
+ &vmstate_pmp,
+ NULL
}
};
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index c394e867f8..2eda8e1e2f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -136,18 +136,8 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
}
}
-
-/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
- * end address values.
- * This function is called relatively infrequently whereas the check that
- * an address is within a pmp rule is called often, so optimise that one
- */
-static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
+void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
{
- int i;
-
- env->pmp_state.num_rules = 0;
-
uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
target_ulong prev_addr = 0u;
@@ -186,7 +176,13 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
env->pmp_state.addr[pmp_index].sa = sa;
env->pmp_state.addr[pmp_index].ea = ea;
+}
+void pmp_update_rule_nums(CPURISCVState *env)
+{
+ int i;
+
+ env->pmp_state.num_rules = 0;
for (i = 0; i < MAX_RISCV_PMPS; i++) {
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
@@ -196,6 +192,17 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
}
}
+/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
+ * end address values.
+ * This function is called relatively infrequently whereas the check that
+ * an address is within a pmp rule is called often, so optimise that one
+ */
+static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
+{
+ pmp_update_rule_addr(env, pmp_index);
+ pmp_update_rule_nums(env);
+}
+
static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
{
int result = 0;
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 6a8f072871..6c6b4c9bef 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -62,5 +62,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t priv, target_ulong mode);
bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
target_ulong *tlb_size);
+void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
+void pmp_update_rule_nums(CPURISCVState *env);
#endif
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V2 3/5] target/riscv: Add H extension state description
2020-10-10 8:06 ` Yifei Jiang
@ 2020-10-10 8:06 ` Yifei Jiang
-1 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: zhang.zhanghailiang, sagark, kbastian, victor.zhangxiaofeng,
richard.henderson, Yifei Jiang, Alistair.Francis, yinyipeng1,
palmer, wu.wubin, dengkai1
In the case of supporting H extension, add H extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/machine.c | 51 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 8fffd2db3f..af599bf001 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -68,6 +68,56 @@ static const VMStateDescription vmstate_pmp = {
}
};
+static bool hyper_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVH);
+}
+
+static const VMStateDescription vmstate_hyper = {
+ .name = "cpu/hyper",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = hyper_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.hstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
+ VMSTATE_UINTTL(env.hideleg, RISCVCPU),
+ VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.htval, RISCVCPU),
+ VMSTATE_UINTTL(env.htinst, RISCVCPU),
+ VMSTATE_UINTTL(env.hgatp, RISCVCPU),
+ VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+
+ VMSTATE_UINTTL(env.vsstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.vstvec, RISCVCPU),
+ VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
+ VMSTATE_UINTTL(env.vsepc, RISCVCPU),
+ VMSTATE_UINTTL(env.vscause, RISCVCPU),
+ VMSTATE_UINTTL(env.vstval, RISCVCPU),
+ VMSTATE_UINTTL(env.vsatp, RISCVCPU),
+
+ VMSTATE_UINTTL(env.mtval2, RISCVCPU),
+ VMSTATE_UINTTL(env.mtinst, RISCVCPU),
+
+ VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.mstatus_hs, RISCVCPU),
+
+#ifdef TARGET_RISCV32
+ VMSTATE_UINTTL(env.vsstatush, RISCVCPU),
+ VMSTATE_UINTTL(env.mstatush_hs, RISCVCPU),
+#endif
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 1,
@@ -122,6 +172,7 @@ const VMStateDescription vmstate_riscv_cpu = {
},
.subsections = (const VMStateDescription * []) {
&vmstate_pmp,
+ &vmstate_hyper,
NULL
}
};
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH V2 3/5] target/riscv: Add H extension state description
@ 2020-10-10 8:06 ` Yifei Jiang
0 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, richard.henderson,
victor.zhangxiaofeng, wu.wubin, zhang.zhanghailiang, dengkai1,
yinyipeng1, Yifei Jiang
In the case of supporting H extension, add H extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/machine.c | 51 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 8fffd2db3f..af599bf001 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -68,6 +68,56 @@ static const VMStateDescription vmstate_pmp = {
}
};
+static bool hyper_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVH);
+}
+
+static const VMStateDescription vmstate_hyper = {
+ .name = "cpu/hyper",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = hyper_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.hstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
+ VMSTATE_UINTTL(env.hideleg, RISCVCPU),
+ VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.htval, RISCVCPU),
+ VMSTATE_UINTTL(env.htinst, RISCVCPU),
+ VMSTATE_UINTTL(env.hgatp, RISCVCPU),
+ VMSTATE_UINT64(env.htimedelta, RISCVCPU),
+
+ VMSTATE_UINTTL(env.vsstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.vstvec, RISCVCPU),
+ VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
+ VMSTATE_UINTTL(env.vsepc, RISCVCPU),
+ VMSTATE_UINTTL(env.vscause, RISCVCPU),
+ VMSTATE_UINTTL(env.vstval, RISCVCPU),
+ VMSTATE_UINTTL(env.vsatp, RISCVCPU),
+
+ VMSTATE_UINTTL(env.mtval2, RISCVCPU),
+ VMSTATE_UINTTL(env.mtinst, RISCVCPU),
+
+ VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
+ VMSTATE_UINTTL(env.mstatus_hs, RISCVCPU),
+
+#ifdef TARGET_RISCV32
+ VMSTATE_UINTTL(env.vsstatush, RISCVCPU),
+ VMSTATE_UINTTL(env.mstatush_hs, RISCVCPU),
+#endif
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 1,
@@ -122,6 +172,7 @@ const VMStateDescription vmstate_riscv_cpu = {
},
.subsections = (const VMStateDescription * []) {
&vmstate_pmp,
+ &vmstate_hyper,
NULL
}
};
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V2 4/5] target/riscv: Add V extension state description
2020-10-10 8:06 ` Yifei Jiang
@ 2020-10-10 8:06 ` Yifei Jiang
-1 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: zhang.zhanghailiang, sagark, kbastian, victor.zhangxiaofeng,
richard.henderson, Yifei Jiang, Alistair.Francis, yinyipeng1,
palmer, wu.wubin, dengkai1
In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/machine.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index af599bf001..2bd3a7b5b0 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque)
return riscv_has_ext(env, RVH);
}
+static bool vector_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVV);
+}
+
+static const VMStateDescription vmstate_vector = {
+ .name = "cpu/vector",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = vector_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
+ VMSTATE_UINTTL(env.vxrm, RISCVCPU),
+ VMSTATE_UINTTL(env.vxsat, RISCVCPU),
+ VMSTATE_UINTTL(env.vl, RISCVCPU),
+ VMSTATE_UINTTL(env.vstart, RISCVCPU),
+ VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
.version_id = 1,
@@ -173,6 +197,7 @@ const VMStateDescription vmstate_riscv_cpu = {
.subsections = (const VMStateDescription * []) {
&vmstate_pmp,
&vmstate_hyper,
+ &vmstate_vector,
NULL
}
};
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH V2 4/5] target/riscv: Add V extension state description
@ 2020-10-10 8:06 ` Yifei Jiang
0 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, richard.henderson,
victor.zhangxiaofeng, wu.wubin, zhang.zhanghailiang, dengkai1,
yinyipeng1, Yifei Jiang
In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/machine.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index af599bf001..2bd3a7b5b0 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque)
return riscv_has_ext(env, RVH);
}
+static bool vector_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVV);
+}
+
+static const VMStateDescription vmstate_vector = {
+ .name = "cpu/vector",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = vector_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
+ VMSTATE_UINTTL(env.vxrm, RISCVCPU),
+ VMSTATE_UINTTL(env.vxsat, RISCVCPU),
+ VMSTATE_UINTTL(env.vl, RISCVCPU),
+ VMSTATE_UINTTL(env.vstart, RISCVCPU),
+ VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
.version_id = 1,
@@ -173,6 +197,7 @@ const VMStateDescription vmstate_riscv_cpu = {
.subsections = (const VMStateDescription * []) {
&vmstate_pmp,
&vmstate_hyper,
+ &vmstate_vector,
NULL
}
};
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V2 5/5] target/riscv: Add sifive_plic vmstate
2020-10-10 8:06 ` Yifei Jiang
@ 2020-10-10 8:06 ` Yifei Jiang
-1 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: zhang.zhanghailiang, sagark, kbastian, victor.zhangxiaofeng,
richard.henderson, Yifei Jiang, Alistair.Francis, yinyipeng1,
palmer, wu.wubin, dengkai1
Add sifive_plic vmstate for supporting sifive_plic migration.
Current vmstate framework only supports one structure parameter
as num field to describe variable length arrays, so introduce
num_enables.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
hw/intc/sifive_plic.c | 26 +++++++++++++++++++++++++-
hw/intc/sifive_plic.h | 1 +
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f42fd695d8..97a1a27a9a 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -30,6 +30,7 @@
#include "hw/intc/sifive_plic.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
#define RISCV_DEBUG_PLIC 0
@@ -448,11 +449,12 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
TYPE_SIFIVE_PLIC, plic->aperture_size);
parse_hart_config(plic);
plic->bitfield_words = (plic->num_sources + 31) >> 5;
+ plic->num_enables = plic->bitfield_words * plic->num_addrs;
plic->source_priority = g_new0(uint32_t, plic->num_sources);
plic->target_priority = g_new(uint32_t, plic->num_addrs);
plic->pending = g_new0(uint32_t, plic->bitfield_words);
plic->claimed = g_new0(uint32_t, plic->bitfield_words);
- plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
+ plic->enable = g_new0(uint32_t, plic->num_enables);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
@@ -472,12 +474,34 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
msi_nonbroken = true;
}
+static const VMStateDescription vmstate_sifive_plic = {
+ .name = "riscv_sifive_plic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
+ num_sources, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
+ num_addrs, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void sifive_plic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
device_class_set_props(dc, sifive_plic_properties);
dc->realize = sifive_plic_realize;
+ dc->vmsd = &vmstate_sifive_plic;
}
static const TypeInfo sifive_plic_info = {
diff --git a/hw/intc/sifive_plic.h b/hw/intc/sifive_plic.h
index b75b1f145d..1e451a270c 100644
--- a/hw/intc/sifive_plic.h
+++ b/hw/intc/sifive_plic.h
@@ -52,6 +52,7 @@ struct SiFivePLICState {
uint32_t num_addrs;
uint32_t num_harts;
uint32_t bitfield_words;
+ uint32_t num_enables;
PLICAddr *addr_config;
uint32_t *source_priority;
uint32_t *target_priority;
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH V2 5/5] target/riscv: Add sifive_plic vmstate
@ 2020-10-10 8:06 ` Yifei Jiang
0 siblings, 0 replies; 22+ messages in thread
From: Yifei Jiang @ 2020-10-10 8:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, Alistair.Francis, sagark, kbastian, richard.henderson,
victor.zhangxiaofeng, wu.wubin, zhang.zhanghailiang, dengkai1,
yinyipeng1, Yifei Jiang
Add sifive_plic vmstate for supporting sifive_plic migration.
Current vmstate framework only supports one structure parameter
as num field to describe variable length arrays, so introduce
num_enables.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
hw/intc/sifive_plic.c | 26 +++++++++++++++++++++++++-
hw/intc/sifive_plic.h | 1 +
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f42fd695d8..97a1a27a9a 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -30,6 +30,7 @@
#include "hw/intc/sifive_plic.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
#define RISCV_DEBUG_PLIC 0
@@ -448,11 +449,12 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
TYPE_SIFIVE_PLIC, plic->aperture_size);
parse_hart_config(plic);
plic->bitfield_words = (plic->num_sources + 31) >> 5;
+ plic->num_enables = plic->bitfield_words * plic->num_addrs;
plic->source_priority = g_new0(uint32_t, plic->num_sources);
plic->target_priority = g_new(uint32_t, plic->num_addrs);
plic->pending = g_new0(uint32_t, plic->bitfield_words);
plic->claimed = g_new0(uint32_t, plic->bitfield_words);
- plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
+ plic->enable = g_new0(uint32_t, plic->num_enables);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
@@ -472,12 +474,34 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
msi_nonbroken = true;
}
+static const VMStateDescription vmstate_sifive_plic = {
+ .name = "riscv_sifive_plic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
+ num_sources, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
+ num_addrs, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
+ vmstate_info_uint32, uint32_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void sifive_plic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
device_class_set_props(dc, sifive_plic_properties);
dc->realize = sifive_plic_realize;
+ dc->vmsd = &vmstate_sifive_plic;
}
static const TypeInfo sifive_plic_info = {
diff --git a/hw/intc/sifive_plic.h b/hw/intc/sifive_plic.h
index b75b1f145d..1e451a270c 100644
--- a/hw/intc/sifive_plic.h
+++ b/hw/intc/sifive_plic.h
@@ -52,6 +52,7 @@ struct SiFivePLICState {
uint32_t num_addrs;
uint32_t num_harts;
uint32_t bitfield_words;
+ uint32_t num_enables;
PLICAddr *addr_config;
uint32_t *source_priority;
uint32_t *target_priority;
--
2.19.1
^ permalink raw reply related [flat|nested] 22+ messages in thread