All of lore.kernel.org
 help / color / mirror / Atom feed
From: Viresh Kumar <viresh.kumar@linaro.org>
To: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	"Joe.C" <yingjoe.chen@mediatek.com>,
	Eddie Huang <eddie.huang@mediatek.com>,
	Howard Chen <ibanezchen@gmail.com>,
	Ashwin Chaugule <ashwin.chaugule@linaro.org>,
	Mike Turquette <mturquette@linaro.org>,
	Chen Fan <fan.chen@mediatek.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
	Linaro Kernel Mailman List <linaro-kernel@lists.linaro.org>,
	linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v2 1/4] cpufreq-dt: add clock domain and intermediate frequency support
Date: Thu, 5 Mar 2015 09:28:38 +0530	[thread overview]
Message-ID: <CAKohpo=zPsezGs8rqVzx3ChQkavs5z7eFMMETe12pc2mjm-8OA@mail.gmail.com> (raw)
In-Reply-To: <CALx668XCh46yMLajThuVzba9RRSxf+tEkNuMP9J7w-=vsZN8-Q@mail.gmail.com>

On 5 March 2015 at 09:02, Pi-Cheng Chen <pi-cheng.chen@linaro.org> wrote:
> In the case of Mediatek SoC, the intermediate frequency might not be one entry
> of OPP table. To elaborate, the source clock node of the CPUs/Cluster on
> Mediatek SoC is a mux. The mux has several PLLs as parents. When we are
> doing CPU frequency scaling, the mux should re-parent to another stable PLL,
> wait until the original parent PLL become stable, and then switch back to the
> original parent. In this case, we could but we might not want the intermediate
> frequency as part of OPP table. Therefore I save intermediate_freq instead of
> intermediate frequency index in the cpufreq_dt_platform_datat struct.

Hmm, I remember that discussion. Okay leave it as is.

> BTW, is this case that intermediate frequency is not necessarily be one entry
> of OPP table supported in the OPPv2 bindings?

Not yet, but will add a property for that.

WARNING: multiple messages have this Message-ID (diff)
From: Viresh Kumar <viresh.kumar@linaro.org>
To: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	"Joe.C" <yingjoe.chen@mediatek.com>,
	Eddie Huang <eddie.huang@mediatek.com>,
	Howard Chen <ibanezchen@gmail.com>,
	Ashwin Chaugule <ashwin.chaugule@linaro.org>,
	Mike Turquette <mturquette@linaro.org>,
	Chen Fan <fan.chen@mediatek.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	"linux-pm@vger.kernel.org" <linux-pm@vger.k>
Subject: Re: [PATCH v2 1/4] cpufreq-dt: add clock domain and intermediate frequency support
Date: Thu, 5 Mar 2015 09:28:38 +0530	[thread overview]
Message-ID: <CAKohpo=zPsezGs8rqVzx3ChQkavs5z7eFMMETe12pc2mjm-8OA@mail.gmail.com> (raw)
In-Reply-To: <CALx668XCh46yMLajThuVzba9RRSxf+tEkNuMP9J7w-=vsZN8-Q@mail.gmail.com>

On 5 March 2015 at 09:02, Pi-Cheng Chen <pi-cheng.chen@linaro.org> wrote:
> In the case of Mediatek SoC, the intermediate frequency might not be one entry
> of OPP table. To elaborate, the source clock node of the CPUs/Cluster on
> Mediatek SoC is a mux. The mux has several PLLs as parents. When we are
> doing CPU frequency scaling, the mux should re-parent to another stable PLL,
> wait until the original parent PLL become stable, and then switch back to the
> original parent. In this case, we could but we might not want the intermediate
> frequency as part of OPP table. Therefore I save intermediate_freq instead of
> intermediate frequency index in the cpufreq_dt_platform_datat struct.

Hmm, I remember that discussion. Okay leave it as is.

> BTW, is this case that intermediate frequency is not necessarily be one entry
> of OPP table supported in the OPPv2 bindings?

Not yet, but will add a property for that.

WARNING: multiple messages have this Message-ID (diff)
From: viresh.kumar@linaro.org (Viresh Kumar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/4] cpufreq-dt: add clock domain and intermediate frequency support
Date: Thu, 5 Mar 2015 09:28:38 +0530	[thread overview]
Message-ID: <CAKohpo=zPsezGs8rqVzx3ChQkavs5z7eFMMETe12pc2mjm-8OA@mail.gmail.com> (raw)
In-Reply-To: <CALx668XCh46yMLajThuVzba9RRSxf+tEkNuMP9J7w-=vsZN8-Q@mail.gmail.com>

On 5 March 2015 at 09:02, Pi-Cheng Chen <pi-cheng.chen@linaro.org> wrote:
> In the case of Mediatek SoC, the intermediate frequency might not be one entry
> of OPP table. To elaborate, the source clock node of the CPUs/Cluster on
> Mediatek SoC is a mux. The mux has several PLLs as parents. When we are
> doing CPU frequency scaling, the mux should re-parent to another stable PLL,
> wait until the original parent PLL become stable, and then switch back to the
> original parent. In this case, we could but we might not want the intermediate
> frequency as part of OPP table. Therefore I save intermediate_freq instead of
> intermediate frequency index in the cpufreq_dt_platform_datat struct.

Hmm, I remember that discussion. Okay leave it as is.

> BTW, is this case that intermediate frequency is not necessarily be one entry
> of OPP table supported in the OPPv2 bindings?

Not yet, but will add a property for that.

  reply	other threads:[~2015-03-05  3:58 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-04  8:49 [PATCH v2 0/4] cpufreq: add cpufreq driver for Mediatek MT8173 SoC pi-cheng.chen
2015-03-04  8:49 ` pi-cheng.chen
2015-03-04  8:49 ` [PATCH v2 1/4] cpufreq-dt: add clock domain and intermediate frequency support pi-cheng.chen
2015-03-04  8:49   ` pi-cheng.chen
2015-03-04  8:49   ` pi-cheng.chen
2015-03-04 10:15   ` Viresh Kumar
2015-03-04 10:15     ` Viresh Kumar
2015-03-04 10:15     ` Viresh Kumar
2015-03-04 10:17     ` Viresh Kumar
2015-03-04 10:17       ` Viresh Kumar
2015-03-04 10:17       ` Viresh Kumar
2015-03-05  3:32     ` Pi-Cheng Chen
2015-03-05  3:32       ` Pi-Cheng Chen
2015-03-05  3:32       ` Pi-Cheng Chen
2015-03-05  3:58       ` Viresh Kumar [this message]
2015-03-05  3:58         ` Viresh Kumar
2015-03-05  3:58         ` Viresh Kumar
2015-03-05  7:28         ` Pi-Cheng Chen
2015-03-05  7:28           ` Pi-Cheng Chen
2015-03-05  7:28           ` Pi-Cheng Chen
2015-03-04  8:49 ` [PATCH v2 2/4] cpufreq: dt-bindings: add bindings for mtk-cpufreq driver pi-cheng.chen
2015-03-04  8:49   ` pi-cheng.chen
2015-03-04 10:29   ` Viresh Kumar
2015-03-04 10:29     ` Viresh Kumar
2015-03-04 10:29     ` Viresh Kumar
2015-03-04  8:49 ` [PATCH v2 3/4] cpufreq: mediatek: add Mediatek cpufreq driver pi-cheng.chen
2015-03-04  8:49   ` pi-cheng.chen
2015-03-04 11:09   ` Viresh Kumar
2015-03-04 11:09     ` Viresh Kumar
2015-03-04 11:09     ` Viresh Kumar
2015-03-05  7:27     ` Pi-Cheng Chen
2015-03-05  7:27       ` Pi-Cheng Chen
2015-03-05  7:27       ` Pi-Cheng Chen
2015-03-05  9:55       ` Viresh Kumar
2015-03-05  9:55         ` Viresh Kumar
2015-03-05  9:55         ` Viresh Kumar
2015-03-06  5:49         ` Pi-Cheng Chen
2015-03-06  5:49           ` Pi-Cheng Chen
2015-03-06  5:49           ` Pi-Cheng Chen
2015-03-10  2:50           ` Viresh Kumar
2015-03-10  2:50             ` Viresh Kumar
2015-03-10  2:50             ` Viresh Kumar
2015-03-11 10:53             ` Mark Brown
2015-03-11 10:53               ` Mark Brown
2015-03-11 10:53               ` Mark Brown
2015-03-11 11:03               ` Viresh Kumar
2015-03-11 11:03                 ` Viresh Kumar
2015-03-11 11:03                 ` Viresh Kumar
2015-03-11 11:42                 ` Lucas Stach
2015-03-11 11:42                   ` Lucas Stach
2015-03-11 11:42                   ` Lucas Stach
2015-03-11 11:46                   ` Viresh Kumar
2015-03-11 11:46                     ` Viresh Kumar
2015-03-11 11:46                     ` Viresh Kumar
2015-03-11 12:46                     ` Mark Brown
2015-03-11 12:46                       ` Mark Brown
2015-03-11 12:46                       ` Mark Brown
2015-03-11 12:45                 ` Mark Brown
2015-03-11 12:45                   ` Mark Brown
2015-03-11 12:45                   ` Mark Brown
2015-03-12  9:28                   ` Viresh Kumar
2015-03-12  9:28                     ` Viresh Kumar
2015-03-12  9:28                     ` Viresh Kumar
2015-03-12 11:15                     ` Pi-Cheng Chen
2015-03-12 11:15                       ` Pi-Cheng Chen
2015-03-12 11:15                       ` Pi-Cheng Chen
2015-03-18  6:59                       ` Viresh Kumar
2015-03-18  6:59                         ` Viresh Kumar
2015-03-18  6:59                         ` Viresh Kumar
2015-03-09 16:28   ` Russell King - ARM Linux
2015-03-09 16:28     ` Russell King - ARM Linux
2015-03-10  1:57     ` Pi-Cheng Chen
2015-03-10  1:57       ` Pi-Cheng Chen
2015-03-10  1:57       ` Pi-Cheng Chen
2015-03-04  8:49 ` [PATCH v2 4/4] ARM64: dts: mediatek: add cpufreq dts for MT8173 SoC pi-cheng.chen
2015-03-04  8:49   ` pi-cheng.chen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAKohpo=zPsezGs8rqVzx3ChQkavs5z7eFMMETe12pc2mjm-8OA@mail.gmail.com' \
    --to=viresh.kumar@linaro.org \
    --cc=ashwin.chaugule@linaro.org \
    --cc=catalin.marinas@arm.com \
    --cc=devicetree@vger.kernel.org \
    --cc=eddie.huang@mediatek.com \
    --cc=fan.chen@mediatek.com \
    --cc=galak@codeaurora.org \
    --cc=ibanezchen@gmail.com \
    --cc=ijc+devicetree@hellion.org.uk \
    --cc=linaro-kernel@lists.linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=matthias.bgg@gmail.com \
    --cc=mturquette@linaro.org \
    --cc=pawel.moll@arm.com \
    --cc=pi-cheng.chen@linaro.org \
    --cc=rjw@rjwysocki.net \
    --cc=robh+dt@kernel.org \
    --cc=thomas.petazzoni@free-electrons.com \
    --cc=will.deacon@arm.com \
    --cc=yingjoe.chen@mediatek.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.