* [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-10-28 16:59 ` Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
entry-class social infrastructure gateway control and industrial gateway
control.
This patch series adds initial SoC DTSi support for Renesas RZ/Five
(R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Useful links:
-------------
[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
[1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Patch series depends on the below patches (which are queued in the Renesas tree for v6.2):
------------------------------------------------------------------------------------
[0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=c27ce08b806d606cd5cd0e8252d1ed2b729b5b55
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=7dd1d57c052e88f98b9e9145461b13bca019d108
[2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-soc-for-v6.2&id=b3acbca3c80e612478b354e43c1480c3fc15873e
[3] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=49669da644cf000eb79dbede55bd04acf3f2f0a0
[4] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=b9a0be2054964026aa58966ce9724b672f210835
v4 -> v5:
---------
* Rebased patches on -next
* Included RB tags
* Dropped patches #1 and #4 (form v4) as they are queued up by Renesas trees
* Patch #7 from v4 was not needed anymore so dropped it
* Patches #4 and #5 are new
v4: https://lore.kernel.org/all/20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Below are the logs from RZ/Five SMARC EVK:
------------------------------------------
/ # uname -ra;
Linux (none) 6.1.0-rc2-00036-gbad82a074f62 #145 SMP Fri Oct 28 17:18:41 BST 2022 riscv64 GNU/Linux
/ # cat /proc/cpuinfo;
processor : 0
hart : 0
isa : rv64imafdc
mmu : sv39
uarch : andestech,ax45mp
mvendorid : 0x31e
marchid : 0x8000000000008a45
mimpid : 0x500
/ # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
soc0/$i; done
machine: Renesas SMARC EVK based on r9a07g043f01
family: RZ/Five
soc_id: r9a07g043
revision: 0
/ #
/ # cat /proc/interrupts
CPU0
1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
2: 16 SiFive PLIC 414 Level 1004b800.serial:rx full
3: 402 SiFive PLIC 415 Level 1004b800.serial:tx empty
4: 0 SiFive PLIC 413 Level 1004b800.serial:break
5: 41826 RISC-V INTC 5 Edge riscv-timer
6: 10 SiFive PLIC 416 Level 1004b800.serial:rx ready
IPI0: 0 Rescheduling interrupts
IPI1: 0 Function call interrupts
IPI2: 0 CPU stop interrupts
IPI3: 0 IRQ work interrupts
IPI4: 0 Timer broadcast interrupts
/ #
/ # cat /proc/meminfo
MemTotal: 882252 kB
MemFree: 860848 kB
MemAvailable: 858608 kB
Buffers: 0 kB
Cached: 1796 kB
SwapCached: 0 kB
Active: 0 kB
Inactive: 72 kB
Active(anon): 0 kB
Inactive(anon): 72 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 1796 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 108 kB
Mapped: 1200 kB
Shmem: 0 kB
KReclaimable: 6760 kB
Slab: 12360 kB
SReclaimable: 6760 kB
SUnreclaim: 5600 kB
KernelStack: 620 kB
PageTables: 32 kB
SecPageTables: 0 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 441124 kB
Committed_AS: 592 kB
VmallocTotal: 67108864 kB
VmallocUsed: 1132 kB
VmallocChunk: 0 kB
Percpu: 84 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
/ #
/ #
Cheers,
Prabhakar
Lad Prabhakar (7):
dt-bindings: riscv: Sort the CPU core list alphabetically
dt-bindings: riscv: Add Andes AX45MP core to the list
riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
MAINTAINERS: Add entry for Renesas RISC-V
riscv: configs: defconfig: Enable Renesas RZ/Five SoC
.../devicetree/bindings/riscv/cpus.yaml | 11 ++-
MAINTAINERS | 3 +-
arch/riscv/Kconfig.socs | 5 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 ++++++++++++
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
arch/riscv/configs/defconfig | 3 +
10 files changed, 252 insertions(+), 6 deletions(-)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
2022-10-28 16:59 ` Prabhakar
@ 2022-10-28 16:59 ` Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar, Krzysztof Kozlowski
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v4 -> v5
* Included RB tag from Conor
v3 -> v4
* Included RB tag from Heiko
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included RB tag from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 90a7cabf58fe..ae7963e99225 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,17 +28,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
@ 2022-10-28 16:59 ` Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar, Krzysztof Kozlowski
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v4 -> v5
* Included RB tag from Conor
v3 -> v4
* Included RB tag from Heiko
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included RB tag from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 90a7cabf58fe..ae7963e99225 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,17 +28,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 92+ messages in thread* Re: [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
2022-10-28 16:59 ` Prabhakar
@ 2022-10-29 4:20 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:20 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar, Krzysztof Kozlowski
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Sort the CPU cores list alphabetically for maintenance.
Reviewed-by: Guo Ren <guoren@kernel.org>
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Included RB tag from Conor
>
> v3 -> v4
> * Included RB tag from Heiko
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * Included RB tag from Krzysztof
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 90a7cabf58fe..ae7963e99225 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -28,17 +28,17 @@ properties:
> oneOf:
> - items:
> - enum:
> - - sifive,rocket0
> + - canaan,k210
> - sifive,bullet0
> - sifive,e5
> - sifive,e7
> - sifive,e71
> - - sifive,u74-mc
> - - sifive,u54
> - - sifive,u74
> + - sifive,rocket0
> - sifive,u5
> + - sifive,u54
> - sifive,u7
> - - canaan,k210
> + - sifive,u74
> + - sifive,u74-mc
> - const: riscv
> - items:
> - enum:
> --
> 2.25.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
@ 2022-10-29 4:20 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:20 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar, Krzysztof Kozlowski
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Sort the CPU cores list alphabetically for maintenance.
Reviewed-by: Guo Ren <guoren@kernel.org>
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Included RB tag from Conor
>
> v3 -> v4
> * Included RB tag from Heiko
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * Included RB tag from Krzysztof
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 90a7cabf58fe..ae7963e99225 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -28,17 +28,17 @@ properties:
> oneOf:
> - items:
> - enum:
> - - sifive,rocket0
> + - canaan,k210
> - sifive,bullet0
> - sifive,e5
> - sifive,e7
> - sifive,e71
> - - sifive,u74-mc
> - - sifive,u54
> - - sifive,u74
> + - sifive,rocket0
> - sifive,u5
> + - sifive,u54
> - sifive,u7
> - - canaan,k210
> + - sifive,u74
> + - sifive,u74-mc
> - const: riscv
> - items:
> - enum:
> --
> 2.25.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
2022-10-28 16:59 ` Prabhakar
@ 2022-10-28 16:59 ` Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar, Krzysztof Kozlowski
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v4 -> v5
* Included RB tag from Conor
v3 -> v4
* No change
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included ack from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index ae7963e99225..2bf91829c8de 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,6 +28,7 @@ properties:
oneOf:
- items:
- enum:
+ - andestech,ax45mp
- canaan,k210
- sifive,bullet0
- sifive,e5
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
@ 2022-10-28 16:59 ` Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar, Krzysztof Kozlowski
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v4 -> v5
* Included RB tag from Conor
v3 -> v4
* No change
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included ack from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index ae7963e99225..2bf91829c8de 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,6 +28,7 @@ properties:
oneOf:
- items:
- enum:
+ - andestech,ax45mp
- canaan,k210
- sifive,bullet0
- sifive,e5
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 92+ messages in thread* Re: [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
2022-10-28 16:59 ` Prabhakar
@ 2022-10-29 4:20 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:20 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar, Krzysztof Kozlowski
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
>
> More details about Andes AX45MP core can be found here:
> [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Included RB tag from Conor
>
> v3 -> v4
> * No change
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * Included ack from Krzysztof
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index ae7963e99225..2bf91829c8de 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -28,6 +28,7 @@ properties:
> oneOf:
> - items:
> - enum:
> + - andestech,ax45mp
Reviewed-by: Guo Ren <guoren@kernel.org>
> - canaan,k210
> - sifive,bullet0
> - sifive,e5
> --
> 2.25.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
@ 2022-10-29 4:20 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:20 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar, Krzysztof Kozlowski
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
>
> More details about Andes AX45MP core can be found here:
> [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Included RB tag from Conor
>
> v3 -> v4
> * No change
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * Included ack from Krzysztof
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index ae7963e99225..2bf91829c8de 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -28,6 +28,7 @@ properties:
> oneOf:
> - items:
> - enum:
> + - andestech,ax45mp
Reviewed-by: Guo Ren <guoren@kernel.org>
> - canaan,k210
> - sifive,bullet0
> - sifive,e5
> --
> 2.25.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
2022-10-28 16:59 ` Prabhakar
@ 2022-10-28 16:59 ` Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v4 -> v5
* Sorted as per SoC name
* Included RB tag from Conor
v3 -> v4
* Dropped SOC_RENESAS_RZFIVE config option
* Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
under ARCH_RENESAS
* Updated commit message
* Dropped RB tag
* Used riscv instead of RISC-V in subject line
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* No Change
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..75fb0390d6bd 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE
help
This enables support for Microchip PolarFire SoC platforms.
+config ARCH_RENESAS
+ bool "Renesas RISC-V SoCs"
+ help
+ This enables support for the RISC-V based Renesas SoCs.
+
config SOC_SIFIVE
bool "SiFive SoCs"
select SERIAL_SIFIVE if TTY
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
@ 2022-10-28 16:59 ` Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v4 -> v5
* Sorted as per SoC name
* Included RB tag from Conor
v3 -> v4
* Dropped SOC_RENESAS_RZFIVE config option
* Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
under ARCH_RENESAS
* Updated commit message
* Dropped RB tag
* Used riscv instead of RISC-V in subject line
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* No Change
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..75fb0390d6bd 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE
help
This enables support for Microchip PolarFire SoC platforms.
+config ARCH_RENESAS
+ bool "Renesas RISC-V SoCs"
+ help
+ This enables support for the RISC-V based Renesas SoCs.
+
config SOC_SIFIVE
bool "SiFive SoCs"
select SERIAL_SIFIVE if TTY
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 92+ messages in thread
* Re: [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
2022-10-28 16:59 ` Prabhakar
@ 2022-10-29 4:18 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:18 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
> We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Sorted as per SoC name
> * Included RB tag from Conor
>
> v3 -> v4
> * Dropped SOC_RENESAS_RZFIVE config option
> * Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
> under ARCH_RENESAS
> * Updated commit message
> * Dropped RB tag
> * Used riscv instead of RISC-V in subject line
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * No Change
> ---
> arch/riscv/Kconfig.socs | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..75fb0390d6bd 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE
> help
> This enables support for Microchip PolarFire SoC platforms.
>
> +config ARCH_RENESAS
> + bool "Renesas RISC-V SoCs"
> + help
> + This enables support for the RISC-V based Renesas SoCs.
> +
Looks good.
Reviewed-by: Guo Ren <guoren@kernel.org>
> config SOC_SIFIVE
> bool "SiFive SoCs"
> select SERIAL_SIFIVE if TTY
> --
> 2.25.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
@ 2022-10-29 4:18 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:18 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
> We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Sorted as per SoC name
> * Included RB tag from Conor
>
> v3 -> v4
> * Dropped SOC_RENESAS_RZFIVE config option
> * Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
> under ARCH_RENESAS
> * Updated commit message
> * Dropped RB tag
> * Used riscv instead of RISC-V in subject line
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * No Change
> ---
> arch/riscv/Kconfig.socs | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..75fb0390d6bd 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE
> help
> This enables support for Microchip PolarFire SoC platforms.
>
> +config ARCH_RENESAS
> + bool "Renesas RISC-V SoCs"
> + help
> + This enables support for the RISC-V based Renesas SoCs.
> +
Looks good.
Reviewed-by: Guo Ren <guoren@kernel.org>
> config SOC_SIFIVE
> bool "SiFive SoCs"
> select SERIAL_SIFIVE if TTY
> --
> 2.25.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
2022-10-28 16:59 ` Prabhakar
@ 2022-11-08 15:37 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 15:37 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
> We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Sorted as per SoC name
> * Included RB tag from Conor
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
@ 2022-11-08 15:37 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 15:37 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
> We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Sorted as per SoC name
> * Included RB tag from Conor
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-28 16:59 ` Prabhakar
@ 2022-10-28 16:59 ` Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).
RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
Below are the RZ/Five SoC specific blocks added in the initial DTSI which
can be used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- PLIC
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4 -> v5
* Fixed riscv,ndev value (should be 511)
* Reworked completely (sort of new patch)
v3 -> v4
* No change
v2 -> v3
* Fixed clock entry for CPU core
* Fixed timebase frequency to 12MHz
* Fixed sorting of the nodes
* Included RB tags
v1 -> v2
* Dropped including makefile change
* Updated ndev count
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
new file mode 100644
index 000000000000..50134be548f5
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
+
+#include <arm64/renesas/r9a07g043.dtsi>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <12000000>;
+
+ cpu0: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x40>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x40>;
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+};
+
+&soc {
+ interrupt-parent = <&plic>;
+
+ plic: interrupt-controller@12c00000 {
+ compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ riscv,ndev = <511>;
+ interrupt-controller;
+ reg = <0x0 0x12c00000 0 0x400000>;
+ clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-28 16:59 ` Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).
RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
Below are the RZ/Five SoC specific blocks added in the initial DTSI which
can be used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- PLIC
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4 -> v5
* Fixed riscv,ndev value (should be 511)
* Reworked completely (sort of new patch)
v3 -> v4
* No change
v2 -> v3
* Fixed clock entry for CPU core
* Fixed timebase frequency to 12MHz
* Fixed sorting of the nodes
* Included RB tags
v1 -> v2
* Dropped including makefile change
* Updated ndev count
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
new file mode 100644
index 000000000000..50134be548f5
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
+
+#include <arm64/renesas/r9a07g043.dtsi>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <12000000>;
+
+ cpu0: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x40>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x40>;
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+};
+
+&soc {
+ interrupt-parent = <&plic>;
+
+ plic: interrupt-controller@12c00000 {
+ compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ riscv,ndev = <511>;
+ interrupt-controller;
+ reg = <0x0 0x12c00000 0 0x400000>;
+ clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+ };
+};
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-28 16:59 ` Prabhakar
@ 2022-10-29 4:25 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:25 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
>
> Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - PLIC
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Fixed riscv,ndev value (should be 511)
> * Reworked completely (sort of new patch)
>
> v3 -> v4
> * No change
>
> v2 -> v3
> * Fixed clock entry for CPU core
> * Fixed timebase frequency to 12MHz
> * Fixed sorting of the nodes
> * Included RB tags
>
> v1 -> v2
> * Dropped including makefile change
> * Updated ndev count
> ---
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> 1 file changed, 57 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
>
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> new file mode 100644
> index 000000000000..50134be548f5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> +
> +#include <arm64/renesas/r9a07g043.dtsi>
The initial patch shouldn't be broken. Combine them together with the
minimal components and add others late. Don't separate the DTS files.
> +
> +/ {
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <12000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "andestech,ax45mp", "riscv";
> + device_type = "cpu";
> + reg = <0x0>;
> + status = "okay";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <0x40>;
> + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +};
> +
> +&soc {
> + interrupt-parent = <&plic>;
> +
> + plic: interrupt-controller@12c00000 {
> + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + riscv,ndev = <511>;
> + interrupt-controller;
> + reg = <0x0 0x12c00000 0 0x400000>;
> + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
Ditto, Where is cpg? in r9a07g043.dtsi?
> + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> + };
> +};
> --
> 2.25.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-29 4:25 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:25 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
>
> Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - PLIC
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Fixed riscv,ndev value (should be 511)
> * Reworked completely (sort of new patch)
>
> v3 -> v4
> * No change
>
> v2 -> v3
> * Fixed clock entry for CPU core
> * Fixed timebase frequency to 12MHz
> * Fixed sorting of the nodes
> * Included RB tags
>
> v1 -> v2
> * Dropped including makefile change
> * Updated ndev count
> ---
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> 1 file changed, 57 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
>
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> new file mode 100644
> index 000000000000..50134be548f5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> +
> +#include <arm64/renesas/r9a07g043.dtsi>
The initial patch shouldn't be broken. Combine them together with the
minimal components and add others late. Don't separate the DTS files.
> +
> +/ {
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <12000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "andestech,ax45mp", "riscv";
> + device_type = "cpu";
> + reg = <0x0>;
> + status = "okay";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <0x40>;
> + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +};
> +
> +&soc {
> + interrupt-parent = <&plic>;
> +
> + plic: interrupt-controller@12c00000 {
> + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + riscv,ndev = <511>;
> + interrupt-controller;
> + reg = <0x0 0x12c00000 0 0x400000>;
> + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
Ditto, Where is cpg? in r9a07g043.dtsi?
> + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> + };
> +};
> --
> 2.25.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-29 4:25 ` Guo Ren
@ 2022-10-29 19:10 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-29 19:10 UTC (permalink / raw)
To: Guo Ren
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Guo,
Thank you for the review.
On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
>
> On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> >
> > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - PLIC
> >
> > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v4 -> v5
> > * Fixed riscv,ndev value (should be 511)
> > * Reworked completely (sort of new patch)
> >
> > v3 -> v4
> > * No change
> >
> > v2 -> v3
> > * Fixed clock entry for CPU core
> > * Fixed timebase frequency to 12MHz
> > * Fixed sorting of the nodes
> > * Included RB tags
> >
> > v1 -> v2
> > * Dropped including makefile change
> > * Updated ndev count
> > ---
> > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > 1 file changed, 57 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > new file mode 100644
> > index 000000000000..50134be548f5
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -0,0 +1,57 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > +
> > +#include <arm64/renesas/r9a07g043.dtsi>
> The initial patch shouldn't be broken. Combine them together with the
> minimal components and add others late. Don't separate the DTS files.
>
r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
more patches [1] which are required and are currently queued up in the
Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
letter).
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> > +
> > +/ {
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <12000000>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "andestech,ax45mp", "riscv";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + status = "okay";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <0x40>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <0x40>;
> > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&soc {
> > + interrupt-parent = <&plic>;
> > +
> > + plic: interrupt-controller@12c00000 {
> > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > + #interrupt-cells = <2>;
> > + #address-cells = <0>;
> > + riscv,ndev = <511>;
> > + interrupt-controller;
> > + reg = <0x0 0x12c00000 0 0x400000>;
> > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> Ditto, Where is cpg? in r9a07g043.dtsi?
>
Yes CPG node is in r9a07g043.dtsi.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-29 19:10 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-29 19:10 UTC (permalink / raw)
To: Guo Ren
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Guo,
Thank you for the review.
On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
>
> On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> >
> > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - PLIC
> >
> > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v4 -> v5
> > * Fixed riscv,ndev value (should be 511)
> > * Reworked completely (sort of new patch)
> >
> > v3 -> v4
> > * No change
> >
> > v2 -> v3
> > * Fixed clock entry for CPU core
> > * Fixed timebase frequency to 12MHz
> > * Fixed sorting of the nodes
> > * Included RB tags
> >
> > v1 -> v2
> > * Dropped including makefile change
> > * Updated ndev count
> > ---
> > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > 1 file changed, 57 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > new file mode 100644
> > index 000000000000..50134be548f5
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -0,0 +1,57 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > +
> > +#include <arm64/renesas/r9a07g043.dtsi>
> The initial patch shouldn't be broken. Combine them together with the
> minimal components and add others late. Don't separate the DTS files.
>
r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
more patches [1] which are required and are currently queued up in the
Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
letter).
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> > +
> > +/ {
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <12000000>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "andestech,ax45mp", "riscv";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + status = "okay";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <0x40>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <0x40>;
> > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&soc {
> > + interrupt-parent = <&plic>;
> > +
> > + plic: interrupt-controller@12c00000 {
> > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > + #interrupt-cells = <2>;
> > + #address-cells = <0>;
> > + riscv,ndev = <511>;
> > + interrupt-controller;
> > + reg = <0x0 0x12c00000 0 0x400000>;
> > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> Ditto, Where is cpg? in r9a07g043.dtsi?
>
Yes CPG node is in r9a07g043.dtsi.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-29 19:10 ` Lad, Prabhakar
@ 2022-10-30 0:02 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-30 0:02 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Guo,
>
> Thank you for the review.
>
> On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> >
> > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > Single).
> > >
> > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > >
> > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > - AX45MP CPU
> > > - PLIC
> > >
> > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v4 -> v5
> > > * Fixed riscv,ndev value (should be 511)
> > > * Reworked completely (sort of new patch)
> > >
> > > v3 -> v4
> > > * No change
> > >
> > > v2 -> v3
> > > * Fixed clock entry for CPU core
> > > * Fixed timebase frequency to 12MHz
> > > * Fixed sorting of the nodes
> > > * Included RB tags
> > >
> > > v1 -> v2
> > > * Dropped including makefile change
> > > * Updated ndev count
> > > ---
> > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > 1 file changed, 57 insertions(+)
> > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > >
> > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > new file mode 100644
> > > index 000000000000..50134be548f5
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > @@ -0,0 +1,57 @@
> > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +/*
> > > + * Device Tree Source for the RZ/Five SoC
> > > + *
> > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > +
> > > +#include <arm64/renesas/r9a07g043.dtsi>
> > The initial patch shouldn't be broken. Combine them together with the
> > minimal components and add others late. Don't separate the DTS files.
> >
> r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> more patches [1] which are required and are currently queued up in the
> Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> letter).
You could just move the below part to the second dtsi patch. Then
compile won't be broken.
clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> > > +
> > > +/ {
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + timebase-frequency = <12000000>;
> > > +
> > > + cpu0: cpu@0 {
> > > + compatible = "andestech,ax45mp", "riscv";
> > > + device_type = "cpu";
> > > + reg = <0x0>;
> > > + status = "okay";
> > > + riscv,isa = "rv64imafdc";
> > > + mmu-type = "riscv,sv39";
> > > + i-cache-size = <0x8000>;
> > > + i-cache-line-size = <0x40>;
> > > + d-cache-size = <0x8000>;
> > > + d-cache-line-size = <0x40>;
> > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> > > +
> > > + cpu0_intc: interrupt-controller {
> > > + #interrupt-cells = <1>;
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&soc {
> > > + interrupt-parent = <&plic>;
> > > +
> > > + plic: interrupt-controller@12c00000 {
> > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > > + #interrupt-cells = <2>;
> > > + #address-cells = <0>;
> > > + riscv,ndev = <511>;
> > > + interrupt-controller;
> > > + reg = <0x0 0x12c00000 0 0x400000>;
> > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > + power-domains = <&cpg>;
> > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > Ditto, Where is cpg? in r9a07g043.dtsi?
> >
> Yes CPG node is in r9a07g043.dtsi.
>
> Cheers,
> Prabhakar
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-30 0:02 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-30 0:02 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Guo,
>
> Thank you for the review.
>
> On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> >
> > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > Single).
> > >
> > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > >
> > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > - AX45MP CPU
> > > - PLIC
> > >
> > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v4 -> v5
> > > * Fixed riscv,ndev value (should be 511)
> > > * Reworked completely (sort of new patch)
> > >
> > > v3 -> v4
> > > * No change
> > >
> > > v2 -> v3
> > > * Fixed clock entry for CPU core
> > > * Fixed timebase frequency to 12MHz
> > > * Fixed sorting of the nodes
> > > * Included RB tags
> > >
> > > v1 -> v2
> > > * Dropped including makefile change
> > > * Updated ndev count
> > > ---
> > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > 1 file changed, 57 insertions(+)
> > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > >
> > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > new file mode 100644
> > > index 000000000000..50134be548f5
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > @@ -0,0 +1,57 @@
> > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +/*
> > > + * Device Tree Source for the RZ/Five SoC
> > > + *
> > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > +
> > > +#include <arm64/renesas/r9a07g043.dtsi>
> > The initial patch shouldn't be broken. Combine them together with the
> > minimal components and add others late. Don't separate the DTS files.
> >
> r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> more patches [1] which are required and are currently queued up in the
> Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> letter).
You could just move the below part to the second dtsi patch. Then
compile won't be broken.
clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> > > +
> > > +/ {
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + timebase-frequency = <12000000>;
> > > +
> > > + cpu0: cpu@0 {
> > > + compatible = "andestech,ax45mp", "riscv";
> > > + device_type = "cpu";
> > > + reg = <0x0>;
> > > + status = "okay";
> > > + riscv,isa = "rv64imafdc";
> > > + mmu-type = "riscv,sv39";
> > > + i-cache-size = <0x8000>;
> > > + i-cache-line-size = <0x40>;
> > > + d-cache-size = <0x8000>;
> > > + d-cache-line-size = <0x40>;
> > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> > > +
> > > + cpu0_intc: interrupt-controller {
> > > + #interrupt-cells = <1>;
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +&soc {
> > > + interrupt-parent = <&plic>;
> > > +
> > > + plic: interrupt-controller@12c00000 {
> > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > > + #interrupt-cells = <2>;
> > > + #address-cells = <0>;
> > > + riscv,ndev = <511>;
> > > + interrupt-controller;
> > > + reg = <0x0 0x12c00000 0 0x400000>;
> > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > + power-domains = <&cpg>;
> > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > Ditto, Where is cpg? in r9a07g043.dtsi?
> >
> Yes CPG node is in r9a07g043.dtsi.
>
> Cheers,
> Prabhakar
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-30 0:02 ` Guo Ren
@ 2022-10-30 18:16 ` Conor Dooley
-1 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-10-30 18:16 UTC (permalink / raw)
To: Guo Ren
Cc: Lad, Prabhakar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote:
> On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Guo,
> >
> > Thank you for the review.
> >
> > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > >
> > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > Single).
> > > >
> > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > >
> > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > - AX45MP CPU
> > > > - PLIC
> > > >
> > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v4 -> v5
> > > > * Fixed riscv,ndev value (should be 511)
> > > > * Reworked completely (sort of new patch)
> > > >
> > > > v3 -> v4
> > > > * No change
> > > >
> > > > v2 -> v3
> > > > * Fixed clock entry for CPU core
> > > > * Fixed timebase frequency to 12MHz
> > > > * Fixed sorting of the nodes
> > > > * Included RB tags
> > > >
> > > > v1 -> v2
> > > > * Dropped including makefile change
> > > > * Updated ndev count
> > > > ---
> > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > 1 file changed, 57 insertions(+)
> > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > new file mode 100644
> > > > index 000000000000..50134be548f5
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > @@ -0,0 +1,57 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +/*
> > > > + * Device Tree Source for the RZ/Five SoC
> > > > + *
> > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > + */
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > +
> > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > +
> > > > +#include <arm64/renesas/r9a07g043.dtsi>
> > > The initial patch shouldn't be broken. Combine them together with the
> > > minimal components and add others late. Don't separate the DTS files.
> > >
> > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > more patches [1] which are required and are currently queued up in the
> > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > letter).
>
> You could just move the below part to the second dtsi patch. Then
> compile won't be broken.
>
> clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> power-domains = <&cpg>;
> resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
The makefile for this directory is not added until the next patch right?
The compile shouldn't be broken here since it therefore cannot be
compiled?
Slightly confused,
Conor.
>
> >
> > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > > > +
> > > > +/ {
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + timebase-frequency = <12000000>;
> > > > +
> > > > + cpu0: cpu@0 {
> > > > + compatible = "andestech,ax45mp", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <0x0>;
> > > > + status = "okay";
> > > > + riscv,isa = "rv64imafdc";
> > > > + mmu-type = "riscv,sv39";
> > > > + i-cache-size = <0x8000>;
> > > > + i-cache-line-size = <0x40>;
> > > > + d-cache-size = <0x8000>;
> > > > + d-cache-line-size = <0x40>;
> > > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> > > > +
> > > > + cpu0_intc: interrupt-controller {
> > > > + #interrupt-cells = <1>;
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + };
> > > > + };
> > > > + };
> > > > +};
> > > > +
> > > > +&soc {
> > > > + interrupt-parent = <&plic>;
> > > > +
> > > > + plic: interrupt-controller@12c00000 {
> > > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > > > + #interrupt-cells = <2>;
> > > > + #address-cells = <0>;
> > > > + riscv,ndev = <511>;
> > > > + interrupt-controller;
> > > > + reg = <0x0 0x12c00000 0 0x400000>;
> > > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > > + power-domains = <&cpg>;
> > > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > > Ditto, Where is cpg? in r9a07g043.dtsi?
> > >
> > Yes CPG node is in r9a07g043.dtsi.
> >
> > Cheers,
> > Prabhakar
>
>
>
> --
> Best Regards
> Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-30 18:16 ` Conor Dooley
0 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-10-30 18:16 UTC (permalink / raw)
To: Guo Ren
Cc: Lad, Prabhakar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote:
> On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Guo,
> >
> > Thank you for the review.
> >
> > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > >
> > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > Single).
> > > >
> > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > >
> > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > - AX45MP CPU
> > > > - PLIC
> > > >
> > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v4 -> v5
> > > > * Fixed riscv,ndev value (should be 511)
> > > > * Reworked completely (sort of new patch)
> > > >
> > > > v3 -> v4
> > > > * No change
> > > >
> > > > v2 -> v3
> > > > * Fixed clock entry for CPU core
> > > > * Fixed timebase frequency to 12MHz
> > > > * Fixed sorting of the nodes
> > > > * Included RB tags
> > > >
> > > > v1 -> v2
> > > > * Dropped including makefile change
> > > > * Updated ndev count
> > > > ---
> > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > 1 file changed, 57 insertions(+)
> > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > new file mode 100644
> > > > index 000000000000..50134be548f5
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > @@ -0,0 +1,57 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +/*
> > > > + * Device Tree Source for the RZ/Five SoC
> > > > + *
> > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > + */
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > +
> > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > +
> > > > +#include <arm64/renesas/r9a07g043.dtsi>
> > > The initial patch shouldn't be broken. Combine them together with the
> > > minimal components and add others late. Don't separate the DTS files.
> > >
> > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > more patches [1] which are required and are currently queued up in the
> > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > letter).
>
> You could just move the below part to the second dtsi patch. Then
> compile won't be broken.
>
> clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> power-domains = <&cpg>;
> resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
The makefile for this directory is not added until the next patch right?
The compile shouldn't be broken here since it therefore cannot be
compiled?
Slightly confused,
Conor.
>
> >
> > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > > > +
> > > > +/ {
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + timebase-frequency = <12000000>;
> > > > +
> > > > + cpu0: cpu@0 {
> > > > + compatible = "andestech,ax45mp", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <0x0>;
> > > > + status = "okay";
> > > > + riscv,isa = "rv64imafdc";
> > > > + mmu-type = "riscv,sv39";
> > > > + i-cache-size = <0x8000>;
> > > > + i-cache-line-size = <0x40>;
> > > > + d-cache-size = <0x8000>;
> > > > + d-cache-line-size = <0x40>;
> > > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> > > > +
> > > > + cpu0_intc: interrupt-controller {
> > > > + #interrupt-cells = <1>;
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + };
> > > > + };
> > > > + };
> > > > +};
> > > > +
> > > > +&soc {
> > > > + interrupt-parent = <&plic>;
> > > > +
> > > > + plic: interrupt-controller@12c00000 {
> > > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > > > + #interrupt-cells = <2>;
> > > > + #address-cells = <0>;
> > > > + riscv,ndev = <511>;
> > > > + interrupt-controller;
> > > > + reg = <0x0 0x12c00000 0 0x400000>;
> > > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > > + power-domains = <&cpg>;
> > > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > > Ditto, Where is cpg? in r9a07g043.dtsi?
> > >
> > Yes CPG node is in r9a07g043.dtsi.
> >
> > Cheers,
> > Prabhakar
>
>
>
> --
> Best Regards
> Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-30 18:16 ` Conor Dooley
@ 2022-10-30 22:27 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-30 22:27 UTC (permalink / raw)
To: Conor Dooley
Cc: Guo Ren, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Sun, Oct 30, 2022 at 6:16 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote:
> > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > >
> > > Hi Guo,
> > >
> > > Thank you for the review.
> > >
> > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > > >
> > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > > Single).
> > > > >
> > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > > >
> > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > - AX45MP CPU
> > > > > - PLIC
> > > > >
> > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v4 -> v5
> > > > > * Fixed riscv,ndev value (should be 511)
> > > > > * Reworked completely (sort of new patch)
> > > > >
> > > > > v3 -> v4
> > > > > * No change
> > > > >
> > > > > v2 -> v3
> > > > > * Fixed clock entry for CPU core
> > > > > * Fixed timebase frequency to 12MHz
> > > > > * Fixed sorting of the nodes
> > > > > * Included RB tags
> > > > >
> > > > > v1 -> v2
> > > > > * Dropped including makefile change
> > > > > * Updated ndev count
> > > > > ---
> > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > > 1 file changed, 57 insertions(+)
> > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > >
> > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > new file mode 100644
> > > > > index 000000000000..50134be548f5
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > @@ -0,0 +1,57 @@
> > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > +/*
> > > > > + * Device Tree Source for the RZ/Five SoC
> > > > > + *
> > > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > > + */
> > > > > +
> > > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > > +
> > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > > +
> > > > > +#include <arm64/renesas/r9a07g043.dtsi>
> > > > The initial patch shouldn't be broken. Combine them together with the
> > > > minimal components and add others late. Don't separate the DTS files.
> > > >
> > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > > more patches [1] which are required and are currently queued up in the
> > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > > letter).
> >
> > You could just move the below part to the second dtsi patch. Then
> > compile won't be broken.
> >
> > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > power-domains = <&cpg>;
> > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>
> The makefile for this directory is not added until the next patch right?
> The compile shouldn't be broken here since it therefore cannot be
> compiled?
>
These nodes are already present in the kernel [0] so the makefile
change in the next patch if made here still won't break the
compilation alone of SoC DTSI (included in dts).
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-30 22:27 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-30 22:27 UTC (permalink / raw)
To: Conor Dooley
Cc: Guo Ren, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Sun, Oct 30, 2022 at 6:16 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote:
> > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > >
> > > Hi Guo,
> > >
> > > Thank you for the review.
> > >
> > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > > >
> > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > > Single).
> > > > >
> > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > > >
> > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > - AX45MP CPU
> > > > > - PLIC
> > > > >
> > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v4 -> v5
> > > > > * Fixed riscv,ndev value (should be 511)
> > > > > * Reworked completely (sort of new patch)
> > > > >
> > > > > v3 -> v4
> > > > > * No change
> > > > >
> > > > > v2 -> v3
> > > > > * Fixed clock entry for CPU core
> > > > > * Fixed timebase frequency to 12MHz
> > > > > * Fixed sorting of the nodes
> > > > > * Included RB tags
> > > > >
> > > > > v1 -> v2
> > > > > * Dropped including makefile change
> > > > > * Updated ndev count
> > > > > ---
> > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > > 1 file changed, 57 insertions(+)
> > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > >
> > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > new file mode 100644
> > > > > index 000000000000..50134be548f5
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > @@ -0,0 +1,57 @@
> > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > +/*
> > > > > + * Device Tree Source for the RZ/Five SoC
> > > > > + *
> > > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > > + */
> > > > > +
> > > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > > +
> > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > > +
> > > > > +#include <arm64/renesas/r9a07g043.dtsi>
> > > > The initial patch shouldn't be broken. Combine them together with the
> > > > minimal components and add others late. Don't separate the DTS files.
> > > >
> > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > > more patches [1] which are required and are currently queued up in the
> > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > > letter).
> >
> > You could just move the below part to the second dtsi patch. Then
> > compile won't be broken.
> >
> > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > power-domains = <&cpg>;
> > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>
> The makefile for this directory is not added until the next patch right?
> The compile shouldn't be broken here since it therefore cannot be
> compiled?
>
These nodes are already present in the kernel [0] so the makefile
change in the next patch if made here still won't break the
compilation alone of SoC DTSI (included in dts).
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-30 22:27 ` Lad, Prabhakar
@ 2022-10-30 22:39 ` Conor Dooley
-1 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-10-30 22:39 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Guo Ren, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
On Sun, Oct 30, 2022 at 10:27:17PM +0000, Lad, Prabhakar wrote:
> Hi Conor,
> > > You could just move the below part to the second dtsi patch. Then
> > > compile won't be broken.
> > >
> > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > power-domains = <&cpg>;
> > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> >
> > The makefile for this directory is not added until the next patch right?
> > The compile shouldn't be broken here since it therefore cannot be
> > compiled?
> >
> These nodes are already present in the kernel [0] so the makefile
> change in the next patch if made here still won't break the
> compilation alone of SoC DTSI (included in dts).
Yeah I know, I did actually build the dtb ;)
I was just confused as to how Guo Ren had found a build issue with this
patch that the follow on patch would fix, when this dtsi is not
buildable in this patch.
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-30 22:39 ` Conor Dooley
0 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-10-30 22:39 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Guo Ren, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
On Sun, Oct 30, 2022 at 10:27:17PM +0000, Lad, Prabhakar wrote:
> Hi Conor,
> > > You could just move the below part to the second dtsi patch. Then
> > > compile won't be broken.
> > >
> > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > power-domains = <&cpg>;
> > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> >
> > The makefile for this directory is not added until the next patch right?
> > The compile shouldn't be broken here since it therefore cannot be
> > compiled?
> >
> These nodes are already present in the kernel [0] so the makefile
> change in the next patch if made here still won't break the
> compilation alone of SoC DTSI (included in dts).
Yeah I know, I did actually build the dtb ;)
I was just confused as to how Guo Ren had found a build issue with this
patch that the follow on patch would fix, when this dtsi is not
buildable in this patch.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-30 22:27 ` Lad, Prabhakar
@ 2022-10-31 1:11 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-31 1:11 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
On Mon, Oct 31, 2022 at 6:27 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Conor,
>
> On Sun, Oct 30, 2022 at 6:16 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote:
> > > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > >
> > > > Hi Guo,
> > > >
> > > > Thank you for the review.
> > > >
> > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > > > >
> > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > >
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > > > Single).
> > > > > >
> > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > > > >
> > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > > - AX45MP CPU
> > > > > > - PLIC
> > > > > >
> > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > ---
> > > > > > v4 -> v5
> > > > > > * Fixed riscv,ndev value (should be 511)
> > > > > > * Reworked completely (sort of new patch)
> > > > > >
> > > > > > v3 -> v4
> > > > > > * No change
> > > > > >
> > > > > > v2 -> v3
> > > > > > * Fixed clock entry for CPU core
> > > > > > * Fixed timebase frequency to 12MHz
> > > > > > * Fixed sorting of the nodes
> > > > > > * Included RB tags
> > > > > >
> > > > > > v1 -> v2
> > > > > > * Dropped including makefile change
> > > > > > * Updated ndev count
> > > > > > ---
> > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > > > 1 file changed, 57 insertions(+)
> > > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > >
> > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > > new file mode 100644
> > > > > > index 000000000000..50134be548f5
> > > > > > --- /dev/null
> > > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > > @@ -0,0 +1,57 @@
> > > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > +/*
> > > > > > + * Device Tree Source for the RZ/Five SoC
> > > > > > + *
> > > > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > > > + */
> > > > > > +
> > > > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > > > +
> > > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > > > +
> > > > > > +#include <arm64/renesas/r9a07g043.dtsi>
> > > > > The initial patch shouldn't be broken. Combine them together with the
> > > > > minimal components and add others late. Don't separate the DTS files.
> > > > >
> > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > > > more patches [1] which are required and are currently queued up in the
> > > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > > > letter).
> > >
> > > You could just move the below part to the second dtsi patch. Then
> > > compile won't be broken.
> > >
> > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > power-domains = <&cpg>;
> > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> >
> > The makefile for this directory is not added until the next patch right?
> > The compile shouldn't be broken here since it therefore cannot be
> > compiled?
> >
> These nodes are already present in the kernel [0] so the makefile
> change in the next patch if made here still won't break the
> compilation alone of SoC DTSI (included in dts).
Oh... Sorry, I screwed up. The
arch/arm64/boot/dts/renesas/r9a07g043.dtsi is not belonged to the
patch series.
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563
>
> Cheers,
> Prabhakar
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-31 1:11 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-31 1:11 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
On Mon, Oct 31, 2022 at 6:27 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Conor,
>
> On Sun, Oct 30, 2022 at 6:16 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote:
> > > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > >
> > > > Hi Guo,
> > > >
> > > > Thank you for the review.
> > > >
> > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > > > >
> > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > >
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > > > Single).
> > > > > >
> > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > > > >
> > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > > - AX45MP CPU
> > > > > > - PLIC
> > > > > >
> > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > ---
> > > > > > v4 -> v5
> > > > > > * Fixed riscv,ndev value (should be 511)
> > > > > > * Reworked completely (sort of new patch)
> > > > > >
> > > > > > v3 -> v4
> > > > > > * No change
> > > > > >
> > > > > > v2 -> v3
> > > > > > * Fixed clock entry for CPU core
> > > > > > * Fixed timebase frequency to 12MHz
> > > > > > * Fixed sorting of the nodes
> > > > > > * Included RB tags
> > > > > >
> > > > > > v1 -> v2
> > > > > > * Dropped including makefile change
> > > > > > * Updated ndev count
> > > > > > ---
> > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > > > 1 file changed, 57 insertions(+)
> > > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > >
> > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > > new file mode 100644
> > > > > > index 000000000000..50134be548f5
> > > > > > --- /dev/null
> > > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > > @@ -0,0 +1,57 @@
> > > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > +/*
> > > > > > + * Device Tree Source for the RZ/Five SoC
> > > > > > + *
> > > > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > > > + */
> > > > > > +
> > > > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > > > +
> > > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > > > +
> > > > > > +#include <arm64/renesas/r9a07g043.dtsi>
> > > > > The initial patch shouldn't be broken. Combine them together with the
> > > > > minimal components and add others late. Don't separate the DTS files.
> > > > >
> > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > > > more patches [1] which are required and are currently queued up in the
> > > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > > > letter).
> > >
> > > You could just move the below part to the second dtsi patch. Then
> > > compile won't be broken.
> > >
> > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > power-domains = <&cpg>;
> > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> >
> > The makefile for this directory is not added until the next patch right?
> > The compile shouldn't be broken here since it therefore cannot be
> > compiled?
> >
> These nodes are already present in the kernel [0] so the makefile
> change in the next patch if made here still won't break the
> compilation alone of SoC DTSI (included in dts).
Oh... Sorry, I screwed up. The
arch/arm64/boot/dts/renesas/r9a07g043.dtsi is not belonged to the
patch series.
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563
>
> Cheers,
> Prabhakar
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-30 18:16 ` Conor Dooley
@ 2022-10-31 0:45 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-31 0:45 UTC (permalink / raw)
To: Conor Dooley
Cc: Lad, Prabhakar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
On Mon, Oct 31, 2022 at 2:16 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote:
> > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > >
> > > Hi Guo,
> > >
> > > Thank you for the review.
> > >
> > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > > >
> > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > > Single).
> > > > >
> > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > > >
> > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > - AX45MP CPU
> > > > > - PLIC
> > > > >
> > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v4 -> v5
> > > > > * Fixed riscv,ndev value (should be 511)
> > > > > * Reworked completely (sort of new patch)
> > > > >
> > > > > v3 -> v4
> > > > > * No change
> > > > >
> > > > > v2 -> v3
> > > > > * Fixed clock entry for CPU core
> > > > > * Fixed timebase frequency to 12MHz
> > > > > * Fixed sorting of the nodes
> > > > > * Included RB tags
> > > > >
> > > > > v1 -> v2
> > > > > * Dropped including makefile change
> > > > > * Updated ndev count
> > > > > ---
> > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > > 1 file changed, 57 insertions(+)
> > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > >
> > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > new file mode 100644
> > > > > index 000000000000..50134be548f5
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > @@ -0,0 +1,57 @@
> > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > +/*
> > > > > + * Device Tree Source for the RZ/Five SoC
> > > > > + *
> > > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > > + */
> > > > > +
> > > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > > +
> > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > > +
> > > > > +#include <arm64/renesas/r9a07g043.dtsi>
> > > > The initial patch shouldn't be broken. Combine them together with the
> > > > minimal components and add others late. Don't separate the DTS files.
> > > >
> > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > > more patches [1] which are required and are currently queued up in the
> > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > > letter).
> >
> > You could just move the below part to the second dtsi patch. Then
> > compile won't be broken.
> >
> > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > power-domains = <&cpg>;
> > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>
> The makefile for this directory is not added until the next patch right?
> The compile shouldn't be broken here since it therefore cannot be
> compiled?
If you put a DTS without a makefile added, it's an unused code in the
repo. I still prefer to add them one by one and ensure every patch
could be properly compiled.
This patch series unnecessarily broke the compilation of the first patches.
>
> Slightly confused,
> Conor.
>
> >
> > >
> > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> > >
> > > > > +
> > > > > +/ {
> > > > > + cpus {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + timebase-frequency = <12000000>;
> > > > > +
> > > > > + cpu0: cpu@0 {
> > > > > + compatible = "andestech,ax45mp", "riscv";
> > > > > + device_type = "cpu";
> > > > > + reg = <0x0>;
> > > > > + status = "okay";
> > > > > + riscv,isa = "rv64imafdc";
> > > > > + mmu-type = "riscv,sv39";
> > > > > + i-cache-size = <0x8000>;
> > > > > + i-cache-line-size = <0x40>;
> > > > > + d-cache-size = <0x8000>;
> > > > > + d-cache-line-size = <0x40>;
> > > > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> > > > > +
> > > > > + cpu0_intc: interrupt-controller {
> > > > > + #interrupt-cells = <1>;
> > > > > + compatible = "riscv,cpu-intc";
> > > > > + interrupt-controller;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&soc {
> > > > > + interrupt-parent = <&plic>;
> > > > > +
> > > > > + plic: interrupt-controller@12c00000 {
> > > > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > > > > + #interrupt-cells = <2>;
> > > > > + #address-cells = <0>;
> > > > > + riscv,ndev = <511>;
> > > > > + interrupt-controller;
> > > > > + reg = <0x0 0x12c00000 0 0x400000>;
> > > > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > > > + power-domains = <&cpg>;
> > > > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > > > Ditto, Where is cpg? in r9a07g043.dtsi?
> > > >
> > > Yes CPG node is in r9a07g043.dtsi.
> > >
> > > Cheers,
> > > Prabhakar
> >
> >
> >
> > --
> > Best Regards
> > Guo Ren
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-31 0:45 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-31 0:45 UTC (permalink / raw)
To: Conor Dooley
Cc: Lad, Prabhakar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley, Anup Patel,
Atish Patra, Heinrich Schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, Biju Das, Lad Prabhakar
On Mon, Oct 31, 2022 at 2:16 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote:
> > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > >
> > > Hi Guo,
> > >
> > > Thank you for the review.
> > >
> > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > > >
> > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > > Single).
> > > > >
> > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > > >
> > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > - AX45MP CPU
> > > > > - PLIC
> > > > >
> > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v4 -> v5
> > > > > * Fixed riscv,ndev value (should be 511)
> > > > > * Reworked completely (sort of new patch)
> > > > >
> > > > > v3 -> v4
> > > > > * No change
> > > > >
> > > > > v2 -> v3
> > > > > * Fixed clock entry for CPU core
> > > > > * Fixed timebase frequency to 12MHz
> > > > > * Fixed sorting of the nodes
> > > > > * Included RB tags
> > > > >
> > > > > v1 -> v2
> > > > > * Dropped including makefile change
> > > > > * Updated ndev count
> > > > > ---
> > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > > 1 file changed, 57 insertions(+)
> > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > >
> > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > new file mode 100644
> > > > > index 000000000000..50134be548f5
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > > @@ -0,0 +1,57 @@
> > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > +/*
> > > > > + * Device Tree Source for the RZ/Five SoC
> > > > > + *
> > > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > > + */
> > > > > +
> > > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > > +
> > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > > +
> > > > > +#include <arm64/renesas/r9a07g043.dtsi>
> > > > The initial patch shouldn't be broken. Combine them together with the
> > > > minimal components and add others late. Don't separate the DTS files.
> > > >
> > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > > more patches [1] which are required and are currently queued up in the
> > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > > letter).
> >
> > You could just move the below part to the second dtsi patch. Then
> > compile won't be broken.
> >
> > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > power-domains = <&cpg>;
> > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>
> The makefile for this directory is not added until the next patch right?
> The compile shouldn't be broken here since it therefore cannot be
> compiled?
If you put a DTS without a makefile added, it's an unused code in the
repo. I still prefer to add them one by one and ensure every patch
could be properly compiled.
This patch series unnecessarily broke the compilation of the first patches.
>
> Slightly confused,
> Conor.
>
> >
> > >
> > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> > >
> > > > > +
> > > > > +/ {
> > > > > + cpus {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + timebase-frequency = <12000000>;
> > > > > +
> > > > > + cpu0: cpu@0 {
> > > > > + compatible = "andestech,ax45mp", "riscv";
> > > > > + device_type = "cpu";
> > > > > + reg = <0x0>;
> > > > > + status = "okay";
> > > > > + riscv,isa = "rv64imafdc";
> > > > > + mmu-type = "riscv,sv39";
> > > > > + i-cache-size = <0x8000>;
> > > > > + i-cache-line-size = <0x40>;
> > > > > + d-cache-size = <0x8000>;
> > > > > + d-cache-line-size = <0x40>;
> > > > > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> > > > > +
> > > > > + cpu0_intc: interrupt-controller {
> > > > > + #interrupt-cells = <1>;
> > > > > + compatible = "riscv,cpu-intc";
> > > > > + interrupt-controller;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&soc {
> > > > > + interrupt-parent = <&plic>;
> > > > > +
> > > > > + plic: interrupt-controller@12c00000 {
> > > > > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > > > > + #interrupt-cells = <2>;
> > > > > + #address-cells = <0>;
> > > > > + riscv,ndev = <511>;
> > > > > + interrupt-controller;
> > > > > + reg = <0x0 0x12c00000 0 0x400000>;
> > > > > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > > > > + power-domains = <&cpg>;
> > > > > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > > > Ditto, Where is cpg? in r9a07g043.dtsi?
> > > >
> > > Yes CPG node is in r9a07g043.dtsi.
> > >
> > > Cheers,
> > > Prabhakar
> >
> >
> >
> > --
> > Best Regards
> > Guo Ren
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-30 0:02 ` Guo Ren
@ 2022-10-30 22:23 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-30 22:23 UTC (permalink / raw)
To: Guo Ren
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Guo,
On Sun, Oct 30, 2022 at 1:02 AM Guo Ren <guoren@kernel.org> wrote:
>
> On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Guo,
> >
> > Thank you for the review.
> >
> > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > >
> > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > Single).
> > > >
> > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > >
> > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > - AX45MP CPU
> > > > - PLIC
> > > >
> > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v4 -> v5
> > > > * Fixed riscv,ndev value (should be 511)
> > > > * Reworked completely (sort of new patch)
> > > >
> > > > v3 -> v4
> > > > * No change
> > > >
> > > > v2 -> v3
> > > > * Fixed clock entry for CPU core
> > > > * Fixed timebase frequency to 12MHz
> > > > * Fixed sorting of the nodes
> > > > * Included RB tags
> > > >
> > > > v1 -> v2
> > > > * Dropped including makefile change
> > > > * Updated ndev count
> > > > ---
> > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > 1 file changed, 57 insertions(+)
> > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > new file mode 100644
> > > > index 000000000000..50134be548f5
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > @@ -0,0 +1,57 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +/*
> > > > + * Device Tree Source for the RZ/Five SoC
> > > > + *
> > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > + */
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > +
> > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > +
> > > > +#include <arm64/renesas/r9a07g043.dtsi>
^^^ look below...
> > > The initial patch shouldn't be broken. Combine them together with the
> > > minimal components and add others late. Don't separate the DTS files.
> > >
> > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > more patches [1] which are required and are currently queued up in the
> > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > letter).
>
> You could just move the below part to the second dtsi patch. Then
> compile won't be broken.
>
> clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> power-domains = <&cpg>;
> resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>
Compile won't break at all, the CPG node [0] and the pinctrl node [1]
already exists in the kernel which is being re-used by this SoC DTSI.
... the include file above already exists in the kernel and is not
part of the next follow up patch.
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n541
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-10-30 22:23 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-30 22:23 UTC (permalink / raw)
To: Guo Ren
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Guo,
On Sun, Oct 30, 2022 at 1:02 AM Guo Ren <guoren@kernel.org> wrote:
>
> On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Guo,
> >
> > Thank you for the review.
> >
> > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote:
> > >
> > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > > > Single).
> > > >
> > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
> > > >
> > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> > > > can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > - AX45MP CPU
> > > > - PLIC
> > > >
> > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v4 -> v5
> > > > * Fixed riscv,ndev value (should be 511)
> > > > * Reworked completely (sort of new patch)
> > > >
> > > > v3 -> v4
> > > > * No change
> > > >
> > > > v2 -> v3
> > > > * Fixed clock entry for CPU core
> > > > * Fixed timebase frequency to 12MHz
> > > > * Fixed sorting of the nodes
> > > > * Included RB tags
> > > >
> > > > v1 -> v2
> > > > * Dropped including makefile change
> > > > * Updated ndev count
> > > > ---
> > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
> > > > 1 file changed, 57 insertions(+)
> > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > new file mode 100644
> > > > index 000000000000..50134be548f5
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > > > @@ -0,0 +1,57 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +/*
> > > > + * Device Tree Source for the RZ/Five SoC
> > > > + *
> > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > + */
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > +
> > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> > > > +
> > > > +#include <arm64/renesas/r9a07g043.dtsi>
^^^ look below...
> > > The initial patch shouldn't be broken. Combine them together with the
> > > minimal components and add others late. Don't separate the DTS files.
> > >
> > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is
> > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two
> > more patches [1] which are required and are currently queued up in the
> > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover
> > letter).
>
> You could just move the below part to the second dtsi patch. Then
> compile won't be broken.
>
> clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> power-domains = <&cpg>;
> resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>
Compile won't break at all, the CPG node [0] and the pinctrl node [1]
already exists in the kernel which is being re-used by this SoC DTSI.
... the include file above already exists in the kernel and is not
part of the next follow up patch.
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n541
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-10-28 16:59 ` Prabhakar
@ 2022-11-08 15:43 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 15:43 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
>
> Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - PLIC
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Fixed riscv,ndev value (should be 511)
> * Reworked completely (sort of new patch)
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-11-08 15:43 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 15:43 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
> will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
> r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
>
> Below are the RZ/Five SoC specific blocks added in the initial DTSI which
> can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - PLIC
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Fixed riscv,ndev value (should be 511)
> * Reworked completely (sort of new patch)
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
2022-10-28 16:59 ` Prabhakar
@ 2022-10-28 16:59 ` Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable the minimal blocks required for booting the Renesas RZ/Five
SMARC EVK with initramfs.
Below are the blocks which are enabled:
- CPG
- CPU0
- DDR (memory regions)
- PINCTRL
- PLIC
- SCIF0
As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and
carrier [2] board DTSIs which enables almost all the blocks supported
by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually
enabling the blocks hence the aliases for ETH/I2C are deleted and rest
of the IP blocks are marked as disabled/deleted.
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
[1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
[2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4 -> v5
* Reworked completely (sort of new patch)
v3 -> v4
* Dropped deleting place holder nodes
* Updated SW1 settings comment
* Update commit message
v2 -> v3
* Dropped RB tags from Conor and Geert
* Now re-using the SoM and carrier board DTS/I from RZ/G2UL
v1 -> v2
* New patch
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
5 files changed, 179 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += renesas
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..2d3f5751a649
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
new file mode 100644
index 000000000000..2aa8515451d3
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/*
+ * DIP-Switch SW1 setting
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
+ * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
+ * Please change below macros according to SW1 setting on the SoM
+ */
+#define SW_SW0_DEV_SEL 1
+#define SW_ET0_EN_N 1
+
+#include "r9a07g043f.dtsi"
+#include "rzfive-smarc-som.dtsi"
+#include "rzfive-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g043f01";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
new file mode 100644
index 000000000000..45a182fa3b4b
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK SOM
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ ethernet0;
+ /delete-property/ ethernet1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ };
+
+ /delete-node/opp-table-0;
+ /delete-node/thermal-zones;
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dmac {
+ status = "disabled";
+};
+
+ð0 {
+ status = "disabled";
+};
+
+ð1 {
+ status = "disabled";
+};
+
+&ostm1 {
+ status = "disabled";
+};
+
+&ostm2 {
+ status = "disabled";
+};
+
+&sdhi0 {
+ status = "disabled";
+};
+
+&tsu {
+ status = "disabled";
+};
+
+&wdt0 {
+ status = "disabled";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
new file mode 100644
index 000000000000..e64f0e5f8e30
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK carrier board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ i2c0;
+ /delete-property/ i2c1;
+ };
+};
+
+&canfd {
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+};
+
+&ehci0 {
+ status = "disabled";
+};
+
+&ehci1 {
+ status = "disabled";
+};
+
+&hsusb {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "disabled";
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "disabled";
+};
+
+&ohci1 {
+ status = "disabled";
+};
+
+&phyrst {
+ status = "disabled";
+};
+
+&sdhi1 {
+ status = "disabled";
+};
+
+&snd_rzg2l {
+ status = "disabled";
+};
+
+&spi1 {
+ status = "disabled";
+};
+
+&ssi1 {
+ status = "disabled";
+};
+
+&usb0_vbus_otg {
+ status = "disabled";
+};
+
+&usb2_phy0 {
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ status = "disabled";
+};
+
+&vccq_sdhi1 {
+ status = "disabled";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread* [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
@ 2022-10-28 16:59 ` Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable the minimal blocks required for booting the Renesas RZ/Five
SMARC EVK with initramfs.
Below are the blocks which are enabled:
- CPG
- CPU0
- DDR (memory regions)
- PINCTRL
- PLIC
- SCIF0
As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and
carrier [2] board DTSIs which enables almost all the blocks supported
by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually
enabling the blocks hence the aliases for ETH/I2C are deleted and rest
of the IP blocks are marked as disabled/deleted.
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
[1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
[2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4 -> v5
* Reworked completely (sort of new patch)
v3 -> v4
* Dropped deleting place holder nodes
* Updated SW1 settings comment
* Update commit message
v2 -> v3
* Dropped RB tags from Conor and Geert
* Now re-using the SoM and carrier board DTS/I from RZ/G2UL
v1 -> v2
* New patch
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
5 files changed, 179 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += renesas
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..2d3f5751a649
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
new file mode 100644
index 000000000000..2aa8515451d3
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/*
+ * DIP-Switch SW1 setting
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
+ * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
+ * Please change below macros according to SW1 setting on the SoM
+ */
+#define SW_SW0_DEV_SEL 1
+#define SW_ET0_EN_N 1
+
+#include "r9a07g043f.dtsi"
+#include "rzfive-smarc-som.dtsi"
+#include "rzfive-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g043f01";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
new file mode 100644
index 000000000000..45a182fa3b4b
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK SOM
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ ethernet0;
+ /delete-property/ ethernet1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ };
+
+ /delete-node/opp-table-0;
+ /delete-node/thermal-zones;
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dmac {
+ status = "disabled";
+};
+
+ð0 {
+ status = "disabled";
+};
+
+ð1 {
+ status = "disabled";
+};
+
+&ostm1 {
+ status = "disabled";
+};
+
+&ostm2 {
+ status = "disabled";
+};
+
+&sdhi0 {
+ status = "disabled";
+};
+
+&tsu {
+ status = "disabled";
+};
+
+&wdt0 {
+ status = "disabled";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
new file mode 100644
index 000000000000..e64f0e5f8e30
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK carrier board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ i2c0;
+ /delete-property/ i2c1;
+ };
+};
+
+&canfd {
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+};
+
+&ehci0 {
+ status = "disabled";
+};
+
+&ehci1 {
+ status = "disabled";
+};
+
+&hsusb {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "disabled";
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "disabled";
+};
+
+&ohci1 {
+ status = "disabled";
+};
+
+&phyrst {
+ status = "disabled";
+};
+
+&sdhi1 {
+ status = "disabled";
+};
+
+&snd_rzg2l {
+ status = "disabled";
+};
+
+&spi1 {
+ status = "disabled";
+};
+
+&ssi1 {
+ status = "disabled";
+};
+
+&usb0_vbus_otg {
+ status = "disabled";
+};
+
+&usb2_phy0 {
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ status = "disabled";
+};
+
+&vccq_sdhi1 {
+ status = "disabled";
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 92+ messages in thread* Re: [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
2022-10-28 16:59 ` Prabhakar
@ 2022-10-29 4:26 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:26 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
This should combine with the previous one, which makes the patch complete.
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
>
> Below are the blocks which are enabled:
> - CPG
> - CPU0
> - DDR (memory regions)
> - PINCTRL
> - PLIC
> - SCIF0
>
> As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and
> carrier [2] board DTSIs which enables almost all the blocks supported
> by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually
> enabling the blocks hence the aliases for ETH/I2C are deleted and rest
> of the IP blocks are marked as disabled/deleted.
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Reworked completely (sort of new patch)
>
> v3 -> v4
> * Dropped deleting place holder nodes
> * Updated SW1 settings comment
> * Update commit message
>
> v2 -> v3
> * Dropped RB tags from Conor and Geert
> * Now re-using the SoM and carrier board DTS/I from RZ/G2UL
>
> v1 -> v2
> * New patch
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
> 5 files changed, 179 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
> new file mode 100644
> index 000000000000..2d3f5751a649
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> new file mode 100644
> index 000000000000..2aa8515451d3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +/*
> + * DIP-Switch SW1 setting
> + * 1 : High; 0: Low
> + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
> + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
> + * Please change below macros according to SW1 setting on the SoM
> + */
> +#define SW_SW0_DEV_SEL 1
> +#define SW_ET0_EN_N 1
> +
> +#include "r9a07g043f.dtsi"
> +#include "rzfive-smarc-som.dtsi"
> +#include "rzfive-smarc.dtsi"
> +
> +/ {
> + model = "Renesas SMARC EVK based on r9a07g043f01";
> + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
> +};
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> new file mode 100644
> index 000000000000..45a182fa3b4b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK SOM
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
> +
> +/ {
> + aliases {
> + /delete-property/ ethernet0;
> + /delete-property/ ethernet1;
> + };
> +
> + chosen {
> + bootargs = "ignore_loglevel";
> + };
> +
> + /delete-node/opp-table-0;
> + /delete-node/thermal-zones;
> +};
> +
> +&adc {
> + status = "disabled";
> +};
> +
> +&dmac {
> + status = "disabled";
> +};
> +
> +ð0 {
> + status = "disabled";
> +};
> +
> +ð1 {
> + status = "disabled";
> +};
> +
> +&ostm1 {
> + status = "disabled";
> +};
> +
> +&ostm2 {
> + status = "disabled";
> +};
> +
> +&sdhi0 {
> + status = "disabled";
> +};
> +
> +&tsu {
> + status = "disabled";
> +};
> +
> +&wdt0 {
> + status = "disabled";
> +};
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> new file mode 100644
> index 000000000000..e64f0e5f8e30
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK carrier board
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <arm64/renesas/rzg2ul-smarc.dtsi>
> +
> +/ {
> + aliases {
> + /delete-property/ i2c0;
> + /delete-property/ i2c1;
> + };
> +};
> +
> +&canfd {
> + status = "disabled";
> +
> + channel0 {
> + status = "disabled";
> + };
> +
> + channel1 {
> + status = "disabled";
> + };
> +};
> +
> +&ehci0 {
> + status = "disabled";
> +};
> +
> +&ehci1 {
> + status = "disabled";
> +};
> +
> +&hsusb {
> + status = "disabled";
> +};
> +
> +&i2c0 {
> + status = "disabled";
> +};
> +
> +&i2c1 {
> + status = "disabled";
> +};
> +
> +&ohci0 {
> + status = "disabled";
> +};
> +
> +&ohci1 {
> + status = "disabled";
> +};
> +
> +&phyrst {
> + status = "disabled";
> +};
> +
> +&sdhi1 {
> + status = "disabled";
> +};
> +
> +&snd_rzg2l {
> + status = "disabled";
> +};
> +
> +&spi1 {
> + status = "disabled";
> +};
> +
> +&ssi1 {
> + status = "disabled";
> +};
> +
> +&usb0_vbus_otg {
> + status = "disabled";
> +};
> +
> +&usb2_phy0 {
> + status = "disabled";
> +};
> +
> +&usb2_phy1 {
> + status = "disabled";
> +};
> +
> +&vccq_sdhi1 {
> + status = "disabled";
> +};
> --
> 2.25.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
@ 2022-10-29 4:26 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:26 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
This should combine with the previous one, which makes the patch complete.
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
>
> Below are the blocks which are enabled:
> - CPG
> - CPU0
> - DDR (memory regions)
> - PINCTRL
> - PLIC
> - SCIF0
>
> As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and
> carrier [2] board DTSIs which enables almost all the blocks supported
> by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually
> enabling the blocks hence the aliases for ETH/I2C are deleted and rest
> of the IP blocks are marked as disabled/deleted.
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Reworked completely (sort of new patch)
>
> v3 -> v4
> * Dropped deleting place holder nodes
> * Updated SW1 settings comment
> * Update commit message
>
> v2 -> v3
> * Dropped RB tags from Conor and Geert
> * Now re-using the SoM and carrier board DTS/I from RZ/G2UL
>
> v1 -> v2
> * New patch
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
> 5 files changed, 179 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
> new file mode 100644
> index 000000000000..2d3f5751a649
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> new file mode 100644
> index 000000000000..2aa8515451d3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +/*
> + * DIP-Switch SW1 setting
> + * 1 : High; 0: Low
> + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
> + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
> + * Please change below macros according to SW1 setting on the SoM
> + */
> +#define SW_SW0_DEV_SEL 1
> +#define SW_ET0_EN_N 1
> +
> +#include "r9a07g043f.dtsi"
> +#include "rzfive-smarc-som.dtsi"
> +#include "rzfive-smarc.dtsi"
> +
> +/ {
> + model = "Renesas SMARC EVK based on r9a07g043f01";
> + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
> +};
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> new file mode 100644
> index 000000000000..45a182fa3b4b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK SOM
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
> +
> +/ {
> + aliases {
> + /delete-property/ ethernet0;
> + /delete-property/ ethernet1;
> + };
> +
> + chosen {
> + bootargs = "ignore_loglevel";
> + };
> +
> + /delete-node/opp-table-0;
> + /delete-node/thermal-zones;
> +};
> +
> +&adc {
> + status = "disabled";
> +};
> +
> +&dmac {
> + status = "disabled";
> +};
> +
> +ð0 {
> + status = "disabled";
> +};
> +
> +ð1 {
> + status = "disabled";
> +};
> +
> +&ostm1 {
> + status = "disabled";
> +};
> +
> +&ostm2 {
> + status = "disabled";
> +};
> +
> +&sdhi0 {
> + status = "disabled";
> +};
> +
> +&tsu {
> + status = "disabled";
> +};
> +
> +&wdt0 {
> + status = "disabled";
> +};
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> new file mode 100644
> index 000000000000..e64f0e5f8e30
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> @@ -0,0 +1,91 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK carrier board
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <arm64/renesas/rzg2ul-smarc.dtsi>
> +
> +/ {
> + aliases {
> + /delete-property/ i2c0;
> + /delete-property/ i2c1;
> + };
> +};
> +
> +&canfd {
> + status = "disabled";
> +
> + channel0 {
> + status = "disabled";
> + };
> +
> + channel1 {
> + status = "disabled";
> + };
> +};
> +
> +&ehci0 {
> + status = "disabled";
> +};
> +
> +&ehci1 {
> + status = "disabled";
> +};
> +
> +&hsusb {
> + status = "disabled";
> +};
> +
> +&i2c0 {
> + status = "disabled";
> +};
> +
> +&i2c1 {
> + status = "disabled";
> +};
> +
> +&ohci0 {
> + status = "disabled";
> +};
> +
> +&ohci1 {
> + status = "disabled";
> +};
> +
> +&phyrst {
> + status = "disabled";
> +};
> +
> +&sdhi1 {
> + status = "disabled";
> +};
> +
> +&snd_rzg2l {
> + status = "disabled";
> +};
> +
> +&spi1 {
> + status = "disabled";
> +};
> +
> +&ssi1 {
> + status = "disabled";
> +};
> +
> +&usb0_vbus_otg {
> + status = "disabled";
> +};
> +
> +&usb2_phy0 {
> + status = "disabled";
> +};
> +
> +&usb2_phy1 {
> + status = "disabled";
> +};
> +
> +&vccq_sdhi1 {
> + status = "disabled";
> +};
> --
> 2.25.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
2022-10-29 4:26 ` Guo Ren
@ 2022-10-29 19:14 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-29 19:14 UTC (permalink / raw)
To: Guo Ren
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Guo,
On Sat, Oct 29, 2022 at 5:26 AM Guo Ren <guoren@kernel.org> wrote:
>
> This should combine with the previous one, which makes the patch complete.
>
For easier review purposes we tend to have separate patches for SoC
and the board on ARM/64 which is what I have followed here. If you
insist I can merge this along with the SoC DTSI patch.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
@ 2022-10-29 19:14 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-29 19:14 UTC (permalink / raw)
To: Guo Ren
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Guo,
On Sat, Oct 29, 2022 at 5:26 AM Guo Ren <guoren@kernel.org> wrote:
>
> This should combine with the previous one, which makes the patch complete.
>
For easier review purposes we tend to have separate patches for SoC
and the board on ARM/64 which is what I have followed here. If you
insist I can merge this along with the SoC DTSI patch.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
2022-10-28 16:59 ` Prabhakar
@ 2022-11-08 15:44 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 15:44 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
>
> Below are the blocks which are enabled:
> - CPG
> - CPU0
> - DDR (memory regions)
> - PINCTRL
> - PLIC
> - SCIF0
>
> As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and
> carrier [2] board DTSIs which enables almost all the blocks supported
> by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually
> enabling the blocks hence the aliases for ETH/I2C are deleted and rest
> of the IP blocks are marked as disabled/deleted.
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Reworked completely (sort of new patch)
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
@ 2022-11-08 15:44 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 15:44 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
>
> Below are the blocks which are enabled:
> - CPG
> - CPU0
> - DDR (memory regions)
> - PINCTRL
> - PLIC
> - SCIF0
>
> As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and
> carrier [2] board DTSIs which enables almost all the blocks supported
> by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually
> enabling the blocks hence the aliases for ETH/I2C are deleted and rest
> of the IP blocks are marked as disabled/deleted.
>
> [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v4 -> v5
> * Reworked completely (sort of new patch)
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
2022-10-28 16:59 ` Prabhakar
@ 2022-10-28 16:59 ` Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add RISC-V architecture as part of ARM/Renesas architecture, as they have
the same maintainers, use the same development collaboration
infrastructure, and share many files.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v4 -> v5
* Rebased on -next
* Included RB tag from Conor
v3 -> v4
* Included RB tag from Geert
v2 -> v3
* Merged as part of ARM
v1 -> v2
* New patch
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6cdc2a74c7a2..0204f106d8c2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2691,7 +2691,7 @@ F: arch/arm/boot/dts/rtd*
F: arch/arm/mach-realtek/
F: arch/arm64/boot/dts/realtek/
-ARM/RENESAS ARCHITECTURE
+ARM/RISC-V/RENESAS ARCHITECTURE
M: Geert Uytterhoeven <geert+renesas@glider.be>
M: Magnus Damm <magnus.damm@gmail.com>
L: linux-renesas-soc@vger.kernel.org
@@ -2713,6 +2713,7 @@ F: arch/arm/include/debug/renesas-scif.S
F: arch/arm/mach-shmobile/
F: arch/arm64/boot/dts/renesas/
F: arch/arm64/configs/renesas_defconfig
+F: arch/riscv/boot/dts/renesas/
F: drivers/soc/renesas/
F: include/linux/soc/renesas/
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
@ 2022-10-28 16:59 ` Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add RISC-V architecture as part of ARM/Renesas architecture, as they have
the same maintainers, use the same development collaboration
infrastructure, and share many files.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v4 -> v5
* Rebased on -next
* Included RB tag from Conor
v3 -> v4
* Included RB tag from Geert
v2 -> v3
* Merged as part of ARM
v1 -> v2
* New patch
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6cdc2a74c7a2..0204f106d8c2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2691,7 +2691,7 @@ F: arch/arm/boot/dts/rtd*
F: arch/arm/mach-realtek/
F: arch/arm64/boot/dts/realtek/
-ARM/RENESAS ARCHITECTURE
+ARM/RISC-V/RENESAS ARCHITECTURE
M: Geert Uytterhoeven <geert+renesas@glider.be>
M: Magnus Damm <magnus.damm@gmail.com>
L: linux-renesas-soc@vger.kernel.org
@@ -2713,6 +2713,7 @@ F: arch/arm/include/debug/renesas-scif.S
F: arch/arm/mach-shmobile/
F: arch/arm64/boot/dts/renesas/
F: arch/arm64/configs/renesas_defconfig
+F: arch/riscv/boot/dts/renesas/
F: drivers/soc/renesas/
F: include/linux/soc/renesas/
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 92+ messages in thread
* Re: [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
2022-10-28 16:59 ` Prabhakar
@ 2022-10-29 4:27 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:27 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add RISC-V architecture as part of ARM/Renesas architecture, as they have
> the same maintainers, use the same development collaboration
> infrastructure, and share many files.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Rebased on -next
> * Included RB tag from Conor
>
> v3 -> v4
> * Included RB tag from Geert
>
> v2 -> v3
> * Merged as part of ARM
>
> v1 -> v2
> * New patch
> ---
> MAINTAINERS | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6cdc2a74c7a2..0204f106d8c2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2691,7 +2691,7 @@ F: arch/arm/boot/dts/rtd*
> F: arch/arm/mach-realtek/
> F: arch/arm64/boot/dts/realtek/
>
> -ARM/RENESAS ARCHITECTURE
> +ARM/RISC-V/RENESAS ARCHITECTURE
Great! Good luck RISC-V RENESAS ARCHITECTURE.
Reviewed-by: Guo Ren <guoren@kernel.org>
> M: Geert Uytterhoeven <geert+renesas@glider.be>
> M: Magnus Damm <magnus.damm@gmail.com>
> L: linux-renesas-soc@vger.kernel.org
> @@ -2713,6 +2713,7 @@ F: arch/arm/include/debug/renesas-scif.S
> F: arch/arm/mach-shmobile/
> F: arch/arm64/boot/dts/renesas/
> F: arch/arm64/configs/renesas_defconfig
> +F: arch/riscv/boot/dts/renesas/
> F: drivers/soc/renesas/
> F: include/linux/soc/renesas/
>
> --
> 2.25.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
@ 2022-10-29 4:27 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:27 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add RISC-V architecture as part of ARM/Renesas architecture, as they have
> the same maintainers, use the same development collaboration
> infrastructure, and share many files.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Rebased on -next
> * Included RB tag from Conor
>
> v3 -> v4
> * Included RB tag from Geert
>
> v2 -> v3
> * Merged as part of ARM
>
> v1 -> v2
> * New patch
> ---
> MAINTAINERS | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6cdc2a74c7a2..0204f106d8c2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2691,7 +2691,7 @@ F: arch/arm/boot/dts/rtd*
> F: arch/arm/mach-realtek/
> F: arch/arm64/boot/dts/realtek/
>
> -ARM/RENESAS ARCHITECTURE
> +ARM/RISC-V/RENESAS ARCHITECTURE
Great! Good luck RISC-V RENESAS ARCHITECTURE.
Reviewed-by: Guo Ren <guoren@kernel.org>
> M: Geert Uytterhoeven <geert+renesas@glider.be>
> M: Magnus Damm <magnus.damm@gmail.com>
> L: linux-renesas-soc@vger.kernel.org
> @@ -2713,6 +2713,7 @@ F: arch/arm/include/debug/renesas-scif.S
> F: arch/arm/mach-shmobile/
> F: arch/arm64/boot/dts/renesas/
> F: arch/arm64/configs/renesas_defconfig
> +F: arch/riscv/boot/dts/renesas/
> F: drivers/soc/renesas/
> F: include/linux/soc/renesas/
>
> --
> 2.25.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-10-28 16:59 ` Prabhakar
@ 2022-10-28 16:59 ` Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable Renesas RZ/Five SoC config in defconfig. It allows the default
upstream kernel to boot on RZ/Five SMARC EVK board.
Alongside enable SERIAL_SH_SCI config so that the serial driver used by
RZ/Five SoC is built-in.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4 -> v5
* No change
v3 -> v4
* Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
tags with this change)
* Used riscv instead of RISC-V in subject line
v2 -> v3
* Included RB tags
* Updated commit description
v1 -> v2
* New patch
---
arch/riscv/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..97fba7884d7a 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R9A07G043=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
@@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
--
2.25.1
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-10-28 16:59 ` Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Prabhakar @ 2022-10-28 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable Renesas RZ/Five SoC config in defconfig. It allows the default
upstream kernel to boot on RZ/Five SMARC EVK board.
Alongside enable SERIAL_SH_SCI config so that the serial driver used by
RZ/Five SoC is built-in.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4 -> v5
* No change
v3 -> v4
* Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
tags with this change)
* Used riscv instead of RISC-V in subject line
v2 -> v3
* Included RB tags
* Updated commit description
v1 -> v2
* New patch
---
arch/riscv/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..97fba7884d7a 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R9A07G043=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
@@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-10-28 16:59 ` Prabhakar
@ 2022-10-29 4:28 ` Guo Ren
-1 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:28 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Reviewed-by: Guo Ren <guoren@kernel.org>
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> upstream kernel to boot on RZ/Five SMARC EVK board.
>
> Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> RZ/Five SoC is built-in.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4 -> v5
> * No change
>
> v3 -> v4
> * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> tags with this change)
> * Used riscv instead of RISC-V in subject line
>
> v2 -> v3
> * Included RB tags
> * Updated commit description
>
> v1 -> v2
> * New patch
> ---
> arch/riscv/configs/defconfig | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 05fd5fcf24f9..97fba7884d7a 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_ARCH_RENESAS=y
> +CONFIG_ARCH_R9A07G043=y
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> CONFIG_PM=y
> @@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_SERIAL_SH_SCI=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> --
> 2.25.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-10-29 4:28 ` Guo Ren
0 siblings, 0 replies; 92+ messages in thread
From: Guo Ren @ 2022-10-29 4:28 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Reviewed-by: Guo Ren <guoren@kernel.org>
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> upstream kernel to boot on RZ/Five SMARC EVK board.
>
> Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> RZ/Five SoC is built-in.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4 -> v5
> * No change
>
> v3 -> v4
> * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> tags with this change)
> * Used riscv instead of RISC-V in subject line
>
> v2 -> v3
> * Included RB tags
> * Updated commit description
>
> v1 -> v2
> * New patch
> ---
> arch/riscv/configs/defconfig | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 05fd5fcf24f9..97fba7884d7a 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_ARCH_RENESAS=y
> +CONFIG_ARCH_R9A07G043=y
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> CONFIG_PM=y
> @@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y
> CONFIG_SERIAL_8250=y
> CONFIG_SERIAL_8250_CONSOLE=y
> CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_SERIAL_SH_SCI=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> --
> 2.25.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-10-28 16:59 ` Prabhakar
@ 2022-11-08 15:51 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 15:51 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> upstream kernel to boot on RZ/Five SMARC EVK board.
>
> Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> RZ/Five SoC is built-in.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4 -> v5
> * No change
>
> v3 -> v4
> * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> tags with this change)
> * Used riscv instead of RISC-V in subject line
Thanks for the update!
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_ARCH_RENESAS=y
> +CONFIG_ARCH_R9A07G043=y
You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> CONFIG_PM=y
PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
resp. SOC_RENESAS, so they can be dropped. But it's better to do this
after the release of v6.2-rc1, when all pieces have fallen together.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-11-08 15:51 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 15:51 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> upstream kernel to boot on RZ/Five SMARC EVK board.
>
> Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> RZ/Five SoC is built-in.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4 -> v5
> * No change
>
> v3 -> v4
> * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> tags with this change)
> * Used riscv instead of RISC-V in subject line
Thanks for the update!
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_ARCH_RENESAS=y
> +CONFIG_ARCH_R9A07G043=y
You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> CONFIG_PM=y
PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
resp. SOC_RENESAS, so they can be dropped. But it's better to do this
after the release of v6.2-rc1, when all pieces have fallen together.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-11-08 15:51 ` Geert Uytterhoeven
@ 2022-11-08 16:06 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-08 16:06 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Geert,
Thank you for the review.
On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > upstream kernel to boot on RZ/Five SMARC EVK board.
> >
> > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > RZ/Five SoC is built-in.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > v4 -> v5
> > * No change
> >
> > v3 -> v4
> > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > tags with this change)
> > * Used riscv instead of RISC-V in subject line
>
> Thanks for the update!
>
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_STARFIVE=y
> > CONFIG_SOC_VIRT=y
> > +CONFIG_ARCH_RENESAS=y
> > +CONFIG_ARCH_R9A07G043=y
>
> You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
>
Sorry I missed your point here, could you please elaborate.
> > CONFIG_SMP=y
> > CONFIG_HOTPLUG_CPU=y
> > CONFIG_PM=y
>
> PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> after the release of v6.2-rc1, when all pieces have fallen together.
>
Are you suggesting dropping it from defconfig?
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-11-08 16:06 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-08 16:06 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Geert,
Thank you for the review.
On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > upstream kernel to boot on RZ/Five SMARC EVK board.
> >
> > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > RZ/Five SoC is built-in.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > v4 -> v5
> > * No change
> >
> > v3 -> v4
> > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > tags with this change)
> > * Used riscv instead of RISC-V in subject line
>
> Thanks for the update!
>
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_STARFIVE=y
> > CONFIG_SOC_VIRT=y
> > +CONFIG_ARCH_RENESAS=y
> > +CONFIG_ARCH_R9A07G043=y
>
> You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
>
Sorry I missed your point here, could you please elaborate.
> > CONFIG_SMP=y
> > CONFIG_HOTPLUG_CPU=y
> > CONFIG_PM=y
>
> PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> after the release of v6.2-rc1, when all pieces have fallen together.
>
Are you suggesting dropping it from defconfig?
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-11-08 16:06 ` Lad, Prabhakar
@ 2022-11-08 16:12 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 16:12 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > >
> > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > RZ/Five SoC is built-in.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > ---
> > > v4 -> v5
> > > * No change
> > >
> > > v3 -> v4
> > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > tags with this change)
> > > * Used riscv instead of RISC-V in subject line
> >
> > Thanks for the update!
> >
> > > --- a/arch/riscv/configs/defconfig
> > > +++ b/arch/riscv/configs/defconfig
> > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > CONFIG_SOC_SIFIVE=y
> > > CONFIG_SOC_STARFIVE=y
> > > CONFIG_SOC_VIRT=y
> > > +CONFIG_ARCH_RENESAS=y
> > > +CONFIG_ARCH_R9A07G043=y
> >
> > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> >
> Sorry I missed your point here, could you please elaborate.
I mean that the options have moved, so you should update
your patch like this:
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -26,11 +26,10 @@ CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_PROFILING=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
+CONFIG_ARCH_RENESAS=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_ARCH_R9A07G043=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
@@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_VIRTIO=y
+CONFIG_ARCH_R9A07G043=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
> > > CONFIG_SMP=y
> > > CONFIG_HOTPLUG_CPU=y
> > > CONFIG_PM=y
> >
> > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > after the release of v6.2-rc1, when all pieces have fallen together.
> >
> Are you suggesting dropping it from defconfig?
Yes, but not right now, as that would make it depend on my
renesas-drivers-for-v6.2 branch to keep them enabled.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-11-08 16:12 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 16:12 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > >
> > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > RZ/Five SoC is built-in.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > ---
> > > v4 -> v5
> > > * No change
> > >
> > > v3 -> v4
> > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > tags with this change)
> > > * Used riscv instead of RISC-V in subject line
> >
> > Thanks for the update!
> >
> > > --- a/arch/riscv/configs/defconfig
> > > +++ b/arch/riscv/configs/defconfig
> > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > CONFIG_SOC_SIFIVE=y
> > > CONFIG_SOC_STARFIVE=y
> > > CONFIG_SOC_VIRT=y
> > > +CONFIG_ARCH_RENESAS=y
> > > +CONFIG_ARCH_R9A07G043=y
> >
> > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> >
> Sorry I missed your point here, could you please elaborate.
I mean that the options have moved, so you should update
your patch like this:
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -26,11 +26,10 @@ CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_PROFILING=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
+CONFIG_ARCH_RENESAS=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_ARCH_R9A07G043=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
@@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_VIRTIO=y
+CONFIG_ARCH_R9A07G043=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
> > > CONFIG_SMP=y
> > > CONFIG_HOTPLUG_CPU=y
> > > CONFIG_PM=y
> >
> > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > after the release of v6.2-rc1, when all pieces have fallen together.
> >
> Are you suggesting dropping it from defconfig?
Yes, but not right now, as that would make it depend on my
renesas-drivers-for-v6.2 branch to keep them enabled.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-11-08 16:12 ` Geert Uytterhoeven
@ 2022-11-08 17:22 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-08 17:22 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Geert,
On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > >
> > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > RZ/Five SoC is built-in.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > ---
> > > > v4 -> v5
> > > > * No change
> > > >
> > > > v3 -> v4
> > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > tags with this change)
> > > > * Used riscv instead of RISC-V in subject line
> > >
> > > Thanks for the update!
> > >
> > > > --- a/arch/riscv/configs/defconfig
> > > > +++ b/arch/riscv/configs/defconfig
> > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > CONFIG_SOC_SIFIVE=y
> > > > CONFIG_SOC_STARFIVE=y
> > > > CONFIG_SOC_VIRT=y
> > > > +CONFIG_ARCH_RENESAS=y
> > > > +CONFIG_ARCH_R9A07G043=y
> > >
> > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > >
> > Sorry I missed your point here, could you please elaborate.
>
> I mean that the options have moved, so you should update
> your patch like this:
>
Ouch got that.
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> CONFIG_PROFILING=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> +CONFIG_ARCH_RENESAS=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_SOC_VIRT=y
> -CONFIG_ARCH_RENESAS=y
> -CONFIG_ARCH_R9A07G043=y
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> CONFIG_PM=y
> @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> CONFIG_RPMSG_CHAR=y
> CONFIG_RPMSG_CTRL=y
> CONFIG_RPMSG_VIRTIO=y
> +CONFIG_ARCH_R9A07G043=y
> CONFIG_EXT4_FS=y
> CONFIG_EXT4_FS_POSIX_ACL=y
> CONFIG_EXT4_FS_SECURITY=y
>
> > > > CONFIG_SMP=y
> > > > CONFIG_HOTPLUG_CPU=y
> > > > CONFIG_PM=y
> > >
> > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > after the release of v6.2-rc1, when all pieces have fallen together.
> > >
> > Are you suggesting dropping it from defconfig?
>
> Yes, but not right now, as that would make it depend on my
> renesas-drivers-for-v6.2 branch to keep them enabled.
>
I was wondering if that's required by other platforms though.
CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-11-08 17:22 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-08 17:22 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Geert,
On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > >
> > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > RZ/Five SoC is built-in.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > ---
> > > > v4 -> v5
> > > > * No change
> > > >
> > > > v3 -> v4
> > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > tags with this change)
> > > > * Used riscv instead of RISC-V in subject line
> > >
> > > Thanks for the update!
> > >
> > > > --- a/arch/riscv/configs/defconfig
> > > > +++ b/arch/riscv/configs/defconfig
> > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > CONFIG_SOC_SIFIVE=y
> > > > CONFIG_SOC_STARFIVE=y
> > > > CONFIG_SOC_VIRT=y
> > > > +CONFIG_ARCH_RENESAS=y
> > > > +CONFIG_ARCH_R9A07G043=y
> > >
> > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > >
> > Sorry I missed your point here, could you please elaborate.
>
> I mean that the options have moved, so you should update
> your patch like this:
>
Ouch got that.
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> CONFIG_PROFILING=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> +CONFIG_ARCH_RENESAS=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_SOC_VIRT=y
> -CONFIG_ARCH_RENESAS=y
> -CONFIG_ARCH_R9A07G043=y
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> CONFIG_PM=y
> @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> CONFIG_RPMSG_CHAR=y
> CONFIG_RPMSG_CTRL=y
> CONFIG_RPMSG_VIRTIO=y
> +CONFIG_ARCH_R9A07G043=y
> CONFIG_EXT4_FS=y
> CONFIG_EXT4_FS_POSIX_ACL=y
> CONFIG_EXT4_FS_SECURITY=y
>
> > > > CONFIG_SMP=y
> > > > CONFIG_HOTPLUG_CPU=y
> > > > CONFIG_PM=y
> > >
> > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > after the release of v6.2-rc1, when all pieces have fallen together.
> > >
> > Are you suggesting dropping it from defconfig?
>
> Yes, but not right now, as that would make it depend on my
> renesas-drivers-for-v6.2 branch to keep them enabled.
>
I was wondering if that's required by other platforms though.
CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-11-08 17:22 ` Lad, Prabhakar
@ 2022-11-08 19:19 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 19:19 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Tue, Nov 8, 2022 at 6:23 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > > >
> > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > > RZ/Five SoC is built-in.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > ---
> > > > > v4 -> v5
> > > > > * No change
> > > > >
> > > > > v3 -> v4
> > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > > tags with this change)
> > > > > * Used riscv instead of RISC-V in subject line
> > > >
> > > > Thanks for the update!
> > > >
> > > > > --- a/arch/riscv/configs/defconfig
> > > > > +++ b/arch/riscv/configs/defconfig
> > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > CONFIG_SOC_SIFIVE=y
> > > > > CONFIG_SOC_STARFIVE=y
> > > > > CONFIG_SOC_VIRT=y
> > > > > +CONFIG_ARCH_RENESAS=y
> > > > > +CONFIG_ARCH_R9A07G043=y
> > > >
> > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > > >
> > > Sorry I missed your point here, could you please elaborate.
> >
> > I mean that the options have moved, so you should update
> > your patch like this:
> >
> Ouch got that.
>
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> > # CONFIG_SYSFS_SYSCALL is not set
> > CONFIG_PROFILING=y
> > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > +CONFIG_ARCH_RENESAS=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_STARFIVE=y
> > CONFIG_SOC_VIRT=y
> > -CONFIG_ARCH_RENESAS=y
> > -CONFIG_ARCH_R9A07G043=y
> > CONFIG_SMP=y
> > CONFIG_HOTPLUG_CPU=y
> > CONFIG_PM=y
> > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> > CONFIG_RPMSG_CHAR=y
> > CONFIG_RPMSG_CTRL=y
> > CONFIG_RPMSG_VIRTIO=y
> > +CONFIG_ARCH_R9A07G043=y
> > CONFIG_EXT4_FS=y
> > CONFIG_EXT4_FS_POSIX_ACL=y
> > CONFIG_EXT4_FS_SECURITY=y
> >
> > > > > CONFIG_SMP=y
> > > > > CONFIG_HOTPLUG_CPU=y
> > > > > CONFIG_PM=y
> > > >
> > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > > after the release of v6.2-rc1, when all pieces have fallen together.
> > > >
> > > Are you suggesting dropping it from defconfig?
> >
> > Yes, but not right now, as that would make it depend on my
> > renesas-drivers-for-v6.2 branch to keep them enabled.
> >
> I was wondering if that's required by other platforms though.
> CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
Does that matter? They would still get it, as long as they use the
defconfig.
If you want to remove unwanted platforms from your configuration,
you do that in the .config file, not in the defconfig file.
If you have CONFIG_PM=y in your .config, it will be retained.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-11-08 19:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 19:19 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Tue, Nov 8, 2022 at 6:23 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > > >
> > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > > RZ/Five SoC is built-in.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > ---
> > > > > v4 -> v5
> > > > > * No change
> > > > >
> > > > > v3 -> v4
> > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > > tags with this change)
> > > > > * Used riscv instead of RISC-V in subject line
> > > >
> > > > Thanks for the update!
> > > >
> > > > > --- a/arch/riscv/configs/defconfig
> > > > > +++ b/arch/riscv/configs/defconfig
> > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > CONFIG_SOC_SIFIVE=y
> > > > > CONFIG_SOC_STARFIVE=y
> > > > > CONFIG_SOC_VIRT=y
> > > > > +CONFIG_ARCH_RENESAS=y
> > > > > +CONFIG_ARCH_R9A07G043=y
> > > >
> > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > > >
> > > Sorry I missed your point here, could you please elaborate.
> >
> > I mean that the options have moved, so you should update
> > your patch like this:
> >
> Ouch got that.
>
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> > # CONFIG_SYSFS_SYSCALL is not set
> > CONFIG_PROFILING=y
> > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > +CONFIG_ARCH_RENESAS=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_STARFIVE=y
> > CONFIG_SOC_VIRT=y
> > -CONFIG_ARCH_RENESAS=y
> > -CONFIG_ARCH_R9A07G043=y
> > CONFIG_SMP=y
> > CONFIG_HOTPLUG_CPU=y
> > CONFIG_PM=y
> > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> > CONFIG_RPMSG_CHAR=y
> > CONFIG_RPMSG_CTRL=y
> > CONFIG_RPMSG_VIRTIO=y
> > +CONFIG_ARCH_R9A07G043=y
> > CONFIG_EXT4_FS=y
> > CONFIG_EXT4_FS_POSIX_ACL=y
> > CONFIG_EXT4_FS_SECURITY=y
> >
> > > > > CONFIG_SMP=y
> > > > > CONFIG_HOTPLUG_CPU=y
> > > > > CONFIG_PM=y
> > > >
> > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > > after the release of v6.2-rc1, when all pieces have fallen together.
> > > >
> > > Are you suggesting dropping it from defconfig?
> >
> > Yes, but not right now, as that would make it depend on my
> > renesas-drivers-for-v6.2 branch to keep them enabled.
> >
> I was wondering if that's required by other platforms though.
> CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
Does that matter? They would still get it, as long as they use the
defconfig.
If you want to remove unwanted platforms from your configuration,
you do that in the .config file, not in the defconfig file.
If you have CONFIG_PM=y in your .config, it will be retained.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-11-08 19:19 ` Geert Uytterhoeven
@ 2022-11-08 22:01 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-08 22:01 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Geert,
On Tue, Nov 8, 2022 at 7:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 8, 2022 at 6:23 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > > > >
> > > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > > > RZ/Five SoC is built-in.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > > ---
> > > > > > v4 -> v5
> > > > > > * No change
> > > > > >
> > > > > > v3 -> v4
> > > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > > > tags with this change)
> > > > > > * Used riscv instead of RISC-V in subject line
> > > > >
> > > > > Thanks for the update!
> > > > >
> > > > > > --- a/arch/riscv/configs/defconfig
> > > > > > +++ b/arch/riscv/configs/defconfig
> > > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > > CONFIG_SOC_SIFIVE=y
> > > > > > CONFIG_SOC_STARFIVE=y
> > > > > > CONFIG_SOC_VIRT=y
> > > > > > +CONFIG_ARCH_RENESAS=y
> > > > > > +CONFIG_ARCH_R9A07G043=y
> > > > >
> > > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > > > >
> > > > Sorry I missed your point here, could you please elaborate.
> > >
> > > I mean that the options have moved, so you should update
> > > your patch like this:
> > >
> > Ouch got that.
> >
> > > --- a/arch/riscv/configs/defconfig
> > > +++ b/arch/riscv/configs/defconfig
> > > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> > > # CONFIG_SYSFS_SYSCALL is not set
> > > CONFIG_PROFILING=y
> > > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > +CONFIG_ARCH_RENESAS=y
> > > CONFIG_SOC_SIFIVE=y
> > > CONFIG_SOC_STARFIVE=y
> > > CONFIG_SOC_VIRT=y
> > > -CONFIG_ARCH_RENESAS=y
> > > -CONFIG_ARCH_R9A07G043=y
> > > CONFIG_SMP=y
> > > CONFIG_HOTPLUG_CPU=y
> > > CONFIG_PM=y
> > > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> > > CONFIG_RPMSG_CHAR=y
> > > CONFIG_RPMSG_CTRL=y
> > > CONFIG_RPMSG_VIRTIO=y
> > > +CONFIG_ARCH_R9A07G043=y
> > > CONFIG_EXT4_FS=y
> > > CONFIG_EXT4_FS_POSIX_ACL=y
> > > CONFIG_EXT4_FS_SECURITY=y
> > >
> > > > > > CONFIG_SMP=y
> > > > > > CONFIG_HOTPLUG_CPU=y
> > > > > > CONFIG_PM=y
> > > > >
> > > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > > > after the release of v6.2-rc1, when all pieces have fallen together.
> > > > >
> > > > Are you suggesting dropping it from defconfig?
> > >
> > > Yes, but not right now, as that would make it depend on my
> > > renesas-drivers-for-v6.2 branch to keep them enabled.
> > >
^^^
> > I was wondering if that's required by other platforms though.
> > CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
>
> Does that matter? They would still get it, as long as they use the
> defconfig.
>
Confused, didnt you say about dropping it from defconfig...
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-11-08 22:01 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-08 22:01 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Geert,
On Tue, Nov 8, 2022 at 7:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 8, 2022 at 6:23 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > > > >
> > > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > > > RZ/Five SoC is built-in.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > > ---
> > > > > > v4 -> v5
> > > > > > * No change
> > > > > >
> > > > > > v3 -> v4
> > > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > > > tags with this change)
> > > > > > * Used riscv instead of RISC-V in subject line
> > > > >
> > > > > Thanks for the update!
> > > > >
> > > > > > --- a/arch/riscv/configs/defconfig
> > > > > > +++ b/arch/riscv/configs/defconfig
> > > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > > CONFIG_SOC_SIFIVE=y
> > > > > > CONFIG_SOC_STARFIVE=y
> > > > > > CONFIG_SOC_VIRT=y
> > > > > > +CONFIG_ARCH_RENESAS=y
> > > > > > +CONFIG_ARCH_R9A07G043=y
> > > > >
> > > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > > > >
> > > > Sorry I missed your point here, could you please elaborate.
> > >
> > > I mean that the options have moved, so you should update
> > > your patch like this:
> > >
> > Ouch got that.
> >
> > > --- a/arch/riscv/configs/defconfig
> > > +++ b/arch/riscv/configs/defconfig
> > > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> > > # CONFIG_SYSFS_SYSCALL is not set
> > > CONFIG_PROFILING=y
> > > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > +CONFIG_ARCH_RENESAS=y
> > > CONFIG_SOC_SIFIVE=y
> > > CONFIG_SOC_STARFIVE=y
> > > CONFIG_SOC_VIRT=y
> > > -CONFIG_ARCH_RENESAS=y
> > > -CONFIG_ARCH_R9A07G043=y
> > > CONFIG_SMP=y
> > > CONFIG_HOTPLUG_CPU=y
> > > CONFIG_PM=y
> > > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> > > CONFIG_RPMSG_CHAR=y
> > > CONFIG_RPMSG_CTRL=y
> > > CONFIG_RPMSG_VIRTIO=y
> > > +CONFIG_ARCH_R9A07G043=y
> > > CONFIG_EXT4_FS=y
> > > CONFIG_EXT4_FS_POSIX_ACL=y
> > > CONFIG_EXT4_FS_SECURITY=y
> > >
> > > > > > CONFIG_SMP=y
> > > > > > CONFIG_HOTPLUG_CPU=y
> > > > > > CONFIG_PM=y
> > > > >
> > > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > > > after the release of v6.2-rc1, when all pieces have fallen together.
> > > > >
> > > > Are you suggesting dropping it from defconfig?
> > >
> > > Yes, but not right now, as that would make it depend on my
> > > renesas-drivers-for-v6.2 branch to keep them enabled.
> > >
^^^
> > I was wondering if that's required by other platforms though.
> > CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
>
> Does that matter? They would still get it, as long as they use the
> defconfig.
>
Confused, didnt you say about dropping it from defconfig...
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-11-08 22:01 ` Lad, Prabhakar
@ 2022-11-09 7:46 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-09 7:46 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Tue, Nov 8, 2022 at 11:05 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Tue, Nov 8, 2022 at 7:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Nov 8, 2022 at 6:23 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> > > > <prabhakar.csengg@gmail.com> wrote:
> > > > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > >
> > > > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > > > > >
> > > > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > > > > RZ/Five SoC is built-in.
> > > > > > >
> > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > > > ---
> > > > > > > v4 -> v5
> > > > > > > * No change
> > > > > > >
> > > > > > > v3 -> v4
> > > > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > > > > tags with this change)
> > > > > > > * Used riscv instead of RISC-V in subject line
> > > > > >
> > > > > > Thanks for the update!
> > > > > >
> > > > > > > --- a/arch/riscv/configs/defconfig
> > > > > > > +++ b/arch/riscv/configs/defconfig
> > > > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > > > CONFIG_SOC_SIFIVE=y
> > > > > > > CONFIG_SOC_STARFIVE=y
> > > > > > > CONFIG_SOC_VIRT=y
> > > > > > > +CONFIG_ARCH_RENESAS=y
> > > > > > > +CONFIG_ARCH_R9A07G043=y
> > > > > >
> > > > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > > > > >
> > > > > Sorry I missed your point here, could you please elaborate.
> > > >
> > > > I mean that the options have moved, so you should update
> > > > your patch like this:
> > > >
> > > Ouch got that.
> > >
> > > > --- a/arch/riscv/configs/defconfig
> > > > +++ b/arch/riscv/configs/defconfig
> > > > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> > > > # CONFIG_SYSFS_SYSCALL is not set
> > > > CONFIG_PROFILING=y
> > > > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > +CONFIG_ARCH_RENESAS=y
> > > > CONFIG_SOC_SIFIVE=y
> > > > CONFIG_SOC_STARFIVE=y
> > > > CONFIG_SOC_VIRT=y
> > > > -CONFIG_ARCH_RENESAS=y
> > > > -CONFIG_ARCH_R9A07G043=y
> > > > CONFIG_SMP=y
> > > > CONFIG_HOTPLUG_CPU=y
> > > > CONFIG_PM=y
> > > > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> > > > CONFIG_RPMSG_CHAR=y
> > > > CONFIG_RPMSG_CTRL=y
> > > > CONFIG_RPMSG_VIRTIO=y
> > > > +CONFIG_ARCH_R9A07G043=y
> > > > CONFIG_EXT4_FS=y
> > > > CONFIG_EXT4_FS_POSIX_ACL=y
> > > > CONFIG_EXT4_FS_SECURITY=y
> > > >
> > > > > > > CONFIG_SMP=y
> > > > > > > CONFIG_HOTPLUG_CPU=y
> > > > > > > CONFIG_PM=y
> > > > > >
> > > > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > > > > after the release of v6.2-rc1, when all pieces have fallen together.
> > > > > >
> > > > > Are you suggesting dropping it from defconfig?
> > > >
> > > > Yes, but not right now, as that would make it depend on my
> > > > renesas-drivers-for-v6.2 branch to keep them enabled.
> > > >
> ^^^
> > > I was wondering if that's required by other platforms though.
> > > CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
> >
> > Does that matter? They would still get it, as long as they use the
> > defconfig.
> >
> Confused, didnt you say about dropping it from defconfig...
Yes, I did, but not right now, only after v6.2-rc1.
- Once the defconfig has CONFIG_ARCH_R9A07G043=y, ARCH_RZG2L will
be auto-selected (commit ebd0e06f3063cc2e ("soc: renesas: Identify
RZ/Five SoC") is already upstream), and CONFIG_PM as well. So there
is no longer a need for the defconfig to enable it explicitly.
- Once the defconfig has CONFIG_ARCH_RENESAS=y, SOC_RENESAS will
be auto-selected, but auto-selecting CONFIG_GPIOLIB depends on commit
b3acbca3c80e6124 ("soc: renesas: Kconfig: Explicitly select GPIOLIB and
PINCTRL config under SOC_RENESAS") is only in renesas-drivers-for-v6.2.
Please run "make savedefconfig", and compare the generated defconfig
with arch/riscv/configs/defconfig.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-11-09 7:46 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-09 7:46 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Tue, Nov 8, 2022 at 11:05 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Tue, Nov 8, 2022 at 7:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Nov 8, 2022 at 6:23 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> > > > <prabhakar.csengg@gmail.com> wrote:
> > > > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > >
> > > > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > > > > >
> > > > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > > > > RZ/Five SoC is built-in.
> > > > > > >
> > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > > > ---
> > > > > > > v4 -> v5
> > > > > > > * No change
> > > > > > >
> > > > > > > v3 -> v4
> > > > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > > > > tags with this change)
> > > > > > > * Used riscv instead of RISC-V in subject line
> > > > > >
> > > > > > Thanks for the update!
> > > > > >
> > > > > > > --- a/arch/riscv/configs/defconfig
> > > > > > > +++ b/arch/riscv/configs/defconfig
> > > > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > > > CONFIG_SOC_SIFIVE=y
> > > > > > > CONFIG_SOC_STARFIVE=y
> > > > > > > CONFIG_SOC_VIRT=y
> > > > > > > +CONFIG_ARCH_RENESAS=y
> > > > > > > +CONFIG_ARCH_R9A07G043=y
> > > > > >
> > > > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > > > > >
> > > > > Sorry I missed your point here, could you please elaborate.
> > > >
> > > > I mean that the options have moved, so you should update
> > > > your patch like this:
> > > >
> > > Ouch got that.
> > >
> > > > --- a/arch/riscv/configs/defconfig
> > > > +++ b/arch/riscv/configs/defconfig
> > > > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> > > > # CONFIG_SYSFS_SYSCALL is not set
> > > > CONFIG_PROFILING=y
> > > > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > +CONFIG_ARCH_RENESAS=y
> > > > CONFIG_SOC_SIFIVE=y
> > > > CONFIG_SOC_STARFIVE=y
> > > > CONFIG_SOC_VIRT=y
> > > > -CONFIG_ARCH_RENESAS=y
> > > > -CONFIG_ARCH_R9A07G043=y
> > > > CONFIG_SMP=y
> > > > CONFIG_HOTPLUG_CPU=y
> > > > CONFIG_PM=y
> > > > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> > > > CONFIG_RPMSG_CHAR=y
> > > > CONFIG_RPMSG_CTRL=y
> > > > CONFIG_RPMSG_VIRTIO=y
> > > > +CONFIG_ARCH_R9A07G043=y
> > > > CONFIG_EXT4_FS=y
> > > > CONFIG_EXT4_FS_POSIX_ACL=y
> > > > CONFIG_EXT4_FS_SECURITY=y
> > > >
> > > > > > > CONFIG_SMP=y
> > > > > > > CONFIG_HOTPLUG_CPU=y
> > > > > > > CONFIG_PM=y
> > > > > >
> > > > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > > > > after the release of v6.2-rc1, when all pieces have fallen together.
> > > > > >
> > > > > Are you suggesting dropping it from defconfig?
> > > >
> > > > Yes, but not right now, as that would make it depend on my
> > > > renesas-drivers-for-v6.2 branch to keep them enabled.
> > > >
> ^^^
> > > I was wondering if that's required by other platforms though.
> > > CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
> >
> > Does that matter? They would still get it, as long as they use the
> > defconfig.
> >
> Confused, didnt you say about dropping it from defconfig...
Yes, I did, but not right now, only after v6.2-rc1.
- Once the defconfig has CONFIG_ARCH_R9A07G043=y, ARCH_RZG2L will
be auto-selected (commit ebd0e06f3063cc2e ("soc: renesas: Identify
RZ/Five SoC") is already upstream), and CONFIG_PM as well. So there
is no longer a need for the defconfig to enable it explicitly.
- Once the defconfig has CONFIG_ARCH_RENESAS=y, SOC_RENESAS will
be auto-selected, but auto-selecting CONFIG_GPIOLIB depends on commit
b3acbca3c80e6124 ("soc: renesas: Kconfig: Explicitly select GPIOLIB and
PINCTRL config under SOC_RENESAS") is only in renesas-drivers-for-v6.2.
Please run "make savedefconfig", and compare the generated defconfig
with arch/riscv/configs/defconfig.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-11-09 7:46 ` Geert Uytterhoeven
@ 2022-11-09 9:16 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-09 9:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Geert,
On Wed, Nov 9, 2022 at 7:48 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 8, 2022 at 11:05 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Nov 8, 2022 at 7:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Tue, Nov 8, 2022 at 6:23 PM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> > > > > <prabhakar.csengg@gmail.com> wrote:
> > > > > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > >
> > > > > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > > > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > > > > > >
> > > > > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > > > > > RZ/Five SoC is built-in.
> > > > > > > >
> > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > > > > ---
> > > > > > > > v4 -> v5
> > > > > > > > * No change
> > > > > > > >
> > > > > > > > v3 -> v4
> > > > > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > > > > > tags with this change)
> > > > > > > > * Used riscv instead of RISC-V in subject line
> > > > > > >
> > > > > > > Thanks for the update!
> > > > > > >
> > > > > > > > --- a/arch/riscv/configs/defconfig
> > > > > > > > +++ b/arch/riscv/configs/defconfig
> > > > > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > > > > CONFIG_SOC_SIFIVE=y
> > > > > > > > CONFIG_SOC_STARFIVE=y
> > > > > > > > CONFIG_SOC_VIRT=y
> > > > > > > > +CONFIG_ARCH_RENESAS=y
> > > > > > > > +CONFIG_ARCH_R9A07G043=y
> > > > > > >
> > > > > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > > > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > > > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > > > > > >
> > > > > > Sorry I missed your point here, could you please elaborate.
> > > > >
> > > > > I mean that the options have moved, so you should update
> > > > > your patch like this:
> > > > >
> > > > Ouch got that.
> > > >
> > > > > --- a/arch/riscv/configs/defconfig
> > > > > +++ b/arch/riscv/configs/defconfig
> > > > > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> > > > > # CONFIG_SYSFS_SYSCALL is not set
> > > > > CONFIG_PROFILING=y
> > > > > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > +CONFIG_ARCH_RENESAS=y
> > > > > CONFIG_SOC_SIFIVE=y
> > > > > CONFIG_SOC_STARFIVE=y
> > > > > CONFIG_SOC_VIRT=y
> > > > > -CONFIG_ARCH_RENESAS=y
> > > > > -CONFIG_ARCH_R9A07G043=y
> > > > > CONFIG_SMP=y
> > > > > CONFIG_HOTPLUG_CPU=y
> > > > > CONFIG_PM=y
> > > > > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> > > > > CONFIG_RPMSG_CHAR=y
> > > > > CONFIG_RPMSG_CTRL=y
> > > > > CONFIG_RPMSG_VIRTIO=y
> > > > > +CONFIG_ARCH_R9A07G043=y
> > > > > CONFIG_EXT4_FS=y
> > > > > CONFIG_EXT4_FS_POSIX_ACL=y
> > > > > CONFIG_EXT4_FS_SECURITY=y
> > > > >
> > > > > > > > CONFIG_SMP=y
> > > > > > > > CONFIG_HOTPLUG_CPU=y
> > > > > > > > CONFIG_PM=y
> > > > > > >
> > > > > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > > > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > > > > > after the release of v6.2-rc1, when all pieces have fallen together.
> > > > > > >
> > > > > > Are you suggesting dropping it from defconfig?
> > > > >
> > > > > Yes, but not right now, as that would make it depend on my
> > > > > renesas-drivers-for-v6.2 branch to keep them enabled.
> > > > >
> > ^^^
> > > > I was wondering if that's required by other platforms though.
> > > > CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
> > >
> > > Does that matter? They would still get it, as long as they use the
> > > defconfig.
> > >
> > Confused, didnt you say about dropping it from defconfig...
>
> Yes, I did, but not right now, only after v6.2-rc1.
>
> - Once the defconfig has CONFIG_ARCH_R9A07G043=y, ARCH_RZG2L will
> be auto-selected (commit ebd0e06f3063cc2e ("soc: renesas: Identify
> RZ/Five SoC") is already upstream), and CONFIG_PM as well. So there
> is no longer a need for the defconfig to enable it explicitly.
> - Once the defconfig has CONFIG_ARCH_RENESAS=y, SOC_RENESAS will
> be auto-selected, but auto-selecting CONFIG_GPIOLIB depends on commit
> b3acbca3c80e6124 ("soc: renesas: Kconfig: Explicitly select GPIOLIB and
> PINCTRL config under SOC_RENESAS") is only in renesas-drivers-for-v6.2.
>
> Please run "make savedefconfig", and compare the generated defconfig
> with arch/riscv/configs/defconfig.
>
Thanks for the detailed explanation, I got you now :)
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
@ 2022-11-09 9:16 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-09 9:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Conor Dooley,
Guo Ren, Anup Patel, Atish Patra, Heinrich Schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Geert,
On Wed, Nov 9, 2022 at 7:48 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 8, 2022 at 11:05 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Nov 8, 2022 at 7:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Tue, Nov 8, 2022 at 6:23 PM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar
> > > > > <prabhakar.csengg@gmail.com> wrote:
> > > > > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > >
> > > > > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default
> > > > > > > > upstream kernel to boot on RZ/Five SMARC EVK board.
> > > > > > > >
> > > > > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by
> > > > > > > > RZ/Five SoC is built-in.
> > > > > > > >
> > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > > > > > ---
> > > > > > > > v4 -> v5
> > > > > > > > * No change
> > > > > > > >
> > > > > > > > v3 -> v4
> > > > > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
> > > > > > > > tags with this change)
> > > > > > > > * Used riscv instead of RISC-V in subject line
> > > > > > >
> > > > > > > Thanks for the update!
> > > > > > >
> > > > > > > > --- a/arch/riscv/configs/defconfig
> > > > > > > > +++ b/arch/riscv/configs/defconfig
> > > > > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > > > > CONFIG_SOC_SIFIVE=y
> > > > > > > > CONFIG_SOC_STARFIVE=y
> > > > > > > > CONFIG_SOC_VIRT=y
> > > > > > > > +CONFIG_ARCH_RENESAS=y
> > > > > > > > +CONFIG_ARCH_R9A07G043=y
> > > > > > >
> > > > > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv:
> > > > > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on
> > > > > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig.
> > > > > > >
> > > > > > Sorry I missed your point here, could you please elaborate.
> > > > >
> > > > > I mean that the options have moved, so you should update
> > > > > your patch like this:
> > > > >
> > > > Ouch got that.
> > > >
> > > > > --- a/arch/riscv/configs/defconfig
> > > > > +++ b/arch/riscv/configs/defconfig
> > > > > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y
> > > > > # CONFIG_SYSFS_SYSCALL is not set
> > > > > CONFIG_PROFILING=y
> > > > > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > > > > +CONFIG_ARCH_RENESAS=y
> > > > > CONFIG_SOC_SIFIVE=y
> > > > > CONFIG_SOC_STARFIVE=y
> > > > > CONFIG_SOC_VIRT=y
> > > > > -CONFIG_ARCH_RENESAS=y
> > > > > -CONFIG_ARCH_R9A07G043=y
> > > > > CONFIG_SMP=y
> > > > > CONFIG_HOTPLUG_CPU=y
> > > > > CONFIG_PM=y
> > > > > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y
> > > > > CONFIG_RPMSG_CHAR=y
> > > > > CONFIG_RPMSG_CTRL=y
> > > > > CONFIG_RPMSG_VIRTIO=y
> > > > > +CONFIG_ARCH_R9A07G043=y
> > > > > CONFIG_EXT4_FS=y
> > > > > CONFIG_EXT4_FS_POSIX_ACL=y
> > > > > CONFIG_EXT4_FS_SECURITY=y
> > > > >
> > > > > > > > CONFIG_SMP=y
> > > > > > > > CONFIG_HOTPLUG_CPU=y
> > > > > > > > CONFIG_PM=y
> > > > > > >
> > > > > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L)
> > > > > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this
> > > > > > > after the release of v6.2-rc1, when all pieces have fallen together.
> > > > > > >
> > > > > > Are you suggesting dropping it from defconfig?
> > > > >
> > > > > Yes, but not right now, as that would make it depend on my
> > > > > renesas-drivers-for-v6.2 branch to keep them enabled.
> > > > >
> > ^^^
> > > > I was wondering if that's required by other platforms though.
> > > > CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive.
> > >
> > > Does that matter? They would still get it, as long as they use the
> > > defconfig.
> > >
> > Confused, didnt you say about dropping it from defconfig...
>
> Yes, I did, but not right now, only after v6.2-rc1.
>
> - Once the defconfig has CONFIG_ARCH_R9A07G043=y, ARCH_RZG2L will
> be auto-selected (commit ebd0e06f3063cc2e ("soc: renesas: Identify
> RZ/Five SoC") is already upstream), and CONFIG_PM as well. So there
> is no longer a need for the defconfig to enable it explicitly.
> - Once the defconfig has CONFIG_ARCH_RENESAS=y, SOC_RENESAS will
> be auto-selected, but auto-selecting CONFIG_GPIOLIB depends on commit
> b3acbca3c80e6124 ("soc: renesas: Kconfig: Explicitly select GPIOLIB and
> PINCTRL config under SOC_RENESAS") is only in renesas-drivers-for-v6.2.
>
> Please run "make savedefconfig", and compare the generated defconfig
> with arch/riscv/configs/defconfig.
>
Thanks for the detailed explanation, I got you now :)
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-10-28 16:59 ` Prabhakar
@ 2022-10-30 18:24 ` Conor Dooley
-1 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-10-30 18:24 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> entry-class social infrastructure gateway control and industrial gateway
> control.
>
> This patch series adds initial SoC DTSi support for Renesas RZ/Five
> (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
Hey,
Looks like you've got a pair of warnings here from dtbs_check. I tested
this on top of 20221028's next, with the three branches below merged in,
hopefully my merges aren't the source of them:
linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
With this sorted, whatever wasn't already is now:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for putting up with my messing around re: kconfig symbols and I
am glad that we ended up being able to share the dts across archs in the
end, so thanks to everyone involved in that :)
> - PLIC
> - SCIF0
> - SYSC
>
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Patch series depends on the below patches (which are queued in the Renesas tree for v6.2):
> ------------------------------------------------------------------------------------
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=c27ce08b806d606cd5cd0e8252d1ed2b729b5b55
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=7dd1d57c052e88f98b9e9145461b13bca019d108
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-soc-for-v6.2&id=b3acbca3c80e612478b354e43c1480c3fc15873e
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=49669da644cf000eb79dbede55bd04acf3f2f0a0
> [4] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=b9a0be2054964026aa58966ce9724b672f210835
>
> v4 -> v5:
> ---------
> * Rebased patches on -next
> * Included RB tags
> * Dropped patches #1 and #4 (form v4) as they are queued up by Renesas trees
> * Patch #7 from v4 was not needed anymore so dropped it
> * Patches #4 and #5 are new
>
> v4: https://lore.kernel.org/all/20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> Below are the logs from RZ/Five SMARC EVK:
> ------------------------------------------
>
> / # uname -ra;
> Linux (none) 6.1.0-rc2-00036-gbad82a074f62 #145 SMP Fri Oct 28 17:18:41 BST 2022 riscv64 GNU/Linux
> / # cat /proc/cpuinfo;
> processor : 0
> hart : 0
> isa : rv64imafdc
> mmu : sv39
> uarch : andestech,ax45mp
> mvendorid : 0x31e
> marchid : 0x8000000000008a45
> mimpid : 0x500
>
> / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
> soc0/$i; done
> machine: Renesas SMARC EVK based on r9a07g043f01
> family: RZ/Five
> soc_id: r9a07g043
> revision: 0
> / #
> / # cat /proc/interrupts
> CPU0
> 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
> 2: 16 SiFive PLIC 414 Level 1004b800.serial:rx full
> 3: 402 SiFive PLIC 415 Level 1004b800.serial:tx empty
> 4: 0 SiFive PLIC 413 Level 1004b800.serial:break
> 5: 41826 RISC-V INTC 5 Edge riscv-timer
> 6: 10 SiFive PLIC 416 Level 1004b800.serial:rx ready
> IPI0: 0 Rescheduling interrupts
> IPI1: 0 Function call interrupts
> IPI2: 0 CPU stop interrupts
> IPI3: 0 IRQ work interrupts
> IPI4: 0 Timer broadcast interrupts
> / #
> / # cat /proc/meminfo
> MemTotal: 882252 kB
> MemFree: 860848 kB
> MemAvailable: 858608 kB
> Buffers: 0 kB
> Cached: 1796 kB
> SwapCached: 0 kB
> Active: 0 kB
> Inactive: 72 kB
> Active(anon): 0 kB
> Inactive(anon): 72 kB
> Active(file): 0 kB
> Inactive(file): 0 kB
> Unevictable: 1796 kB
> Mlocked: 0 kB
> SwapTotal: 0 kB
> SwapFree: 0 kB
> Dirty: 0 kB
> Writeback: 0 kB
> AnonPages: 108 kB
> Mapped: 1200 kB
> Shmem: 0 kB
> KReclaimable: 6760 kB
> Slab: 12360 kB
> SReclaimable: 6760 kB
> SUnreclaim: 5600 kB
> KernelStack: 620 kB
> PageTables: 32 kB
> SecPageTables: 0 kB
> NFS_Unstable: 0 kB
> Bounce: 0 kB
> WritebackTmp: 0 kB
> CommitLimit: 441124 kB
> Committed_AS: 592 kB
> VmallocTotal: 67108864 kB
> VmallocUsed: 1132 kB
> VmallocChunk: 0 kB
> Percpu: 84 kB
> HugePages_Total: 0
> HugePages_Free: 0
> HugePages_Rsvd: 0
> HugePages_Surp: 0
> Hugepagesize: 2048 kB
> Hugetlb: 0 kB
> / #
> / #
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (7):
> dt-bindings: riscv: Sort the CPU core list alphabetically
> dt-bindings: riscv: Add Andes AX45MP core to the list
> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> MAINTAINERS: Add entry for Renesas RISC-V
> riscv: configs: defconfig: Enable Renesas RZ/Five SoC
>
> .../devicetree/bindings/riscv/cpus.yaml | 11 ++-
> MAINTAINERS | 3 +-
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 ++++++++++++
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
> arch/riscv/configs/defconfig | 3 +
> 10 files changed, 252 insertions(+), 6 deletions(-)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-10-30 18:24 ` Conor Dooley
0 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-10-30 18:24 UTC (permalink / raw)
To: Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> entry-class social infrastructure gateway control and industrial gateway
> control.
>
> This patch series adds initial SoC DTSi support for Renesas RZ/Five
> (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
Hey,
Looks like you've got a pair of warnings here from dtbs_check. I tested
this on top of 20221028's next, with the three branches below merged in,
hopefully my merges aren't the source of them:
linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
With this sorted, whatever wasn't already is now:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for putting up with my messing around re: kconfig symbols and I
am glad that we ended up being able to share the dts across archs in the
end, so thanks to everyone involved in that :)
> - PLIC
> - SCIF0
> - SYSC
>
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Patch series depends on the below patches (which are queued in the Renesas tree for v6.2):
> ------------------------------------------------------------------------------------
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=c27ce08b806d606cd5cd0e8252d1ed2b729b5b55
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=7dd1d57c052e88f98b9e9145461b13bca019d108
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-soc-for-v6.2&id=b3acbca3c80e612478b354e43c1480c3fc15873e
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=49669da644cf000eb79dbede55bd04acf3f2f0a0
> [4] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=b9a0be2054964026aa58966ce9724b672f210835
>
> v4 -> v5:
> ---------
> * Rebased patches on -next
> * Included RB tags
> * Dropped patches #1 and #4 (form v4) as they are queued up by Renesas trees
> * Patch #7 from v4 was not needed anymore so dropped it
> * Patches #4 and #5 are new
>
> v4: https://lore.kernel.org/all/20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> Below are the logs from RZ/Five SMARC EVK:
> ------------------------------------------
>
> / # uname -ra;
> Linux (none) 6.1.0-rc2-00036-gbad82a074f62 #145 SMP Fri Oct 28 17:18:41 BST 2022 riscv64 GNU/Linux
> / # cat /proc/cpuinfo;
> processor : 0
> hart : 0
> isa : rv64imafdc
> mmu : sv39
> uarch : andestech,ax45mp
> mvendorid : 0x31e
> marchid : 0x8000000000008a45
> mimpid : 0x500
>
> / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
> soc0/$i; done
> machine: Renesas SMARC EVK based on r9a07g043f01
> family: RZ/Five
> soc_id: r9a07g043
> revision: 0
> / #
> / # cat /proc/interrupts
> CPU0
> 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
> 2: 16 SiFive PLIC 414 Level 1004b800.serial:rx full
> 3: 402 SiFive PLIC 415 Level 1004b800.serial:tx empty
> 4: 0 SiFive PLIC 413 Level 1004b800.serial:break
> 5: 41826 RISC-V INTC 5 Edge riscv-timer
> 6: 10 SiFive PLIC 416 Level 1004b800.serial:rx ready
> IPI0: 0 Rescheduling interrupts
> IPI1: 0 Function call interrupts
> IPI2: 0 CPU stop interrupts
> IPI3: 0 IRQ work interrupts
> IPI4: 0 Timer broadcast interrupts
> / #
> / # cat /proc/meminfo
> MemTotal: 882252 kB
> MemFree: 860848 kB
> MemAvailable: 858608 kB
> Buffers: 0 kB
> Cached: 1796 kB
> SwapCached: 0 kB
> Active: 0 kB
> Inactive: 72 kB
> Active(anon): 0 kB
> Inactive(anon): 72 kB
> Active(file): 0 kB
> Inactive(file): 0 kB
> Unevictable: 1796 kB
> Mlocked: 0 kB
> SwapTotal: 0 kB
> SwapFree: 0 kB
> Dirty: 0 kB
> Writeback: 0 kB
> AnonPages: 108 kB
> Mapped: 1200 kB
> Shmem: 0 kB
> KReclaimable: 6760 kB
> Slab: 12360 kB
> SReclaimable: 6760 kB
> SUnreclaim: 5600 kB
> KernelStack: 620 kB
> PageTables: 32 kB
> SecPageTables: 0 kB
> NFS_Unstable: 0 kB
> Bounce: 0 kB
> WritebackTmp: 0 kB
> CommitLimit: 441124 kB
> Committed_AS: 592 kB
> VmallocTotal: 67108864 kB
> VmallocUsed: 1132 kB
> VmallocChunk: 0 kB
> Percpu: 84 kB
> HugePages_Total: 0
> HugePages_Free: 0
> HugePages_Rsvd: 0
> HugePages_Surp: 0
> Hugepagesize: 2048 kB
> Hugetlb: 0 kB
> / #
> / #
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (7):
> dt-bindings: riscv: Sort the CPU core list alphabetically
> dt-bindings: riscv: Add Andes AX45MP core to the list
> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> MAINTAINERS: Add entry for Renesas RISC-V
> riscv: configs: defconfig: Enable Renesas RZ/Five SoC
>
> .../devicetree/bindings/riscv/cpus.yaml | 11 ++-
> MAINTAINERS | 3 +-
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 ++++++++++++
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
> arch/riscv/configs/defconfig | 3 +
> 10 files changed, 252 insertions(+), 6 deletions(-)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
>
> --
> 2.25.1
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-10-30 18:24 ` Conor Dooley
@ 2022-10-30 22:37 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-30 22:37 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Hi All,
> >
> > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > entry-class social infrastructure gateway control and industrial gateway
> > control.
> >
> > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
>
> Hey,
> Looks like you've got a pair of warnings here from dtbs_check. I tested
> this on top of 20221028's next, with the three branches below merged in,
> hopefully my merges aren't the source of them:
>
> linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
>
Thanks for the review and test. The warnings above are coming from [0]
as support for IRQC is missing, once that is added the warnings should
go away.
> With this sorted, whatever wasn't already is now:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Thanks for putting up with my messing around re: kconfig symbols and I
> am glad that we ended up being able to share the dts across archs in the
> end, so thanks to everyone involved in that :)
>
:-)
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-10-30 22:37 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-30 22:37 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Hi All,
> >
> > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > entry-class social infrastructure gateway control and industrial gateway
> > control.
> >
> > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
>
> Hey,
> Looks like you've got a pair of warnings here from dtbs_check. I tested
> this on top of 20221028's next, with the three branches below merged in,
> hopefully my merges aren't the source of them:
>
> linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
>
Thanks for the review and test. The warnings above are coming from [0]
as support for IRQC is missing, once that is added the warnings should
go away.
> With this sorted, whatever wasn't already is now:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Thanks for putting up with my messing around re: kconfig symbols and I
> am glad that we ended up being able to share the dts across archs in the
> end, so thanks to everyone involved in that :)
>
:-)
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-10-30 22:37 ` Lad, Prabhakar
@ 2022-10-30 22:45 ` Conor Dooley
-1 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-10-30 22:45 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> Hi Conor,
>
> On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Hi All,
> > >
> > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > entry-class social infrastructure gateway control and industrial gateway
> > > control.
> > >
> > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > - AX45MP CPU
> > > - CPG
> > > - PINCTRL
> >
> > Hey,
> > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > this on top of 20221028's next, with the three branches below merged in,
> > hopefully my merges aren't the source of them:
> >
> > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> >
> Thanks for the review and test. The warnings above are coming from [0]
> as support for IRQC is missing, once that is added the warnings should
> go away.
Right. I merged in the stuff in Geert's trees & I don't think I saw any
pending patches in the cover that I missed. Is there something else that
adds the support that's not going to make v6.2? I got rid of all the
dtbs_check warnings for v6.1 and I'd really like to keep things that
way!
> > With this sorted, whatever wasn't already is now:
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Thanks for putting up with my messing around re: kconfig symbols and I
> > am glad that we ended up being able to share the dts across archs in the
> > end, so thanks to everyone involved in that :)
> >
> :-)
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
>
> Cheers,
> Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-10-30 22:45 ` Conor Dooley
0 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-10-30 22:45 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> Hi Conor,
>
> On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Hi All,
> > >
> > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > entry-class social infrastructure gateway control and industrial gateway
> > > control.
> > >
> > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > - AX45MP CPU
> > > - CPG
> > > - PINCTRL
> >
> > Hey,
> > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > this on top of 20221028's next, with the three branches below merged in,
> > hopefully my merges aren't the source of them:
> >
> > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> >
> Thanks for the review and test. The warnings above are coming from [0]
> as support for IRQC is missing, once that is added the warnings should
> go away.
Right. I merged in the stuff in Geert's trees & I don't think I saw any
pending patches in the cover that I missed. Is there something else that
adds the support that's not going to make v6.2? I got rid of all the
dtbs_check warnings for v6.1 and I'd really like to keep things that
way!
> > With this sorted, whatever wasn't already is now:
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Thanks for putting up with my messing around re: kconfig symbols and I
> > am glad that we ended up being able to share the dts across archs in the
> > end, so thanks to everyone involved in that :)
> >
> :-)
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
>
> Cheers,
> Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-10-30 22:45 ` Conor Dooley
@ 2022-10-30 23:01 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-30 23:01 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Hi All,
> > > >
> > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > entry-class social infrastructure gateway control and industrial gateway
> > > > control.
> > > >
> > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > - AX45MP CPU
> > > > - CPG
> > > > - PINCTRL
> > >
> > > Hey,
> > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > this on top of 20221028's next, with the three branches below merged in,
> > > hopefully my merges aren't the source of them:
> > >
> > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > >
> > Thanks for the review and test. The warnings above are coming from [0]
> > as support for IRQC is missing, once that is added the warnings should
> > go away.
>
> Right. I merged in the stuff in Geert's trees & I don't think I saw any
> pending patches in the cover that I missed. Is there something else that
> adds the support that's not going to make v6.2? I got rid of all the
> dtbs_check warnings for v6.1 and I'd really like to keep things that
> way!
>
Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
cover letter. I'll make sure I get it posted asap and merged for v6.2.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-10-30 23:01 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-10-30 23:01 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Hi All,
> > > >
> > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > entry-class social infrastructure gateway control and industrial gateway
> > > > control.
> > > >
> > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > - AX45MP CPU
> > > > - CPG
> > > > - PINCTRL
> > >
> > > Hey,
> > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > this on top of 20221028's next, with the three branches below merged in,
> > > hopefully my merges aren't the source of them:
> > >
> > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > >
> > Thanks for the review and test. The warnings above are coming from [0]
> > as support for IRQC is missing, once that is added the warnings should
> > go away.
>
> Right. I merged in the stuff in Geert's trees & I don't think I saw any
> pending patches in the cover that I missed. Is there something else that
> adds the support that's not going to make v6.2? I got rid of all the
> dtbs_check warnings for v6.1 and I'd really like to keep things that
> way!
>
Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
cover letter. I'll make sure I get it posted asap and merged for v6.2.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-10-30 23:01 ` Lad, Prabhakar
@ 2022-11-07 18:03 ` Lad, Prabhakar
-1 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-07 18:03 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Conor,
>
> On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > > Hi Conor,
> > >
> > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > > >
> > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Hi All,
> > > > >
> > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > > entry-class social infrastructure gateway control and industrial gateway
> > > > > control.
> > > > >
> > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > - AX45MP CPU
> > > > > - CPG
> > > > > - PINCTRL
> > > >
> > > > Hey,
> > > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > > this on top of 20221028's next, with the three branches below merged in,
> > > > hopefully my merges aren't the source of them:
> > > >
> > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > >
> > > Thanks for the review and test. The warnings above are coming from [0]
> > > as support for IRQC is missing, once that is added the warnings should
> > > go away.
> >
> > Right. I merged in the stuff in Geert's trees & I don't think I saw any
> > pending patches in the cover that I missed. Is there something else that
> > adds the support that's not going to make v6.2? I got rid of all the
> > dtbs_check warnings for v6.1 and I'd really like to keep things that
> > way!
> >
> Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
> cover letter. I'll make sure I get it posted asap and merged for v6.2.
>
I have got the patches out [0] which will fix the warnings seen above.
BTW on the riscv patchwork I see status as fail "Patch does not apply
to for-next" does that mean I need to resend re-basing on your tree?
[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-11-07 18:03 ` Lad, Prabhakar
0 siblings, 0 replies; 92+ messages in thread
From: Lad, Prabhakar @ 2022-11-07 18:03 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Conor,
>
> On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > > Hi Conor,
> > >
> > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > > >
> > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Hi All,
> > > > >
> > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > > entry-class social infrastructure gateway control and industrial gateway
> > > > > control.
> > > > >
> > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > - AX45MP CPU
> > > > > - CPG
> > > > > - PINCTRL
> > > >
> > > > Hey,
> > > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > > this on top of 20221028's next, with the three branches below merged in,
> > > > hopefully my merges aren't the source of them:
> > > >
> > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > >
> > > Thanks for the review and test. The warnings above are coming from [0]
> > > as support for IRQC is missing, once that is added the warnings should
> > > go away.
> >
> > Right. I merged in the stuff in Geert's trees & I don't think I saw any
> > pending patches in the cover that I missed. Is there something else that
> > adds the support that's not going to make v6.2? I got rid of all the
> > dtbs_check warnings for v6.1 and I'd really like to keep things that
> > way!
> >
> Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
> cover letter. I'll make sure I get it posted asap and merged for v6.2.
>
I have got the patches out [0] which will fix the warnings seen above.
BTW on the riscv patchwork I see status as fail "Patch does not apply
to for-next" does that mean I need to resend re-basing on your tree?
[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-11-07 18:03 ` Lad, Prabhakar
@ 2022-11-07 18:17 ` Conor Dooley
-1 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-11-07 18:17 UTC (permalink / raw)
To: Lad, Prabhakar, geert+renesas
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
On Mon, Nov 07, 2022 at 06:03:41PM +0000, Lad, Prabhakar wrote:
> Hi Conor,
>
> On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Conor,
> >
> > On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > > > Hi Conor,
> > > >
> > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > > > >
> > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Hi All,
> > > > > >
> > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > > > entry-class social infrastructure gateway control and industrial gateway
> > > > > > control.
> > > > > >
> > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > > - AX45MP CPU
> > > > > > - CPG
> > > > > > - PINCTRL
> > > > >
> > > > > Hey,
> > > > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > > > this on top of 20221028's next, with the three branches below merged in,
> > > > > hopefully my merges aren't the source of them:
> > > > >
> > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > >
> > > > Thanks for the review and test. The warnings above are coming from [0]
> > > > as support for IRQC is missing, once that is added the warnings should
> > > > go away.
> > >
> > > Right. I merged in the stuff in Geert's trees & I don't think I saw any
> > > pending patches in the cover that I missed. Is there something else that
> > > adds the support that's not going to make v6.2? I got rid of all the
> > > dtbs_check warnings for v6.1 and I'd really like to keep things that
> > > way!
> > >
> > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
> > cover letter. I'll make sure I get it posted asap and merged for v6.2.
> >
> I have got the patches out [0] which will fix the warnings seen above.
Cool, thanks :)
>
> BTW on the riscv patchwork I see status as fail "Patch does not apply
> to for-next" does that mean I need to resend re-basing on your tree?
Nah, I though that Geert would be applying this patchset, no?
If that's the case, it only needs to apply to his tree.
Geert, are you waiting for an ack from Palmer?
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> Cheers,
> Prabhakar
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-11-07 18:17 ` Conor Dooley
0 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-11-07 18:17 UTC (permalink / raw)
To: Lad, Prabhakar, geert+renesas
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
On Mon, Nov 07, 2022 at 06:03:41PM +0000, Lad, Prabhakar wrote:
> Hi Conor,
>
> On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> >
> > Hi Conor,
> >
> > On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > > > Hi Conor,
> > > >
> > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > > > >
> > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Hi All,
> > > > > >
> > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > > > entry-class social infrastructure gateway control and industrial gateway
> > > > > > control.
> > > > > >
> > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > > - AX45MP CPU
> > > > > > - CPG
> > > > > > - PINCTRL
> > > > >
> > > > > Hey,
> > > > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > > > this on top of 20221028's next, with the three branches below merged in,
> > > > > hopefully my merges aren't the source of them:
> > > > >
> > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > >
> > > > Thanks for the review and test. The warnings above are coming from [0]
> > > > as support for IRQC is missing, once that is added the warnings should
> > > > go away.
> > >
> > > Right. I merged in the stuff in Geert's trees & I don't think I saw any
> > > pending patches in the cover that I missed. Is there something else that
> > > adds the support that's not going to make v6.2? I got rid of all the
> > > dtbs_check warnings for v6.1 and I'd really like to keep things that
> > > way!
> > >
> > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
> > cover letter. I'll make sure I get it posted asap and merged for v6.2.
> >
> I have got the patches out [0] which will fix the warnings seen above.
Cool, thanks :)
>
> BTW on the riscv patchwork I see status as fail "Patch does not apply
> to for-next" does that mean I need to resend re-basing on your tree?
Nah, I though that Geert would be applying this patchset, no?
If that's the case, it only needs to apply to his tree.
Geert, are you waiting for an ack from Palmer?
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> Cheers,
> Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-11-07 18:17 ` Conor Dooley
@ 2022-11-08 16:02 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 16:02 UTC (permalink / raw)
To: Conor Dooley
Cc: Lad, Prabhakar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@kernel.org> wrote:
> On Mon, Nov 07, 2022 at 06:03:41PM +0000, Lad, Prabhakar wrote:
> > On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
> > > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > > > > entry-class social infrastructure gateway control and industrial gateway
> > > > > > > control.
> > > > > > >
> > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > > > - AX45MP CPU
> > > > > > > - CPG
> > > > > > > - PINCTRL
> > > > > >
> > > > > > Hey,
> > > > > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > > > > this on top of 20221028's next, with the three branches below merged in,
> > > > > > hopefully my merges aren't the source of them:
> > > > > >
> > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > > >
> > > > > Thanks for the review and test. The warnings above are coming from [0]
> > > > > as support for IRQC is missing, once that is added the warnings should
> > > > > go away.
> > > >
> > > > Right. I merged in the stuff in Geert's trees & I don't think I saw any
> > > > pending patches in the cover that I missed. Is there something else that
> > > > adds the support that's not going to make v6.2? I got rid of all the
> > > > dtbs_check warnings for v6.1 and I'd really like to keep things that
> > > > way!
> > > >
> > > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
> > > cover letter. I'll make sure I get it posted asap and merged for v6.2.
> > BTW on the riscv patchwork I see status as fail "Patch does not apply
> > to for-next" does that mean I need to resend re-basing on your tree?
>
> Nah, I though that Geert would be applying this patchset, no?
> If that's the case, it only needs to apply to his tree.
>
> Geert, are you waiting for an ack from Palmer?
I can take:
- [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for
Renesas RZ/Five SoC
- [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas
RZ/Five SMARC EVK
- [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
(4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel
them to the SoC-people.
I can take
- [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
- [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
with an ack from Palmer.
The rest
- [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
- [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
should probably go through the riscv tree, to avoid merge conflicts
when support for other SoCs is added?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-11-08 16:02 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-08 16:02 UTC (permalink / raw)
To: Conor Dooley
Cc: Lad, Prabhakar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@kernel.org> wrote:
> On Mon, Nov 07, 2022 at 06:03:41PM +0000, Lad, Prabhakar wrote:
> > On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
> > > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > > > > entry-class social infrastructure gateway control and industrial gateway
> > > > > > > control.
> > > > > > >
> > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > > > - AX45MP CPU
> > > > > > > - CPG
> > > > > > > - PINCTRL
> > > > > >
> > > > > > Hey,
> > > > > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > > > > this on top of 20221028's next, with the three branches below merged in,
> > > > > > hopefully my merges aren't the source of them:
> > > > > >
> > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > > > > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > > > > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > > >
> > > > > Thanks for the review and test. The warnings above are coming from [0]
> > > > > as support for IRQC is missing, once that is added the warnings should
> > > > > go away.
> > > >
> > > > Right. I merged in the stuff in Geert's trees & I don't think I saw any
> > > > pending patches in the cover that I missed. Is there something else that
> > > > adds the support that's not going to make v6.2? I got rid of all the
> > > > dtbs_check warnings for v6.1 and I'd really like to keep things that
> > > > way!
> > > >
> > > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
> > > cover letter. I'll make sure I get it posted asap and merged for v6.2.
> > BTW on the riscv patchwork I see status as fail "Patch does not apply
> > to for-next" does that mean I need to resend re-basing on your tree?
>
> Nah, I though that Geert would be applying this patchset, no?
> If that's the case, it only needs to apply to his tree.
>
> Geert, are you waiting for an ack from Palmer?
I can take:
- [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for
Renesas RZ/Five SoC
- [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas
RZ/Five SMARC EVK
- [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
(4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel
them to the SoC-people.
I can take
- [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
- [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
with an ack from Palmer.
The rest
- [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
- [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
should probably go through the riscv tree, to avoid merge conflicts
when support for other SoCs is added?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-11-08 16:02 ` Geert Uytterhoeven
@ 2022-11-08 19:29 ` Conor Dooley
-1 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-11-08 19:29 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad, Prabhakar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
On Tue, Nov 08, 2022 at 05:02:57PM +0100, Geert Uytterhoeven wrote:
> Hi Conor,
> On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@kernel.org> wrote:
> > Geert, are you waiting for an ack from Palmer?
>
> I can take:
> - [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for
> Renesas RZ/Five SoC
> - [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas
> RZ/Five SMARC EVK
> - [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
> (4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel
> them to the SoC-people.
>
> I can take
> - [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> - [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
> with an ack from Palmer.
>
> The rest
> - [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
> - [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
> should probably go through the riscv tree, to avoid merge conflicts
> when support for other SoCs is added?
Or depending on the outcome of [0], maybe I take the dt-binding stuff?
Either way, looks like an ack from Palmer is needed for 3 & 7. I can do
the video call version of a ping on that tomorrow at the pw sync thing.
[0] - https://lore.kernel.org/linux-riscv/Y2puchRvbo6+YJSy@wendy/T/#me49f1e779dee210d3ab6fc4bc308dbaed036e1a8
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-11-08 19:29 ` Conor Dooley
0 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-11-08 19:29 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad, Prabhakar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner,
Conor Dooley, Guo Ren, Anup Patel, Atish Patra,
Heinrich Schuchardt, devicetree, linux-riscv, linux-kernel,
linux-renesas-soc, Biju Das, Lad Prabhakar
On Tue, Nov 08, 2022 at 05:02:57PM +0100, Geert Uytterhoeven wrote:
> Hi Conor,
> On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@kernel.org> wrote:
> > Geert, are you waiting for an ack from Palmer?
>
> I can take:
> - [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for
> Renesas RZ/Five SoC
> - [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas
> RZ/Five SMARC EVK
> - [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
> (4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel
> them to the SoC-people.
>
> I can take
> - [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> - [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
> with an ack from Palmer.
>
> The rest
> - [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
> - [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
> should probably go through the riscv tree, to avoid merge conflicts
> when support for other SoCs is added?
Or depending on the outcome of [0], maybe I take the dt-binding stuff?
Either way, looks like an ack from Palmer is needed for 3 & 7. I can do
the video call version of a ping on that tomorrow at the pw sync thing.
[0] - https://lore.kernel.org/linux-riscv/Y2puchRvbo6+YJSy@wendy/T/#me49f1e779dee210d3ab6fc4bc308dbaed036e1a8
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-10-28 16:59 ` Prabhakar
@ 2022-11-09 19:55 ` Palmer Dabbelt
-1 siblings, 0 replies; 92+ messages in thread
From: Palmer Dabbelt @ 2022-11-09 19:55 UTC (permalink / raw)
To: prabhakar.csengg
Cc: Paul Walmsley, aou, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, heiko, Conor Dooley, guoren, anup,
Atish Patra, heinrich.schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, prabhakar.csengg, biju.das.jz,
prabhakar.mahadev-lad.rj
On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> entry-class social infrastructure gateway control and industrial gateway
> control.
>
> This patch series adds initial SoC DTSi support for Renesas RZ/Five
> (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Patch series depends on the below patches (which are queued in the Renesas tree for v6.2):
> ------------------------------------------------------------------------------------
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=c27ce08b806d606cd5cd0e8252d1ed2b729b5b55
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=7dd1d57c052e88f98b9e9145461b13bca019d108
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-soc-for-v6.2&id=b3acbca3c80e612478b354e43c1480c3fc15873e
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=49669da644cf000eb79dbede55bd04acf3f2f0a0
> [4] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=b9a0be2054964026aa58966ce9724b672f210835
>
> v4 -> v5:
> ---------
> * Rebased patches on -next
> * Included RB tags
> * Dropped patches #1 and #4 (form v4) as they are queued up by Renesas trees
> * Patch #7 from v4 was not needed anymore so dropped it
> * Patches #4 and #5 are new
>
> v4: https://lore.kernel.org/all/20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> Below are the logs from RZ/Five SMARC EVK:
> ------------------------------------------
>
> / # uname -ra;
> Linux (none) 6.1.0-rc2-00036-gbad82a074f62 #145 SMP Fri Oct 28 17:18:41 BST 2022 riscv64 GNU/Linux
> / # cat /proc/cpuinfo;
> processor : 0
> hart : 0
> isa : rv64imafdc
> mmu : sv39
> uarch : andestech,ax45mp
> mvendorid : 0x31e
> marchid : 0x8000000000008a45
> mimpid : 0x500
>
> / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
> soc0/$i; done
> machine: Renesas SMARC EVK based on r9a07g043f01
> family: RZ/Five
> soc_id: r9a07g043
> revision: 0
> / #
> / # cat /proc/interrupts
> CPU0
> 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
> 2: 16 SiFive PLIC 414 Level 1004b800.serial:rx full
> 3: 402 SiFive PLIC 415 Level 1004b800.serial:tx empty
> 4: 0 SiFive PLIC 413 Level 1004b800.serial:break
> 5: 41826 RISC-V INTC 5 Edge riscv-timer
> 6: 10 SiFive PLIC 416 Level 1004b800.serial:rx ready
> IPI0: 0 Rescheduling interrupts
> IPI1: 0 Function call interrupts
> IPI2: 0 CPU stop interrupts
> IPI3: 0 IRQ work interrupts
> IPI4: 0 Timer broadcast interrupts
> / #
> / # cat /proc/meminfo
> MemTotal: 882252 kB
> MemFree: 860848 kB
> MemAvailable: 858608 kB
> Buffers: 0 kB
> Cached: 1796 kB
> SwapCached: 0 kB
> Active: 0 kB
> Inactive: 72 kB
> Active(anon): 0 kB
> Inactive(anon): 72 kB
> Active(file): 0 kB
> Inactive(file): 0 kB
> Unevictable: 1796 kB
> Mlocked: 0 kB
> SwapTotal: 0 kB
> SwapFree: 0 kB
> Dirty: 0 kB
> Writeback: 0 kB
> AnonPages: 108 kB
> Mapped: 1200 kB
> Shmem: 0 kB
> KReclaimable: 6760 kB
> Slab: 12360 kB
> SReclaimable: 6760 kB
> SUnreclaim: 5600 kB
> KernelStack: 620 kB
> PageTables: 32 kB
> SecPageTables: 0 kB
> NFS_Unstable: 0 kB
> Bounce: 0 kB
> WritebackTmp: 0 kB
> CommitLimit: 441124 kB
> Committed_AS: 592 kB
> VmallocTotal: 67108864 kB
> VmallocUsed: 1132 kB
> VmallocChunk: 0 kB
> Percpu: 84 kB
> HugePages_Total: 0
> HugePages_Free: 0
> HugePages_Rsvd: 0
> HugePages_Surp: 0
> Hugepagesize: 2048 kB
> Hugetlb: 0 kB
> / #
> / #
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (7):
> dt-bindings: riscv: Sort the CPU core list alphabetically
> dt-bindings: riscv: Add Andes AX45MP core to the list
> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> MAINTAINERS: Add entry for Renesas RISC-V
> riscv: configs: defconfig: Enable Renesas RZ/Five SoC
>
> .../devicetree/bindings/riscv/cpus.yaml | 11 ++-
> MAINTAINERS | 3 +-
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 ++++++++++++
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
> arch/riscv/configs/defconfig | 3 +
> 10 files changed, 252 insertions(+), 6 deletions(-)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
Geert was mentioning taking these though one of his trees, that works
for me so
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Happy to do a shared tag or whatever, but I think we can just skip that
here. The only conflicts would be defconfig and Kconfig.socs, but I
don't think anything big is in the works for either -- unless Conor was
planning on re-spinning that Kconfig.socs rework?
Thanks!
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-11-09 19:55 ` Palmer Dabbelt
0 siblings, 0 replies; 92+ messages in thread
From: Palmer Dabbelt @ 2022-11-09 19:55 UTC (permalink / raw)
To: prabhakar.csengg
Cc: Paul Walmsley, aou, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, heiko, Conor Dooley, guoren, anup,
Atish Patra, heinrich.schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, prabhakar.csengg, biju.das.jz,
prabhakar.mahadev-lad.rj
On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> entry-class social infrastructure gateway control and industrial gateway
> control.
>
> This patch series adds initial SoC DTSi support for Renesas RZ/Five
> (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Patch series depends on the below patches (which are queued in the Renesas tree for v6.2):
> ------------------------------------------------------------------------------------
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=c27ce08b806d606cd5cd0e8252d1ed2b729b5b55
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-dt-bindings-for-v6.2&id=7dd1d57c052e88f98b9e9145461b13bca019d108
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-soc-for-v6.2&id=b3acbca3c80e612478b354e43c1480c3fc15873e
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=49669da644cf000eb79dbede55bd04acf3f2f0a0
> [4] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=renesas-arm-dt-for-v6.2&id=b9a0be2054964026aa58966ce9724b672f210835
>
> v4 -> v5:
> ---------
> * Rebased patches on -next
> * Included RB tags
> * Dropped patches #1 and #4 (form v4) as they are queued up by Renesas trees
> * Patch #7 from v4 was not needed anymore so dropped it
> * Patches #4 and #5 are new
>
> v4: https://lore.kernel.org/all/20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> Below are the logs from RZ/Five SMARC EVK:
> ------------------------------------------
>
> / # uname -ra;
> Linux (none) 6.1.0-rc2-00036-gbad82a074f62 #145 SMP Fri Oct 28 17:18:41 BST 2022 riscv64 GNU/Linux
> / # cat /proc/cpuinfo;
> processor : 0
> hart : 0
> isa : rv64imafdc
> mmu : sv39
> uarch : andestech,ax45mp
> mvendorid : 0x31e
> marchid : 0x8000000000008a45
> mimpid : 0x500
>
> / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
> soc0/$i; done
> machine: Renesas SMARC EVK based on r9a07g043f01
> family: RZ/Five
> soc_id: r9a07g043
> revision: 0
> / #
> / # cat /proc/interrupts
> CPU0
> 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
> 2: 16 SiFive PLIC 414 Level 1004b800.serial:rx full
> 3: 402 SiFive PLIC 415 Level 1004b800.serial:tx empty
> 4: 0 SiFive PLIC 413 Level 1004b800.serial:break
> 5: 41826 RISC-V INTC 5 Edge riscv-timer
> 6: 10 SiFive PLIC 416 Level 1004b800.serial:rx ready
> IPI0: 0 Rescheduling interrupts
> IPI1: 0 Function call interrupts
> IPI2: 0 CPU stop interrupts
> IPI3: 0 IRQ work interrupts
> IPI4: 0 Timer broadcast interrupts
> / #
> / # cat /proc/meminfo
> MemTotal: 882252 kB
> MemFree: 860848 kB
> MemAvailable: 858608 kB
> Buffers: 0 kB
> Cached: 1796 kB
> SwapCached: 0 kB
> Active: 0 kB
> Inactive: 72 kB
> Active(anon): 0 kB
> Inactive(anon): 72 kB
> Active(file): 0 kB
> Inactive(file): 0 kB
> Unevictable: 1796 kB
> Mlocked: 0 kB
> SwapTotal: 0 kB
> SwapFree: 0 kB
> Dirty: 0 kB
> Writeback: 0 kB
> AnonPages: 108 kB
> Mapped: 1200 kB
> Shmem: 0 kB
> KReclaimable: 6760 kB
> Slab: 12360 kB
> SReclaimable: 6760 kB
> SUnreclaim: 5600 kB
> KernelStack: 620 kB
> PageTables: 32 kB
> SecPageTables: 0 kB
> NFS_Unstable: 0 kB
> Bounce: 0 kB
> WritebackTmp: 0 kB
> CommitLimit: 441124 kB
> Committed_AS: 592 kB
> VmallocTotal: 67108864 kB
> VmallocUsed: 1132 kB
> VmallocChunk: 0 kB
> Percpu: 84 kB
> HugePages_Total: 0
> HugePages_Free: 0
> HugePages_Rsvd: 0
> HugePages_Surp: 0
> Hugepagesize: 2048 kB
> Hugetlb: 0 kB
> / #
> / #
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (7):
> dt-bindings: riscv: Sort the CPU core list alphabetically
> dt-bindings: riscv: Add Andes AX45MP core to the list
> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> MAINTAINERS: Add entry for Renesas RISC-V
> riscv: configs: defconfig: Enable Renesas RZ/Five SoC
>
> .../devicetree/bindings/riscv/cpus.yaml | 11 ++-
> MAINTAINERS | 3 +-
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 ++++++++++++
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++
> arch/riscv/configs/defconfig | 3 +
> 10 files changed, 252 insertions(+), 6 deletions(-)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
Geert was mentioning taking these though one of his trees, that works
for me so
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Happy to do a shared tag or whatever, but I think we can just skip that
here. The only conflicts would be defconfig and Kconfig.socs, but I
don't think anything big is in the works for either -- unless Conor was
planning on re-spinning that Kconfig.socs rework?
Thanks!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-11-09 19:55 ` Palmer Dabbelt
@ 2022-11-09 21:21 ` Conor Dooley
-1 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-11-09 21:21 UTC (permalink / raw)
To: Palmer Dabbelt, geert+renesas
Cc: prabhakar.csengg, Paul Walmsley, aou, geert+renesas, magnus.damm,
robh+dt, krzysztof.kozlowski+dt, heiko, Conor Dooley, guoren,
anup, Atish Patra, heinrich.schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, biju.das.jz,
prabhakar.mahadev-lad.rj
On Wed, Nov 09, 2022 at 11:55:24AM -0800, Palmer Dabbelt wrote:
> On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Lad Prabhakar (7):
> > dt-bindings: riscv: Sort the CPU core list alphabetically
> > dt-bindings: riscv: Add Andes AX45MP core to the list
> > riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> > riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> > riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> > MAINTAINERS: Add entry for Renesas RISC-V
> > riscv: configs: defconfig: Enable Renesas RZ/Five SoC
> Geert was mentioning taking these though one of his trees, that works for me
> so
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Happy to do a shared tag or whatever, but I think we can just skip that
> here. The only conflicts would be defconfig and Kconfig.socs, but I don't
> think anything big is in the works for either -- unless Conor was planning
> on re-spinning that Kconfig.socs rework?
Uh, nah. I've got a wee bit (the removal of selects) that is "ready" but
there's zero urgency so it can wait for after v6.2-rc1. I don't think
it'd conflict anyway. The rest of it I need to sort out a v1 of, but I've
been distracted. Should be safe to take the defconfig & Kconfig.socs stuff
in terms of me doing anything.
Geert, would you be able to apply the first two patches on top of
v6.1-rc1 just in case, as you mentioned previously, it needs to become
part of a shared branch? Seems unlikely at this point in the cycle
though.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-11-09 21:21 ` Conor Dooley
0 siblings, 0 replies; 92+ messages in thread
From: Conor Dooley @ 2022-11-09 21:21 UTC (permalink / raw)
To: Palmer Dabbelt, geert+renesas
Cc: prabhakar.csengg, Paul Walmsley, aou, geert+renesas, magnus.damm,
robh+dt, krzysztof.kozlowski+dt, heiko, Conor Dooley, guoren,
anup, Atish Patra, heinrich.schuchardt, devicetree, linux-riscv,
linux-kernel, linux-renesas-soc, biju.das.jz,
prabhakar.mahadev-lad.rj
On Wed, Nov 09, 2022 at 11:55:24AM -0800, Palmer Dabbelt wrote:
> On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Lad Prabhakar (7):
> > dt-bindings: riscv: Sort the CPU core list alphabetically
> > dt-bindings: riscv: Add Andes AX45MP core to the list
> > riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> > riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> > riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> > MAINTAINERS: Add entry for Renesas RISC-V
> > riscv: configs: defconfig: Enable Renesas RZ/Five SoC
> Geert was mentioning taking these though one of his trees, that works for me
> so
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Happy to do a shared tag or whatever, but I think we can just skip that
> here. The only conflicts would be defconfig and Kconfig.socs, but I don't
> think anything big is in the works for either -- unless Conor was planning
> on re-spinning that Kconfig.socs rework?
Uh, nah. I've got a wee bit (the removal of selects) that is "ready" but
there's zero urgency so it can wait for after v6.2-rc1. I don't think
it'd conflict anyway. The rest of it I need to sort out a v1 of, but I've
been distracted. Should be safe to take the defconfig & Kconfig.socs stuff
in terms of me doing anything.
Geert, would you be able to apply the first two patches on top of
v6.1-rc1 just in case, as you mentioned previously, it needs to become
part of a shared branch? Seems unlikely at this point in the cycle
though.
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
2022-11-09 21:21 ` Conor Dooley
@ 2022-11-10 16:17 ` Geert Uytterhoeven
-1 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-10 16:17 UTC (permalink / raw)
To: Conor Dooley
Cc: Palmer Dabbelt, prabhakar.csengg, Paul Walmsley, aou,
magnus.damm, robh+dt, krzysztof.kozlowski+dt, heiko,
Conor Dooley, guoren, anup, Atish Patra, heinrich.schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
biju.das.jz, prabhakar.mahadev-lad.rj
Hi Conor,
On Wed, Nov 9, 2022 at 10:21 PM Conor Dooley <conor@kernel.org> wrote:
> On Wed, Nov 09, 2022 at 11:55:24AM -0800, Palmer Dabbelt wrote:
> > On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote:
> > > Lad Prabhakar (7):
> > > dt-bindings: riscv: Sort the CPU core list alphabetically
> > > dt-bindings: riscv: Add Andes AX45MP core to the list
> > > riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> > > riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> > > riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> > > MAINTAINERS: Add entry for Renesas RISC-V
> > > riscv: configs: defconfig: Enable Renesas RZ/Five SoC
>
> > Geert was mentioning taking these though one of his trees, that works for me
> > so
> >
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Series queued in renesas-devel for v6.2, spread across a few existing
and new branches to be pulled by soc, taking into account dependencies.
> > Happy to do a shared tag or whatever, but I think we can just skip that
> > here. The only conflicts would be defconfig and Kconfig.socs, but I don't
> > think anything big is in the works for either -- unless Conor was planning
> > on re-spinning that Kconfig.socs rework?
>
> Uh, nah. I've got a wee bit (the removal of selects) that is "ready" but
> there's zero urgency so it can wait for after v6.2-rc1. I don't think
> it'd conflict anyway. The rest of it I need to sort out a v1 of, but I've
> been distracted. Should be safe to take the defconfig & Kconfig.socs stuff
> in terms of me doing anything.
>
> Geert, would you be able to apply the first two patches on top of
> v6.1-rc1 just in case, as you mentioned previously, it needs to become
> part of a shared branch? Seems unlikely at this point in the cycle
> though.
The bindings are in the existing renesas-dt-bindings-for-v6.2 branch,
which is based on v6.1-rc1, and only had RZ/Five related commits anyway.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 92+ messages in thread* Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
@ 2022-11-10 16:17 ` Geert Uytterhoeven
0 siblings, 0 replies; 92+ messages in thread
From: Geert Uytterhoeven @ 2022-11-10 16:17 UTC (permalink / raw)
To: Conor Dooley
Cc: Palmer Dabbelt, prabhakar.csengg, Paul Walmsley, aou,
magnus.damm, robh+dt, krzysztof.kozlowski+dt, heiko,
Conor Dooley, guoren, anup, Atish Patra, heinrich.schuchardt,
devicetree, linux-riscv, linux-kernel, linux-renesas-soc,
biju.das.jz, prabhakar.mahadev-lad.rj
Hi Conor,
On Wed, Nov 9, 2022 at 10:21 PM Conor Dooley <conor@kernel.org> wrote:
> On Wed, Nov 09, 2022 at 11:55:24AM -0800, Palmer Dabbelt wrote:
> > On Fri, 28 Oct 2022 09:59:14 PDT (-0700), prabhakar.csengg@gmail.com wrote:
> > > Lad Prabhakar (7):
> > > dt-bindings: riscv: Sort the CPU core list alphabetically
> > > dt-bindings: riscv: Add Andes AX45MP core to the list
> > > riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> > > riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> > > riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> > > MAINTAINERS: Add entry for Renesas RISC-V
> > > riscv: configs: defconfig: Enable Renesas RZ/Five SoC
>
> > Geert was mentioning taking these though one of his trees, that works for me
> > so
> >
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Series queued in renesas-devel for v6.2, spread across a few existing
and new branches to be pulled by soc, taking into account dependencies.
> > Happy to do a shared tag or whatever, but I think we can just skip that
> > here. The only conflicts would be defconfig and Kconfig.socs, but I don't
> > think anything big is in the works for either -- unless Conor was planning
> > on re-spinning that Kconfig.socs rework?
>
> Uh, nah. I've got a wee bit (the removal of selects) that is "ready" but
> there's zero urgency so it can wait for after v6.2-rc1. I don't think
> it'd conflict anyway. The rest of it I need to sort out a v1 of, but I've
> been distracted. Should be safe to take the defconfig & Kconfig.socs stuff
> in terms of me doing anything.
>
> Geert, would you be able to apply the first two patches on top of
> v6.1-rc1 just in case, as you mentioned previously, it needs to become
> part of a shared branch? Seems unlikely at this point in the cycle
> though.
The bindings are in the existing renesas-dt-bindings-for-v6.2 branch,
which is based on v6.1-rc1, and only had RZ/Five related commits anyway.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 92+ messages in thread