From: Atish Patra <atishp@atishpatra.org>
To: Anup Patel <anup.patel@wdc.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
KVM General <kvm@vger.kernel.org>,
kvm-riscv@lists.infradead.org,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions
Date: Thu, 16 Dec 2021 21:42:35 -0800 [thread overview]
Message-ID: <CAOnJCU+=SfN0e-prQsrR8BHfcs7hP9Ab61cnD-yOEZZQ2Gh9cA@mail.gmail.com> (raw)
In-Reply-To: <20211129075451.418122-2-anup.patel@wdc.com>
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The SBI experimental extension space is for temporary (or experimental)
> stuff whereas SBI vendor extension space is for hardware vendor specific
> stuff. Both these SBI extension spaces won't be standardized by the SBI
> specification so let's blindly forward such SBI calls to the userspace.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/kvm/vcpu_sbi.c | 4 ++++
> arch/riscv/kvm/vcpu_sbi_base.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index f62d25bc9733..78aa3db76225 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -46,6 +46,8 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor;
>
> static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_v01,
> @@ -54,6 +56,8 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_ipi,
> &vcpu_sbi_ext_rfence,
> &vcpu_sbi_ext_hsm,
> + &vcpu_sbi_ext_experimental,
> + &vcpu_sbi_ext_vendor,
> };
>
> void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 641015549d12..ac0537d479d8 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -68,3 +68,30 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base = {
> .extid_end = SBI_EXT_BASE,
> .handler = kvm_sbi_ext_base_handler,
> };
> +
> +static int kvm_sbi_ext_forward_handler(struct kvm_vcpu *vcpu,
> + struct kvm_run *run,
> + unsigned long *out_val,
> + struct kvm_cpu_trap *utrap,
> + bool *exit)
> +{
> + /*
> + * Both SBI experimental and vendor extensions are
> + * unconditionally forwarded to userspace.
> + */
> + kvm_riscv_vcpu_sbi_forward(vcpu, run);
> + *exit = true;
> + return 0;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental = {
> + .extid_start = SBI_EXT_EXPERIMENTAL_START,
> + .extid_end = SBI_EXT_EXPERIMENTAL_END,
> + .handler = kvm_sbi_ext_forward_handler,
> +};
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor = {
> + .extid_start = SBI_EXT_VENDOR_START,
> + .extid_end = SBI_EXT_VENDOR_END,
> + .handler = kvm_sbi_ext_forward_handler,
> +};
> --
> 2.25.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
--
Regards,
Atish
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@atishpatra.org>
To: Anup Patel <anup.patel@wdc.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
KVM General <kvm@vger.kernel.org>,
kvm-riscv@lists.infradead.org,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions
Date: Thu, 16 Dec 2021 21:42:35 -0800 [thread overview]
Message-ID: <CAOnJCU+=SfN0e-prQsrR8BHfcs7hP9Ab61cnD-yOEZZQ2Gh9cA@mail.gmail.com> (raw)
In-Reply-To: <20211129075451.418122-2-anup.patel@wdc.com>
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The SBI experimental extension space is for temporary (or experimental)
> stuff whereas SBI vendor extension space is for hardware vendor specific
> stuff. Both these SBI extension spaces won't be standardized by the SBI
> specification so let's blindly forward such SBI calls to the userspace.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/kvm/vcpu_sbi.c | 4 ++++
> arch/riscv/kvm/vcpu_sbi_base.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index f62d25bc9733..78aa3db76225 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -46,6 +46,8 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor;
>
> static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_v01,
> @@ -54,6 +56,8 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_ipi,
> &vcpu_sbi_ext_rfence,
> &vcpu_sbi_ext_hsm,
> + &vcpu_sbi_ext_experimental,
> + &vcpu_sbi_ext_vendor,
> };
>
> void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 641015549d12..ac0537d479d8 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -68,3 +68,30 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base = {
> .extid_end = SBI_EXT_BASE,
> .handler = kvm_sbi_ext_base_handler,
> };
> +
> +static int kvm_sbi_ext_forward_handler(struct kvm_vcpu *vcpu,
> + struct kvm_run *run,
> + unsigned long *out_val,
> + struct kvm_cpu_trap *utrap,
> + bool *exit)
> +{
> + /*
> + * Both SBI experimental and vendor extensions are
> + * unconditionally forwarded to userspace.
> + */
> + kvm_riscv_vcpu_sbi_forward(vcpu, run);
> + *exit = true;
> + return 0;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental = {
> + .extid_start = SBI_EXT_EXPERIMENTAL_START,
> + .extid_end = SBI_EXT_EXPERIMENTAL_END,
> + .handler = kvm_sbi_ext_forward_handler,
> +};
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor = {
> + .extid_start = SBI_EXT_VENDOR_START,
> + .extid_end = SBI_EXT_VENDOR_END,
> + .handler = kvm_sbi_ext_forward_handler,
> +};
> --
> 2.25.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-12-17 5:42 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-29 7:54 [PATCH v2 0/4] KVM RISC-V 64-bit selftests support Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-11-29 7:54 ` [PATCH v2 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-12-17 5:42 ` Atish Patra [this message]
2021-12-17 5:42 ` Atish Patra
2021-11-29 7:54 ` [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-12-17 5:47 ` Atish Patra
2021-12-17 5:47 ` Atish Patra
2021-12-17 6:08 ` Anup Patel
2021-12-17 6:08 ` Anup Patel
2021-12-17 8:28 ` Paolo Bonzini
2021-12-17 8:28 ` Paolo Bonzini
2021-11-29 7:54 ` [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-12-17 5:50 ` Atish Patra
2021-12-17 5:50 ` Atish Patra
2021-12-20 19:45 ` Sean Christopherson
2021-12-20 19:45 ` Sean Christopherson
2021-12-21 9:18 ` Anup Patel
2021-12-21 9:18 ` Anup Patel
2021-11-29 7:54 ` [PATCH v2 4/4] KVM: selftests: Add initial support for RISC-V 64-bit Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-12-22 8:48 ` Atish Patra
2021-12-22 8:48 ` Atish Patra
2021-12-11 3:41 ` [PATCH v2 0/4] KVM RISC-V 64-bit selftests support Anup Patel
2021-12-11 3:41 ` Anup Patel
2021-12-22 8:51 ` Atish Patra
2021-12-22 8:51 ` Atish Patra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAOnJCU+=SfN0e-prQsrR8BHfcs7hP9Ab61cnD-yOEZZQ2Gh9cA@mail.gmail.com' \
--to=atishp@atishpatra.org \
--cc=Alistair.Francis@wdc.com \
--cc=anup.patel@wdc.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=pbonzini@redhat.com \
--cc=shuah@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.