From: Sam Protsenko <semen.protsenko@linaro.org> To: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Linus Walleij <linus.walleij@linaro.org>, Tomasz Figa <tomasz.figa@gmail.com>, Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Jiri Slaby <jirislaby@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Charles Keepax <ckeepax@opensource.wolfsonmicro.com>, Ryu Euiyoul <ryu.real@samsung.com>, Tom Gall <tom.gall@linaro.org>, Sumit Semwal <sumit.semwal@linaro.org>, John Stultz <john.stultz@linaro.org>, Amit Pundir <amit.pundir@linaro.org>, devicetree <devicetree@vger.kernel.org>, linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>, linux-clk <linux-clk@vger.kernel.org>, "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Linux Samsung SOC <linux-samsung-soc@vger.kernel.org>, "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org> Subject: Re: [PATCH 02/12] pinctrl: samsung: Add Exynos850 SoC specific data Date: Mon, 2 Aug 2021 22:24:22 +0300 [thread overview] Message-ID: <CAPLW+4=ewQf8_hMKFFqPRaoqQxhRZZ1=NGboLstvVBOYcTc3aw@mail.gmail.com> (raw) In-Reply-To: <a2b6b868-e984-440c-75b1-599680537cc9@canonical.com> On Fri, 30 Jul 2021 at 18:22, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> wrote: > > On 30/07/2021 16:49, Sam Protsenko wrote: > > Add Samsung Exynos850 SoC specific data to enable pinctrl support for > > all platforms based on Exynos850. > > > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > > --- > > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 129 ++++++++++++++++++ > > drivers/pinctrl/samsung/pinctrl-exynos.h | 29 ++++ > > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > > drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + > > 4 files changed, 161 insertions(+) > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > index b6e56422a700..9c71ff84ba7e 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { > > .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > > }; > > > > +/* > > + * Bank type for non-alive type. Bit fields: > > + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 > > + */ > > +static struct samsung_pin_bank_type exynos850_bank_type_off = { > > + .fld_width = { 4, 1, 4, 4, 2, 4, }, > > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, > > +}; > > + > > +/* > > + * Bank type for alive type. Bit fields: > > + * CON: 4, DAT: 1, PUD: 4, DRV: 4 > > + */ > > +static struct samsung_pin_bank_type exynos850_bank_type_alive = { > > + .fld_width = { 4, 1, 4, 4, }, > > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > > +}; > > + > > /* Pad retention control code for accessing PMU regmap */ > > static atomic_t exynos_shared_retention_refcnt; > > > > @@ -422,3 +440,114 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { > > .ctrl = exynos7_pin_ctrl, > > .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), > > }; > > + > > +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks0[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), > > Why EXYNOS9 not EXYNOS850? Is it really shared with 96xx, 98xx and 9x0 > series? > Yeah, I double checked and those macros are actually used for 96xx SoCs. So I suggest we leave it as is, as it seems to be related to the whole architecture series, not only to Exynos850. > > + EXYNOS9_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), > > + EXYNOS9_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), > > + EXYNOS9_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), > > + EXYNOS9_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), > > + EXYNOS9_PIN_BANK_EINTN(3, 0x0A0, "gpq0"), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 1 (CMGP) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks1[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 2 (AUD) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks2[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), > > + EXYNOS9_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 3 (HSI) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks3[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 4 (CORE) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks4[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), > > + EXYNOS9_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 5 (PERI) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks5[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), > > + EXYNOS9_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), > > + EXYNOS9_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), > > + EXYNOS9_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0C), > > + EXYNOS9_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), > > + EXYNOS9_PIN_BANK_EINTG(8, 0x0A0, "gpg2", 0x14), > > + EXYNOS9_PIN_BANK_EINTG(1, 0x0C0, "gpg3", 0x18), > > + EXYNOS9_PIN_BANK_EINTG(3, 0x0E0, "gpc0", 0x1C), > > + EXYNOS9_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), > > +}; > > + > > +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { > > + { > > + /* pin-controller instance 0 ALIVE data */ > > + .pin_banks = exynos850_pin_banks0, > > + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .eint_wkup_init = exynos_eint_wkup_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > I guess retention registers will follow sometime later. > Good point, never noticed retention control is needed for suspend/resume to work properly. I will remove suspend/resume ops in v2, and PM support will be sent later. > Best regards, > Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Sam Protsenko <semen.protsenko@linaro.org> To: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Linus Walleij <linus.walleij@linaro.org>, Tomasz Figa <tomasz.figa@gmail.com>, Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Jiri Slaby <jirislaby@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Charles Keepax <ckeepax@opensource.wolfsonmicro.com>, Ryu Euiyoul <ryu.real@samsung.com>, Tom Gall <tom.gall@linaro.org>, Sumit Semwal <sumit.semwal@linaro.org>, John Stultz <john.stultz@linaro.org>, Amit Pundir <amit.pundir@linaro.org>, devicetree <devicetree@vger.kernel.org>, linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>, linux-clk <linux-clk@vger.kernel.org>, "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Linux Samsung SOC <linux-samsung-soc@vger.kernel.org>, "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org> Subject: Re: [PATCH 02/12] pinctrl: samsung: Add Exynos850 SoC specific data Date: Mon, 2 Aug 2021 22:24:22 +0300 [thread overview] Message-ID: <CAPLW+4=ewQf8_hMKFFqPRaoqQxhRZZ1=NGboLstvVBOYcTc3aw@mail.gmail.com> (raw) In-Reply-To: <a2b6b868-e984-440c-75b1-599680537cc9@canonical.com> On Fri, 30 Jul 2021 at 18:22, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> wrote: > > On 30/07/2021 16:49, Sam Protsenko wrote: > > Add Samsung Exynos850 SoC specific data to enable pinctrl support for > > all platforms based on Exynos850. > > > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > > --- > > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 129 ++++++++++++++++++ > > drivers/pinctrl/samsung/pinctrl-exynos.h | 29 ++++ > > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > > drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + > > 4 files changed, 161 insertions(+) > > > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > index b6e56422a700..9c71ff84ba7e 100644 > > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { > > .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > > }; > > > > +/* > > + * Bank type for non-alive type. Bit fields: > > + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 > > + */ > > +static struct samsung_pin_bank_type exynos850_bank_type_off = { > > + .fld_width = { 4, 1, 4, 4, 2, 4, }, > > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, > > +}; > > + > > +/* > > + * Bank type for alive type. Bit fields: > > + * CON: 4, DAT: 1, PUD: 4, DRV: 4 > > + */ > > +static struct samsung_pin_bank_type exynos850_bank_type_alive = { > > + .fld_width = { 4, 1, 4, 4, }, > > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, > > +}; > > + > > /* Pad retention control code for accessing PMU regmap */ > > static atomic_t exynos_shared_retention_refcnt; > > > > @@ -422,3 +440,114 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { > > .ctrl = exynos7_pin_ctrl, > > .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), > > }; > > + > > +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks0[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), > > Why EXYNOS9 not EXYNOS850? Is it really shared with 96xx, 98xx and 9x0 > series? > Yeah, I double checked and those macros are actually used for 96xx SoCs. So I suggest we leave it as is, as it seems to be related to the whole architecture series, not only to Exynos850. > > + EXYNOS9_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), > > + EXYNOS9_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), > > + EXYNOS9_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), > > + EXYNOS9_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), > > + EXYNOS9_PIN_BANK_EINTN(3, 0x0A0, "gpq0"), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 1 (CMGP) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks1[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), > > + EXYNOS9_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 2 (AUD) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks2[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), > > + EXYNOS9_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 3 (HSI) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks3[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 4 (CORE) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks4[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), > > + EXYNOS9_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), > > +}; > > + > > +/* pin banks of exynos850 pin-controller 5 (PERI) */ > > +static struct samsung_pin_bank_data exynos850_pin_banks5[] = { > > + /* Must start with EINTG banks, ordered by EINT group number. */ > > + EXYNOS9_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), > > + EXYNOS9_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), > > + EXYNOS9_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), > > + EXYNOS9_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0C), > > + EXYNOS9_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), > > + EXYNOS9_PIN_BANK_EINTG(8, 0x0A0, "gpg2", 0x14), > > + EXYNOS9_PIN_BANK_EINTG(1, 0x0C0, "gpg3", 0x18), > > + EXYNOS9_PIN_BANK_EINTG(3, 0x0E0, "gpc0", 0x1C), > > + EXYNOS9_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), > > +}; > > + > > +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { > > + { > > + /* pin-controller instance 0 ALIVE data */ > > + .pin_banks = exynos850_pin_banks0, > > + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), > > + .eint_gpio_init = exynos_eint_gpio_init, > > + .eint_wkup_init = exynos_eint_wkup_init, > > + .suspend = exynos_pinctrl_suspend, > > + .resume = exynos_pinctrl_resume, > > I guess retention registers will follow sometime later. > Good point, never noticed retention control is needed for suspend/resume to work properly. I will remove suspend/resume ops in v2, and PM support will be sent later. > Best regards, > Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-02 19:24 UTC|newest] Thread overview: 134+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-30 14:49 [PATCH 00/12] Add minimal support for Exynos850 SoC Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 14:49 ` [PATCH 01/12] pinctrl: samsung: Fix pinctrl bank pin count Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 14:49 ` [PATCH 02/12] pinctrl: samsung: Add Exynos850 SoC specific data Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 15:22 ` Krzysztof Kozlowski 2021-07-30 15:22 ` Krzysztof Kozlowski 2021-08-02 19:24 ` Sam Protsenko [this message] 2021-08-02 19:24 ` Sam Protsenko 2021-07-30 14:49 ` [PATCH 03/12] dt-bindings: pinctrl: samsung: Add Exynos850 doc Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 15:24 ` Krzysztof Kozlowski 2021-07-30 15:24 ` Krzysztof Kozlowski 2021-07-30 19:31 ` Sam Protsenko 2021-07-30 19:31 ` Sam Protsenko 2021-07-30 14:49 ` [PATCH 04/12] tty: serial: samsung: Init USI to keep clocks running Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 16:31 ` Krzysztof Kozlowski 2021-07-30 16:31 ` Krzysztof Kozlowski 2021-08-02 23:06 ` Sam Protsenko 2021-08-02 23:06 ` Sam Protsenko 2021-08-03 7:37 ` Krzysztof Kozlowski 2021-08-03 7:37 ` Krzysztof Kozlowski 2021-08-03 11:41 ` Sam Protsenko 2021-08-03 11:41 ` Sam Protsenko 2021-07-30 14:49 ` [PATCH 05/12] tty: serial: samsung: Fix driver data macros style Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 16:34 ` Krzysztof Kozlowski 2021-07-30 16:34 ` Krzysztof Kozlowski 2021-07-30 14:49 ` [PATCH 06/12] tty: serial: samsung: Add Exynos850 SoC data Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 15:05 ` Andy Shevchenko 2021-07-30 15:05 ` Andy Shevchenko 2021-07-30 16:05 ` Krzysztof Kozlowski 2021-07-30 16:05 ` Krzysztof Kozlowski 2021-07-30 23:10 ` Sam Protsenko 2021-07-30 23:10 ` Sam Protsenko 2021-07-31 7:12 ` Krzysztof Kozlowski 2021-07-31 7:12 ` Krzysztof Kozlowski 2021-07-30 14:49 ` [PATCH 07/12] dt-bindings: serial: samsung: Add Exynos850 doc Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 16:35 ` Krzysztof Kozlowski 2021-07-30 16:35 ` Krzysztof Kozlowski 2021-07-30 19:04 ` Sam Protsenko 2021-07-30 19:04 ` Sam Protsenko 2021-07-30 14:49 ` [PATCH 08/12] MAINTAINERS: Cover Samsung clock YAML bindings Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 15:06 ` Andy Shevchenko 2021-07-30 15:06 ` Andy Shevchenko 2021-07-30 15:25 ` Krzysztof Kozlowski 2021-07-30 15:25 ` Krzysztof Kozlowski 2021-07-30 17:32 ` Sam Protsenko 2021-07-30 17:32 ` Sam Protsenko 2021-07-30 14:49 ` [PATCH 09/12] dt-bindings: clock: Add bindings for Exynos850 clock controller Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 15:43 ` Krzysztof Kozlowski 2021-07-30 15:43 ` Krzysztof Kozlowski 2021-08-03 11:55 ` Sam Protsenko 2021-08-03 11:55 ` Sam Protsenko 2021-07-30 22:28 ` Rob Herring 2021-07-30 22:28 ` Rob Herring 2021-07-30 14:49 ` [PATCH 10/12] clk: samsung: Add Exynos850 clock driver stub Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 15:11 ` Andy Shevchenko 2021-07-30 15:11 ` Andy Shevchenko 2021-07-30 17:24 ` Sam Protsenko 2021-07-30 17:24 ` Sam Protsenko 2021-07-31 5:28 ` kernel test robot 2021-07-31 10:57 ` kernel test robot 2021-07-30 14:49 ` [PATCH 11/12] dt-bindings: interrupt-controller: Add IRQ constants for Exynos850 Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-31 8:45 ` Krzysztof Kozlowski 2021-07-31 8:45 ` Krzysztof Kozlowski 2021-08-03 12:58 ` Sam Protsenko 2021-08-03 12:58 ` Sam Protsenko 2021-07-30 14:49 ` [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support Sam Protsenko 2021-07-30 14:49 ` Sam Protsenko 2021-07-30 16:50 ` Marc Zyngier 2021-07-30 16:50 ` Marc Zyngier 2021-08-04 14:39 ` Sam Protsenko 2021-08-04 14:39 ` Sam Protsenko 2021-08-04 15:01 ` Marc Zyngier 2021-08-04 15:01 ` Marc Zyngier 2021-08-04 18:37 ` Sam Protsenko 2021-08-04 18:37 ` Sam Protsenko 2021-08-05 7:39 ` Marc Zyngier 2021-08-05 7:39 ` Marc Zyngier 2021-08-05 15:30 ` Sam Protsenko 2021-08-05 15:30 ` Sam Protsenko 2021-08-05 15:50 ` Marc Zyngier 2021-08-05 15:50 ` Marc Zyngier 2021-08-04 18:36 ` Krzysztof Kozlowski 2021-08-04 18:36 ` Krzysztof Kozlowski 2021-08-04 21:30 ` Sam Protsenko 2021-08-04 21:30 ` Sam Protsenko 2021-08-05 7:17 ` Krzysztof Kozlowski 2021-08-05 7:17 ` Krzysztof Kozlowski 2021-08-05 7:30 ` Marc Zyngier 2021-08-05 7:30 ` Marc Zyngier 2021-08-05 7:35 ` Krzysztof Kozlowski 2021-08-05 7:35 ` Krzysztof Kozlowski 2021-07-31 9:03 ` Krzysztof Kozlowski 2021-07-31 9:03 ` Krzysztof Kozlowski 2021-08-05 23:06 ` Sam Protsenko 2021-08-05 23:06 ` Sam Protsenko 2021-08-06 7:48 ` Krzysztof Kozlowski 2021-08-06 7:48 ` Krzysztof Kozlowski 2021-08-06 12:07 ` Sam Protsenko 2021-08-06 12:07 ` Sam Protsenko 2021-08-06 12:32 ` Krzysztof Kozlowski 2021-08-06 12:32 ` Krzysztof Kozlowski 2021-08-06 12:48 ` Krzysztof Kozlowski 2021-08-06 12:48 ` Krzysztof Kozlowski 2021-08-06 16:57 ` Sam Protsenko 2021-08-06 16:57 ` Sam Protsenko 2021-08-06 20:32 ` Paweł Chmiel 2021-08-06 20:32 ` Paweł Chmiel 2021-09-06 15:16 ` Sam Protsenko 2021-09-06 15:16 ` Sam Protsenko 2021-07-30 15:18 ` [PATCH 00/12] Add minimal support for Exynos850 SoC Krzysztof Kozlowski 2021-07-30 15:18 ` Krzysztof Kozlowski 2021-07-30 17:21 ` Krzysztof Kozlowski 2021-07-30 17:21 ` Krzysztof Kozlowski 2021-07-30 19:02 ` Sam Protsenko 2021-07-30 19:02 ` Sam Protsenko 2021-07-31 7:29 ` Krzysztof Kozlowski 2021-07-31 7:29 ` Krzysztof Kozlowski 2021-07-31 8:12 ` Krzysztof Kozlowski 2021-07-31 8:12 ` Krzysztof Kozlowski 2021-08-02 23:27 ` Sam Protsenko 2021-08-02 23:27 ` Sam Protsenko 2021-08-03 7:41 ` Krzysztof Kozlowski 2021-08-03 7:41 ` Krzysztof Kozlowski
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