All of lore.kernel.org
 help / color / mirror / Atom feed
From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
To: Sam Protsenko <semen.protsenko@linaro.org>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Tomasz Figa <tomasz.figa@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Jiri Slaby <jirislaby@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Charles Keepax <ckeepax@opensource.wolfsonmicro.com>,
	Ryu Euiyoul <ryu.real@samsung.com>,
	Tom Gall <tom.gall@linaro.org>,
	Sumit Semwal <sumit.semwal@linaro.org>,
	John Stultz <john.stultz@linaro.org>,
	Amit Pundir <amit.pundir@linaro.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
	linux-serial@vger.kernel.org
Subject: Re: [PATCH 04/12] tty: serial: samsung: Init USI to keep clocks running
Date: Fri, 30 Jul 2021 18:31:56 +0200	[thread overview]
Message-ID: <a1701931-136e-235c-8392-a3f64c050d74@canonical.com> (raw)
In-Reply-To: <20210730144922.29111-5-semen.protsenko@linaro.org>

On 30/07/2021 16:49, Sam Protsenko wrote:
> UART block is a part of USI (Universal Serial Interface) IP-core in
> Samsung SoCs since Exynos9810 (e.g. in Exynos850). USI allows one to
> enable one of three types of serial interface: UART, SPI or I2C. That's
> possible because USI shares almost all internal circuits within each
> protocol. USI also provides some additional registers so it's possible
> to configure it.
> 
> One USI register called USI_OPTION has reset value of 0x0. Because of
> this the clock gating behavior is controlled by hardware (HWACG =
> Hardware Auto Clock Gating), which simply means the serial won't work
> after reset as is. In order to make it work, USI_OPTION[2:1] bits must
> be set to 0b01, so that HWACG is controlled manually (by software).
> Bits meaning:
>   - CLKREQ_ON = 1: clock is continuously provided to IP
>   - CLKSTOP_ON = 0: drive IP_CLKREQ to High (needs to be set along with
>                     CLKREQ_ON = 1)
> 
> USI is not present on older chips, like s3c2410, s3c2412, s3c2440,
> s3c6400, s5pv210, exynos5433, exynos4210. So the new boolean field
> '.has_usi' was added to struct s3c24xx_uart_info. USI registers will be
> only actually accessed when '.has_usi' field is set to "1".
> 
> This feature is needed for further serial enablement on Exynos850, but
> some other new Exynos chips (like Exynos9810) may benefit from this
> feature as well.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
>  drivers/tty/serial/samsung_tty.c | 33 +++++++++++++++++++++++++++++++-
>  include/linux/serial_s3c.h       |  9 +++++++++
>  2 files changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index 9fbc61151c2e..0f3cbd0b37e3 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -65,6 +65,7 @@ enum s3c24xx_port_type {
>  struct s3c24xx_uart_info {
>  	char			*name;
>  	enum s3c24xx_port_type	type;
> +	unsigned int		has_usi;
>  	unsigned int		port_type;
>  	unsigned int		fifosize;
>  	unsigned long		rx_fifomask;
> @@ -1352,6 +1353,29 @@ static int apple_s5l_serial_startup(struct uart_port *port)
>  	return ret;
>  }
>  
> +static void exynos_usi_init(struct uart_port *port)
> +{
> +	struct s3c24xx_uart_port *ourport = to_ourport(port);
> +	struct s3c24xx_uart_info *info = ourport->info;
> +
> +	if (!info->has_usi)
> +		return;
> +
> +	/*
> +	 * USI_RESET is an active High signal. Reset value of USI_RESET is 0x1
> +	 * to drive stable value to PAD. Due to this feature, the USI_RESET must
> +	 * be cleared (set as 0x0) before starting a transaction.

"before starting a transaction" suggests it is related with transaction
or something before starting it. Don't you need it simply after reset or
resume?

> +	 */
> +	wr_regl(port, USI_CON, USI_RESET);

You are clearing entire register, not only USI_RESET bitfield. Is it
really what you want?

> +	udelay(1);
> +
> +	/*
> +	 * Set the HWACG option bit in case of UART Rx mode.
> +	 * CLKREQ_ON = 1, CLKSTOP_ON = 0 (set USI_OPTION[2:1] = 0x1).
> +	 */
> +	wr_regl(port, USI_OPTION, USI_HWACG_CLKREQ_ON);
> +}
> +
>  /* power power management control */
>  
>  static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
> @@ -1379,6 +1403,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
>  		if (!IS_ERR(ourport->baudclk))
>  			clk_prepare_enable(ourport->baudclk);
>  
> +		exynos_usi_init(port);
>  		break;
>  	default:
>  		dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
> @@ -2102,6 +2127,8 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
>  	if (ret)
>  		pr_warn("uart: failed to enable baudclk\n");
>  
> +	exynos_usi_init(port);
> +
>  	/* Keep all interrupts masked and cleared */
>  	switch (ourport->info->type) {
>  	case TYPE_S3C6400:
> @@ -2750,10 +2777,11 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
>  #endif
>  
>  #if defined(CONFIG_ARCH_EXYNOS)
> -#define EXYNOS_COMMON_SERIAL_DRV_DATA				\
> +#define EXYNOS_COMMON_SERIAL_DRV_DATA_USI(_has_usi)		\
>  	.info = &(struct s3c24xx_uart_info) {			\
>  		.name		= "Samsung Exynos UART",	\
>  		.type		= TYPE_S3C6400,			\
> +		.has_usi	= _has_usi,			\
>  		.port_type	= PORT_S3C6400,			\
>  		.has_divslot	= 1,				\
>  		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,	\
> @@ -2773,6 +2801,9 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
>  		.has_fracval	= 1,				\
>  	}							\
>  
> +#define EXYNOS_COMMON_SERIAL_DRV_DATA				\
> +	EXYNOS_COMMON_SERIAL_DRV_DATA_USI(0)
> +
>  static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
>  	EXYNOS_COMMON_SERIAL_DRV_DATA,
>  	.fifosize = { 256, 64, 16, 16 },
> diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h
> index f6c3323fc4c5..013c2646863e 100644
> --- a/include/linux/serial_s3c.h
> +++ b/include/linux/serial_s3c.h
> @@ -28,6 +28,15 @@
>  #define S3C2410_UFSTAT	  (0x18)
>  #define S3C2410_UMSTAT	  (0x1C)
>  
> +/* USI Control Register offset */
> +#define USI_CON			(0xC4)
> +/* USI Option Register offset */
> +#define USI_OPTION		(0xC8)
> +/* USI_CON[0] = 0b0: clear USI global software reset (Active High) */
> +#define USI_RESET		(0<<0)

Just 0x0. I understand you wanted to hint it is a bit field, but the
shift of 0 actually creates more questions.


Best regards,
Krzysztof

WARNING: multiple messages have this Message-ID
From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
To: Sam Protsenko <semen.protsenko@linaro.org>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Tomasz Figa <tomasz.figa@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Jiri Slaby <jirislaby@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Charles Keepax <ckeepax@opensource.wolfsonmicro.com>,
	Ryu Euiyoul <ryu.real@samsung.com>,
	Tom Gall <tom.gall@linaro.org>,
	Sumit Semwal <sumit.semwal@linaro.org>,
	John Stultz <john.stultz@linaro.org>,
	Amit Pundir <amit.pundir@linaro.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
	linux-serial@vger.kernel.org
Subject: Re: [PATCH 04/12] tty: serial: samsung: Init USI to keep clocks running
Date: Fri, 30 Jul 2021 18:31:56 +0200	[thread overview]
Message-ID: <a1701931-136e-235c-8392-a3f64c050d74@canonical.com> (raw)
In-Reply-To: <20210730144922.29111-5-semen.protsenko@linaro.org>

On 30/07/2021 16:49, Sam Protsenko wrote:
> UART block is a part of USI (Universal Serial Interface) IP-core in
> Samsung SoCs since Exynos9810 (e.g. in Exynos850). USI allows one to
> enable one of three types of serial interface: UART, SPI or I2C. That's
> possible because USI shares almost all internal circuits within each
> protocol. USI also provides some additional registers so it's possible
> to configure it.
> 
> One USI register called USI_OPTION has reset value of 0x0. Because of
> this the clock gating behavior is controlled by hardware (HWACG =
> Hardware Auto Clock Gating), which simply means the serial won't work
> after reset as is. In order to make it work, USI_OPTION[2:1] bits must
> be set to 0b01, so that HWACG is controlled manually (by software).
> Bits meaning:
>   - CLKREQ_ON = 1: clock is continuously provided to IP
>   - CLKSTOP_ON = 0: drive IP_CLKREQ to High (needs to be set along with
>                     CLKREQ_ON = 1)
> 
> USI is not present on older chips, like s3c2410, s3c2412, s3c2440,
> s3c6400, s5pv210, exynos5433, exynos4210. So the new boolean field
> '.has_usi' was added to struct s3c24xx_uart_info. USI registers will be
> only actually accessed when '.has_usi' field is set to "1".
> 
> This feature is needed for further serial enablement on Exynos850, but
> some other new Exynos chips (like Exynos9810) may benefit from this
> feature as well.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> ---
>  drivers/tty/serial/samsung_tty.c | 33 +++++++++++++++++++++++++++++++-
>  include/linux/serial_s3c.h       |  9 +++++++++
>  2 files changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index 9fbc61151c2e..0f3cbd0b37e3 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -65,6 +65,7 @@ enum s3c24xx_port_type {
>  struct s3c24xx_uart_info {
>  	char			*name;
>  	enum s3c24xx_port_type	type;
> +	unsigned int		has_usi;
>  	unsigned int		port_type;
>  	unsigned int		fifosize;
>  	unsigned long		rx_fifomask;
> @@ -1352,6 +1353,29 @@ static int apple_s5l_serial_startup(struct uart_port *port)
>  	return ret;
>  }
>  
> +static void exynos_usi_init(struct uart_port *port)
> +{
> +	struct s3c24xx_uart_port *ourport = to_ourport(port);
> +	struct s3c24xx_uart_info *info = ourport->info;
> +
> +	if (!info->has_usi)
> +		return;
> +
> +	/*
> +	 * USI_RESET is an active High signal. Reset value of USI_RESET is 0x1
> +	 * to drive stable value to PAD. Due to this feature, the USI_RESET must
> +	 * be cleared (set as 0x0) before starting a transaction.

"before starting a transaction" suggests it is related with transaction
or something before starting it. Don't you need it simply after reset or
resume?

> +	 */
> +	wr_regl(port, USI_CON, USI_RESET);

You are clearing entire register, not only USI_RESET bitfield. Is it
really what you want?

> +	udelay(1);
> +
> +	/*
> +	 * Set the HWACG option bit in case of UART Rx mode.
> +	 * CLKREQ_ON = 1, CLKSTOP_ON = 0 (set USI_OPTION[2:1] = 0x1).
> +	 */
> +	wr_regl(port, USI_OPTION, USI_HWACG_CLKREQ_ON);
> +}
> +
>  /* power power management control */
>  
>  static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
> @@ -1379,6 +1403,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
>  		if (!IS_ERR(ourport->baudclk))
>  			clk_prepare_enable(ourport->baudclk);
>  
> +		exynos_usi_init(port);
>  		break;
>  	default:
>  		dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
> @@ -2102,6 +2127,8 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
>  	if (ret)
>  		pr_warn("uart: failed to enable baudclk\n");
>  
> +	exynos_usi_init(port);
> +
>  	/* Keep all interrupts masked and cleared */
>  	switch (ourport->info->type) {
>  	case TYPE_S3C6400:
> @@ -2750,10 +2777,11 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
>  #endif
>  
>  #if defined(CONFIG_ARCH_EXYNOS)
> -#define EXYNOS_COMMON_SERIAL_DRV_DATA				\
> +#define EXYNOS_COMMON_SERIAL_DRV_DATA_USI(_has_usi)		\
>  	.info = &(struct s3c24xx_uart_info) {			\
>  		.name		= "Samsung Exynos UART",	\
>  		.type		= TYPE_S3C6400,			\
> +		.has_usi	= _has_usi,			\
>  		.port_type	= PORT_S3C6400,			\
>  		.has_divslot	= 1,				\
>  		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,	\
> @@ -2773,6 +2801,9 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
>  		.has_fracval	= 1,				\
>  	}							\
>  
> +#define EXYNOS_COMMON_SERIAL_DRV_DATA				\
> +	EXYNOS_COMMON_SERIAL_DRV_DATA_USI(0)
> +
>  static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
>  	EXYNOS_COMMON_SERIAL_DRV_DATA,
>  	.fifosize = { 256, 64, 16, 16 },
> diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h
> index f6c3323fc4c5..013c2646863e 100644
> --- a/include/linux/serial_s3c.h
> +++ b/include/linux/serial_s3c.h
> @@ -28,6 +28,15 @@
>  #define S3C2410_UFSTAT	  (0x18)
>  #define S3C2410_UMSTAT	  (0x1C)
>  
> +/* USI Control Register offset */
> +#define USI_CON			(0xC4)
> +/* USI Option Register offset */
> +#define USI_OPTION		(0xC8)
> +/* USI_CON[0] = 0b0: clear USI global software reset (Active High) */
> +#define USI_RESET		(0<<0)

Just 0x0. I understand you wanted to hint it is a bit field, but the
shift of 0 actually creates more questions.


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-07-30 16:32 UTC|newest]

Thread overview: 132+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-30 14:49 [PATCH 00/12] Add minimal support for Exynos850 SoC Sam Protsenko
2021-07-30 14:49 ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 01/12] pinctrl: samsung: Fix pinctrl bank pin count Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 02/12] pinctrl: samsung: Add Exynos850 SoC specific data Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 15:22   ` Krzysztof Kozlowski
2021-07-30 15:22     ` Krzysztof Kozlowski
2021-08-02 19:24     ` Sam Protsenko
2021-08-02 19:24       ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 03/12] dt-bindings: pinctrl: samsung: Add Exynos850 doc Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 15:24   ` Krzysztof Kozlowski
2021-07-30 15:24     ` Krzysztof Kozlowski
2021-07-30 19:31     ` Sam Protsenko
2021-07-30 19:31       ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 04/12] tty: serial: samsung: Init USI to keep clocks running Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 16:31   ` Krzysztof Kozlowski [this message]
2021-07-30 16:31     ` Krzysztof Kozlowski
2021-08-02 23:06     ` Sam Protsenko
2021-08-02 23:06       ` Sam Protsenko
2021-08-03  7:37       ` Krzysztof Kozlowski
2021-08-03  7:37         ` Krzysztof Kozlowski
2021-08-03 11:41         ` Sam Protsenko
2021-08-03 11:41           ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 05/12] tty: serial: samsung: Fix driver data macros style Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 16:34   ` Krzysztof Kozlowski
2021-07-30 16:34     ` Krzysztof Kozlowski
2021-07-30 14:49 ` [PATCH 06/12] tty: serial: samsung: Add Exynos850 SoC data Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 15:05   ` Andy Shevchenko
2021-07-30 15:05     ` Andy Shevchenko
2021-07-30 16:05   ` Krzysztof Kozlowski
2021-07-30 16:05     ` Krzysztof Kozlowski
2021-07-30 23:10     ` Sam Protsenko
2021-07-30 23:10       ` Sam Protsenko
2021-07-31  7:12       ` Krzysztof Kozlowski
2021-07-31  7:12         ` Krzysztof Kozlowski
2021-07-30 14:49 ` [PATCH 07/12] dt-bindings: serial: samsung: Add Exynos850 doc Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 16:35   ` Krzysztof Kozlowski
2021-07-30 16:35     ` Krzysztof Kozlowski
2021-07-30 19:04     ` Sam Protsenko
2021-07-30 19:04       ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 08/12] MAINTAINERS: Cover Samsung clock YAML bindings Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 15:06   ` Andy Shevchenko
2021-07-30 15:06     ` Andy Shevchenko
2021-07-30 15:25     ` Krzysztof Kozlowski
2021-07-30 15:25       ` Krzysztof Kozlowski
2021-07-30 17:32       ` Sam Protsenko
2021-07-30 17:32         ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 09/12] dt-bindings: clock: Add bindings for Exynos850 clock controller Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 15:43   ` Krzysztof Kozlowski
2021-07-30 15:43     ` Krzysztof Kozlowski
2021-08-03 11:55     ` Sam Protsenko
2021-08-03 11:55       ` Sam Protsenko
2021-07-30 22:28   ` Rob Herring
2021-07-30 22:28     ` Rob Herring
2021-07-30 14:49 ` [PATCH 10/12] clk: samsung: Add Exynos850 clock driver stub Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 15:11   ` Andy Shevchenko
2021-07-30 15:11     ` Andy Shevchenko
2021-07-30 17:24     ` Sam Protsenko
2021-07-30 17:24       ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 11/12] dt-bindings: interrupt-controller: Add IRQ constants for Exynos850 Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-31  8:45   ` Krzysztof Kozlowski
2021-07-31  8:45     ` Krzysztof Kozlowski
2021-08-03 12:58     ` Sam Protsenko
2021-08-03 12:58       ` Sam Protsenko
2021-07-30 14:49 ` [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support Sam Protsenko
2021-07-30 14:49   ` Sam Protsenko
2021-07-30 16:50   ` Marc Zyngier
2021-07-30 16:50     ` Marc Zyngier
2021-08-04 14:39     ` Sam Protsenko
2021-08-04 14:39       ` Sam Protsenko
2021-08-04 15:01       ` Marc Zyngier
2021-08-04 15:01         ` Marc Zyngier
2021-08-04 18:37         ` Sam Protsenko
2021-08-04 18:37           ` Sam Protsenko
2021-08-05  7:39           ` Marc Zyngier
2021-08-05  7:39             ` Marc Zyngier
2021-08-05 15:30             ` Sam Protsenko
2021-08-05 15:30               ` Sam Protsenko
2021-08-05 15:50               ` Marc Zyngier
2021-08-05 15:50                 ` Marc Zyngier
2021-08-04 18:36       ` Krzysztof Kozlowski
2021-08-04 18:36         ` Krzysztof Kozlowski
2021-08-04 21:30         ` Sam Protsenko
2021-08-04 21:30           ` Sam Protsenko
2021-08-05  7:17           ` Krzysztof Kozlowski
2021-08-05  7:17             ` Krzysztof Kozlowski
2021-08-05  7:30             ` Marc Zyngier
2021-08-05  7:30               ` Marc Zyngier
2021-08-05  7:35               ` Krzysztof Kozlowski
2021-08-05  7:35                 ` Krzysztof Kozlowski
2021-07-31  9:03   ` Krzysztof Kozlowski
2021-07-31  9:03     ` Krzysztof Kozlowski
2021-08-05 23:06     ` Sam Protsenko
2021-08-05 23:06       ` Sam Protsenko
2021-08-06  7:48       ` Krzysztof Kozlowski
2021-08-06  7:48         ` Krzysztof Kozlowski
2021-08-06 12:07         ` Sam Protsenko
2021-08-06 12:07           ` Sam Protsenko
2021-08-06 12:32           ` Krzysztof Kozlowski
2021-08-06 12:32             ` Krzysztof Kozlowski
2021-08-06 12:48             ` Krzysztof Kozlowski
2021-08-06 12:48               ` Krzysztof Kozlowski
2021-08-06 16:57               ` Sam Protsenko
2021-08-06 16:57                 ` Sam Protsenko
2021-08-06 20:32             ` Paweł Chmiel
2021-08-06 20:32               ` Paweł Chmiel
2021-09-06 15:16               ` Sam Protsenko
2021-09-06 15:16                 ` Sam Protsenko
2021-07-30 15:18 ` [PATCH 00/12] Add minimal support for Exynos850 SoC Krzysztof Kozlowski
2021-07-30 15:18   ` Krzysztof Kozlowski
2021-07-30 17:21   ` Krzysztof Kozlowski
2021-07-30 17:21     ` Krzysztof Kozlowski
2021-07-30 19:02     ` Sam Protsenko
2021-07-30 19:02       ` Sam Protsenko
2021-07-31  7:29       ` Krzysztof Kozlowski
2021-07-31  7:29         ` Krzysztof Kozlowski
2021-07-31  8:12         ` Krzysztof Kozlowski
2021-07-31  8:12           ` Krzysztof Kozlowski
2021-08-02 23:27           ` Sam Protsenko
2021-08-02 23:27             ` Sam Protsenko
2021-08-03  7:41             ` Krzysztof Kozlowski
2021-08-03  7:41               ` Krzysztof Kozlowski

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=a1701931-136e-235c-8392-a3f64c050d74@canonical.com \
    --to=krzysztof.kozlowski@canonical.com \
    --cc=amit.pundir@linaro.org \
    --cc=ckeepax@opensource.wolfsonmicro.com \
    --cc=cw00.choi@samsung.com \
    --cc=devicetree@vger.kernel.org \
    --cc=gregkh@linuxfoundation.org \
    --cc=jirislaby@kernel.org \
    --cc=john.stultz@linaro.org \
    --cc=linus.walleij@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-gpio@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-samsung-soc@vger.kernel.org \
    --cc=linux-serial@vger.kernel.org \
    --cc=mturquette@baylibre.com \
    --cc=robh+dt@kernel.org \
    --cc=ryu.real@samsung.com \
    --cc=s.nawrocki@samsung.com \
    --cc=sboyd@kernel.org \
    --cc=semen.protsenko@linaro.org \
    --cc=sumit.semwal@linaro.org \
    --cc=tom.gall@linaro.org \
    --cc=tomasz.figa@gmail.com \
    --subject='Re: [PATCH 04/12] tty: serial: samsung: Init USI to keep clocks running' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.