* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
@ 2010-04-09 8:29 Albert Aribaud
2010-04-09 8:29 ` [U-Boot] [PATCH V6 2/3] Add Orion5x support to 16550 device driver Albert Aribaud
2010-04-10 21:16 ` [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC Wolfgang Denk
0 siblings, 2 replies; 23+ messages in thread
From: Albert Aribaud @ 2010-04-09 8:29 UTC (permalink / raw)
To: u-boot
This patch adds support for the Marvell Orion5x SoC.
It has no use alone, and must be followed by a patch
to add Orion5x support for serial, then support for
the ED Mini V2, an Orion5x-based product from LaCie.
---
Patchset history
V1: Initial monolithic patch.
V2: split in three patches : orion, serial, edmini;
checkpatch'ed, with only 6 errors, in patch 1/3,
all 6 errors being false positives.
V3: useless GPIO and MPP programming support removed;
low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
V4: all files licensed GPLv2-only removed;
RAM bank size detection now uses get_ram_size().
V5: Replaced macros by C structs in dram code.
Removed compilation warnings in dram code.
Added comments to legacy flash definitions.
Split low level init code into SoC- and Chip-specifics.
V6: Set copyright dates to 2010, and put standard GPL notice
mentioning Marvell's copyright on *_lowlevel_init.S files.
Patch 1 of 3 still checkpatches with 6 spurious errors and one
spurious warning. Patches 2 and 3 have 0 errors and 0 warnings.
cpu/arm926ejs/orion5x/Makefile | 55 ++++++
cpu/arm926ejs/orion5x/cpu.c | 263 ++++++++++++++++++++++++++
cpu/arm926ejs/orion5x/dram.c | 63 +++++++
cpu/arm926ejs/orion5x/lowlevel_init.S | 298 ++++++++++++++++++++++++++++++
cpu/arm926ejs/orion5x/timer.c | 181 ++++++++++++++++++
include/asm-arm/arch-orion5x/cpu.h | 203 ++++++++++++++++++++
include/asm-arm/arch-orion5x/mv88f5182.h | 40 ++++
include/asm-arm/arch-orion5x/orion5x.h | 69 +++++++
8 files changed, 1172 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm926ejs/orion5x/Makefile
create mode 100644 cpu/arm926ejs/orion5x/cpu.c
create mode 100644 cpu/arm926ejs/orion5x/dram.c
create mode 100644 cpu/arm926ejs/orion5x/lowlevel_init.S
create mode 100644 cpu/arm926ejs/orion5x/timer.c
create mode 100644 include/asm-arm/arch-orion5x/cpu.h
create mode 100644 include/asm-arm/arch-orion5x/mv88f5182.h
create mode 100644 include/asm-arm/arch-orion5x/orion5x.h
diff --git a/cpu/arm926ejs/orion5x/Makefile b/cpu/arm926ejs/orion5x/Makefile
new file mode 100644
index 0000000..11f4141
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS-y = cpu.o
+COBJS-y += dram.o
+COBJS-y += timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/orion5x/cpu.c b/cpu/arm926ejs/orion5x/cpu.c
new file mode 100644
index 0000000..ba2c678
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/cpu.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/arch/orion5x.h>
+#include <hush.h>
+
+#define BUFLEN 16
+
+void reset_cpu(unsigned long ignored)
+{
+ struct orion5x_cpu_registers *cpureg =
+ (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
+
+ writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+ &cpureg->rstoutn_mask);
+ writel(readl(&cpureg->sys_soft_rst) | 1,
+ &cpureg->sys_soft_rst);
+ while (1)
+ ;
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
+{
+ int i;
+ unsigned int j = 0;
+ u32 val = sizeval >> 1;
+
+ for (i = 0; val > 0x10000; i++) {
+ j |= (1 << i);
+ val = val >> 1;
+ }
+ return 0x0000ffff & j;
+}
+
+/*
+ * orion5x_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Orion5x Soc to addess different
+ * devices. Each window can be configured for size, BAR and remap addr
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ *
+ * Reference Documentation:
+ * Mbus-L to Mbus Bridge Registers Configuration.
+ * (Sec 25.1 and 25.3 of Datasheet)
+ */
+int orion5x_config_adr_windows(void)
+{
+ struct orion5x_win_registers *winregs =
+ (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
+
+ /* Window 0: PCIE MEM address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
+ ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
+ ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+ writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
+ writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
+ writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
+
+ /* Window 1: PCIE IO address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
+ ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
+ ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+ writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
+ writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
+ writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
+
+ /* Window 2: PCI MEM address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
+ ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
+ ORION5X_WIN_ENABLE), &winregs[2].ctrl);
+ writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
+
+ /* Window 3: PCI IO address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
+ ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
+ ORION5X_WIN_ENABLE), &winregs[3].ctrl);
+ writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
+
+ /* Window 4: DEV_CS0 address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
+ ORION5X_WIN_ENABLE), &winregs[4].ctrl);
+ writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
+
+ /* Window 5: DEV_CS1 address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
+ ORION5X_WIN_ENABLE), &winregs[5].ctrl);
+ writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
+
+ /* Window 6: DEV_CS2 address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+ ORION5X_WIN_ENABLE), &winregs[6].ctrl);
+ writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
+
+ /* Window 7: BOOT Memory address space */
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
+ ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
+ ORION5X_WIN_ENABLE), &winregs[7].ctrl);
+ writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
+
+ return 0;
+}
+
+/*
+ * Orion5x identification is done through PCIE space.
+ */
+
+u32 orion5x_device_id(void)
+{
+ return readl(PCIE_DEV_ID_OFF) >> 16;
+}
+
+u32 orion5x_device_rev(void)
+{
+ return readl(PCIE_DEV_REV_OFF) & 0xff;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+
+/* Display device and revision IDs.
+ * This function must cover all known device/revision
+ * combinations, not only the one for which u-boot is
+ * compiled; this way, one can identify actual HW in
+ * case of a mismatch.
+ */
+int print_cpuinfo(void)
+{
+ char dev_str[] = "0x0000";
+ char rev_str[] = "0x00";
+ char *dev_name = NULL;
+ char *rev_name = NULL;
+
+ u32 dev = orion5x_device_id();
+ u32 rev = orion5x_device_rev();
+
+ if (dev == MV88F5181_DEV_ID) {
+ dev_name = "MV88F5181";
+ if (rev == MV88F5181_REV_B1)
+ rev_name = "B1";
+ else if (rev == MV88F5181L_REV_A1) {
+ dev_name = "MV88F5181L";
+ rev_name = "A1";
+ } else if (rev == MV88F5181L_REV_A0) {
+ dev_name = "MV88F5181L";
+ rev_name = "A0";
+ }
+ } else if (dev == MV88F5182_DEV_ID) {
+ dev_name = "MV88F5182";
+ if (rev == MV88F5182_REV_A2)
+ rev_name = "A2";
+ } else if (dev == MV88F5281_DEV_ID) {
+ dev_name = "MV88F5281";
+ if (rev == MV88F5281_REV_D2)
+ rev_name = "D2";
+ else if (rev == MV88F5281_REV_D1)
+ rev_name = "D1";
+ else if (rev == MV88F5281_REV_D0)
+ rev_name = "D0";
+ } else if (dev == MV88F6183_DEV_ID) {
+ dev_name = "MV88F6183";
+ if (rev == MV88F6183_REV_B0)
+ rev_name = "B0";
+ }
+ if (dev_name == NULL) {
+ sprintf(dev_str, "0x%04x", dev);
+ dev_name = dev_str;
+ }
+ if (rev_name == NULL) {
+ sprintf(rev_str, "0x%02x", rev);
+ rev_name = rev_str;
+ }
+
+ printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ /* Enable and invalidate L2 cache in write through mode */
+ invalidate_l2_cache();
+
+ orion5x_config_adr_windows();
+
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ u32 temp;
+
+ /*CPU streaming & write allocate */
+ temp = readfr_extra_feature_reg();
+ temp &= ~(1 << 28); /* disable wr alloc */
+ writefr_extra_feature_reg(temp);
+
+ temp = readfr_extra_feature_reg();
+ temp &= ~(1 << 29); /* streaming disabled */
+ writefr_extra_feature_reg(temp);
+
+ /* L2Cache settings */
+ temp = readfr_extra_feature_reg();
+ /* Disable L2C pre fetch - Set bit 24 */
+ temp |= (1 << 24);
+ /* enable L2C - Set bit 22 */
+ temp |= (1 << 22);
+ writefr_extra_feature_reg(temp);
+
+ icache_enable();
+ /* Change reset vector to address 0x0 */
+ temp = get_cr();
+ set_cr(temp & ~CR_V);
+
+ return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
diff --git a/cpu/arm926ejs/orion5x/dram.c b/cpu/arm926ejs/orion5x/dram.c
new file mode 100644
index 0000000..824ebc1
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/dram.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/orion5x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * orion5x_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 orion5x_sdram_bar(enum memory_bank bank)
+{
+ struct orion5x_ddr_addr_decode_registers *winregs =
+ (struct orion5x_ddr_addr_decode_registers *)ORION5X_CPU_WIN_BASE;
+
+ u32 result = 0;
+ u32 enable = 0x01 & winregs[bank].size;
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+
+ result = winregs[bank].base;
+ return result;
+}
+
+int dram_init(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
+ gd->bd->bi_dram[i].size = get_ram_size(
+ (volatile long *) (gd->bd->bi_dram[i].start),
+ CONFIG_MAX_RAM_BANK_SIZE);
+ }
+ return 0;
+}
diff --git a/cpu/arm926ejs/orion5x/lowlevel_init.S b/cpu/arm926ejs/orion5x/lowlevel_init.S
new file mode 100644
index 0000000..c04e1ac
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/lowlevel_init.S
@@ -0,0 +1,298 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include "asm/arch/orion5x.h"
+
+/*
+ * Configuration values for SDRAM access setup
+ */
+
+#define SDRAM_CONFIG 0x3148400
+#define SDRAM_MODE 0x62
+#define SDRAM_CONTROL 0x4041000
+#define SDRAM_TIME_CTRL_LOW 0x11602220
+#define SDRAM_TIME_CTRL_HI 0x40c
+#define SDRAM_OPEN_PAGE_EN 0x0
+/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
+#define SDRAM_BANK0_SIZE 0x3ff0001
+#define SDRAM_ADDR_CTRL 0x10
+
+#define SDRAM_OP_NOP 0x05
+#define SDRAM_OP_SETMODE 0x03
+
+#define SDRAM_PAD_CTRL_WR_EN 0x80000000
+#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
+#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
+#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
+
+/*
+ * For Guideline MEM-3 - Drive Strength value
+ */
+
+#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
+#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
+
+/*
+ * For Guideline MEM-4 - DQS Reference Delay Tuning
+ */
+
+#define MSAR_ARMDDRCLCK_MASK 0x000000f0
+#define MSAR_ARMDDRCLCK_H_MASK 0x00000100
+
+#define MSAR_ARMDDRCLCK_333_167 0x00000000
+#define MSAR_ARMDDRCLCK_500_167 0x00000030
+#define MSAR_ARMDDRCLCK_667_167 0x00000060
+#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
+#define MSAR_ARMDDRCLCK_400_200 0x00000010
+#define MSAR_ARMDDRCLCK_600_200 0x00000050
+#define MSAR_ARMDDRCLCK_800_200 0x00000070
+
+#define FTDLL_DDR1_166MHZ 0x0047F001
+
+#define FTDLL_DDR1_200MHZ 0x0044D001
+
+/*
+ * Low-level init happens right after start.S has switched to SVC32,
+ * flushed and disabled caches and disabled MMU. We're still running
+ * from the boot chip select, so the first thing we should do is set
+ * up RAM for us to relocate into.
+ *
+ * board_lowlevel_init is expected to set the board's MPPs and GPIOs.
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+ /* Use 'r4 as the base for internal register accesses */
+ ldr r4, =ORION5X_REGS_PHY_BASE
+
+ /* move internal registers from the default 0xD0000000
+ * to their intended location, defined by SoC */
+ ldr r3, =0xD0000000
+ add r3, r3, #0x20000
+ str r4, [r3, #0x80]
+
+ /* board-specific inits -- see comment above */
+ bl board_lowlevel_init
+
+ /* Use R3 as the base for DRAM registers */
+ add r3, r4, #0x01000
+
+ /*DDR SDRAM Initialization Control */
+ ldr r6, =0x00000001
+ str r6, [r3, #0x480]
+
+ /* Use R3 as the base for PCI registers */
+ add r3, r4, #0x31000
+
+ /* Disable arbiter */
+ ldr r6, =0x00000030
+ str r6, [r3, #0xd00]
+
+ /* Use R3 as the base for DRAM registers */
+ add r3, r4, #0x01000
+
+ /* set all dram windows to 0 */
+ mov r6, #0
+ str r6, [r3, #0x504]
+ str r6, [r3, #0x50C]
+ str r6, [r3, #0x514]
+ str r6, [r3, #0x51C]
+
+ /* 1) Configure SDRAM */
+ ldr r6, =SDRAM_CONFIG
+ str r6, [r3, #0x400]
+
+ /* 2) Set SDRAM Control reg */
+ ldr r6, =SDRAM_CONTROL
+ str r6, [r3, #0x404]
+
+ /* 3) Write SDRAM address control register */
+ ldr r6, =SDRAM_ADDR_CTRL
+ str r6, [r3, #0x410]
+
+ /* 4) Write SDRAM bank 0 size register */
+ ldr r6, =SDRAM_BANK0_SIZE
+ str r6, [r3, #0x504]
+ /* keep other banks disabled */
+
+ /* 5) Write SDRAM open pages control register */
+ ldr r6, =SDRAM_OPEN_PAGE_EN
+ str r6, [r3, #0x414]
+
+ /* 6) Write SDRAM timing Low register */
+ ldr r6, =SDRAM_TIME_CTRL_LOW
+ str r6, [r3, #0x408]
+
+ /* 7) Write SDRAM timing High register */
+ ldr r6, =SDRAM_TIME_CTRL_HI
+ str r6, [r3, #0x40C]
+
+ /* 8) Write SDRAM mode register */
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to its new value. */
+
+ /* 8.1 write 'nop' to SDRAM operation */
+ ldr r6, =SDRAM_OP_NOP
+ str r6, [r3, #0x418]
+
+ /* 8.2 poll SDRAM operation until back in 'normal' mode. */
+1:
+ ldr r6, [r3, #0x418]
+ cmp r6, #0
+ bne 1b
+
+ /* 8.3 Now its safe to write new value to SDRAM Mode register */
+ ldr r6, =SDRAM_MODE
+ str r6, [r3, #0x41C]
+
+ /* 8.4 Set new mode */
+ ldr r6, =SDRAM_OP_SETMODE
+ str r6, [r3, #0x418]
+
+ /* 8.5 poll SDRAM operation until back in 'normal' mode. */
+2:
+ ldr r6, [r3, #0x418]
+ cmp r6, #0
+ bne 2b
+
+ /* DDR SDRAM Address/Control Pads Calibration */
+ ldr r6, [r3, #0x4C0]
+
+ /* Set Bit [31] to make the register writable */
+ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ str r6, [r3, #0x4C0]
+
+ bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+ bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r6
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r6, r6, r1
+ str r6, [r3, #0x4C0]
+
+ /* DDR SDRAM Data Pads Calibration */
+ ldr r6, [r3, #0x4C4]
+
+ /* Set Bit [31] to make the register writable */
+ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ str r6, [r3, #0x4C4]
+
+ bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+ bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r6
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26
+ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r6, r6, r1
+
+ str r6, [r3, #0x4C4]
+
+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+
+ ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
+
+ /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
+ ldr r6, [r3, #0x4C0]
+ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ str r6, [r3, #0x4C0]
+
+ /* Correct strength and disable writes again */
+ bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+ orr r6, r6, r1
+ str r6, [r3, #0x4C0]
+
+ /* Enable writes to DDR SDRAM Data Pads Calibration register */
+ ldr r6, [r3, #0x4C4]
+ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ str r6, [r3, #0x4C4]
+
+ /* Correct strength and disable writes again */
+ bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+ bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ orr r6, r6, r1
+ str r6, [r3, #0x4C4]
+
+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+
+ /* Get the "sample on reset" register for the DDR frequancy */
+ ldr r3, =0x10000
+ ldr r6, [r3, #0x010]
+ ldr r1, =MSAR_ARMDDRCLCK_MASK
+ and r1, r6, r1
+
+ ldr r6, =FTDLL_DDR1_166MHZ
+ cmp r1, #MSAR_ARMDDRCLCK_333_167
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_500_167
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_667_167
+ beq 3f
+
+ ldr r6, =FTDLL_DDR1_200MHZ
+ cmp r1, #MSAR_ARMDDRCLCK_400_200_1
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_400_200
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_600_200
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_800_200
+ beq 3f
+
+ ldr r6, =0
+
+3:
+ /* Use R3 as the base for DRAM registers */
+ add r3, r4, #0x01000
+
+ ldr r2, [r3, #0x484]
+ orr r2, r2, r6
+ str r2, [r3, #0x484]
+
+ /* Return to U-boot via saved link register */
+ mov pc, lr
diff --git a/cpu/arm926ejs/orion5x/timer.c b/cpu/arm926ejs/orion5x/timer.c
new file mode 100644
index 0000000..115448f
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/timer.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/orion5x.h>
+
+#define UBOOT_CNTR 0 /* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct orion5x_tmr_val {
+ u32 reload; /* Timer reload reg */
+ u32 val; /* Timer value reg */
+};
+
+/* Timer registers */
+struct orion5x_tmr_registers {
+ u32 ctrl; /* Timer control reg */
+ u32 pad[3];
+ struct orion5x_tmr_val tmr[2];
+ u32 wdt_reload;
+ u32 wdt_val;
+};
+
+struct orion5x_tmr_registers *orion5x_tmr_regs =
+ (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
+#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
+#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS 0
+#define TRG_ARM_TIMER_REL_MASK 0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS 0
+#define TVR_ARM_TIMER_MASK 0xffffffff
+#define TVR_ARM_TIMER_MAX 0xffffffff
+#define TIMER_LOAD_VAL 0xffffffff
+
+static inline ulong read_timer(void)
+{
+ return readl(CNTMR_VAL_REG(UBOOT_CNTR))
+ / (CONFIG_SYS_TCLK / 1000);
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = read_timer();
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = read_timer();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec +
+ (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+static inline ulong uboot_cntr_val(void)
+{
+ return readl(CNTMR_VAL_REG(UBOOT_CNTR));
+}
+
+void __udelay(unsigned long usec)
+{
+ uint current;
+ ulong delayticks;
+
+ current = uboot_cntr_val();
+ delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+ if (current < delayticks) {
+ delayticks -= current;
+ while (uboot_cntr_val() < current)
+ ;
+ while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
+ ;
+ } else {
+ while (uboot_cntr_val() > (current - delayticks))
+ ;
+ }
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+ unsigned int cntmrctrl;
+
+ /* load value into timer */
+ writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+ writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+ /* enable timer in auto reload mode */
+ cntmrctrl = readl(CNTMR_CTRL_REG);
+ cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+ cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+ writel(cntmrctrl, CNTMR_CTRL_REG);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
diff --git a/include/asm-arm/arch-orion5x/cpu.h b/include/asm-arm/arch-orion5x/cpu.h
new file mode 100644
index 0000000..911a72c
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/cpu.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirorion5x_ood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ORION5X_CPU_H
+#define _ORION5X_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+ | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
+
+#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \
+ ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
+
+enum memory_bank {
+ BANK0,
+ BANK1,
+ BANK2,
+ BANK3
+};
+
+enum orion5x_cpu_winen {
+ ORION5X_WIN_DISABLE,
+ ORION5X_WIN_ENABLE
+};
+
+enum orion5x_cpu_target {
+ ORION5X_TARGET_DRAM = 0,
+ ORION5X_TARGET_DEVICE = 1,
+ ORION5X_TARGET_PCI = 3,
+ ORION5X_TARGET_PCIE = 4,
+ ORION5X_TARGET_SASRAM = 9
+};
+
+enum orion5x_cpu_attrib {
+ ORION5X_ATTR_DRAM_CS0 = 0x0e,
+ ORION5X_ATTR_DRAM_CS1 = 0x0d,
+ ORION5X_ATTR_DRAM_CS2 = 0x0b,
+ ORION5X_ATTR_DRAM_CS3 = 0x07,
+ ORION5X_ATTR_PCI_MEM = 0x59,
+ ORION5X_ATTR_PCI_IO = 0x51,
+ ORION5X_ATTR_PCIE_MEM = 0x59,
+ ORION5X_ATTR_PCIE_IO = 0x51,
+ ORION5X_ATTR_SASRAM = 0x00,
+ ORION5X_ATTR_DEV_CS0 = 0x1e,
+ ORION5X_ATTR_DEV_CS1 = 0x1d,
+ ORION5X_ATTR_DEV_CS2 = 0x1b,
+ ORION5X_ATTR_BOOTROM = 0x0f
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define ORION5X_DEFADR_PCIE_MEM 0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0
+#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024)
+
+#define ORION5X_DEFADR_PCIE_IO 0xf0000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0
+#define ORION5X_DEFSZ_PCIE_IO (64*1024)
+
+#define ORION5X_DEFADR_PCI_MEM 0x98000000
+#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024)
+
+#define ORION5X_DEFADR_PCI_IO 0xf0100000
+#define ORION5X_DEFSZ_PCI_IO (64*1024)
+
+#define ORION5X_DEFADR_DEV_CS0 0xfa000000
+#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS1 0xf8000000
+#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS2 0xfa800000
+#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024)
+
+#define ORION5X_DEFADR_BOOTROM 0xFFF80000
+#define ORION5X_DEFSZ_BOOTROM (512*1024)
+
+/*
+ * PCIE registers are used for SoC device ID and revision
+ */
+#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
+#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
+
+/*
+ * The following definitions are intended for identifying
+ * the real device and revision on which u-boot is running
+ * even if it was compiled only for a specific one. Thus,
+ * these constants must not be considered chip-specific.
+ */
+
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID 0x5181
+#define MV88F5181_REV_B1 3
+#define MV88F5181L_REV_A0 8
+#define MV88F5181L_REV_A1 9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID 0x5182
+#define MV88F5182_REV_A2 2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID 0x5281
+#define MV88F5281_REV_D0 4
+#define MV88F5281_REV_D1 5
+#define MV88F5281_REV_D2 6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID 0x6183
+#define MV88F6183_REV_B0 3
+
+/*
+ * read feroceon core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+ unsigned int val;
+ asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
+ (val)::"cc");
+ return val;
+}
+
+/*
+ * write feroceon core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+ asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
+ (val):"cc");
+ isb();
+}
+
+/*
+ * AHB to Mbus Bridge Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.4
+ * Note: only windows 0 and 1 have remap capability.
+ */
+struct orion5x_win_registers {
+ u32 ctrl;
+ u32 base;
+ u32 remap_lo;
+ u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.4
+ */
+struct orion5x_cpu_registers {
+ u32 config; /*0x20100 */
+ u32 ctrl_stat; /*0x20104 */
+ u32 rstoutn_mask; /* 0x20108 */
+ u32 sys_soft_rst; /* 0x2010C */
+ u32 ahb_mbus_cause_irq; /* 0x20110 */
+ u32 ahb_mbus_mask_irq; /* 0x20114 */
+};
+
+/*
+ * DDR SDRAM Controller Address Decode Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.5.1
+ */
+struct orion5x_ddr_addr_decode_registers {
+ u32 base;
+ u32 size;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+u32 orion5x_device_id(void);
+u32 orion5x_device_rev(void);
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
+#endif /* __ASSEMBLY__ */
+#endif /* _ORION5X_CPU_H */
diff --git a/include/asm-arm/arch-orion5x/mv88f5182.h b/include/asm-arm/arch-orion5x/mv88f5182.h
new file mode 100644
index 0000000..86ba08d
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/mv88f5182.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood 88F6182 support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88F5182 SOC.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_88F5182_H
+#define _CONFIG_88F5182_H
+
+/* SOC specific definitions */
+#define F88F5182_REGS_PHYS_BASE 0xf1000000
+#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE
+
+/* TCLK Core Clock defination */
+#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+
+#endif /* _CONFIG_88F5182_H */
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
new file mode 100644
index 0000000..4008c84
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Marvell's Orion SoC with Feroceon CPU core.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ORION5X_H
+#define _ASM_ARCH_ORION5X_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* __ASSEMBLY__ */
+
+#if defined(CONFIG_FEROCEON)
+#include <asm/arch/cpu.h>
+
+/* SOC specific definations */
+#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
+
+/* Documented registers */
+#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
+#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
+#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
+#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000))
+#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100))
+#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000))
+#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100))
+#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300))
+#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000))
+#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000))
+#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000))
+#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
+#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
+
+#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
+
+/* include here SoC variants. 5181, 5281, 6183 should go here when
+ adding support for them, and this comment should then be updated. */
+#if defined(CONFIG_88F5182)
+#include <asm/arch/mv88f5182.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_FEROCEON */
+#endif /* _ASM_ARCH_ORION5X_H */
--
1.6.4.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 2/3] Add Orion5x support to 16550 device driver
2010-04-09 8:29 [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC Albert Aribaud
@ 2010-04-09 8:29 ` Albert Aribaud
2010-04-09 8:29 ` [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED Mini V2 board Albert Aribaud
2010-04-10 21:16 ` [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC Wolfgang Denk
1 sibling, 1 reply; 23+ messages in thread
From: Albert Aribaud @ 2010-04-09 8:29 UTC (permalink / raw)
To: u-boot
This patch provides access to the 16550-compatible
serial device of the Orion5x SoC.
---
drivers/serial/serial.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index dd5f332..18686a2 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -30,6 +30,9 @@
#ifdef CONFIG_KIRKWOOD
#include <asm/arch/kirkwood.h>
#endif
+#ifdef CONFIG_ORION5X
+#include <asm/arch/orion5x.h>
+#endif
#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>
--
1.6.4.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED Mini V2 board
2010-04-09 8:29 ` [U-Boot] [PATCH V6 2/3] Add Orion5x support to 16550 device driver Albert Aribaud
@ 2010-04-09 8:29 ` Albert Aribaud
2010-04-09 9:37 ` Prafulla Wadaskar
0 siblings, 1 reply; 23+ messages in thread
From: Albert Aribaud @ 2010-04-09 8:29 UTC (permalink / raw)
To: u-boot
This patch adds support for the LaCie ED Mini V2 product
which is based on the Marvell Orion5x SoC.
---
MAINTAINERS | 4 +
MAKEALL | 1 +
Makefile | 3 +
board/LaCie/edminiv2/Makefile | 58 +++++++++++
board/LaCie/edminiv2/board_lowlevel_init.S | 59 +++++++++++
board/LaCie/edminiv2/config.mk | 27 +++++
board/LaCie/edminiv2/edminiv2.c | 93 ++++++++++++++++++
board/LaCie/edminiv2/edminiv2.h | 54 ++++++++++
include/configs/edminiv2.h | 147 ++++++++++++++++++++++++++++
9 files changed, 446 insertions(+), 0 deletions(-)
create mode 100644 board/LaCie/edminiv2/Makefile
create mode 100644 board/LaCie/edminiv2/board_lowlevel_init.S
create mode 100644 board/LaCie/edminiv2/config.mk
create mode 100644 board/LaCie/edminiv2/edminiv2.c
create mode 100644 board/LaCie/edminiv2/edminiv2.h
create mode 100644 include/configs/edminiv2.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 0658bc3..ac49654 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -515,6 +515,10 @@ Unknown / orphaned boards:
# Board CPU #
#########################################################################
+Albert ARIBAUD <albert.aribaud@free.fr>
+
+ edminiv2 ARM926EJS (Orion5x SoC)
+
Rowel Atienza <rowel@diwalabs.com>
armadillo ARM720T
diff --git a/MAKEALL b/MAKEALL
index a88c31e..d659f92 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -559,6 +559,7 @@ LIST_ARM9=" \
edb9312 \
edb9315 \
edb9315a \
+ edminiv2 \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
diff --git a/Makefile b/Makefile
index 4532550..5ae3976 100644
--- a/Makefile
+++ b/Makefile
@@ -2936,6 +2936,9 @@ davinci_dm365evm_config : unconfig
davinci_dm6467evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
+edminiv2_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) LaCie orion5x
+
imx27lite_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile
new file mode 100644
index 0000000..0d6e83d
--- /dev/null
+++ b/board/LaCie/edminiv2/Makefile
@@ -0,0 +1,58 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := edminiv2.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := board_lowlevel_init.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/LaCie/edminiv2/board_lowlevel_init.S b/board/LaCie/edminiv2/board_lowlevel_init.S
new file mode 100644
index 0000000..00e68e9
--- /dev/null
+++ b/board/LaCie/edminiv2/board_lowlevel_init.S
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "edminiv2.h"
+
+/*
+ * Low-level init happens right after start.S has switched to SVC32,
+ * flushed and disabled caches and disabled MMU. We're still running
+ * from the boot chip select, so the first thing we should do is set
+ * up RAM for us to relocate into.
+ *
+ * board_low_level_init is called by the Orion5x lowlevel_init code,
+ * and sets up board-specifics such as MPPs and GPIOs.
+ */
+
+.globl board_lowlevel_init
+
+board_lowlevel_init:
+
+ /* Use R3 as the base for Device Bus registers */
+ add r3, r4, #0x10000
+
+ /* init MPPs */
+ ldr r6, =EDMINIV2_MPP0_7
+ str r6, [r3, #0x000]
+ ldr r6, =EDMINIV2_MPP8_15
+ str r6, [r3, #0x004]
+ ldr r6, =EDMINIV2_MPP16_23
+ str r6, [r3, #0x050]
+
+ /* init GPIOs */
+ ldr r6, =EDMINIV2_GPIO_OUT_ENABLE
+ str r6, [r3, #0x104]
+
+ /* Return to lowlevel_init via saved link register */
+ mov pc, lr
diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk
new file mode 100644
index 0000000..3dec1aa
--- /dev/null
+++ b/board/LaCie/edminiv2/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00100000
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
new file mode 100644
index 0000000..8337990
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+#include "edminiv2.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
+ * which CFI does not properly detect, hence the LEGACY config.
+ */
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
+ int sect;
+
+ if (base != CONFIG_SYS_FLASH_BASE)
+ return 0;
+
+ info->size = 0;
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ /* set each sector's start address and size based */
+ for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
+ info->start[sect] = base+info->size;
+ info->size += sectsz[sect];
+ }
+ /* This flash must be accessed in 8-bits mode, no buffer. */
+ info->flash_id = 0x01000000;
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->buffer_size = 0;
+ /* timings are derived from the Macronix datasheet. */
+ info->erase_blk_tout = 1000;
+ info->write_tout = 10;
+ info->buffer_write_tout = 300;
+ /* Commands and addresses are for AMD mode 8-bit access. */
+ info->vendor = CFI_CMDSET_AMD_LEGACY;
+ info->cmd_reset = 0xF0;
+ info->interface = FLASH_CFI_X8;
+ info->legacy_unlock = 0;
+ info->ext_addr = 0;
+ info->addr_unlock1 = 0x00000aaa;
+ info->addr_unlock2 = 0x00000555;
+ /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
+ info->manufacturer_id = 0x22;
+ info->device_id = 0xBA;
+ info->device_id2 = 0;
+ info->cfi_version = 0x3133;
+ info->cfi_offset = 0x0000;
+ info->name = "MX29LV400CB";
+
+ return 1;
+}
+#endif /* CONFIG_SYS_FLASH_CFI */
+
+int board_init(void)
+{
+ /* arch number of board */
+ gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+ /* boot parameter start at 256th byte of RAM base */
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h
new file mode 100644
index 0000000..3e20b61
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_H
+#define __EDMINIV2_H
+
+/*
+ * Board-specific values for Orion5x MPP low level init:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
+ * MPP16 to MPP19, mode 0 for others
+ */
+
+#define EDMINIV2_MPP0_7 0x00000003
+#define EDMINIV2_MPP8_15 0x55550000
+#define EDMINIV2_MPP16_23 0x00000000
+
+/*
+ * Board-specific values for Orion5x GPIO low level init:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - Last GPIO is 26, further bits are supposed to be 0.
+ * Enable mask has ones for INPUT, 0 for OUTPUT.
+ * Default is LED ON.
+ */
+
+#define EDMINIV2_GPIO_OUT_ENABLE 0x03fcffff
+
+#endif /* __EDMINIV2_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
new file mode 100644
index 0000000..d0f9aea
--- /dev/null
+++ b/include/configs/edminiv2.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_EDMINIV2_H
+#define _CONFIG_EDMINIV2_H
+
+/*
+ * Version number information
+ */
+
+#define CONFIG_IDENT_STRING " EDMiniV2"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON 1 /* CPU Core subversion */
+#define CONFIG_ORION5X 1 /* SOC Family Name */
+#define CONFIG_88F5182 1 /* SOC Name */
+#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
+
+/*
+ * CLKs configurations
+ */
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
+
+/*
+ * FLASH configuration
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE 0xfff80000
+#define CONFIG_SYS_FLASH_SECTSZ \
+ {16384, 8192, 8192, 32768, \
+ 65536, 65536, 65536, 65536, 65536, 65536, 65536}
+
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration - using default command set for now
+ */
+#include <config_cmd_default.h>
+/*
+ * Disabling some default commands for staggered bring-up
+ */
+#undef CONFIG_CMD_BOOTD /* no bootd since no net */
+#undef CONFIG_CMD_NET /* no net since no eth */
+#undef CONFIG_CMD_NFS /* no NFS since no net */
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_STACKSIZE 0x00100000
+#define CONFIG_SYS_LOAD_ADDR 0x00800000
+#define CONFIG_SYS_MEMTEST_START 0x00400000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
+#define CONFIG_SYS_MAXARGS 16
+
+#endif /* _CONFIG_EDMINIV2_H */
--
1.6.4.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED Mini V2 board
2010-04-09 8:29 ` [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED Mini V2 board Albert Aribaud
@ 2010-04-09 9:37 ` Prafulla Wadaskar
2010-04-12 11:13 ` Prafulla Wadaskar
0 siblings, 1 reply; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-04-09 9:37 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Friday, April 09, 2010 1:59 PM
> To: U-Boot at lists.denx.de
> Subject: [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED
> Mini V2 board
>
> This patch adds support for the LaCie ED Mini V2 product
> which is based on the Marvell Orion5x SoC.
> ---
> MAINTAINERS | 4 +
> MAKEALL | 1 +
> Makefile | 3 +
> board/LaCie/edminiv2/Makefile | 58 +++++++++++
> board/LaCie/edminiv2/board_lowlevel_init.S | 59 +++++++++++
> board/LaCie/edminiv2/config.mk | 27 +++++
> board/LaCie/edminiv2/edminiv2.c | 93 ++++++++++++++++++
> board/LaCie/edminiv2/edminiv2.h | 54 ++++++++++
> include/configs/edminiv2.h | 147
> ++++++++++++++++++++++++++++
> 9 files changed, 446 insertions(+), 0 deletions(-)
> create mode 100644 board/LaCie/edminiv2/Makefile
> create mode 100644 board/LaCie/edminiv2/board_lowlevel_init.S
> create mode 100644 board/LaCie/edminiv2/config.mk
> create mode 100644 board/LaCie/edminiv2/edminiv2.c
> create mode 100644 board/LaCie/edminiv2/edminiv2.h
> create mode 100644 include/configs/edminiv2.h
>
..snip..
> diff --git a/board/LaCie/edminiv2/board_lowlevel_init.S
> b/board/LaCie/edminiv2/board_lowlevel_init.S
> new file mode 100644
> index 0000000..00e68e9
> --- /dev/null
> +++ b/board/LaCie/edminiv2/board_lowlevel_init.S
> @@ -0,0 +1,59 @@
> +/*
> + * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
> + *
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include "edminiv2.h"
> +
> +/*
> + * Low-level init happens right after start.S has switched to SVC32,
> + * flushed and disabled caches and disabled MMU. We're still running
> + * from the boot chip select, so the first thing we should do is set
> + * up RAM for us to relocate into.
> + *
> + * board_low_level_init is called by the Orion5x lowlevel_init code,
> + * and sets up board-specifics such as MPPs and GPIOs.
> + */
> +
> +.globl board_lowlevel_init
> +
> +board_lowlevel_init:
> +
> + /* Use R3 as the base for Device Bus registers */
> + add r3, r4, #0x10000
> +
> + /* init MPPs */
> + ldr r6, =EDMINIV2_MPP0_7
> + str r6, [r3, #0x000]
> + ldr r6, =EDMINIV2_MPP8_15
> + str r6, [r3, #0x004]
> + ldr r6, =EDMINIV2_MPP16_23
> + str r6, [r3, #0x050]
> +
> + /* init GPIOs */
> + ldr r6, =EDMINIV2_GPIO_OUT_ENABLE
> + str r6, [r3, #0x104]
> +
> + /* Return to lowlevel_init via saved link register */
> + mov pc, lr
Dear Albert
You are just doing mpp and gpio settings here, those are IO specific only
you can have mpp and gpio configs as in case of Kirkwood (c functions) and call them from your bard_init.
Please remove this file.
and dependency of this code with lowlevel_init.S in patch 1/2
That's it.
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-09 8:29 [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC Albert Aribaud
2010-04-09 8:29 ` [U-Boot] [PATCH V6 2/3] Add Orion5x support to 16550 device driver Albert Aribaud
@ 2010-04-10 21:16 ` Wolfgang Denk
2010-04-11 7:35 ` Albert ARIBAUD
1 sibling, 1 reply; 23+ messages in thread
From: Wolfgang Denk @ 2010-04-10 21:16 UTC (permalink / raw)
To: u-boot
Dear Albert Aribaud,
In message <1270801745-18852-1-git-send-email-albert.aribaud@free.fr> you wrote:
> This patch adds support for the Marvell Orion5x SoC.
> It has no use alone, and must be followed by a patch
> to add Orion5x support for serial, then support for
> the ED Mini V2, an Orion5x-based product from LaCie.
> ---
> Patchset history
>
> V1: Initial monolithic patch.
> V2: split in three patches : orion, serial, edmini;
> checkpatch'ed, with only 6 errors, in patch 1/3,
> all 6 errors being false positives.
> V3: useless GPIO and MPP programming support removed;
> low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
> V4: all files licensed GPLv2-only removed;
> RAM bank size detection now uses get_ram_size().
> V5: Replaced macros by C structs in dram code.
> Removed compilation warnings in dram code.
> Added comments to legacy flash definitions.
> Split low level init code into SoC- and Chip-specifics.
> V6: Set copyright dates to 2010, and put standard GPL notice
> mentioning Marvell's copyright on *_lowlevel_init.S files.
Just to be sure: do you have Marvell's permission to change the
licensing terms?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
He'd heard her use that sweet, innocent tone of voice before. It
meant that, pretty soon, there was going to be trouble.
- Terry Pratchett, _Truckers_
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-10 21:16 ` [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC Wolfgang Denk
@ 2010-04-11 7:35 ` Albert ARIBAUD
2010-04-11 7:41 ` Albert ARIBAUD
2010-04-11 11:56 ` Wolfgang Denk
0 siblings, 2 replies; 23+ messages in thread
From: Albert ARIBAUD @ 2010-04-11 7:35 UTC (permalink / raw)
To: u-boot
Wi Wolfgang,
Wolfgang Denk a ?crit :
> Dear Albert Aribaud,
>
> In message <1270801745-18852-1-git-send-email-albert.aribaud@free.fr> you wrote:
>> This patch adds support for the Marvell Orion5x SoC.
>> It has no use alone, and must be followed by a patch
>> to add Orion5x support for serial, then support for
>> the ED Mini V2, an Orion5x-based product from LaCie.
>> ---
>> Patchset history
>>
>> V1: Initial monolithic patch.
>> V2: split in three patches : orion, serial, edmini;
>> checkpatch'ed, with only 6 errors, in patch 1/3,
>> all 6 errors being false positives.
>> V3: useless GPIO and MPP programming support removed;
>> low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
>> V4: all files licensed GPLv2-only removed;
>> RAM bank size detection now uses get_ram_size().
>> V5: Replaced macros by C structs in dram code.
>> Removed compilation warnings in dram code.
>> Added comments to legacy flash definitions.
>> Split low level init code into SoC- and Chip-specifics.
>> V6: Set copyright dates to 2010, and put standard GPL notice
>> mentioning Marvell's copyright on *_lowlevel_init.S files.
>
> Just to be sure: do you have Marvell's permission to change the
> licensing terms?
Actually this was checked by Prafulla in december:
<http://lists.denx.de/pipermail/u-boot/2009-December/065797.html>
> Best regards,
>
> Wolfgang Denk
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-11 7:35 ` Albert ARIBAUD
@ 2010-04-11 7:41 ` Albert ARIBAUD
2010-04-12 8:32 ` Prafulla Wadaskar
2010-04-11 11:56 ` Wolfgang Denk
1 sibling, 1 reply; 23+ messages in thread
From: Albert ARIBAUD @ 2010-04-11 7:41 UTC (permalink / raw)
To: u-boot
Albert ARIBAUD a ?crit :
> Wi Wolfgang,
>
> Wolfgang Denk a ?crit :
>
>> Dear Albert Aribaud,
>>
>> In message <1270801745-18852-1-git-send-email-albert.aribaud@free.fr>
>> you wrote:
>>> This patch adds support for the Marvell Orion5x SoC.
>>> It has no use alone, and must be followed by a patch
>>> to add Orion5x support for serial, then support for
>>> the ED Mini V2, an Orion5x-based product from LaCie.
>>> ---
>>> Patchset history
>>>
>>> V1: Initial monolithic patch.
>>> V2: split in three patches : orion, serial, edmini;
>>> checkpatch'ed, with only 6 errors, in patch 1/3,
>>> all 6 errors being false positives.
>>> V3: useless GPIO and MPP programming support removed;
>>> low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
>>> V4: all files licensed GPLv2-only removed;
>>> RAM bank size detection now uses get_ram_size().
>>> V5: Replaced macros by C structs in dram code.
>>> Removed compilation warnings in dram code.
>>> Added comments to legacy flash definitions.
>>> Split low level init code into SoC- and Chip-specifics.
>>> V6: Set copyright dates to 2010, and put standard GPL notice
>>> mentioning Marvell's copyright on *_lowlevel_init.S files.
>>
>> Just to be sure: do you have Marvell's permission to change the
>> licensing terms?
>
> Actually this was checked by Prafulla in december:
>
> <http://lists.denx.de/pipermail/u-boot/2009-December/065797.html>
My mistake--this was for the linux-imported files only.
As for the Marvell-created files, Prafulla (added to To:) should be in
position to get us the needed permission.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-11 7:35 ` Albert ARIBAUD
2010-04-11 7:41 ` Albert ARIBAUD
@ 2010-04-11 11:56 ` Wolfgang Denk
1 sibling, 0 replies; 23+ messages in thread
From: Wolfgang Denk @ 2010-04-11 11:56 UTC (permalink / raw)
To: u-boot
Dear Albert ARIBAUD,
In message <4BC17BDF.70904@free.fr> you wrote:
>
> > Just to be sure: do you have Marvell's permission to change the
> > licensing terms?
>
> Actually this was checked by Prafulla in december:
>
> <http://lists.denx.de/pipermail/u-boot/2009-December/065797.html>
Prafulla wrote:
>> I got a GREEN flag from respective owners, we can update these
>> files for GPL v2, I will send the patch soon.
But "GPL v2" is not sufficient. We need "GPL, either version 2, or (at
your option) any later version".
This is a small, but important difference.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is practically impossible to teach good programming style to stu-
dents that have had prior exposure to BASIC: as potential programmers
they are mentally mutilated beyond hope of regeneration. - Dijkstra
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-11 7:41 ` Albert ARIBAUD
@ 2010-04-12 8:32 ` Prafulla Wadaskar
2010-04-12 10:42 ` Albert ARIBAUD
2010-04-12 10:45 ` Wolfgang Denk
0 siblings, 2 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-04-12 8:32 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Sunday, April 11, 2010 1:12 PM
> To: Albert ARIBAUD
> Cc: Wolfgang Denk; U-Boot at lists.denx.de; Prafulla Wadaskar
> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
> Marvell Orion5x SoC
>
> Albert ARIBAUD a ?crit :
> > Wi Wolfgang,
> >
> > Wolfgang Denk a ?crit :
> >
> >> Dear Albert Aribaud,
> >>
> >> In message
> <1270801745-18852-1-git-send-email-albert.aribaud@free.fr>
> >> you wrote:
> >>> This patch adds support for the Marvell Orion5x SoC.
> >>> It has no use alone, and must be followed by a patch
> >>> to add Orion5x support for serial, then support for
> >>> the ED Mini V2, an Orion5x-based product from LaCie.
> >>> ---
> >>> Patchset history
> >>>
> >>> V1: Initial monolithic patch.
> >>> V2: split in three patches : orion, serial, edmini;
> >>> checkpatch'ed, with only 6 errors, in patch 1/3,
> >>> all 6 errors being false positives.
> >>> V3: useless GPIO and MPP programming support removed;
> >>> low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
> >>> V4: all files licensed GPLv2-only removed;
> >>> RAM bank size detection now uses get_ram_size().
> >>> V5: Replaced macros by C structs in dram code.
> >>> Removed compilation warnings in dram code.
> >>> Added comments to legacy flash definitions.
> >>> Split low level init code into SoC- and Chip-specifics.
> >>> V6: Set copyright dates to 2010, and put standard GPL notice
> >>> mentioning Marvell's copyright on *_lowlevel_init.S files.
> >>
> >> Just to be sure: do you have Marvell's permission to change the
> >> licensing terms?
> >
> > Actually this was checked by Prafulla in december:
> >
> > <http://lists.denx.de/pipermail/u-boot/2009-December/065797.html>
>
> My mistake--this was for the linux-imported files only.
>
> As for the Marvell-created files, Prafulla (added to To:)
> should be in
> position to get us the needed permission.
After re-confirmation with internal teams.
Yes, all the code that is going out from Marvell for U-boot + LSP by any means is meant to be GPL, if something is missing that can/should be corrected.
Hi Albert,
you can modify the headers accordingly.
Regards..
Prafulla . .
>
> Amicalement,
> --
> Albert.
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-12 8:32 ` Prafulla Wadaskar
@ 2010-04-12 10:42 ` Albert ARIBAUD
2010-04-12 10:45 ` Wolfgang Denk
1 sibling, 0 replies; 23+ messages in thread
From: Albert ARIBAUD @ 2010-04-12 10:42 UTC (permalink / raw)
To: u-boot
Prafulla Wadaskar a ?crit :
>
>
>> -----Original Message-----
>> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
>> Sent: Sunday, April 11, 2010 1:12 PM
>> To: Albert ARIBAUD
>> Cc: Wolfgang Denk; U-Boot at lists.denx.de; Prafulla Wadaskar
>> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
>> Marvell Orion5x SoC
>>
>> Albert ARIBAUD a ?crit :
>>> Wi Wolfgang,
>>>
>>> Wolfgang Denk a ?crit :
>>>
>>>> Dear Albert Aribaud,
>>>>
>>>> In message
>> <1270801745-18852-1-git-send-email-albert.aribaud@free.fr>
>>>> you wrote:
>>>>> This patch adds support for the Marvell Orion5x SoC.
>>>>> It has no use alone, and must be followed by a patch
>>>>> to add Orion5x support for serial, then support for
>>>>> the ED Mini V2, an Orion5x-based product from LaCie.
>>>>> ---
>>>>> Patchset history
>>>>>
>>>>> V1: Initial monolithic patch.
>>>>> V2: split in three patches : orion, serial, edmini;
>>>>> checkpatch'ed, with only 6 errors, in patch 1/3,
>>>>> all 6 errors being false positives.
>>>>> V3: useless GPIO and MPP programming support removed;
>>>>> low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
>>>>> V4: all files licensed GPLv2-only removed;
>>>>> RAM bank size detection now uses get_ram_size().
>>>>> V5: Replaced macros by C structs in dram code.
>>>>> Removed compilation warnings in dram code.
>>>>> Added comments to legacy flash definitions.
>>>>> Split low level init code into SoC- and Chip-specifics.
>>>>> V6: Set copyright dates to 2010, and put standard GPL notice
>>>>> mentioning Marvell's copyright on *_lowlevel_init.S files.
>>>> Just to be sure: do you have Marvell's permission to change the
>>>> licensing terms?
>>> Actually this was checked by Prafulla in december:
>>>
>>> <http://lists.denx.de/pipermail/u-boot/2009-December/065797.html>
>> My mistake--this was for the linux-imported files only.
>>
>> As for the Marvell-created files, Prafulla (added to To:)
>> should be in
>> position to get us the needed permission.
>
> After re-confirmation with internal teams.
> Yes, all the code that is going out from Marvell for U-boot + LSP by any means is meant to be GPL, if something is missing that can/should be corrected.
>
> Hi Albert,
> you can modify the headers accordingly.
>
> Regards..
> Prafulla . .
Actually, in V6 of the patch the notices are already "GPL v2 or later"
for all files.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-12 8:32 ` Prafulla Wadaskar
2010-04-12 10:42 ` Albert ARIBAUD
@ 2010-04-12 10:45 ` Wolfgang Denk
2010-04-12 11:09 ` Prafulla Wadaskar
1 sibling, 1 reply; 23+ messages in thread
From: Wolfgang Denk @ 2010-04-12 10:45 UTC (permalink / raw)
To: u-boot
Dear Prafulla,
In message <F766E4F80769BD478052FB6533FA745D1878702635@SC-VEXCH4.marvell.com> you wrote:
>
> After re-confirmation with internal teams.
> Yes, all the code that is going out from Marvell for U-boot + LSP
> by any means is meant to be GPL, if something is missing that
> can/should be corrected.
"GPL" alone is not precise enough - it could mean "GPL v2" or "GPL v3"
or "GPL v2 or later" (which is what we need).
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The software required `Windows 95 or better', so I installed Linux.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-12 10:45 ` Wolfgang Denk
@ 2010-04-12 11:09 ` Prafulla Wadaskar
2010-04-12 12:00 ` Albert ARIBAUD
` (2 more replies)
0 siblings, 3 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-04-12 11:09 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Monday, April 12, 2010 4:16 PM
> To: Prafulla Wadaskar
> Cc: Albert ARIBAUD; U-Boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
> Marvell Orion5x SoC
>
> Dear Prafulla,
>
> In message
> <F766E4F80769BD478052FB6533FA745D1878702635@SC-VEXCH4.marvell.
> com> you wrote:
> >
> > After re-confirmation with internal teams.
> > Yes, all the code that is going out from Marvell for U-boot + LSP
> > by any means is meant to be GPL, if something is missing that
> > can/should be corrected.
>
> "GPL" alone is not precise enough - it could mean "GPL v2" or "GPL v3"
> or "GPL v2 or later" (which is what we need).
Hi Wolfgang
Sorry for typing small word GPL in the earlier email.
My re-confirmation discussion was w.r.to "GPL v2 or later"
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED Mini V2 board
2010-04-09 9:37 ` Prafulla Wadaskar
@ 2010-04-12 11:13 ` Prafulla Wadaskar
0 siblings, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-04-12 11:13 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Prafulla Wadaskar
> Sent: Friday, April 09, 2010 3:08 PM
> To: Albert Aribaud; U-Boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH V6 3/3] Add support for the
> LaCie ED Mini V2 board
>
>
>
> > -----Original Message-----
> > From: u-boot-bounces at lists.denx.de
> > [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> > Sent: Friday, April 09, 2010 1:59 PM
> > To: U-Boot at lists.denx.de
> > Subject: [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED
> > Mini V2 board
> >
> > This patch adds support for the LaCie ED Mini V2 product
> > which is based on the Marvell Orion5x SoC.
> > ---
> > MAINTAINERS | 4 +
> > MAKEALL | 1 +
> > Makefile | 3 +
> > board/LaCie/edminiv2/Makefile | 58 +++++++++++
> > board/LaCie/edminiv2/board_lowlevel_init.S | 59 +++++++++++
> > board/LaCie/edminiv2/config.mk | 27 +++++
> > board/LaCie/edminiv2/edminiv2.c | 93
> ++++++++++++++++++
> > board/LaCie/edminiv2/edminiv2.h | 54 ++++++++++
> > include/configs/edminiv2.h | 147
> > ++++++++++++++++++++++++++++
> > 9 files changed, 446 insertions(+), 0 deletions(-)
> > create mode 100644 board/LaCie/edminiv2/Makefile
> > create mode 100644 board/LaCie/edminiv2/board_lowlevel_init.S
> > create mode 100644 board/LaCie/edminiv2/config.mk
> > create mode 100644 board/LaCie/edminiv2/edminiv2.c
> > create mode 100644 board/LaCie/edminiv2/edminiv2.h
> > create mode 100644 include/configs/edminiv2.h
> >
> ..snip..
> > diff --git a/board/LaCie/edminiv2/board_lowlevel_init.S
> > b/board/LaCie/edminiv2/board_lowlevel_init.S
> > new file mode 100644
> > index 0000000..00e68e9
> > --- /dev/null
> > +++ b/board/LaCie/edminiv2/board_lowlevel_init.S
> > @@ -0,0 +1,59 @@
> > +/*
> > + * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
> > + *
> > + * (C) Copyright 2009
> > + * Marvell Semiconductor <www.marvell.com>
> > + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General
> Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> > + * MA 02110-1301 USA
> > + */
> > +
> > +#include "edminiv2.h"
> > +
> > +/*
> > + * Low-level init happens right after start.S has switched
> to SVC32,
> > + * flushed and disabled caches and disabled MMU. We're
> still running
> > + * from the boot chip select, so the first thing we should
> do is set
> > + * up RAM for us to relocate into.
> > + *
> > + * board_low_level_init is called by the Orion5x
> lowlevel_init code,
> > + * and sets up board-specifics such as MPPs and GPIOs.
> > + */
> > +
> > +.globl board_lowlevel_init
> > +
> > +board_lowlevel_init:
> > +
> > + /* Use R3 as the base for Device Bus registers */
> > + add r3, r4, #0x10000
> > +
> > + /* init MPPs */
> > + ldr r6, =EDMINIV2_MPP0_7
> > + str r6, [r3, #0x000]
> > + ldr r6, =EDMINIV2_MPP8_15
> > + str r6, [r3, #0x004]
> > + ldr r6, =EDMINIV2_MPP16_23
> > + str r6, [r3, #0x050]
> > +
> > + /* init GPIOs */
> > + ldr r6, =EDMINIV2_GPIO_OUT_ENABLE
> > + str r6, [r3, #0x104]
> > +
> > + /* Return to lowlevel_init via saved link register */
> > + mov pc, lr
>
> Dear Albert
>
> You are just doing mpp and gpio settings here, those are IO
> specific only
> you can have mpp and gpio configs as in case of Kirkwood (c
> functions) and call them from your bard_init.
> Please remove this file.
> and dependency of this code with lowlevel_init.S in patch 1/2
>
> That's it.
Dear Albert
Can you pls do the needfull for above and post V7 for this patch?
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-12 11:09 ` Prafulla Wadaskar
@ 2010-04-12 12:00 ` Albert ARIBAUD
2010-04-12 12:41 ` Wolfgang Denk
2010-04-12 15:02 ` Albert ARIBAUD
2 siblings, 0 replies; 23+ messages in thread
From: Albert ARIBAUD @ 2010-04-12 12:00 UTC (permalink / raw)
To: u-boot
Prafulla Wadaskar a ?crit :
>
>
>> -----Original Message-----
>> From: Wolfgang Denk [mailto:wd at denx.de]
>> Sent: Monday, April 12, 2010 4:16 PM
>> To: Prafulla Wadaskar
>> Cc: Albert ARIBAUD; U-Boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
>> Marvell Orion5x SoC
>>
>> Dear Prafulla,
>>
>> In message
>> <F766E4F80769BD478052FB6533FA745D1878702635@SC-VEXCH4.marvell.
>> com> you wrote:
>>> After re-confirmation with internal teams.
>>> Yes, all the code that is going out from Marvell for U-boot + LSP
>>> by any means is meant to be GPL, if something is missing that
>>> can/should be corrected.
>> "GPL" alone is not precise enough - it could mean "GPL v2" or "GPL v3"
>> or "GPL v2 or later" (which is what we need).
>
> Hi Wolfgang
>
> Sorry for typing small word GPL in the earlier email.
> My re-confirmation discussion was w.r.to "GPL v2 or later"
>
> Regards..
> Prafulla . .
Good, then: V6 of my patch is thus fine as regards GPLv2 or later.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-12 11:09 ` Prafulla Wadaskar
2010-04-12 12:00 ` Albert ARIBAUD
@ 2010-04-12 12:41 ` Wolfgang Denk
2010-04-12 15:02 ` Albert ARIBAUD
2 siblings, 0 replies; 23+ messages in thread
From: Wolfgang Denk @ 2010-04-12 12:41 UTC (permalink / raw)
To: u-boot
Dear Prafulla,
In message <F766E4F80769BD478052FB6533FA745D187870268C@SC-VEXCH4.marvell.com> you wrote:
>
> My re-confirmation discussion was w.r.to "GPL v2 or later"
Thanks a lot for this confirmation.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The software required `Windows 95 or better', so I installed Linux.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-12 11:09 ` Prafulla Wadaskar
2010-04-12 12:00 ` Albert ARIBAUD
2010-04-12 12:41 ` Wolfgang Denk
@ 2010-04-12 15:02 ` Albert ARIBAUD
2010-04-13 10:33 ` Prafulla Wadaskar
2 siblings, 1 reply; 23+ messages in thread
From: Albert ARIBAUD @ 2010-04-12 15:02 UTC (permalink / raw)
To: u-boot
(apparently one of Prafulla's answers did not reach me; copy-pasting it
and replying even though it's slightly out of place within the thread)
Prafulla Wadaskar a ?crit :
>
>> -----Original Message-----
>> From: u-boot-bounces at lists.denx.de
>> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Prafulla Wadaskar
>> Sent: Friday, April 09, 2010 3:08 PM
>> To: Albert Aribaud; U-Boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH V6 3/3] Add support for the
>> LaCie ED Mini V2 board
>>
>>
>>
>> > -----Original Message-----
>> > From: u-boot-bounces at lists.denx.de
>> > [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
>> > Sent: Friday, April 09, 2010 1:59 PM
>> > To: U-Boot at lists.denx.de
>> > Subject: [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED
>> > Mini V2 board
>> >
>> > This patch adds support for the LaCie ED Mini V2 product
>> > which is based on the Marvell Orion5x SoC.
>> > ---
>> > MAINTAINERS | 4 +
>> > MAKEALL | 1 +
>> > Makefile | 3 +
>> > board/LaCie/edminiv2/Makefile | 58 +++++++++++
>> > board/LaCie/edminiv2/board_lowlevel_init.S | 59 +++++++++++
>> > board/LaCie/edminiv2/config.mk | 27 +++++
>> > board/LaCie/edminiv2/edminiv2.c | 93
>> ++++++++++++++++++
>> > board/LaCie/edminiv2/edminiv2.h | 54 ++++++++++
>> > include/configs/edminiv2.h | 147
>> > ++++++++++++++++++++++++++++
>> > 9 files changed, 446 insertions(+), 0 deletions(-)
>> > create mode 100644 board/LaCie/edminiv2/Makefile
>> > create mode 100644 board/LaCie/edminiv2/board_lowlevel_init.S
>> > create mode 100644 board/LaCie/edminiv2/config.mk
>> > create mode 100644 board/LaCie/edminiv2/edminiv2.c
>> > create mode 100644 board/LaCie/edminiv2/edminiv2.h
>> > create mode 100644 include/configs/edminiv2.h
>> >
>> ..snip..
>> > diff --git a/board/LaCie/edminiv2/board_lowlevel_init.S
>> > b/board/LaCie/edminiv2/board_lowlevel_init.S
>> > new file mode 100644
>> > index 0000000..00e68e9
>> > --- /dev/null
>> > +++ b/board/LaCie/edminiv2/board_lowlevel_init.S
>> > @@ -0,0 +1,59 @@
>> > +/*
>> > + * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
>> > + *
>> > + * (C) Copyright 2009
>> > + * Marvell Semiconductor <www.marvell.com>
>> > + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
>> > + *
>> > + * See file CREDITS for list of people who contributed to this
>> > + * project.
>> > + *
>> > + * This program is free software; you can redistribute it and/or
>> > + * modify it under the terms of the GNU General Public License as
>> > + * published by the Free Software Foundation; either version 2 of
>> > + * the License, or (at your option) any later version.
>> > + *
>> > + * This program is distributed in the hope that it will be useful,
>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> > + * GNU General Public License for more details.
>> > + *
>> > + * You should have received a copy of the GNU General
>> Public License
>> > + * along with this program; if not, write to the Free Software
>> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
>> > + * MA 02110-1301 USA
>> > + */
>> > +
>> > +#include "edminiv2.h"
>> > +
>> > +/*
>> > + * Low-level init happens right after start.S has switched
>> to SVC32,
>> > + * flushed and disabled caches and disabled MMU. We're
>> still running
>> > + * from the boot chip select, so the first thing we should
>> do is set
>> > + * up RAM for us to relocate into.
>> > + *
>> > + * board_low_level_init is called by the Orion5x
>> lowlevel_init code,
>> > + * and sets up board-specifics such as MPPs and GPIOs.
>> > + */
>> > +
>> > +.globl board_lowlevel_init
>> > +
>> > +board_lowlevel_init:
>> > +
>> > + /* Use R3 as the base for Device Bus registers */
>> > + add r3, r4, #0x10000
>> > +
>> > + /* init MPPs */
>> > + ldr r6, =EDMINIV2_MPP0_7
>> > + str r6, [r3, #0x000]
>> > + ldr r6, =EDMINIV2_MPP8_15
>> > + str r6, [r3, #0x004]
>> > + ldr r6, =EDMINIV2_MPP16_23
>> > + str r6, [r3, #0x050]
>> > +
>> > + /* init GPIOs */
>> > + ldr r6, =EDMINIV2_GPIO_OUT_ENABLE
>> > + str r6, [r3, #0x104]
>> > +
>> > + /* Return to lowlevel_init via saved link register */
>> > + mov pc, lr
>>
>> Dear Albert
>>
>> You are just doing mpp and gpio settings here, those are IO
>> specific only
>> you can have mpp and gpio configs as in case of Kirkwood (c
>> functions) and call them from your bard_init.
>> Please remove this file.
>> and dependency of this code with lowlevel_init.S in patch 1/2
>>
>> That's it.
>
> Dear Albert
>
> Can you pls do the needfull for above and post V7 for this patch?
I can, but IMO that would doing C code for the sake of C code.
The ED Mini board is a product, not a dev board, and has a completely
static and predefined MPP and GPIO configuration; there will not even be
an API to modify them from within U-boot (this was discussed in earlier
iterations of the patch) and thus their whole handling throughout the
whole patch takes no more than these eight ASM statements.
Unless there is a pressing reason to switch to C, I would prefer to keep
MPP+GPIO inits as they are. C code here would not provide any benefit.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-12 15:02 ` Albert ARIBAUD
@ 2010-04-13 10:33 ` Prafulla Wadaskar
2010-04-13 11:08 ` Albert ARIBAUD
0 siblings, 1 reply; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-04-13 10:33 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Monday, April 12, 2010 8:33 PM
> To: Prafulla Wadaskar
> Cc: Wolfgang Denk; U-Boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
> Marvell Orion5x SoC
>
> (apparently one of Prafulla's answers did not reach me;
> copy-pasting it
> and replying even though it's slightly out of place within the thread)
>
> Prafulla Wadaskar a ?crit :
> >
> >> -----Original Message-----
> >> From: u-boot-bounces at lists.denx.de
> >> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of
> Prafulla Wadaskar
> >> Sent: Friday, April 09, 2010 3:08 PM
> >> To: Albert Aribaud; U-Boot at lists.denx.de
> >> Subject: Re: [U-Boot] [PATCH V6 3/3] Add support for the
> >> LaCie ED Mini V2 board
> >>
> >>
> >>
> >> > -----Original Message-----
> >> > From: u-boot-bounces at lists.denx.de
> >> > [mailto:u-boot-bounces at lists.denx.de] On Behalf Of
> Albert Aribaud
> >> > Sent: Friday, April 09, 2010 1:59 PM
> >> > To: U-Boot at lists.denx.de
> >> > Subject: [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED
> >> > Mini V2 board
> >> >
> >> > This patch adds support for the LaCie ED Mini V2 product
> >> > which is based on the Marvell Orion5x SoC.
> >> > ---
> >> > MAINTAINERS | 4 +
> >> > MAKEALL | 1 +
> >> > Makefile | 3 +
> >> > board/LaCie/edminiv2/Makefile | 58 +++++++++++
> >> > board/LaCie/edminiv2/board_lowlevel_init.S | 59 +++++++++++
> >> > board/LaCie/edminiv2/config.mk | 27 +++++
> >> > board/LaCie/edminiv2/edminiv2.c | 93
> >> ++++++++++++++++++
> >> > board/LaCie/edminiv2/edminiv2.h | 54 ++++++++++
> >> > include/configs/edminiv2.h | 147
> >> > ++++++++++++++++++++++++++++
> >> > 9 files changed, 446 insertions(+), 0 deletions(-)
> >> > create mode 100644 board/LaCie/edminiv2/Makefile
> >> > create mode 100644 board/LaCie/edminiv2/board_lowlevel_init.S
> >> > create mode 100644 board/LaCie/edminiv2/config.mk
> >> > create mode 100644 board/LaCie/edminiv2/edminiv2.c
> >> > create mode 100644 board/LaCie/edminiv2/edminiv2.h
> >> > create mode 100644 include/configs/edminiv2.h
> >> >
> >> ..snip..
> >> > diff --git a/board/LaCie/edminiv2/board_lowlevel_init.S
> >> > b/board/LaCie/edminiv2/board_lowlevel_init.S
> >> > new file mode 100644
> >> > index 0000000..00e68e9
> >> > --- /dev/null
> >> > +++ b/board/LaCie/edminiv2/board_lowlevel_init.S
> >> > @@ -0,0 +1,59 @@
> >> > +/*
> >> > + * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
> >> > + *
> >> > + * (C) Copyright 2009
> >> > + * Marvell Semiconductor <www.marvell.com>
> >> > + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> >> > + *
> >> > + * See file CREDITS for list of people who contributed to this
> >> > + * project.
> >> > + *
> >> > + * This program is free software; you can redistribute it and/or
> >> > + * modify it under the terms of the GNU General Public
> License as
> >> > + * published by the Free Software Foundation; either
> version 2 of
> >> > + * the License, or (at your option) any later version.
> >> > + *
> >> > + * This program is distributed in the hope that it will
> be useful,
> >> > + * but WITHOUT ANY WARRANTY; without even the implied
> warranty of
> >> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> > + * GNU General Public License for more details.
> >> > + *
> >> > + * You should have received a copy of the GNU General
> >> Public License
> >> > + * along with this program; if not, write to the Free Software
> >> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> >> > + * MA 02110-1301 USA
> >> > + */
> >> > +
> >> > +#include "edminiv2.h"
> >> > +
> >> > +/*
> >> > + * Low-level init happens right after start.S has switched
> >> to SVC32,
> >> > + * flushed and disabled caches and disabled MMU. We're
> >> still running
> >> > + * from the boot chip select, so the first thing we should
> >> do is set
> >> > + * up RAM for us to relocate into.
> >> > + *
> >> > + * board_low_level_init is called by the Orion5x
> >> lowlevel_init code,
> >> > + * and sets up board-specifics such as MPPs and GPIOs.
> >> > + */
> >> > +
> >> > +.globl board_lowlevel_init
> >> > +
> >> > +board_lowlevel_init:
> >> > +
> >> > + /* Use R3 as the base for Device Bus registers */
> >> > + add r3, r4, #0x10000
> >> > +
> >> > + /* init MPPs */
> >> > + ldr r6, =EDMINIV2_MPP0_7
> >> > + str r6, [r3, #0x000]
> >> > + ldr r6, =EDMINIV2_MPP8_15
> >> > + str r6, [r3, #0x004]
> >> > + ldr r6, =EDMINIV2_MPP16_23
> >> > + str r6, [r3, #0x050]
> >> > +
> >> > + /* init GPIOs */
> >> > + ldr r6, =EDMINIV2_GPIO_OUT_ENABLE
> >> > + str r6, [r3, #0x104]
> >> > +
> >> > + /* Return to lowlevel_init via saved link register */
> >> > + mov pc, lr
> >>
> >> Dear Albert
> >>
> >> You are just doing mpp and gpio settings here, those are IO
> >> specific only
> >> you can have mpp and gpio configs as in case of Kirkwood (c
> >> functions) and call them from your bard_init.
> >> Please remove this file.
> >> and dependency of this code with lowlevel_init.S in patch 1/2
> >>
> >> That's it.
> >
> > Dear Albert
> >
> > Can you pls do the needfull for above and post V7 for this patch?
>
> I can, but IMO that would doing C code for the sake of C code.
>
> The ED Mini board is a product, not a dev board, and has a completely
> static and predefined MPP and GPIO configuration; there will
> not even be
> an API to modify them from within U-boot (this was discussed
> in earlier
> iterations of the patch) and thus their whole handling throughout the
> whole patch takes no more than these eight ASM statements.
>
> Unless there is a pressing reason to switch to C, I would
> prefer to keep
> MPP+GPIO inits as they are. C code here would not provide any benefit.
This is how C evolved :-)
1. Using C itself is benefit over assembly. Stragically prefer C wherever possible.
2. Converting mpp and gpio init in c function and putting them in board_init completely removes this file. patch becomes simple and smaller.
3. cpu/arm926ejs/orion5x/lowlevel_init.S in patch 1/3 will become independent and simple.
Actually you can pull it to board/LaCie/edminiv2/ since it has DRAM configuration and that is board specific.
I have put this as review comment earlier
It is not necessary to use Assembly here.
Our common objective is to add functional, clean, readable and smaller code to the repository.
I hope you will agree with me.
Regards..
Prafulla . .
>
> Amicalement,
> --
> Albert.
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-13 10:33 ` Prafulla Wadaskar
@ 2010-04-13 11:08 ` Albert ARIBAUD
2010-04-13 13:37 ` Prafulla Wadaskar
0 siblings, 1 reply; 23+ messages in thread
From: Albert ARIBAUD @ 2010-04-13 11:08 UTC (permalink / raw)
To: u-boot
Hi Prafulla,
Prafulla Wadaskar a ?crit :
>
>
>> -----Original Message-----
>> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
>> Sent: Monday, April 12, 2010 8:33 PM
>> To: Prafulla Wadaskar
>> Cc: Wolfgang Denk; U-Boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
>> Marvell Orion5x SoC
>>
>> (apparently one of Prafulla's answers did not reach me;
>> copy-pasting it
>> and replying even though it's slightly out of place within the thread)
>>
>> Prafulla Wadaskar a ?crit :
>>>> -----Original Message-----
>>>> From: u-boot-bounces at lists.denx.de
>>>> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of
>> Prafulla Wadaskar
>>>> Sent: Friday, April 09, 2010 3:08 PM
>>>> To: Albert Aribaud; U-Boot at lists.denx.de
>>>> Subject: Re: [U-Boot] [PATCH V6 3/3] Add support for the
>>>> LaCie ED Mini V2 board
>>>>
>>>>
>>>>
>>>>> -----Original Message-----
>>>>> From: u-boot-bounces at lists.denx.de
>>>>> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of
>> Albert Aribaud
>>>>> Sent: Friday, April 09, 2010 1:59 PM
>>>>> To: U-Boot at lists.denx.de
>>>>> Subject: [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED
>>>>> Mini V2 board
>>>>>
>>>>> This patch adds support for the LaCie ED Mini V2 product
>>>>> which is based on the Marvell Orion5x SoC.
>>>>> ---
>>>>> MAINTAINERS | 4 +
>>>>> MAKEALL | 1 +
>>>>> Makefile | 3 +
>>>>> board/LaCie/edminiv2/Makefile | 58 +++++++++++
>>>>> board/LaCie/edminiv2/board_lowlevel_init.S | 59 +++++++++++
>>>>> board/LaCie/edminiv2/config.mk | 27 +++++
>>>>> board/LaCie/edminiv2/edminiv2.c | 93
>>>> ++++++++++++++++++
>>>>> board/LaCie/edminiv2/edminiv2.h | 54 ++++++++++
>>>>> include/configs/edminiv2.h | 147
>>>>> ++++++++++++++++++++++++++++
>>>>> 9 files changed, 446 insertions(+), 0 deletions(-)
>>>>> create mode 100644 board/LaCie/edminiv2/Makefile
>>>>> create mode 100644 board/LaCie/edminiv2/board_lowlevel_init.S
>>>>> create mode 100644 board/LaCie/edminiv2/config.mk
>>>>> create mode 100644 board/LaCie/edminiv2/edminiv2.c
>>>>> create mode 100644 board/LaCie/edminiv2/edminiv2.h
>>>>> create mode 100644 include/configs/edminiv2.h
>>>>>
>>>> ..snip..
>>>>> diff --git a/board/LaCie/edminiv2/board_lowlevel_init.S
>>>>> b/board/LaCie/edminiv2/board_lowlevel_init.S
>>>>> new file mode 100644
>>>>> index 0000000..00e68e9
>>>>> --- /dev/null
>>>>> +++ b/board/LaCie/edminiv2/board_lowlevel_init.S
>>>>> @@ -0,0 +1,59 @@
>>>>> +/*
>>>>> + * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
>>>>> + *
>>>>> + * (C) Copyright 2009
>>>>> + * Marvell Semiconductor <www.marvell.com>
>>>>> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
>>>>> + *
>>>>> + * See file CREDITS for list of people who contributed to this
>>>>> + * project.
>>>>> + *
>>>>> + * This program is free software; you can redistribute it and/or
>>>>> + * modify it under the terms of the GNU General Public
>> License as
>>>>> + * published by the Free Software Foundation; either
>> version 2 of
>>>>> + * the License, or (at your option) any later version.
>>>>> + *
>>>>> + * This program is distributed in the hope that it will
>> be useful,
>>>>> + * but WITHOUT ANY WARRANTY; without even the implied
>> warranty of
>>>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>>>> + * GNU General Public License for more details.
>>>>> + *
>>>>> + * You should have received a copy of the GNU General
>>>> Public License
>>>>> + * along with this program; if not, write to the Free Software
>>>>> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
>>>>> + * MA 02110-1301 USA
>>>>> + */
>>>>> +
>>>>> +#include "edminiv2.h"
>>>>> +
>>>>> +/*
>>>>> + * Low-level init happens right after start.S has switched
>>>> to SVC32,
>>>>> + * flushed and disabled caches and disabled MMU. We're
>>>> still running
>>>>> + * from the boot chip select, so the first thing we should
>>>> do is set
>>>>> + * up RAM for us to relocate into.
>>>>> + *
>>>>> + * board_low_level_init is called by the Orion5x
>>>> lowlevel_init code,
>>>>> + * and sets up board-specifics such as MPPs and GPIOs.
>>>>> + */
>>>>> +
>>>>> +.globl board_lowlevel_init
>>>>> +
>>>>> +board_lowlevel_init:
>>>>> +
>>>>> + /* Use R3 as the base for Device Bus registers */
>>>>> + add r3, r4, #0x10000
>>>>> +
>>>>> + /* init MPPs */
>>>>> + ldr r6, =EDMINIV2_MPP0_7
>>>>> + str r6, [r3, #0x000]
>>>>> + ldr r6, =EDMINIV2_MPP8_15
>>>>> + str r6, [r3, #0x004]
>>>>> + ldr r6, =EDMINIV2_MPP16_23
>>>>> + str r6, [r3, #0x050]
>>>>> +
>>>>> + /* init GPIOs */
>>>>> + ldr r6, =EDMINIV2_GPIO_OUT_ENABLE
>>>>> + str r6, [r3, #0x104]
>>>>> +
>>>>> + /* Return to lowlevel_init via saved link register */
>>>>> + mov pc, lr
>>>> Dear Albert
>>>>
>>>> You are just doing mpp and gpio settings here, those are IO
>>>> specific only
>>>> you can have mpp and gpio configs as in case of Kirkwood (c
>>>> functions) and call them from your bard_init.
>>>> Please remove this file.
>>>> and dependency of this code with lowlevel_init.S in patch 1/2
>>>>
>>>> That's it.
>>> Dear Albert
>>>
>>> Can you pls do the needfull for above and post V7 for this patch?
>> I can, but IMO that would doing C code for the sake of C code.
>>
>> The ED Mini board is a product, not a dev board, and has a completely
>> static and predefined MPP and GPIO configuration; there will
>> not even be
>> an API to modify them from within U-boot (this was discussed
>> in earlier
>> iterations of the patch) and thus their whole handling throughout the
>> whole patch takes no more than these eight ASM statements.
>>
>> Unless there is a pressing reason to switch to C, I would
>> prefer to keep
>> MPP+GPIO inits as they are. C code here would not provide any benefit.
> This is how C evolved :-)
Hmm... It only did because/when assembly became impractical. :)
> 1. Using C itself is benefit over assembly. Stragically prefer C wherever possible.
> 2. Converting mpp and gpio init in c function and putting them in board_init completely removes this file. patch becomes simple and smaller.
> 3. cpu/arm926ejs/orion5x/lowlevel_init.S in patch 1/3 will become independent and simple.
All right. However:
> Actually you can pull it to board/LaCie/edminiv2/ since it has DRAM configuration and that is board specific.
> I have put this as review comment earlier
And I'd answered it I believe. :) The DRAM-setting code is SoC specific,
not board specific. Even the guidelines are variant-specific, not
board-specific.
> It is not necessary to use Assembly here.
Well there it is necessary, because you can't use a C stack yet for
instance, since you don't have RAM initialized yet.
> Our common objective is to add functional, clean, readable and smaller code to the repository.
>
> I hope you will agree with me.
Partly: the DRAM init part has to stay in asm and in the SoC code I'm
afraid.
> Regards..
> Prafulla . .
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-13 11:08 ` Albert ARIBAUD
@ 2010-04-13 13:37 ` Prafulla Wadaskar
2010-04-13 15:40 ` Albert ARIBAUD
0 siblings, 1 reply; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-04-13 13:37 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Tuesday, April 13, 2010 4:39 PM
> To: Prafulla Wadaskar
> Cc: Wolfgang Denk; U-Boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
> Marvell Orion5x SoC
>
...snip...
> >>>>> +.globl board_lowlevel_init
> >>>>> +
> >>>>> +board_lowlevel_init:
> >>>>> +
> >>>>> + /* Use R3 as the base for Device Bus registers */
> >>>>> + add r3, r4, #0x10000
> >>>>> +
> >>>>> + /* init MPPs */
> >>>>> + ldr r6, =EDMINIV2_MPP0_7
> >>>>> + str r6, [r3, #0x000]
> >>>>> + ldr r6, =EDMINIV2_MPP8_15
> >>>>> + str r6, [r3, #0x004]
> >>>>> + ldr r6, =EDMINIV2_MPP16_23
> >>>>> + str r6, [r3, #0x050]
> >>>>> +
> >>>>> + /* init GPIOs */
> >>>>> + ldr r6, =EDMINIV2_GPIO_OUT_ENABLE
> >>>>> + str r6, [r3, #0x104]
> >>>>> +
> >>>>> + /* Return to lowlevel_init via saved link register */
> >>>>> + mov pc, lr
> >>>> Dear Albert
> >>>>
> >>>> You are just doing mpp and gpio settings here, those are IO
> >>>> specific only
> >>>> you can have mpp and gpio configs as in case of Kirkwood (c
> >>>> functions) and call them from your bard_init.
> >>>> Please remove this file.
> >>>> and dependency of this code with lowlevel_init.S in patch 1/2
> >>>>
> >>>> That's it.
> >>> Dear Albert
> >>>
> >>> Can you pls do the needfull for above and post V7 for this patch?
> >> I can, but IMO that would doing C code for the sake of C code.
> >>
> >> The ED Mini board is a product, not a dev board, and has a
> completely
> >> static and predefined MPP and GPIO configuration; there will
> >> not even be
> >> an API to modify them from within U-boot (this was discussed
> >> in earlier
> >> iterations of the patch) and thus their whole handling
> throughout the
> >> whole patch takes no more than these eight ASM statements.
> >>
> >> Unless there is a pressing reason to switch to C, I would
> >> prefer to keep
> >> MPP+GPIO inits as they are. C code here would not provide
> any benefit.
> > This is how C evolved :-)
>
> Hmm... It only did because/when assembly became impractical. :)
>
> > 1. Using C itself is benefit over assembly. Stragically
> prefer C wherever possible.
> > 2. Converting mpp and gpio init in c function and putting
> them in board_init completely removes this file. patch
> becomes simple and smaller.
> > 3. cpu/arm926ejs/orion5x/lowlevel_init.S in patch 1/3 will
> become independent and simple.
>
> All right. However:
>
> > Actually you can pull it to board/LaCie/edminiv2/ since it
> has DRAM configuration and that is board specific.
> > I have put this as review comment earlier
>
> And I'd answered it I believe. :) The DRAM-setting code is
> SoC specific,
You are right, the code is SoC specific, but the values to be programmed are board specific.
if you are interested,
Look at cpu/arm926ejs/at91/lowlevel_init.s how it programs SMRDATA.
Follow similar arch here too.
-Define similar data segment for holding soc_reg_addr and data array
-Define macros for SOC register addresses in soc specific header file
-Define macros for SOC register values in board specific header file
This way we can retain lowlevel_init.S in soc specific folder, whereas you can pass data through board specific macros.
> not board specific. Even the guidelines are variant-specific, not
> board-specific.
To me:
Type of DRAM used, how it is interfaced, clock speed- all are board specific.
If removed mpp and gpio inits from current file,
Lowlevel_init.S mostly represents DRAM configuration here.
For a particular board we know what static configuration is required. Those should be configured through lowlevel_init.S
I am mapping this with Kirkwood kwbimage.cfg implementation.
>
> > It is not necessary to use Assembly here.
>
> Well there it is necessary, because you can't use a C stack yet for
> instance, since you don't have RAM initialized yet.
That's why lowlevel_init should do basic static initialization in asm (i.e. mostly DRAM configuration)
And other initialization in either arch_cpu_init() or arch_misc_init() or board_init().
>
> > Our common objective is to add functional, clean, readable
> and smaller code to the repository.
> >
> > I hope you will agree with me.
>
> Partly: the DRAM init part has to stay in asm and in the SoC code I'm
> afraid.
Sure,
DRAM init should go in lowlevel_init i.e. asm code, that's need of Orion5X
Either its location or its architecture need to change to address board specific issues.
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-13 13:37 ` Prafulla Wadaskar
@ 2010-04-13 15:40 ` Albert ARIBAUD
2010-04-14 7:42 ` Prafulla Wadaskar
0 siblings, 1 reply; 23+ messages in thread
From: Albert ARIBAUD @ 2010-04-13 15:40 UTC (permalink / raw)
To: u-boot
Prafulla Wadaskar a ?crit :
> You are right, the code is SoC specific, but the values to be programmed are board specific.
>
> if you are interested,
> Look at cpu/arm926ejs/at91/lowlevel_init.s how it programs SMRDATA.
> Follow similar arch here too.
> -Define similar data segment for holding soc_reg_addr and data array
> -Define macros for SOC register addresses in soc specific header file
> -Define macros for SOC register values in board specific header file
> This way we can retain lowlevel_init.S in soc specific folder, whereas you can pass data through board specific macros.
Ok.
> DRAM init should go in lowlevel_init i.e. asm code, that's need of Orion5X
> Either its location or its architecture need to change to address board specific issues.
Agreed.
Now, what about that overall cpu/arch hierarchy change that's been
started? Is there a branch with the new file hierarchi that I should
rebase on, or do I keep the current organization in my patch?
> Regards..
> Prafulla . .
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-13 15:40 ` Albert ARIBAUD
@ 2010-04-14 7:42 ` Prafulla Wadaskar
2010-04-15 6:34 ` Albert ARIBAUD
0 siblings, 1 reply; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-04-14 7:42 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Tuesday, April 13, 2010 9:10 PM
> To: Prafulla Wadaskar
> Cc: Wolfgang Denk; U-Boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
> Marvell Orion5x SoC
>
> Prafulla Wadaskar a ?crit :
>
> > You are right, the code is SoC specific, but the values to
> be programmed are board specific.
> >
> > if you are interested,
> > Look at cpu/arm926ejs/at91/lowlevel_init.s how it programs SMRDATA.
> > Follow similar arch here too.
> > -Define similar data segment for holding soc_reg_addr and data array
> > -Define macros for SOC register addresses in soc specific
> header file
> > -Define macros for SOC register values in board specific header file
> > This way we can retain lowlevel_init.S in soc specific
> folder, whereas you can pass data through board specific macros.
>
> Ok.
>
> > DRAM init should go in lowlevel_init i.e. asm code, that's
> need of Orion5X
> > Either its location or its architecture need to change to
> address board specific issues.
>
> Agreed.
>
> Now, what about that overall cpu/arch hierarchy change that's been
> started? Is there a branch with the new file hierarchi that I should
> rebase on, or do I keep the current organization in my patch?
I am waiting for u-boot-arm.git to get rebased so that I can rebase u-boot-mravell.git
Meanwhile this happens, you can post your patches w.r.to u-boot.git.
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-14 7:42 ` Prafulla Wadaskar
@ 2010-04-15 6:34 ` Albert ARIBAUD
2010-04-29 9:57 ` Prafulla Wadaskar
0 siblings, 1 reply; 23+ messages in thread
From: Albert ARIBAUD @ 2010-04-15 6:34 UTC (permalink / raw)
To: u-boot
Prafulla Wadaskar a ?crit :
>
>
>> -----Original Message-----
>> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
>> Sent: Tuesday, April 13, 2010 9:10 PM
>> To: Prafulla Wadaskar
>> Cc: Wolfgang Denk; U-Boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
>> Marvell Orion5x SoC
>>
>> Prafulla Wadaskar a ?crit :
>>
>>> You are right, the code is SoC specific, but the values to
>> be programmed are board specific.
>>> if you are interested,
>>> Look at cpu/arm926ejs/at91/lowlevel_init.s how it programs SMRDATA.
>>> Follow similar arch here too.
>>> -Define similar data segment for holding soc_reg_addr and data array
>>> -Define macros for SOC register addresses in soc specific
>> header file
>>> -Define macros for SOC register values in board specific header file
>>> This way we can retain lowlevel_init.S in soc specific
>> folder, whereas you can pass data through board specific macros.
>>
>> Ok.
>>
>>> DRAM init should go in lowlevel_init i.e. asm code, that's
>> need of Orion5X
>>> Either its location or its architecture need to change to
>> address board specific issues.
>>
>> Agreed.
>>
>> Now, what about that overall cpu/arch hierarchy change that's been
>> started? Is there a branch with the new file hierarchi that I should
>> rebase on, or do I keep the current organization in my patch?
>
> I am waiting for u-boot-arm.git to get rebased so that I can rebase u-boot-mravell.git
> Meanwhile this happens, you can post your patches w.r.to u-boot.git.
>
> Regards..
> Prafulla . .
Prafulla,
FYI, I will unfortunately be unable to work further on this patch until
next wednesday.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC
2010-04-15 6:34 ` Albert ARIBAUD
@ 2010-04-29 9:57 ` Prafulla Wadaskar
0 siblings, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-04-29 9:57 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Thursday, April 15, 2010 12:05 PM
> To: Prafulla Wadaskar
> Cc: Wolfgang Denk; U-Boot at lists.denx.de; Tom
> Subject: Re: [U-Boot] [PATCH V6 1/3] Initial support for
> Marvell Orion5x SoC
>
...snip...
> > I am waiting for u-boot-arm.git to get rebased so that I
> can rebase u-boot-mravell.git
> > Meanwhile this happens, you can post your patches w.r.to u-boot.git.
> >
> > Regards..
> > Prafulla . .
>
> Prafulla,
>
> FYI, I will unfortunately be unable to work further on this
> patch until
> next wednesday.
Ping
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2010-04-29 9:57 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-04-09 8:29 [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC Albert Aribaud
2010-04-09 8:29 ` [U-Boot] [PATCH V6 2/3] Add Orion5x support to 16550 device driver Albert Aribaud
2010-04-09 8:29 ` [U-Boot] [PATCH V6 3/3] Add support for the LaCie ED Mini V2 board Albert Aribaud
2010-04-09 9:37 ` Prafulla Wadaskar
2010-04-12 11:13 ` Prafulla Wadaskar
2010-04-10 21:16 ` [U-Boot] [PATCH V6 1/3] Initial support for Marvell Orion5x SoC Wolfgang Denk
2010-04-11 7:35 ` Albert ARIBAUD
2010-04-11 7:41 ` Albert ARIBAUD
2010-04-12 8:32 ` Prafulla Wadaskar
2010-04-12 10:42 ` Albert ARIBAUD
2010-04-12 10:45 ` Wolfgang Denk
2010-04-12 11:09 ` Prafulla Wadaskar
2010-04-12 12:00 ` Albert ARIBAUD
2010-04-12 12:41 ` Wolfgang Denk
2010-04-12 15:02 ` Albert ARIBAUD
2010-04-13 10:33 ` Prafulla Wadaskar
2010-04-13 11:08 ` Albert ARIBAUD
2010-04-13 13:37 ` Prafulla Wadaskar
2010-04-13 15:40 ` Albert ARIBAUD
2010-04-14 7:42 ` Prafulla Wadaskar
2010-04-15 6:34 ` Albert ARIBAUD
2010-04-29 9:57 ` Prafulla Wadaskar
2010-04-11 11:56 ` Wolfgang Denk
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