[U-Boot] [PATCH v2 0/9] SMP support for RISC-V

From: Anup Patel <Anup.Patel@wdc.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 0/9] SMP support for RISC-V
Date: Wed, 6 Mar 2019 10:07:42 +0000	[thread overview]
Message-ID: <MN2PR04MB60615039D9B1F40BE40C8B458D730@MN2PR04MB6061.namprd04.prod.outlook.com> (raw)
In-Reply-To: <43f4d91c1ae43e5eea5222ad15c2671a6421866f.camel@aisec.fraunhofer.de>

> -----Original Message-----
> From: Auer, Lukas <lukas.auer@aisec.fraunhofer.de>
> Sent: Wednesday, March 6, 2019 2:52 PM
> To: u-boot at lists.denx.de; Anup Patel <Anup.Patel@wdc.com>
> Cc: paul.walmsley at sifive.com; agraf at suse.de; anup at brainfault.org;
> baruch at tkos.co.il; daniel.schwierzeck at gmail.com; bmeng.cn at gmail.com;
> rick at andestech.com; sr at denx.de; schwab at suse.de; palmer at sifive.com;
> Atish Patra <Atish.Patra@wdc.com>
> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V
> 
> On Wed, 2019-03-06 at 04:00 +0000, Anup Patel wrote:
> > > -----Original Message-----
> > > From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > Sent: Wednesday, March 6, 2019 4:23 AM
> > > To: u-boot at lists.denx.de
> > > Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel
> > > <Anup.Patel@wdc.com>; Bin Meng <bmeng.cn@gmail.com>; Andreas
> Schwab
> > > <schwab@suse.de>; Palmer Dabbelt <palmer@sifive.com>; Alexander
> Graf
> > > <agraf@suse.de>; Lukas Auer <lukas.auer@aisec.fraunhofer.de>; Anup
> > > Patel <Anup.Patel@wdc.com>; Anup Patel <anup@brainfault.org>; Rick
> > > Chen <rick@andestech.com>; Baruch Siach <baruch@tkos.co.il>; Atish
> > > Patra <Atish.Patra@wdc.com> ; Stefan Roese <sr@denx.de>; Paul
> > > Walmsley <paul.walmsley@sifive.com> ; Daniel Schwierzeck
> > > <daniel.schwierzeck@gmail.com>
> > > Subject: [PATCH v2 0/9] SMP support for RISC-V
> > >
> > > This patch series adds SMP support for RISC-V to U-Boot. It allows
> > > U-Boot to run on multi-hart systems (hart is the RISC-V terminology
> > > for hardware thread). Images passed to bootm will be started on all
> > > harts.
> > > The bootm command is currently the only one that will boot images on
> > > all harts, bootefi is not yet supported.
> > >
> > > The patches have been successfully tested on both QEMU (machine and
> > > supervisor mode) and the HiFive Unleashed board (supervisor mode),
> > > using BBL and OpenSBI.
> > > Mainline QEMU requires two patches [1, 2] to run in this
> > > configuration.
> > >
> > > [1]: https://patchwork.ozlabs.org/patch/1039493/
> > > [2]: https://patchwork.ozlabs.org/patch/1039082/
> > >
> > > Changes in v2:
> > > - Remove unneeded quotes from NR_CPUS Kconfig entry
> > > - Move memory barrier from send_ipi_many() to handle_ipi()
> > > - Add check in send_ipi_many so that IPIs are only sent to available
> > > harts as indicated by the available_harts mask
> > > - Implement hart lottery to pick main hart to run U-Boot
> > > - Remove CONFIG_MAIN_HART as it is not required anymore
> > > - Register available harts in the available_harts mask
> > > - New patch to populate register a0 with the hart ID from the
> > > mhartid CSR in machine-mode
> > > - New patch to enable SMP on the SiFive FU540, which was previously
> > > sent independently
> > >
> > > Lukas Auer (9):
> > >   riscv: add infrastructure for calling functions on other harts
> > >   riscv: import the supervisor binary interface header file
> > >   riscv: implement IPI platform functions using SBI
> > >   riscv: delay initialization of caches and debug UART
> > >   riscv: add support for multi-hart systems
> > >   riscv: boot images passed to bootm on all harts
> > >   riscv: do not rely on hart ID passed by previous boot stage
> > >   riscv: fu540: enable SMP
> > >   riscv: qemu: enable SMP
> > >
> > >  arch/riscv/Kconfig                   |  28 +++++
> > >  arch/riscv/cpu/cpu.c                 |   9 +-
> > >  arch/riscv/cpu/start.S               | 152
> > > +++++++++++++++++++++++++--
> > >  arch/riscv/include/asm/csr.h         |   1 +
> > >  arch/riscv/include/asm/global_data.h |   6 ++
> > >  arch/riscv/include/asm/sbi.h         |  94 +++++++++++++++++
> > >  arch/riscv/include/asm/smp.h         |  53 ++++++++++
> > >  arch/riscv/lib/Makefile              |   2 +
> > >  arch/riscv/lib/asm-offsets.c         |   1 +
> > >  arch/riscv/lib/bootm.c               |  13 ++-
> > >  arch/riscv/lib/sbi_ipi.c             |  25 +++++
> > >  arch/riscv/lib/smp.c                 | 116 ++++++++++++++++++++
> > >  board/emulation/qemu-riscv/Kconfig   |   1 +
> > >  board/sifive/fu540/Kconfig           |   1 +
> > >  14 files changed, 492 insertions(+), 10 deletions(-)  create mode
> > > 100644
> > > arch/riscv/include/asm/sbi.h  create mode 100644
> > > arch/riscv/include/asm/smp.h  create mode 100644
> > > arch/riscv/lib/sbi_ipi.c create mode 100644 arch/riscv/lib/smp.c
> > >
> > > --
> > > 2.20.1
> >
> > I tried this series on U-Boot-2019.04-rc3 and works fine on SiFive
> > Unleashed board.
> >
> > Tested-by: Anup Patel <anup.patel@wdc.com>
> >
> > I have also pushed these patches to riscv_sifive_fu540_smp_v4 branch
> > of https://github.com/avpatel/u-boot.git
> >
> 
> Thank you for testing the series, Anup!
> Did you observe anymore issues, where not all harts enter Linux?

I tried using cold-boot (using power-on button) worked fine for me
10 times. I did not try more.

We are trying to make OpenSBI stable with warm-boot (using reset
button) as well but I have not tried that with U-Boot using reset button.

Regards,
Anup

> 
> Thanks,
> Lukas