[U-Boot] [PATCH v2 1/2] board: ge: bx50v3: fix AR8033 reset timing issue

[U-Boot] [PATCH v2 1/2] board: ge: bx50v3: fix AR8033 reset timing issue

[Ken Lin]

Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet

Signed-off-by: Ken Lin <yungching0725@gmail.com>
---
Changes from v1
- Fix the missing Signed-off-by issue

 board/ge/bx50v3/bx50v3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 2fc1144cda..80b4ba1b8b 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8033 PHY */
 	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+	mdelay(1);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
-- 
2.11.0

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Ken Lin]

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: Ken Lin <yungching0725@gmail.com>
---
Changes from v1
- New commit message

 board/ge/bx50v3/bx50v3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 80b4ba1b8b..0acf655c0e 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
 	/* set debug port address: SerDes Test and System Mode Control */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	/* enable rgmii tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+	/* set the reserved bits to avoid board specific voltage peak issue*/
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
 	return 0;
 }
-- 
2.11.0

[U-Boot] [PATCH v2 1/2] board: ge: bx50v3: fix AR8033 reset timing issue

[Stefano Babic]

On 21/02/2017 02:56, Ken Lin wrote:
> Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
> 
> Signed-off-by: Ken Lin <yungching0725@gmail.com>
> ---
> Changes from v1
> - Fix the missing Signed-off-by issue
> 
>  board/ge/bx50v3/bx50v3.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
> index 2fc1144cda..80b4ba1b8b 100644
> --- a/board/ge/bx50v3/bx50v3.c
> +++ b/board/ge/bx50v3/bx50v3.c
> @@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
>  
>  	/* Reset AR8033 PHY */
>  	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
> -	udelay(500);
> +	mdelay(10);
>  	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
> +	mdelay(1);
>  }
>  
>  static iomux_v3_cfg_t const usdhc2_pads[] = {
> 

Reviewed-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

-- 
Meet DENX at the Embedded World Trade Show
14 Mar - 16 Mar 2017, Nuremberg Trade Fair Centre, Hall 4, Booth 581
--
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Stefano Babic]

On 21/02/2017 02:56, Ken Lin wrote:
> Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
> to avoid the voltage peak issue while we do the IEEE PHY comformance test
> 
> Signed-off-by: Ken Lin <yungching0725@gmail.com>
> ---
> Changes from v1
> - New commit message
> 
>  board/ge/bx50v3/bx50v3.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
> index 80b4ba1b8b..0acf655c0e 100644
> --- a/board/ge/bx50v3/bx50v3.c
> +++ b/board/ge/bx50v3/bx50v3.c
> @@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
>  	/* set debug port address: SerDes Test and System Mode Control */
>  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>  	/* enable rgmii tx clock delay */
> -	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +	/* set the reserved bits to avoid board specific voltage peak issue*/
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
>  
>  	return 0;
>  }
> 

Reviewed-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

-- 
Meet DENX at the Embedded World Trade Show
14 Mar - 16 Mar 2017, Nuremberg Trade Fair Centre, Hall 4, Booth 581
--
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Ray, Ian]

On 21/02/2017 17:31, Stefano Babic wrote:
>On 21/02/2017 02:56, Ken Lin wrote:
>> Apply the proper setting for the reserved bits in SetDes Test and System Mode
>Control register
>> to avoid the voltage peak issue while we do the IEEE PHY comformance test
>>
>> Signed-off-by: Ken Lin <yungching0725@gmail.com>
>> ---
>> Changes from v1
>> - New commit message
>>
>>  board/ge/bx50v3/bx50v3.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
>> index 80b4ba1b8b..0acf655c0e 100644
>> --- a/board/ge/bx50v3/bx50v3.c
>> +++ b/board/ge/bx50v3/bx50v3.c
>> @@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
>>       /* set debug port address: SerDes Test and System Mode Control */
>>       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>>       /* enable rgmii tx clock delay */
>> -     phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
>> +     /* set the reserved bits to avoid board specific voltage peak issue*/
>> +     phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
>>
>>       return 0;
>>  }
>>
>
>Reviewed-by: Stefano Babic <sbabic@denx.de>

Acked-by: Ian Ray <ian.ray@ge.com>

...

[U-Boot] [PATCH v2 1/2] board: ge: bx50v3: fix AR8033 reset timing issue

[Ray, Ian]

On 21/02/17 17:31, Stefano Babic wrote:
>On 21/02/2017 02:56, Ken Lin wrote:
>> Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-
>reset(1ms) requirement recommended in the AR8033 datasheet
>>
>> Signed-off-by: Ken Lin <yungching0725@gmail.com>
>> ---
>> Changes from v1
>> - Fix the missing Signed-off-by issue
>>
>>  board/ge/bx50v3/bx50v3.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
>> index 2fc1144cda..80b4ba1b8b 100644
>> --- a/board/ge/bx50v3/bx50v3.c
>> +++ b/board/ge/bx50v3/bx50v3.c
>> @@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
>>
>>       /* Reset AR8033 PHY */
>>       gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
>> -     udelay(500);
>> +     mdelay(10);
>>       gpio_set_value(IMX_GPIO_NR(1, 28), 1);
>> +     mdelay(1);
>>  }
>>
>>  static iomux_v3_cfg_t const usdhc2_pads[] = {
>>
>
>Reviewed-by: Stefano Babic <sbabic@denx.de>

Acked-by: Ian Ray <ian.ray@ge.com>

...

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Joe Hershberger]

Hi Stefano,

On Tue, Mar 21, 2017 at 8:57 AM, Ray, Ian (GE Healthcare)
<ian.ray@ge.com> wrote:
> On 21/02/2017 17:31, Stefano Babic wrote:
>>On 21/02/2017 02:56, Ken Lin wrote:
>>> Apply the proper setting for the reserved bits in SetDes Test and System Mode
>>Control register
>>> to avoid the voltage peak issue while we do the IEEE PHY comformance test
>>>
>>> Signed-off-by: Ken Lin <yungching0725@gmail.com>

Are you wanting to pull this series in or should I?

Thanks,
-Joe

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Stefano Babic]

On 26/03/2017 16:34, Joe Hershberger wrote:
> Hi Stefano,
> 
> On Tue, Mar 21, 2017 at 8:57 AM, Ray, Ian (GE Healthcare)
> <ian.ray@ge.com> wrote:
>> On 21/02/2017 17:31, Stefano Babic wrote:
>>> On 21/02/2017 02:56, Ken Lin wrote:
>>>> Apply the proper setting for the reserved bits in SetDes Test and System Mode
>>> Control register
>>>> to avoid the voltage peak issue while we do the IEEE PHY comformance test
>>>>
>>>> Signed-off-by: Ken Lin <yungching0725@gmail.com>
> 
> Are you wanting to pull this series in or should I?

Just searching the patches, I am just seeing that they are assigned to
you (for that reason I have not pulled). On my side they are fine, you
could pull them.

Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Joe Hershberger]

On Sun, Mar 26, 2017 at 10:41 AM, Stefano Babic <sbabic@denx.de> wrote:
> On 26/03/2017 16:34, Joe Hershberger wrote:
>> Hi Stefano,
>>
>> On Tue, Mar 21, 2017 at 8:57 AM, Ray, Ian (GE Healthcare)
>> <ian.ray@ge.com> wrote:
>>> On 21/02/2017 17:31, Stefano Babic wrote:
>>>> On 21/02/2017 02:56, Ken Lin wrote:
>>>>> Apply the proper setting for the reserved bits in SetDes Test and System Mode
>>>> Control register
>>>>> to avoid the voltage peak issue while we do the IEEE PHY comformance test
>>>>>
>>>>> Signed-off-by: Ken Lin <yungching0725@gmail.com>
>>
>> Are you wanting to pull this series in or should I?
>
> Just searching the patches, I am just seeing that they are assigned to
> you (for that reason I have not pulled). On my side they are fine, you
> could pull them.

Will do.

-Joe

[U-Boot] board: ge: bx50v3: fix AR8033 reset timing issue

[Joe Hershberger]

Hi Yung-Ching,

https://patchwork.ozlabs.org/patch/730331/ was applied to u-boot-net.git.

Thanks!
-Joe

[U-Boot] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Joe Hershberger]

Hi Yung-Ching,

https://patchwork.ozlabs.org/patch/730332/ was applied to u-boot-net.git.

Thanks!
-Joe

[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Ken Lin]

Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: Ken Lin <yungching0725@gmail.com>
---
Changes from v1
- New commit message

 board/ge/bx50v3/bx50v3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 80b4ba1b8b..0acf655c0e 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
 	/* set debug port address: SerDes Test and System Mode Control */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	/* enable rgmii tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+	/* set the reserved bits to avoid board specific voltage peak issue*/
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
 	return 0;
 }
-- 
2.11.0