From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvm@vger.kernel.org, kernel-team@android.com,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
Date: Mon, 29 Nov 2021 16:59:21 +0000 [thread overview]
Message-ID: <YaUG6TtiiIRyzL/y@monolith.localdoman> (raw)
In-Reply-To: <20211126115533.217903-1-maz@kernel.org>
Hi Marc,
Tested on FVP and the nasty splat goes away, so it works for me:
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on
register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the
bit behave as RES0, which is the architectural value for the field when
FEAT_PMUv3p7 is absent. So the patch looks correct to me:
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Thanks,
Alex
On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote:
> When running a KVM guest hosted on an ARMv8.7 machine, the host
> kernel complains that it doesn't know about the architected number
> of events.
>
> Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 +
> arch/arm64/kvm/pmu-emul.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index cdb590840b3f..5de90138d0a4 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -1036,6 +1036,7 @@
> #define ID_AA64DFR0_PMUVER_8_1 0x4
> #define ID_AA64DFR0_PMUVER_8_4 0x5
> #define ID_AA64DFR0_PMUVER_8_5 0x6
> +#define ID_AA64DFR0_PMUVER_8_7 0x7
> #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf
>
> #define ID_AA64DFR0_PMSVER_8_2 0x1
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index a5e4bbf5e68f..ca92cc5c71c6 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
> case ID_AA64DFR0_PMUVER_8_1:
> case ID_AA64DFR0_PMUVER_8_4:
> case ID_AA64DFR0_PMUVER_8_5:
> + case ID_AA64DFR0_PMUVER_8_7:
> return GENMASK(15, 0);
> default: /* Shouldn't be here, just for sanity */
> WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
> --
> 2.30.2
>
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
kernel-team@android.com
Subject: Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
Date: Mon, 29 Nov 2021 16:59:21 +0000 [thread overview]
Message-ID: <YaUG6TtiiIRyzL/y@monolith.localdoman> (raw)
In-Reply-To: <20211126115533.217903-1-maz@kernel.org>
Hi Marc,
Tested on FVP and the nasty splat goes away, so it works for me:
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on
register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the
bit behave as RES0, which is the architectural value for the field when
FEAT_PMUv3p7 is absent. So the patch looks correct to me:
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Thanks,
Alex
On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote:
> When running a KVM guest hosted on an ARMv8.7 machine, the host
> kernel complains that it doesn't know about the architected number
> of events.
>
> Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 +
> arch/arm64/kvm/pmu-emul.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index cdb590840b3f..5de90138d0a4 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -1036,6 +1036,7 @@
> #define ID_AA64DFR0_PMUVER_8_1 0x4
> #define ID_AA64DFR0_PMUVER_8_4 0x5
> #define ID_AA64DFR0_PMUVER_8_5 0x6
> +#define ID_AA64DFR0_PMUVER_8_7 0x7
> #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf
>
> #define ID_AA64DFR0_PMSVER_8_2 0x1
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index a5e4bbf5e68f..ca92cc5c71c6 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
> case ID_AA64DFR0_PMUVER_8_1:
> case ID_AA64DFR0_PMUVER_8_4:
> case ID_AA64DFR0_PMUVER_8_5:
> + case ID_AA64DFR0_PMUVER_8_7:
> return GENMASK(15, 0);
> default: /* Shouldn't be here, just for sanity */
> WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
kernel-team@android.com
Subject: Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU
Date: Mon, 29 Nov 2021 16:59:21 +0000 [thread overview]
Message-ID: <YaUG6TtiiIRyzL/y@monolith.localdoman> (raw)
In-Reply-To: <20211126115533.217903-1-maz@kernel.org>
Hi Marc,
Tested on FVP and the nasty splat goes away, so it works for me:
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on
register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the
bit behave as RES0, which is the architectural value for the field when
FEAT_PMUv3p7 is absent. So the patch looks correct to me:
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Thanks,
Alex
On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote:
> When running a KVM guest hosted on an ARMv8.7 machine, the host
> kernel complains that it doesn't know about the architected number
> of events.
>
> Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 +
> arch/arm64/kvm/pmu-emul.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index cdb590840b3f..5de90138d0a4 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -1036,6 +1036,7 @@
> #define ID_AA64DFR0_PMUVER_8_1 0x4
> #define ID_AA64DFR0_PMUVER_8_4 0x5
> #define ID_AA64DFR0_PMUVER_8_5 0x6
> +#define ID_AA64DFR0_PMUVER_8_7 0x7
> #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf
>
> #define ID_AA64DFR0_PMSVER_8_2 0x1
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index a5e4bbf5e68f..ca92cc5c71c6 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm)
> case ID_AA64DFR0_PMUVER_8_1:
> case ID_AA64DFR0_PMUVER_8_4:
> case ID_AA64DFR0_PMUVER_8_5:
> + case ID_AA64DFR0_PMUVER_8_7:
> return GENMASK(15, 0);
> default: /* Shouldn't be here, just for sanity */
> WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver);
> --
> 2.30.2
>
next prev parent reply other threads:[~2021-11-29 16:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 11:55 [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU Marc Zyngier
2021-11-26 11:55 ` Marc Zyngier
2021-11-26 11:55 ` Marc Zyngier
2021-11-29 16:59 ` Alexandru Elisei [this message]
2021-11-29 16:59 ` Alexandru Elisei
2021-11-29 16:59 ` Alexandru Elisei
2021-12-20 14:00 ` [irqchip: irq/irqchip-next] " irqchip-bot for Marc Zyngier
2021-12-20 14:04 ` Marc Zyngier
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