* [RFC PATCH 00/28] phy: qcom-qmp: split register tables
@ 2022-06-10 19:08 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:08 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
As discussed during sc8280xp PHY review, rework and split QMP register
tables. Create separate files for most of QMP register kinds. The only
things left are various DP registers, which will be handled separately.
Dmitry Baryshkov (28):
phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register
phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table
phy: qcom-qmp-combo,usb: add support for separate PCS_USB region
phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3
phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines
phy: qcom-qmp: rename QMP V2 PCS registers
phy: qcom-qmp: use QPHY_V4_PCS for ipq6018 PCIe gen3
phy: qcom-qmp: move QSERDES registers to separate header
phy: qcom-qmp: move QSERDES V3 registers to separate headers
phy: qcom-qmp: move QSERDES V4 registers to separate headers
phy: qcom-qmp: move QSERDES V5 registers to separate headers
phy: qcom-qmp: move QSERDES PLL registers to separate header
phy: qcom-qmp: move PCS V2 registers to separate header
phy: qcom-qmp: move PCS V3 registers to separate headers
phy: qcom-qmp: move PCS V4 registers to separate headers
phy: qcom-qmp: move PCS V5 registers to separate headers
phy: qcom-qmp: move PCIE QHP registers to separate header
phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers
phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers
phy: qcom-qmp: split PCS_UFS V3 symbols to separate header
phy: qcom-qmp: qserdes-com: add missing registers
phy: qcom-qmp: qserdes-com-v3: add missing registers
phy: qcom-qmp: qserdes-com-v4: add missing registers
phy: qcom-qmp: qserdes-com-v5: add missing registers
phy: qcom-qmp: pcs-v3: add missing registers
phy: qcom-qmp: pcs-pcie-v4: add missing registers
phy: qcom-qmp-usb: replace FLL layout writes for msm8996
phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 57 +-
.../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 34 +-
drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h | 123 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 151 +-
.../phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h | 17 +
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h | 72 +
.../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 17 +
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 16 +
.../qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 17 +
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h | 18 +
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h | 31 +
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 27 +
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h | 34 +
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h | 36 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 46 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 145 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h | 135 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h | 15 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 17 +
.../qualcomm/phy-qcom-qmp-qserdes-com-v3.h | 111 ++
.../qualcomm/phy-qcom-qmp-qserdes-com-v4.h | 123 ++
.../qualcomm/phy-qcom-qmp-qserdes-com-v5.h | 124 ++
.../phy/qualcomm/phy-qcom-qmp-qserdes-com.h | 140 ++
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 66 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h | 68 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h | 233 ++++
.../phy-qcom-qmp-qserdes-txrx-v4_20.h | 43 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h | 231 +++
.../phy-qcom-qmp-qserdes-txrx-v5_20.h | 60 +
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h | 205 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 45 +-
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 153 +-
drivers/phy/qualcomm/phy-qcom-qmp.h | 1242 +----------------
33 files changed, 2430 insertions(+), 1422 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56
prerequisite-patch-id: f52dbc05bf69fb568e419d4b3cc3e3167e66fdce
prerequisite-patch-id: 75325349faf0a5d03169c0e346e219aa6e9e2e34
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prerequisite-patch-id: 329e2ad8ea910d6701adac31e163fe82da56dbb6
prerequisite-patch-id: c1f6035eaf8c420eaa6a4f6f462969e63709ce69
prerequisite-patch-id: 515b2bf64463fc98e3e489b5a6e9569f49678cec
prerequisite-patch-id: a66d720ee35e8a332ac346a913f19a3f4753a6d9
prerequisite-patch-id: e7ece8387072ac18443f60fb01f0c017d8f1dcbd
prerequisite-patch-id: 0d06bd0bc88a369e25e41633676b1357cc698748
prerequisite-patch-id: 10992734e33173d2fca08f18bf73799e202a11f3
prerequisite-patch-id: c9e0cbe235a153a47857fa1b06d618dca8dece94
--
2.35.1
^ permalink raw reply [flat|nested] 60+ messages in thread
* [RFC PATCH 00/28] phy: qcom-qmp: split register tables
@ 2022-06-10 19:08 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:08 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
As discussed during sc8280xp PHY review, rework and split QMP register
tables. Create separate files for most of QMP register kinds. The only
things left are various DP registers, which will be handled separately.
Dmitry Baryshkov (28):
phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register
phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table
phy: qcom-qmp-combo,usb: add support for separate PCS_USB region
phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3
phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines
phy: qcom-qmp: rename QMP V2 PCS registers
phy: qcom-qmp: use QPHY_V4_PCS for ipq6018 PCIe gen3
phy: qcom-qmp: move QSERDES registers to separate header
phy: qcom-qmp: move QSERDES V3 registers to separate headers
phy: qcom-qmp: move QSERDES V4 registers to separate headers
phy: qcom-qmp: move QSERDES V5 registers to separate headers
phy: qcom-qmp: move QSERDES PLL registers to separate header
phy: qcom-qmp: move PCS V2 registers to separate header
phy: qcom-qmp: move PCS V3 registers to separate headers
phy: qcom-qmp: move PCS V4 registers to separate headers
phy: qcom-qmp: move PCS V5 registers to separate headers
phy: qcom-qmp: move PCIE QHP registers to separate header
phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers
phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers
phy: qcom-qmp: split PCS_UFS V3 symbols to separate header
phy: qcom-qmp: qserdes-com: add missing registers
phy: qcom-qmp: qserdes-com-v3: add missing registers
phy: qcom-qmp: qserdes-com-v4: add missing registers
phy: qcom-qmp: qserdes-com-v5: add missing registers
phy: qcom-qmp: pcs-v3: add missing registers
phy: qcom-qmp: pcs-pcie-v4: add missing registers
phy: qcom-qmp-usb: replace FLL layout writes for msm8996
phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 57 +-
.../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 34 +-
drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h | 123 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 151 +-
.../phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h | 17 +
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h | 72 +
.../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 17 +
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 16 +
.../qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 17 +
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h | 18 +
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h | 31 +
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 27 +
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h | 34 +
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h | 36 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 46 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 145 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h | 135 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h | 15 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 17 +
.../qualcomm/phy-qcom-qmp-qserdes-com-v3.h | 111 ++
.../qualcomm/phy-qcom-qmp-qserdes-com-v4.h | 123 ++
.../qualcomm/phy-qcom-qmp-qserdes-com-v5.h | 124 ++
.../phy/qualcomm/phy-qcom-qmp-qserdes-com.h | 140 ++
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 66 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h | 68 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h | 233 ++++
.../phy-qcom-qmp-qserdes-txrx-v4_20.h | 43 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h | 231 +++
.../phy-qcom-qmp-qserdes-txrx-v5_20.h | 60 +
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h | 205 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 45 +-
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 153 +-
drivers/phy/qualcomm/phy-qcom-qmp.h | 1242 +----------------
33 files changed, 2430 insertions(+), 1422 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56
prerequisite-patch-id: f52dbc05bf69fb568e419d4b3cc3e3167e66fdce
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prerequisite-patch-id: 515b2bf64463fc98e3e489b5a6e9569f49678cec
prerequisite-patch-id: a66d720ee35e8a332ac346a913f19a3f4753a6d9
prerequisite-patch-id: e7ece8387072ac18443f60fb01f0c017d8f1dcbd
prerequisite-patch-id: 0d06bd0bc88a369e25e41633676b1357cc698748
prerequisite-patch-id: 10992734e33173d2fca08f18bf73799e202a11f3
prerequisite-patch-id: c9e0cbe235a153a47857fa1b06d618dca8dece94
--
2.35.1
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 60+ messages in thread
* [RFC PATCH 01/28] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:08 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:08 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4.
The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl)
should use the 0x1a0 register, as stated in the downstream dtsi tree.
Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index f4ee5884c076..581f09c71667 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -1116,7 +1116,8 @@
#define QSERDES_V5_COM_CORE_CLK_EN 0x174
#define QSERDES_V5_COM_CMN_CONFIG 0x17c
#define QSERDES_V5_COM_CMN_MISC1 0x19c
-#define QSERDES_V5_COM_CMN_MODE 0x1a4
+#define QSERDES_V5_COM_CMN_MODE 0x1a0
+#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 01/28] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register
@ 2022-06-10 19:08 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:08 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4.
The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl)
should use the 0x1a0 register, as stated in the downstream dtsi tree.
Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index f4ee5884c076..581f09c71667 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -1116,7 +1116,8 @@
#define QSERDES_V5_COM_CORE_CLK_EN 0x174
#define QSERDES_V5_COM_CMN_CONFIG 0x17c
#define QSERDES_V5_COM_CMN_MISC1 0x19c
-#define QSERDES_V5_COM_CMN_MODE 0x1a4
+#define QSERDES_V5_COM_CMN_MODE 0x1a0
+#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 02/28] phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:08 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:08 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
The msm8996_ufs_serdes_tbl table contains write to
QPHY_POWER_DOWN_CONTROL, however this register doesn't belong to the
QSERDES register space. Also the PHY power down is already handled in
the qcom_qmp_phy_ufs_com_init(). Drop this entry completely.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index a2526068232b..83330f7ec64c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -163,7 +163,6 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
};
static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 02/28] phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table
@ 2022-06-10 19:08 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:08 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
The msm8996_ufs_serdes_tbl table contains write to
QPHY_POWER_DOWN_CONTROL, however this register doesn't belong to the
QSERDES register space. Also the PHY power down is already handled in
the qcom_qmp_phy_ufs_com_init(). Drop this entry completely.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index a2526068232b..83330f7ec64c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -163,7 +163,6 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
};
static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 03/28] phy: qcom-qmp-combo,usb: add support for separate PCS_USB region
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Different QMP USB PHYs might have different offset from PCS to PCS_USB
register space, but the same PCS_USB register layout. Add separate
PCS_USB region space and merge related PCS_USB definitions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 47 +++++++--
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 118 ++++++++++++++--------
drivers/phy/qualcomm/phy-qcom-qmp.h | 106 +++++++++----------
3 files changed, 163 insertions(+), 108 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 893b5a4bb554..fd7a9c25f27d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -155,8 +155,10 @@ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = 0x44,
[QPHY_PCS_STATUS] = 0x14,
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
+
+ /* In PCS_USB */
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -451,6 +453,9 @@ static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -520,6 +525,9 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -622,6 +630,8 @@ struct qmp_phy_cfg {
int rx_tbl_num;
const struct qmp_phy_init_tbl *pcs_tbl;
int pcs_tbl_num;
+ const struct qmp_phy_init_tbl *pcs_usb_tbl;
+ int pcs_usb_tbl_num;
/* Init sequence for DP PHY block link rates */
const struct qmp_phy_init_tbl *serdes_tbl_rbr;
@@ -667,6 +677,10 @@ struct qmp_phy_cfg {
bool has_phy_dp_com_ctrl;
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
+
+ /* Offset from PCS to PCS_USB region */
+ unsigned int pcs_usb_offset;
+
};
struct qmp_phy_combo_cfg {
@@ -686,6 +700,7 @@ struct qmp_phy_combo_cfg {
* @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
* @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
* @pcs_misc: iomapped memory space for lane's pcs_misc
+ * @pcs_usb: iomapped memory space for lane's pcs_usb
* @pipe_clk: pipe clock
* @index: lane index
* @qmp: QMP phy to which this lane belongs
@@ -705,6 +720,7 @@ struct qmp_phy {
void __iomem *tx2;
void __iomem *rx2;
void __iomem *pcs_misc;
+ void __iomem *pcs_usb;
struct clk *pipe_clk;
unsigned int index;
struct qcom_qmp *qmp;
@@ -898,6 +914,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
.pcs_tbl = sm8150_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -905,6 +923,7 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -971,6 +990,8 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
.pcs_tbl = sm8250_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -978,6 +999,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1862,7 +1884,7 @@ static int qcom_qmp_phy_combo_set_mode(struct phy *phy,
static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
u32 intr_mask;
@@ -1873,15 +1895,15 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
/* Clear any pending interrupts status */
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
/* Enable required PHY autonomous mode interrupts */
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
/* Enable i/o clamp_n for autonomous mode */
if (pcs_misc)
@@ -1891,19 +1913,19 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
static void qcom_qmp_phy_combo_disable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb;
void __iomem *pcs_misc = qphy->pcs_misc;
/* Disable i/o clamp_n on resume for normal mode */
if (pcs_misc)
qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
}
static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev)
@@ -2323,6 +2345,9 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id
if (!qphy->pcs)
return -ENOMEM;
+ if (cfg->pcs_usb_offset)
+ qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
+
/*
* If this is a dual-lane PHY, then there should be registers for the
* second lane. Some old device trees did not specify this, so fall
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index aebe5ed4e4e3..b1f2f825bd21 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -169,26 +169,10 @@ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = 0x44,
[QPHY_PCS_STATUS] = 0x14,
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-};
-static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_SW_RESET] = 0x00,
- [QPHY_START_CTRL] = 0x44,
- [QPHY_PCS_STATUS] = 0x14,
- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-};
-
-static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_SW_RESET] = 0x00,
- [QPHY_START_CTRL] = 0x44,
- [QPHY_PCS_STATUS] = 0x14,
- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
+ /* In PCS_USB */
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
};
static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -777,6 +761,9 @@ static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -878,8 +865,6 @@ static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
@@ -889,6 +874,11 @@ static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
};
+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+};
+
static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
@@ -954,6 +944,9 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -1015,8 +1008,6 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
@@ -1025,6 +1016,11 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
};
+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+};
+
static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
@@ -1171,8 +1167,6 @@ static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
@@ -1187,6 +1181,11 @@ static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -1244,8 +1243,6 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
@@ -1254,6 +1251,11 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
};
+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+};
+
static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1365,6 +1367,8 @@ struct qmp_phy_cfg {
int rx_tbl_num;
const struct qmp_phy_init_tbl *pcs_tbl;
int pcs_tbl_num;
+ const struct qmp_phy_init_tbl *pcs_usb_tbl;
+ int pcs_usb_tbl_num;
/* clock ids to be requested */
const char * const *clk_list;
@@ -1394,6 +1398,9 @@ struct qmp_phy_cfg {
bool has_phy_dp_com_ctrl;
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
+
+ /* Offset from PCS to PCS_USB region */
+ unsigned int pcs_usb_offset;
};
/**
@@ -1408,6 +1415,7 @@ struct qmp_phy_cfg {
* @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
* @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
* @pcs_misc: iomapped memory space for lane's pcs_misc
+ * @pcs_usb: iomapped memory space for lane's pcs_usb
* @pipe_clk: pipe clock
* @index: lane index
* @qmp: QMP phy to which this lane belongs
@@ -1423,6 +1431,7 @@ struct qmp_phy {
void __iomem *tx2;
void __iomem *rx2;
void __iomem *pcs_misc;
+ void __iomem *pcs_usb;
struct clk *pipe_clk;
unsigned int index;
struct qcom_qmp *qmp;
@@ -1703,6 +1712,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
.pcs_tbl = sm8150_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -1710,6 +1721,7 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1736,13 +1748,16 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = qmp_v4_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x600,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1765,6 +1780,8 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
.pcs_tbl = sm8250_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -1772,6 +1789,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1797,13 +1815,16 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = qmp_v4_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x600,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1826,13 +1847,16 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_sdx55_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = qmp_v4_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x600,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1855,13 +1879,16 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_sdx55_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm8350_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x1000,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1884,6 +1911,8 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
.pcs_tbl = sm8350_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -1891,6 +1920,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1916,13 +1946,16 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm8350_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x1000,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -2244,7 +2277,7 @@ static int qcom_qmp_phy_usb_set_mode(struct phy *phy,
static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
u32 intr_mask;
@@ -2255,15 +2288,15 @@ static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
/* Clear any pending interrupts status */
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
/* Enable required PHY autonomous mode interrupts */
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
/* Enable i/o clamp_n for autonomous mode */
if (pcs_misc)
@@ -2273,19 +2306,19 @@ static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
/* Disable i/o clamp_n on resume for normal mode */
if (pcs_misc)
qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
}
static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev)
@@ -2501,6 +2534,9 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
if (!qphy->pcs)
return -ENOMEM;
+ if (cfg->pcs_usb_offset)
+ qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
+
/*
* If this is a dual-lane PHY, then there should be registers for the
* second lane. Some old device trees did not specify this, so fall
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 581f09c71667..c07227f352b3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -1006,29 +1006,31 @@
#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
-#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
-#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
-#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
-#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
-#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c
-#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
-#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338
-#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c
-#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340
-#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344
-#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348
-#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c
-#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350
-#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354
-#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358
+
+/* Only for QMP V4 PHY - USB3 PCS registers */
+#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
+#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
+#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
+#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
+#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
+#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
+#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
+#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
+#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
@@ -1036,10 +1038,6 @@
#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
-/* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */
-#define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618
-#define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638
-
/* Only for QMP V4 PHY - PCS_MISC registers */
#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
@@ -1290,34 +1288,30 @@
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
-#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
-#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
-#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c
-#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
-#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
-#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c
-#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350
-#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354
-#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358
-#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c
-#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360
-
-/* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */
-#define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018
-#define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c
+#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
+#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
+#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
+#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
+#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
+#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
+#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
+#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
+#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
+#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
+#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 03/28] phy: qcom-qmp-combo,usb: add support for separate PCS_USB region
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Different QMP USB PHYs might have different offset from PCS to PCS_USB
register space, but the same PCS_USB register layout. Add separate
PCS_USB region space and merge related PCS_USB definitions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 47 +++++++--
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 118 ++++++++++++++--------
drivers/phy/qualcomm/phy-qcom-qmp.h | 106 +++++++++----------
3 files changed, 163 insertions(+), 108 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 893b5a4bb554..fd7a9c25f27d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -155,8 +155,10 @@ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = 0x44,
[QPHY_PCS_STATUS] = 0x14,
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
+
+ /* In PCS_USB */
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -451,6 +453,9 @@ static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -520,6 +525,9 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -622,6 +630,8 @@ struct qmp_phy_cfg {
int rx_tbl_num;
const struct qmp_phy_init_tbl *pcs_tbl;
int pcs_tbl_num;
+ const struct qmp_phy_init_tbl *pcs_usb_tbl;
+ int pcs_usb_tbl_num;
/* Init sequence for DP PHY block link rates */
const struct qmp_phy_init_tbl *serdes_tbl_rbr;
@@ -667,6 +677,10 @@ struct qmp_phy_cfg {
bool has_phy_dp_com_ctrl;
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
+
+ /* Offset from PCS to PCS_USB region */
+ unsigned int pcs_usb_offset;
+
};
struct qmp_phy_combo_cfg {
@@ -686,6 +700,7 @@ struct qmp_phy_combo_cfg {
* @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
* @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
* @pcs_misc: iomapped memory space for lane's pcs_misc
+ * @pcs_usb: iomapped memory space for lane's pcs_usb
* @pipe_clk: pipe clock
* @index: lane index
* @qmp: QMP phy to which this lane belongs
@@ -705,6 +720,7 @@ struct qmp_phy {
void __iomem *tx2;
void __iomem *rx2;
void __iomem *pcs_misc;
+ void __iomem *pcs_usb;
struct clk *pipe_clk;
unsigned int index;
struct qcom_qmp *qmp;
@@ -898,6 +914,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
.pcs_tbl = sm8150_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -905,6 +923,7 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -971,6 +990,8 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
.pcs_tbl = sm8250_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -978,6 +999,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1862,7 +1884,7 @@ static int qcom_qmp_phy_combo_set_mode(struct phy *phy,
static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
u32 intr_mask;
@@ -1873,15 +1895,15 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
/* Clear any pending interrupts status */
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
/* Enable required PHY autonomous mode interrupts */
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
/* Enable i/o clamp_n for autonomous mode */
if (pcs_misc)
@@ -1891,19 +1913,19 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
static void qcom_qmp_phy_combo_disable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb;
void __iomem *pcs_misc = qphy->pcs_misc;
/* Disable i/o clamp_n on resume for normal mode */
if (pcs_misc)
qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
}
static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev)
@@ -2323,6 +2345,9 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id
if (!qphy->pcs)
return -ENOMEM;
+ if (cfg->pcs_usb_offset)
+ qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
+
/*
* If this is a dual-lane PHY, then there should be registers for the
* second lane. Some old device trees did not specify this, so fall
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index aebe5ed4e4e3..b1f2f825bd21 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -169,26 +169,10 @@ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = 0x44,
[QPHY_PCS_STATUS] = 0x14,
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-};
-static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_SW_RESET] = 0x00,
- [QPHY_START_CTRL] = 0x44,
- [QPHY_PCS_STATUS] = 0x14,
- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-};
-
-static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_SW_RESET] = 0x00,
- [QPHY_START_CTRL] = 0x44,
- [QPHY_PCS_STATUS] = 0x14,
- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
+ /* In PCS_USB */
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
};
static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -777,6 +761,9 @@ static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -878,8 +865,6 @@ static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
@@ -889,6 +874,11 @@ static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
};
+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+};
+
static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
@@ -954,6 +944,9 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -1015,8 +1008,6 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
@@ -1025,6 +1016,11 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
};
+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+};
+
static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
@@ -1171,8 +1167,6 @@ static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
@@ -1187,6 +1181,11 @@ static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
@@ -1244,8 +1243,6 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
@@ -1254,6 +1251,11 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
};
+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+};
+
static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1365,6 +1367,8 @@ struct qmp_phy_cfg {
int rx_tbl_num;
const struct qmp_phy_init_tbl *pcs_tbl;
int pcs_tbl_num;
+ const struct qmp_phy_init_tbl *pcs_usb_tbl;
+ int pcs_usb_tbl_num;
/* clock ids to be requested */
const char * const *clk_list;
@@ -1394,6 +1398,9 @@ struct qmp_phy_cfg {
bool has_phy_dp_com_ctrl;
/* true, if PHY has secondary tx/rx lanes to be configured */
bool is_dual_lane_phy;
+
+ /* Offset from PCS to PCS_USB region */
+ unsigned int pcs_usb_offset;
};
/**
@@ -1408,6 +1415,7 @@ struct qmp_phy_cfg {
* @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
* @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
* @pcs_misc: iomapped memory space for lane's pcs_misc
+ * @pcs_usb: iomapped memory space for lane's pcs_usb
* @pipe_clk: pipe clock
* @index: lane index
* @qmp: QMP phy to which this lane belongs
@@ -1423,6 +1431,7 @@ struct qmp_phy {
void __iomem *tx2;
void __iomem *rx2;
void __iomem *pcs_misc;
+ void __iomem *pcs_usb;
struct clk *pipe_clk;
unsigned int index;
struct qcom_qmp *qmp;
@@ -1703,6 +1712,8 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
.pcs_tbl = sm8150_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -1710,6 +1721,7 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1736,13 +1748,16 @@ static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = qmp_v4_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x600,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1765,6 +1780,8 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
.pcs_tbl = sm8250_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -1772,6 +1789,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1797,13 +1815,16 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = qmp_v4_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x600,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1826,13 +1847,16 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_sdx55_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = qmp_v4_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x600,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1855,13 +1879,16 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_sdx55_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm8350_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x1000,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1884,6 +1911,8 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
.pcs_tbl = sm8350_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
+ .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
@@ -1891,6 +1920,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x300,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -1916,13 +1946,16 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
.rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
.pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
+ .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
.clk_list = qmp_v4_phy_clk_l,
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
- .regs = sm8350_usb3_uniphy_regs_layout,
+ .regs = qmp_v4_usb3phy_regs_layout,
+ .pcs_usb_offset = 0x1000,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
@@ -2244,7 +2277,7 @@ static int qcom_qmp_phy_usb_set_mode(struct phy *phy,
static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
u32 intr_mask;
@@ -2255,15 +2288,15 @@ static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
/* Clear any pending interrupts status */
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
/* Enable required PHY autonomous mode interrupts */
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
/* Enable i/o clamp_n for autonomous mode */
if (pcs_misc)
@@ -2273,19 +2306,19 @@ static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
/* Disable i/o clamp_n on resume for normal mode */
if (pcs_misc)
qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
/* Writing 1 followed by 0 clears the interrupt */
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
+ qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
}
static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev)
@@ -2501,6 +2534,9 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
if (!qphy->pcs)
return -ENOMEM;
+ if (cfg->pcs_usb_offset)
+ qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
+
/*
* If this is a dual-lane PHY, then there should be registers for the
* second lane. Some old device trees did not specify this, so fall
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 581f09c71667..c07227f352b3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -1006,29 +1006,31 @@
#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
-#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
-#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
-#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
-#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
-#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c
-#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
-#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338
-#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c
-#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340
-#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344
-#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348
-#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c
-#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350
-#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354
-#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358
+
+/* Only for QMP V4 PHY - USB3 PCS registers */
+#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
+#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
+#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
+#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
+#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
+#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
+#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
+#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
+#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
@@ -1036,10 +1038,6 @@
#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
-/* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */
-#define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618
-#define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638
-
/* Only for QMP V4 PHY - PCS_MISC registers */
#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
@@ -1290,34 +1288,30 @@
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
-#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
-#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
-#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c
-#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
-#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
-#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c
-#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350
-#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354
-#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358
-#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c
-#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360
-
-/* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */
-#define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018
-#define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c
+#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
+#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
+#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
+#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
+#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
+#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
+#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
+#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
+#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
+#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
+#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
#endif
--
2.35.1
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 04/28] phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Follow the example of other PCIe PHYs and use separate pcs_misc region
to access PCS_PCIE_* resources.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 32 ++++++++++++------------
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index b2cd0cf965d8..987f0b1d023c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -361,6 +361,9 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
+};
+
+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
@@ -1433,6 +1436,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
.pcs_tbl = ipq6018_pcie_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
+ .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
.clk_list = ipq8074_pciephy_clk_l,
.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
.reset_list = ipq8074_pciephy_reset_l,
@@ -2207,6 +2212,10 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
qphy->pcs_misc = of_iomap(np, 3);
}
+ if (!qphy->pcs_misc &&
+ of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
+ qphy->pcs_misc = qphy->pcs + 0x400;
+
if (!qphy->pcs_misc)
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index c07227f352b3..adb155a45923 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -121,22 +121,22 @@
/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
-#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c
-#define PCS_PCIE_POWER_STATE_CONFIG4 0x414
-#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c
-#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484
-#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490
-#define PCS_PCIE_EQ_CONFIG1 0x4a0
-#define PCS_PCIE_EQ_CONFIG2 0x4a4
-#define PCS_PCIE_PRESET_P10_PRE 0x4bc
-#define PCS_PCIE_PRESET_P10_POST 0x4e0
+#define PCS_PCIE_POWER_STATE_CONFIG2 0x00c
+#define PCS_PCIE_POWER_STATE_CONFIG4 0x014
+#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x040
+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x044
+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x048
+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x04c
+#define PCS_PCIE_OSC_DTCT_CONFIG2 0x05c
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x078
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x080
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
+#define PCS_PCIE_OSC_DTCT_ACTIONS 0x090
+#define PCS_PCIE_EQ_CONFIG1 0x0a0
+#define PCS_PCIE_EQ_CONFIG2 0x0a4
+#define PCS_PCIE_PRESET_P10_PRE 0x0bc
+#define PCS_PCIE_PRESET_P10_POST 0x0e0
/* Only for QMP V2 PHY - QSERDES COM registers */
#define QSERDES_COM_BG_TIMER 0x00c
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 04/28] phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Follow the example of other PCIe PHYs and use separate pcs_misc region
to access PCS_PCIE_* resources.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 32 ++++++++++++------------
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index b2cd0cf965d8..987f0b1d023c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -361,6 +361,9 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
+};
+
+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
@@ -1433,6 +1436,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
.rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
.pcs_tbl = ipq6018_pcie_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
+ .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
.clk_list = ipq8074_pciephy_clk_l,
.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
.reset_list = ipq8074_pciephy_reset_l,
@@ -2207,6 +2212,10 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
qphy->pcs_misc = of_iomap(np, 3);
}
+ if (!qphy->pcs_misc &&
+ of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
+ qphy->pcs_misc = qphy->pcs + 0x400;
+
if (!qphy->pcs_misc)
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index c07227f352b3..adb155a45923 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -121,22 +121,22 @@
/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
-#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c
-#define PCS_PCIE_POWER_STATE_CONFIG4 0x414
-#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c
-#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484
-#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490
-#define PCS_PCIE_EQ_CONFIG1 0x4a0
-#define PCS_PCIE_EQ_CONFIG2 0x4a4
-#define PCS_PCIE_PRESET_P10_PRE 0x4bc
-#define PCS_PCIE_PRESET_P10_POST 0x4e0
+#define PCS_PCIE_POWER_STATE_CONFIG2 0x00c
+#define PCS_PCIE_POWER_STATE_CONFIG4 0x014
+#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x040
+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x044
+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x048
+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x04c
+#define PCS_PCIE_OSC_DTCT_CONFIG2 0x05c
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x078
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x080
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
+#define PCS_PCIE_OSC_DTCT_ACTIONS 0x090
+#define PCS_PCIE_EQ_CONFIG1 0x0a0
+#define PCS_PCIE_EQ_CONFIG2 0x0a4
+#define PCS_PCIE_PRESET_P10_PRE 0x0bc
+#define PCS_PCIE_PRESET_P10_POST 0x0e0
/* Only for QMP V2 PHY - QSERDES COM registers */
#define QSERDES_COM_BG_TIMER 0x00c
--
2.35.1
--
linux-phy mailing list
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 05/28] phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Replace separate defines for QMP V2 PHY for PCIe gen3 ports. They are
equivalent to the QSERDES_V4_ symbols.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 66 ++++++++++++------------
drivers/phy/qualcomm/phy-qcom-qmp.h | 40 --------------
2 files changed, 33 insertions(+), 73 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 987f0b1d023c..5e984ad3d3a1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -315,42 +315,42 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
};
static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
};
static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
};
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index adb155a45923..6cb660455088 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -64,46 +64,6 @@
#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
-/* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */
-
-#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c
-#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058
-#define QSERDES_TX0_LANE_MODE_1 0x084
-#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c
-
-/* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */
-
-#define QSERDES_RX0_UCDR_FO_GAIN 0x008
-#define QSERDES_RX0_UCDR_SO_GAIN 0x014
-#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034
-#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044
-#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec
-#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0
-#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4
-#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8
-#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc
-#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
-#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114
-#define QSERDES_RX0_SIGDET_ENABLES 0x118
-#define QSERDES_RX0_SIGDET_CNTRL 0x11c
-#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124
-#define QSERDES_RX0_RX_MODE_00_LOW 0x170
-#define QSERDES_RX0_RX_MODE_00_HIGH 0x174
-#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178
-#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c
-#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180
-#define QSERDES_RX0_RX_MODE_01_LOW 0x184
-#define QSERDES_RX0_RX_MODE_01_HIGH 0x188
-#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c
-#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190
-#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194
-#define QSERDES_RX0_RX_MODE_10_LOW 0x198
-#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c
-#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0
-#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4
-#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8
-#define QSERDES_RX0_DFE_EN_TIMER 0x1b4
-
/* QMP V2 PHY for PCIE gen3 ports - PCS registers */
#define PCS_COM_FLL_CNTRL1 0x098
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 05/28] phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Replace separate defines for QMP V2 PHY for PCIe gen3 ports. They are
equivalent to the QSERDES_V4_ symbols.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 66 ++++++++++++------------
drivers/phy/qualcomm/phy-qcom-qmp.h | 40 --------------
2 files changed, 33 insertions(+), 73 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 987f0b1d023c..5e984ad3d3a1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -315,42 +315,42 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
};
static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
};
static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
};
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index adb155a45923..6cb660455088 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -64,46 +64,6 @@
#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
-/* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */
-
-#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c
-#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058
-#define QSERDES_TX0_LANE_MODE_1 0x084
-#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c
-
-/* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */
-
-#define QSERDES_RX0_UCDR_FO_GAIN 0x008
-#define QSERDES_RX0_UCDR_SO_GAIN 0x014
-#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034
-#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044
-#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec
-#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0
-#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4
-#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8
-#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc
-#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
-#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114
-#define QSERDES_RX0_SIGDET_ENABLES 0x118
-#define QSERDES_RX0_SIGDET_CNTRL 0x11c
-#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124
-#define QSERDES_RX0_RX_MODE_00_LOW 0x170
-#define QSERDES_RX0_RX_MODE_00_HIGH 0x174
-#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178
-#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c
-#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180
-#define QSERDES_RX0_RX_MODE_01_LOW 0x184
-#define QSERDES_RX0_RX_MODE_01_HIGH 0x188
-#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c
-#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190
-#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194
-#define QSERDES_RX0_RX_MODE_10_LOW 0x198
-#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c
-#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0
-#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4
-#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8
-#define QSERDES_RX0_DFE_EN_TIMER 0x1b4
-
/* QMP V2 PHY for PCIE gen3 ports - PCS registers */
#define PCS_COM_FLL_CNTRL1 0x098
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 06/28] phy: qcom-qmp: rename QMP V2 PCS registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Rename QMP V2 PCS registers to follow the usual pattern of
QPHY_V2_PCS_*.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 4 +-
.../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 20 +++----
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 26 ++++-----
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 ++++----
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 12 ++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 54 +++++++++----------
6 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index fd7a9c25f27d..2335658affdb 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -1667,7 +1667,7 @@ static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy)
cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
mutex_unlock(&qmp->phy_mutex);
@@ -1829,7 +1829,7 @@ static int qcom_qmp_phy_combo_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 21103c41ba08..90a4bb8e86a4 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -222,17 +222,17 @@ static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
};
struct qmp_phy;
@@ -637,7 +637,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
* Pull out PHY from POWER DOWN state.
* This is active low enable signal to power-down PHY.
*/
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
if (cfg->has_pwrdn_delay)
usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
@@ -687,7 +687,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 5e984ad3d3a1..161be7a94acc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -438,17 +438,17 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
};
@@ -1824,7 +1824,7 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy)
cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
return 0;
@@ -1933,7 +1933,7 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
* Pull out PHY from POWER DOWN state.
* This is active low enable signal to power-down PHY.
*/
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
if (cfg->has_pwrdn_delay)
usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
@@ -1981,7 +1981,7 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 83330f7ec64c..bfe5f562bcd0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -310,15 +310,15 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SYM_RESYNC_CTRL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
};
static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
@@ -941,7 +941,7 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy)
cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
return 0;
@@ -1083,7 +1083,7 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index b1f2f825bd21..fd169daffb02 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -325,10 +325,10 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
/* Lock Det settings */
- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -2095,7 +2095,7 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
return 0;
@@ -2223,7 +2223,7 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 6cb660455088..64af9720b3f9 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -208,33 +208,33 @@
#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
/* Only for QMP V2 PHY - PCS registers */
-#define QPHY_POWER_DOWN_CONTROL 0x04
-#define QPHY_TXDEEMPH_M6DB_V0 0x24
-#define QPHY_TXDEEMPH_M3P5DB_V0 0x28
-#define QPHY_TX_LARGE_AMP_DRV_LVL 0x34
-#define QPHY_TX_LARGE_AMP_POST_EMP_LVL 0x38
-#define QPHY_TX_SMALL_AMP_DRV_LVL 0x3c
-#define QPHY_TX_SMALL_AMP_POST_EMP_LVL 0x40
-#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
-#define QPHY_RX_IDLE_DTCT_CNTRL 0x58
-#define QPHY_POWER_STATE_CONFIG1 0x60
-#define QPHY_POWER_STATE_CONFIG2 0x64
-#define QPHY_POWER_STATE_CONFIG4 0x6c
-#define QPHY_LOCK_DETECT_CONFIG1 0x80
-#define QPHY_LOCK_DETECT_CONFIG2 0x84
-#define QPHY_LOCK_DETECT_CONFIG3 0x88
-#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
-#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
-#define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
-#define QPHY_RX_SYM_RESYNC_CTRL 0x13c
-#define QPHY_RX_MIN_HIBERN8_TIME 0x140
-#define QPHY_RX_SIGDET_CTRL2 0x148
-#define QPHY_RX_PWM_GEAR_BAND 0x154
-#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
-#define QPHY_OSC_DTCT_ACTIONS 0x1ac
-#define QPHY_RX_SIGDET_LVL 0x1d8
-#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
-#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
+#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24
+#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28
+#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34
+#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38
+#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c
+#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40
+#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54
+#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58
+#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60
+#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64
+#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88
+#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
+#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
+#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
+#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
+#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
+#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
+#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
+#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
+#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 06/28] phy: qcom-qmp: rename QMP V2 PCS registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Rename QMP V2 PCS registers to follow the usual pattern of
QPHY_V2_PCS_*.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 4 +-
.../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 20 +++----
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 26 ++++-----
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 ++++----
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 12 ++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 54 +++++++++----------
6 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index fd7a9c25f27d..2335658affdb 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -1667,7 +1667,7 @@ static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy)
cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
mutex_unlock(&qmp->phy_mutex);
@@ -1829,7 +1829,7 @@ static int qcom_qmp_phy_combo_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 21103c41ba08..90a4bb8e86a4 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -222,17 +222,17 @@ static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
};
struct qmp_phy;
@@ -637,7 +637,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
* Pull out PHY from POWER DOWN state.
* This is active low enable signal to power-down PHY.
*/
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
if (cfg->has_pwrdn_delay)
usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
@@ -687,7 +687,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 5e984ad3d3a1..161be7a94acc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -438,17 +438,17 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
};
@@ -1824,7 +1824,7 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy)
cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
return 0;
@@ -1933,7 +1933,7 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
* Pull out PHY from POWER DOWN state.
* This is active low enable signal to power-down PHY.
*/
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
if (cfg->has_pwrdn_delay)
usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
@@ -1981,7 +1981,7 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 83330f7ec64c..bfe5f562bcd0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -310,15 +310,15 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SYM_RESYNC_CTRL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
};
static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
@@ -941,7 +941,7 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy)
cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
return 0;
@@ -1083,7 +1083,7 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index b1f2f825bd21..fd169daffb02 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -325,10 +325,10 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
/* Lock Det settings */
- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -2095,7 +2095,7 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
return 0;
@@ -2223,7 +2223,7 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
} else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
cfg->pwrdn_ctrl);
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 6cb660455088..64af9720b3f9 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -208,33 +208,33 @@
#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
/* Only for QMP V2 PHY - PCS registers */
-#define QPHY_POWER_DOWN_CONTROL 0x04
-#define QPHY_TXDEEMPH_M6DB_V0 0x24
-#define QPHY_TXDEEMPH_M3P5DB_V0 0x28
-#define QPHY_TX_LARGE_AMP_DRV_LVL 0x34
-#define QPHY_TX_LARGE_AMP_POST_EMP_LVL 0x38
-#define QPHY_TX_SMALL_AMP_DRV_LVL 0x3c
-#define QPHY_TX_SMALL_AMP_POST_EMP_LVL 0x40
-#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
-#define QPHY_RX_IDLE_DTCT_CNTRL 0x58
-#define QPHY_POWER_STATE_CONFIG1 0x60
-#define QPHY_POWER_STATE_CONFIG2 0x64
-#define QPHY_POWER_STATE_CONFIG4 0x6c
-#define QPHY_LOCK_DETECT_CONFIG1 0x80
-#define QPHY_LOCK_DETECT_CONFIG2 0x84
-#define QPHY_LOCK_DETECT_CONFIG3 0x88
-#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
-#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
-#define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
-#define QPHY_RX_SYM_RESYNC_CTRL 0x13c
-#define QPHY_RX_MIN_HIBERN8_TIME 0x140
-#define QPHY_RX_SIGDET_CTRL2 0x148
-#define QPHY_RX_PWM_GEAR_BAND 0x154
-#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
-#define QPHY_OSC_DTCT_ACTIONS 0x1ac
-#define QPHY_RX_SIGDET_LVL 0x1d8
-#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
-#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
+#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24
+#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28
+#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34
+#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38
+#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c
+#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40
+#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54
+#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58
+#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60
+#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64
+#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88
+#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
+#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
+#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
+#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
+#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
+#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
+#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
+#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
+#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 07/28] phy: qcom-qmp: use QPHY_V4_PCS for ipq6018 PCIe gen3
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
PCS_COM_* symbols duplicate the QPHY_V4_PCS_*. PCS_PCIE_* symbols
duplicate the QPHY_V4_PCS_PCIE_*. Use generic register names for the
IPQ6018 tables and drop the custom PCS_COM_*/PCS_PCIE* names.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 +++++++++++-----------
drivers/phy/qualcomm/phy-qcom-qmp.h | 35 +-----------------------
2 files changed, 17 insertions(+), 50 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 161be7a94acc..2992ef6603f3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -354,25 +354,25 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
};
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
};
static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 64af9720b3f9..b2aeace96c09 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -64,40 +64,6 @@
#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
-/* QMP V2 PHY for PCIE gen3 ports - PCS registers */
-
-#define PCS_COM_FLL_CNTRL1 0x098
-#define PCS_COM_FLL_CNTRL2 0x09c
-#define PCS_COM_FLL_CNT_VAL_L 0x0a0
-#define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4
-#define PCS_COM_FLL_MAN_CODE 0x0a8
-#define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc
-#define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c
-#define PCS_COM_RX_SIGDET_LVL 0x188
-#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
-#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
-#define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8
-#define PCS_COM_EQ_CONFIG5 0x1ec
-
-/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
-
-#define PCS_PCIE_POWER_STATE_CONFIG2 0x00c
-#define PCS_PCIE_POWER_STATE_CONFIG4 0x014
-#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x040
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x044
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x048
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x04c
-#define PCS_PCIE_OSC_DTCT_CONFIG2 0x05c
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x078
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x080
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
-#define PCS_PCIE_OSC_DTCT_ACTIONS 0x090
-#define PCS_PCIE_EQ_CONFIG1 0x0a0
-#define PCS_PCIE_EQ_CONFIG2 0x0a4
-#define PCS_PCIE_PRESET_P10_PRE 0x0bc
-#define PCS_PCIE_PRESET_P10_POST 0x0e0
-
/* Only for QMP V2 PHY - QSERDES COM registers */
#define QSERDES_COM_BG_TIMER 0x00c
#define QSERDES_COM_SSC_EN_CENTER 0x010
@@ -1014,6 +980,7 @@
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
+#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 07/28] phy: qcom-qmp: use QPHY_V4_PCS for ipq6018 PCIe gen3
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
PCS_COM_* symbols duplicate the QPHY_V4_PCS_*. PCS_PCIE_* symbols
duplicate the QPHY_V4_PCS_PCIE_*. Use generic register names for the
IPQ6018 tables and drop the custom PCS_COM_*/PCS_PCIE* names.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 +++++++++++-----------
drivers/phy/qualcomm/phy-qcom-qmp.h | 35 +-----------------------
2 files changed, 17 insertions(+), 50 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 161be7a94acc..2992ef6603f3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -354,25 +354,25 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
};
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
};
static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 64af9720b3f9..b2aeace96c09 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -64,40 +64,6 @@
#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
-/* QMP V2 PHY for PCIE gen3 ports - PCS registers */
-
-#define PCS_COM_FLL_CNTRL1 0x098
-#define PCS_COM_FLL_CNTRL2 0x09c
-#define PCS_COM_FLL_CNT_VAL_L 0x0a0
-#define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4
-#define PCS_COM_FLL_MAN_CODE 0x0a8
-#define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc
-#define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c
-#define PCS_COM_RX_SIGDET_LVL 0x188
-#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
-#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
-#define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8
-#define PCS_COM_EQ_CONFIG5 0x1ec
-
-/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
-
-#define PCS_PCIE_POWER_STATE_CONFIG2 0x00c
-#define PCS_PCIE_POWER_STATE_CONFIG4 0x014
-#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x040
-#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x044
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x048
-#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x04c
-#define PCS_PCIE_OSC_DTCT_CONFIG2 0x05c
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x078
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x080
-#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
-#define PCS_PCIE_OSC_DTCT_ACTIONS 0x090
-#define PCS_PCIE_EQ_CONFIG1 0x0a0
-#define PCS_PCIE_EQ_CONFIG2 0x0a4
-#define PCS_PCIE_PRESET_P10_PRE 0x0bc
-#define PCS_PCIE_PRESET_P10_POST 0x0e0
-
/* Only for QMP V2 PHY - QSERDES COM registers */
#define QSERDES_COM_BG_TIMER 0x00c
#define QSERDES_COM_SSC_EN_CENTER 0x010
@@ -1014,6 +980,7 @@
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
+#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 08/28] phy: qcom-qmp: move QSERDES registers to separate header
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES V2 registers to the separate header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-qserdes-com.h | 83 +++++++++++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h | 44 +++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 112 +-----------------
3 files changed, 130 insertions(+), 109 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
new file mode 100644
index 000000000000..9dfa80263707
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_H_
+#define QCOM_PHY_QMP_QSERDES_COM_H_
+
+/* Only for QMP V2 PHY - QSERDES COM registers */
+#define QSERDES_COM_BG_TIMER 0x00c
+#define QSERDES_COM_SSC_EN_CENTER 0x010
+#define QSERDES_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_COM_SSC_ADJ_PER2 0x018
+#define QSERDES_COM_SSC_PER1 0x01c
+#define QSERDES_COM_SSC_PER2 0x020
+#define QSERDES_COM_SSC_STEP_SIZE1 0x024
+#define QSERDES_COM_SSC_STEP_SIZE2 0x028
+#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
+#define QSERDES_COM_CLK_ENABLE1 0x038
+#define QSERDES_COM_SYS_CLK_CTRL 0x03c
+#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
+#define QSERDES_COM_PLL_IVCO 0x048
+#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
+#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
+#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
+#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
+#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
+#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
+#define QSERDES_COM_BG_TRIM 0x070
+#define QSERDES_COM_CLK_EP_DIV 0x074
+#define QSERDES_COM_CP_CTRL_MODE0 0x078
+#define QSERDES_COM_CP_CTRL_MODE1 0x07c
+#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
+#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
+#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
+#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
+#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
+#define QSERDES_COM_RESETSM_CNTRL 0x0b4
+#define QSERDES_COM_RESETSM_CNTRL2 0x0b8
+#define QSERDES_COM_RESTRIM_CTRL 0x0bc
+#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
+#define QSERDES_COM_LOCK_CMP_EN 0x0c8
+#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
+#define QSERDES_COM_DEC_START_MODE0 0x0d0
+#define QSERDES_COM_DEC_START_MODE1 0x0d4
+#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
+#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
+#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
+#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
+#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
+#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
+#define QSERDES_COM_INTEGLOOP_INITVAL 0x100
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
+#define QSERDES_COM_VCO_TUNE_CTRL 0x124
+#define QSERDES_COM_VCO_TUNE_MAP 0x128
+#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
+#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
+#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
+#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
+#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
+#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
+#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
+#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
+#define QSERDES_COM_BG_CTRL 0x170
+#define QSERDES_COM_CLK_SELECT 0x174
+#define QSERDES_COM_HSCLK_SEL 0x178
+#define QSERDES_COM_CORECLK_DIV 0x184
+#define QSERDES_COM_CORE_CLK_EN 0x18c
+#define QSERDES_COM_C_READY_STATUS 0x190
+#define QSERDES_COM_CMN_CONFIG 0x194
+#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
+#define QSERDES_COM_DEBUG_BUS0 0x1a0
+#define QSERDES_COM_DEBUG_BUS1 0x1a4
+#define QSERDES_COM_DEBUG_BUS2 0x1a8
+#define QSERDES_COM_DEBUG_BUS3 0x1ac
+#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
+#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
new file mode 100644
index 000000000000..583098a88b65
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_H_
+
+/* Only for QMP V2 PHY - TX registers */
+#define QSERDES_TX_EMP_POST1_LVL 0x018
+#define QSERDES_TX_SLEW_CNTL 0x040
+#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
+#define QSERDES_TX_DEBUG_BUS_SEL 0x064
+#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
+#define QSERDES_TX_LANE_MODE 0x094
+#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
+
+/* Only for QMP V2 PHY - RX registers */
+#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
+#define QSERDES_RX_UCDR_SO_GAIN 0x01c
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
+#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
+#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
+#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
+#define QSERDES_RX_RX_TERM_BW 0x090
+#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
+#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
+#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
+#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
+#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
+#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
+#define QSERDES_RX_SIGDET_ENABLES 0x110
+#define QSERDES_RX_SIGDET_CNTRL 0x114
+#define QSERDES_RX_SIGDET_LVL 0x118
+#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
+#define QSERDES_RX_RX_BAND 0x120
+#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index b2aeace96c09..6a24d61098e7 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -6,6 +6,9 @@
#ifndef QCOM_PHY_QMP_H_
#define QCOM_PHY_QMP_H_
+#include "phy-qcom-qmp-qserdes-com.h"
+#include "phy-qcom-qmp-qserdes-txrx.h"
+
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
@@ -64,115 +67,6 @@
#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
-/* Only for QMP V2 PHY - QSERDES COM registers */
-#define QSERDES_COM_BG_TIMER 0x00c
-#define QSERDES_COM_SSC_EN_CENTER 0x010
-#define QSERDES_COM_SSC_ADJ_PER1 0x014
-#define QSERDES_COM_SSC_ADJ_PER2 0x018
-#define QSERDES_COM_SSC_PER1 0x01c
-#define QSERDES_COM_SSC_PER2 0x020
-#define QSERDES_COM_SSC_STEP_SIZE1 0x024
-#define QSERDES_COM_SSC_STEP_SIZE2 0x028
-#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
-#define QSERDES_COM_CLK_ENABLE1 0x038
-#define QSERDES_COM_SYS_CLK_CTRL 0x03c
-#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
-#define QSERDES_COM_PLL_IVCO 0x048
-#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
-#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
-#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
-#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
-#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
-#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
-#define QSERDES_COM_BG_TRIM 0x070
-#define QSERDES_COM_CLK_EP_DIV 0x074
-#define QSERDES_COM_CP_CTRL_MODE0 0x078
-#define QSERDES_COM_CP_CTRL_MODE1 0x07c
-#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
-#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
-#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
-#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
-#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
-#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
-#define QSERDES_COM_RESETSM_CNTRL 0x0b4
-#define QSERDES_COM_RESETSM_CNTRL2 0x0b8
-#define QSERDES_COM_RESTRIM_CTRL 0x0bc
-#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
-#define QSERDES_COM_LOCK_CMP_EN 0x0c8
-#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
-#define QSERDES_COM_DEC_START_MODE0 0x0d0
-#define QSERDES_COM_DEC_START_MODE1 0x0d4
-#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
-#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
-#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
-#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
-#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
-#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
-#define QSERDES_COM_INTEGLOOP_INITVAL 0x100
-#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
-#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
-#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
-#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
-#define QSERDES_COM_VCO_TUNE_CTRL 0x124
-#define QSERDES_COM_VCO_TUNE_MAP 0x128
-#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
-#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
-#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
-#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
-#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
-#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
-#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
-#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
-#define QSERDES_COM_BG_CTRL 0x170
-#define QSERDES_COM_CLK_SELECT 0x174
-#define QSERDES_COM_HSCLK_SEL 0x178
-#define QSERDES_COM_CORECLK_DIV 0x184
-#define QSERDES_COM_CORE_CLK_EN 0x18c
-#define QSERDES_COM_C_READY_STATUS 0x190
-#define QSERDES_COM_CMN_CONFIG 0x194
-#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
-#define QSERDES_COM_DEBUG_BUS0 0x1a0
-#define QSERDES_COM_DEBUG_BUS1 0x1a4
-#define QSERDES_COM_DEBUG_BUS2 0x1a8
-#define QSERDES_COM_DEBUG_BUS3 0x1ac
-#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
-#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
-
-/* Only for QMP V2 PHY - TX registers */
-#define QSERDES_TX_EMP_POST1_LVL 0x018
-#define QSERDES_TX_SLEW_CNTL 0x040
-#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
-#define QSERDES_TX_DEBUG_BUS_SEL 0x064
-#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
-#define QSERDES_TX_LANE_MODE 0x094
-#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
-
-/* Only for QMP V2 PHY - RX registers */
-#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
-#define QSERDES_RX_UCDR_SO_GAIN 0x01c
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
-#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
-#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
-#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
-#define QSERDES_RX_RX_TERM_BW 0x090
-#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
-#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
-#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
-#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
-#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
-#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
-#define QSERDES_RX_SIGDET_ENABLES 0x110
-#define QSERDES_RX_SIGDET_CNTRL 0x114
-#define QSERDES_RX_SIGDET_LVL 0x118
-#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
-#define QSERDES_RX_RX_BAND 0x120
-#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
-
/* Only for QMP V2 PHY - PCS registers */
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 08/28] phy: qcom-qmp: move QSERDES registers to separate header
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES V2 registers to the separate header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-qserdes-com.h | 83 +++++++++++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h | 44 +++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 112 +-----------------
3 files changed, 130 insertions(+), 109 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
new file mode 100644
index 000000000000..9dfa80263707
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_H_
+#define QCOM_PHY_QMP_QSERDES_COM_H_
+
+/* Only for QMP V2 PHY - QSERDES COM registers */
+#define QSERDES_COM_BG_TIMER 0x00c
+#define QSERDES_COM_SSC_EN_CENTER 0x010
+#define QSERDES_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_COM_SSC_ADJ_PER2 0x018
+#define QSERDES_COM_SSC_PER1 0x01c
+#define QSERDES_COM_SSC_PER2 0x020
+#define QSERDES_COM_SSC_STEP_SIZE1 0x024
+#define QSERDES_COM_SSC_STEP_SIZE2 0x028
+#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
+#define QSERDES_COM_CLK_ENABLE1 0x038
+#define QSERDES_COM_SYS_CLK_CTRL 0x03c
+#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
+#define QSERDES_COM_PLL_IVCO 0x048
+#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
+#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
+#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
+#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
+#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
+#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
+#define QSERDES_COM_BG_TRIM 0x070
+#define QSERDES_COM_CLK_EP_DIV 0x074
+#define QSERDES_COM_CP_CTRL_MODE0 0x078
+#define QSERDES_COM_CP_CTRL_MODE1 0x07c
+#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
+#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
+#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
+#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
+#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
+#define QSERDES_COM_RESETSM_CNTRL 0x0b4
+#define QSERDES_COM_RESETSM_CNTRL2 0x0b8
+#define QSERDES_COM_RESTRIM_CTRL 0x0bc
+#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
+#define QSERDES_COM_LOCK_CMP_EN 0x0c8
+#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
+#define QSERDES_COM_DEC_START_MODE0 0x0d0
+#define QSERDES_COM_DEC_START_MODE1 0x0d4
+#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
+#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
+#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
+#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
+#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
+#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
+#define QSERDES_COM_INTEGLOOP_INITVAL 0x100
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
+#define QSERDES_COM_VCO_TUNE_CTRL 0x124
+#define QSERDES_COM_VCO_TUNE_MAP 0x128
+#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
+#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
+#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
+#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
+#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
+#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
+#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
+#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
+#define QSERDES_COM_BG_CTRL 0x170
+#define QSERDES_COM_CLK_SELECT 0x174
+#define QSERDES_COM_HSCLK_SEL 0x178
+#define QSERDES_COM_CORECLK_DIV 0x184
+#define QSERDES_COM_CORE_CLK_EN 0x18c
+#define QSERDES_COM_C_READY_STATUS 0x190
+#define QSERDES_COM_CMN_CONFIG 0x194
+#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
+#define QSERDES_COM_DEBUG_BUS0 0x1a0
+#define QSERDES_COM_DEBUG_BUS1 0x1a4
+#define QSERDES_COM_DEBUG_BUS2 0x1a8
+#define QSERDES_COM_DEBUG_BUS3 0x1ac
+#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
+#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
new file mode 100644
index 000000000000..583098a88b65
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_H_
+
+/* Only for QMP V2 PHY - TX registers */
+#define QSERDES_TX_EMP_POST1_LVL 0x018
+#define QSERDES_TX_SLEW_CNTL 0x040
+#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
+#define QSERDES_TX_DEBUG_BUS_SEL 0x064
+#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
+#define QSERDES_TX_LANE_MODE 0x094
+#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
+
+/* Only for QMP V2 PHY - RX registers */
+#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
+#define QSERDES_RX_UCDR_SO_GAIN 0x01c
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
+#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
+#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
+#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
+#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
+#define QSERDES_RX_RX_TERM_BW 0x090
+#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
+#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
+#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
+#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
+#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
+#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
+#define QSERDES_RX_SIGDET_ENABLES 0x110
+#define QSERDES_RX_SIGDET_CNTRL 0x114
+#define QSERDES_RX_SIGDET_LVL 0x118
+#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
+#define QSERDES_RX_RX_BAND 0x120
+#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index b2aeace96c09..6a24d61098e7 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -6,6 +6,9 @@
#ifndef QCOM_PHY_QMP_H_
#define QCOM_PHY_QMP_H_
+#include "phy-qcom-qmp-qserdes-com.h"
+#include "phy-qcom-qmp-qserdes-txrx.h"
+
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
@@ -64,115 +67,6 @@
#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
-/* Only for QMP V2 PHY - QSERDES COM registers */
-#define QSERDES_COM_BG_TIMER 0x00c
-#define QSERDES_COM_SSC_EN_CENTER 0x010
-#define QSERDES_COM_SSC_ADJ_PER1 0x014
-#define QSERDES_COM_SSC_ADJ_PER2 0x018
-#define QSERDES_COM_SSC_PER1 0x01c
-#define QSERDES_COM_SSC_PER2 0x020
-#define QSERDES_COM_SSC_STEP_SIZE1 0x024
-#define QSERDES_COM_SSC_STEP_SIZE2 0x028
-#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
-#define QSERDES_COM_CLK_ENABLE1 0x038
-#define QSERDES_COM_SYS_CLK_CTRL 0x03c
-#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
-#define QSERDES_COM_PLL_IVCO 0x048
-#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
-#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
-#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
-#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
-#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
-#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
-#define QSERDES_COM_BG_TRIM 0x070
-#define QSERDES_COM_CLK_EP_DIV 0x074
-#define QSERDES_COM_CP_CTRL_MODE0 0x078
-#define QSERDES_COM_CP_CTRL_MODE1 0x07c
-#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
-#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
-#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
-#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
-#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
-#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
-#define QSERDES_COM_RESETSM_CNTRL 0x0b4
-#define QSERDES_COM_RESETSM_CNTRL2 0x0b8
-#define QSERDES_COM_RESTRIM_CTRL 0x0bc
-#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
-#define QSERDES_COM_LOCK_CMP_EN 0x0c8
-#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
-#define QSERDES_COM_DEC_START_MODE0 0x0d0
-#define QSERDES_COM_DEC_START_MODE1 0x0d4
-#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
-#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
-#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
-#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
-#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
-#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
-#define QSERDES_COM_INTEGLOOP_INITVAL 0x100
-#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
-#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
-#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
-#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
-#define QSERDES_COM_VCO_TUNE_CTRL 0x124
-#define QSERDES_COM_VCO_TUNE_MAP 0x128
-#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
-#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
-#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
-#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
-#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
-#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
-#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
-#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
-#define QSERDES_COM_BG_CTRL 0x170
-#define QSERDES_COM_CLK_SELECT 0x174
-#define QSERDES_COM_HSCLK_SEL 0x178
-#define QSERDES_COM_CORECLK_DIV 0x184
-#define QSERDES_COM_CORE_CLK_EN 0x18c
-#define QSERDES_COM_C_READY_STATUS 0x190
-#define QSERDES_COM_CMN_CONFIG 0x194
-#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
-#define QSERDES_COM_DEBUG_BUS0 0x1a0
-#define QSERDES_COM_DEBUG_BUS1 0x1a4
-#define QSERDES_COM_DEBUG_BUS2 0x1a8
-#define QSERDES_COM_DEBUG_BUS3 0x1ac
-#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
-#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
-
-/* Only for QMP V2 PHY - TX registers */
-#define QSERDES_TX_EMP_POST1_LVL 0x018
-#define QSERDES_TX_SLEW_CNTL 0x040
-#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
-#define QSERDES_TX_DEBUG_BUS_SEL 0x064
-#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
-#define QSERDES_TX_LANE_MODE 0x094
-#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
-
-/* Only for QMP V2 PHY - RX registers */
-#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
-#define QSERDES_RX_UCDR_SO_GAIN 0x01c
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
-#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
-#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
-#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
-#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
-#define QSERDES_RX_RX_TERM_BW 0x090
-#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
-#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
-#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
-#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
-#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
-#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
-#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
-#define QSERDES_RX_SIGDET_ENABLES 0x110
-#define QSERDES_RX_SIGDET_CNTRL 0x114
-#define QSERDES_RX_SIGDET_LVL 0x118
-#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
-#define QSERDES_RX_RX_BAND 0x120
-#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
-
/* Only for QMP V2 PHY - PCS registers */
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24
--
2.35.1
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 09/28] phy: qcom-qmp: move QSERDES V3 registers to separate headers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES V3 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v3.h | 86 +++++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h | 65 +++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 138 +-----------------
3 files changed, 156 insertions(+), 133 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
new file mode 100644
index 000000000000..a61f8d36d01e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
@@ -0,0 +1,86 @@
+
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V3_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V3_H_
+
+/* Only for QMP V3 PHY - QSERDES COM registers */
+#define QSERDES_V3_COM_ATB_SEL1 0x000
+#define QSERDES_V3_COM_ATB_SEL2 0x004
+#define QSERDES_V3_COM_FREQ_UPDATE 0x008
+#define QSERDES_V3_COM_BG_TIMER 0x00c
+#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
+#define QSERDES_V3_COM_SSC_PER1 0x01c
+#define QSERDES_V3_COM_SSC_PER2 0x020
+#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
+#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
+#define QSERDES_V3_COM_POST_DIV 0x02c
+#define QSERDES_V3_COM_POST_DIV_MUX 0x030
+#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
+#define QSERDES_V3_COM_CLK_ENABLE1 0x038
+#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
+#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
+#define QSERDES_V3_COM_PLL_EN 0x044
+#define QSERDES_V3_COM_PLL_IVCO 0x048
+#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
+#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
+#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
+#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
+#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
+#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
+#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
+#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
+#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
+#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
+#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
+#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
+#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
+#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
+#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
+#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
+#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
+#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
+#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
+#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
+#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
+#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
+#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
+#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
+#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
+#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
+#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
+#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
+#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
+#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
+#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
+#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
+#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
+#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
+#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
+#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
+#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
+#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
+#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
+#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
+#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
+#define QSERDES_V3_COM_CLK_SELECT 0x138
+#define QSERDES_V3_COM_HSCLK_SEL 0x13c
+#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
+#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
+#define QSERDES_V3_COM_CORE_CLK_EN 0x154
+#define QSERDES_V3_COM_C_READY_STATUS 0x158
+#define QSERDES_V3_COM_CMN_CONFIG 0x15c
+#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
+#define QSERDES_V3_COM_DEBUG_BUS0 0x168
+#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
+#define QSERDES_V3_COM_DEBUG_BUS2 0x170
+#define QSERDES_V3_COM_DEBUG_BUS3 0x174
+#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
+#define QSERDES_V3_COM_CMN_MODE 0x184
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
new file mode 100644
index 000000000000..2c7238df38d7
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
+
+/* Only for QMP V3 PHY - TX registers */
+#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
+#define QSERDES_V3_TX_TX_DRV_LVL 0x01c
+#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
+#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
+#define QSERDES_V3_TX_TX_BAND 0x02c
+#define QSERDES_V3_TX_SLEW_CNTL 0x030
+#define QSERDES_V3_TX_INTERFACE_SELECT 0x034
+#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
+#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040
+#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
+#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
+#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
+#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c
+#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
+#define QSERDES_V3_TX_TX_POL_INV 0x064
+#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
+#define QSERDES_V3_TX_LANE_MODE_1 0x08c
+#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
+#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
+#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
+#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0
+
+/* Only for QMP V3 PHY - RX registers */
+#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
+#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
+#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
+#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
+#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
+#define QSERDES_V3_RX_RX_TERM_BW 0x07c
+#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
+#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
+#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
+#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
+#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
+#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
+#define QSERDES_V3_RX_SIGDET_ENABLES 0x100
+#define QSERDES_V3_RX_SIGDET_CNTRL 0x104
+#define QSERDES_V3_RX_SIGDET_LVL 0x108
+#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
+#define QSERDES_V3_RX_RX_BAND 0x110
+#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
+#define QSERDES_V3_RX_RX_MODE_00 0x164
+#define QSERDES_V3_RX_RX_MODE_01 0x168
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 6a24d61098e7..19bbe5aa9354 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -9,6 +9,9 @@
#include "phy-qcom-qmp-qserdes-com.h"
#include "phy-qcom-qmp-qserdes-txrx.h"
+#include "phy-qcom-qmp-qserdes-com-v3.h"
+#include "phy-qcom-qmp-qserdes-txrx-v3.h"
+
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
@@ -105,21 +108,7 @@
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
-/* Only for QMP V3 PHY - QSERDES COM registers */
-#define QSERDES_V3_COM_ATB_SEL1 0x000
-#define QSERDES_V3_COM_ATB_SEL2 0x004
-#define QSERDES_V3_COM_FREQ_UPDATE 0x008
-#define QSERDES_V3_COM_BG_TIMER 0x00c
-#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
-#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
-#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
-#define QSERDES_V3_COM_SSC_PER1 0x01c
-#define QSERDES_V3_COM_SSC_PER2 0x020
-#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
-#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
-#define QSERDES_V3_COM_POST_DIV 0x02c
-#define QSERDES_V3_COM_POST_DIV_MUX 0x030
-#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
+/* QSERDES V3 COM bits */
# define QSERDES_V3_COM_BIAS_EN 0x0001
# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
@@ -127,130 +116,13 @@
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
-#define QSERDES_V3_COM_CLK_ENABLE1 0x038
-#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
-#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
-#define QSERDES_V3_COM_PLL_EN 0x044
-#define QSERDES_V3_COM_PLL_IVCO 0x048
-#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
-#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
-#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
-#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
-#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
-#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
-#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
-#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
-#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
-#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
-#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
-#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
-#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
-#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
-#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
-#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
-#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
-#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
-#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
-#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
-#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
-#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
-#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
-#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
-#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
-#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
-#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
-#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
-#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
-#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
-#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
-#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
-#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
-#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
-#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
-#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
-#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
-#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
-#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
-#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
-#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
-#define QSERDES_V3_COM_CLK_SELECT 0x138
-#define QSERDES_V3_COM_HSCLK_SEL 0x13c
-#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
-#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
-#define QSERDES_V3_COM_CORE_CLK_EN 0x154
-#define QSERDES_V3_COM_C_READY_STATUS 0x158
-#define QSERDES_V3_COM_CMN_CONFIG 0x15c
-#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
-#define QSERDES_V3_COM_DEBUG_BUS0 0x168
-#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
-#define QSERDES_V3_COM_DEBUG_BUS2 0x170
-#define QSERDES_V3_COM_DEBUG_BUS3 0x174
-#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
-#define QSERDES_V3_COM_CMN_MODE 0x184
-/* Only for QMP V3 PHY - TX registers */
-#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
-#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
-#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
+/* QSERDES V3 TX bits */
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
-
-#define QSERDES_V3_TX_TX_DRV_LVL 0x01c
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
-#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
-#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
-
-#define QSERDES_V3_TX_TX_BAND 0x02c
-#define QSERDES_V3_TX_SLEW_CNTL 0x030
-#define QSERDES_V3_TX_INTERFACE_SELECT 0x034
-#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
-#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040
-#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
-#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
-#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
-#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c
-#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
-#define QSERDES_V3_TX_TX_POL_INV 0x064
-#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
-#define QSERDES_V3_TX_LANE_MODE_1 0x08c
-#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
-#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
-#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
-#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0
-
-/* Only for QMP V3 PHY - RX registers */
-#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
-#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
-#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
-#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
-#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
-#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
-#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
-#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
-#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
-#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
-#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
-#define QSERDES_V3_RX_RX_TERM_BW 0x07c
-#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
-#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
-#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
-#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
-#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
-#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
-#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
-#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
-#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
-#define QSERDES_V3_RX_SIGDET_ENABLES 0x100
-#define QSERDES_V3_RX_SIGDET_CNTRL 0x104
-#define QSERDES_V3_RX_SIGDET_LVL 0x108
-#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
-#define QSERDES_V3_RX_RX_BAND 0x110
-#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
-#define QSERDES_V3_RX_RX_MODE_00 0x164
-#define QSERDES_V3_RX_RX_MODE_01 0x168
-
/* Only for QMP V3 PHY - PCS registers */
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
#define QPHY_V3_PCS_TXMGN_V0 0x00c
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 09/28] phy: qcom-qmp: move QSERDES V3 registers to separate headers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES V3 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v3.h | 86 +++++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h | 65 +++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 138 +-----------------
3 files changed, 156 insertions(+), 133 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
new file mode 100644
index 000000000000..a61f8d36d01e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
@@ -0,0 +1,86 @@
+
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V3_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V3_H_
+
+/* Only for QMP V3 PHY - QSERDES COM registers */
+#define QSERDES_V3_COM_ATB_SEL1 0x000
+#define QSERDES_V3_COM_ATB_SEL2 0x004
+#define QSERDES_V3_COM_FREQ_UPDATE 0x008
+#define QSERDES_V3_COM_BG_TIMER 0x00c
+#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
+#define QSERDES_V3_COM_SSC_PER1 0x01c
+#define QSERDES_V3_COM_SSC_PER2 0x020
+#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
+#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
+#define QSERDES_V3_COM_POST_DIV 0x02c
+#define QSERDES_V3_COM_POST_DIV_MUX 0x030
+#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
+#define QSERDES_V3_COM_CLK_ENABLE1 0x038
+#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
+#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
+#define QSERDES_V3_COM_PLL_EN 0x044
+#define QSERDES_V3_COM_PLL_IVCO 0x048
+#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
+#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
+#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
+#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
+#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
+#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
+#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
+#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
+#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
+#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
+#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
+#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
+#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
+#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
+#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
+#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
+#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
+#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
+#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
+#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
+#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
+#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
+#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
+#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
+#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
+#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
+#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
+#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
+#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
+#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
+#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
+#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
+#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
+#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
+#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
+#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
+#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
+#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
+#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
+#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
+#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
+#define QSERDES_V3_COM_CLK_SELECT 0x138
+#define QSERDES_V3_COM_HSCLK_SEL 0x13c
+#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
+#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
+#define QSERDES_V3_COM_CORE_CLK_EN 0x154
+#define QSERDES_V3_COM_C_READY_STATUS 0x158
+#define QSERDES_V3_COM_CMN_CONFIG 0x15c
+#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
+#define QSERDES_V3_COM_DEBUG_BUS0 0x168
+#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
+#define QSERDES_V3_COM_DEBUG_BUS2 0x170
+#define QSERDES_V3_COM_DEBUG_BUS3 0x174
+#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
+#define QSERDES_V3_COM_CMN_MODE 0x184
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
new file mode 100644
index 000000000000..2c7238df38d7
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_
+
+/* Only for QMP V3 PHY - TX registers */
+#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
+#define QSERDES_V3_TX_TX_DRV_LVL 0x01c
+#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
+#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
+#define QSERDES_V3_TX_TX_BAND 0x02c
+#define QSERDES_V3_TX_SLEW_CNTL 0x030
+#define QSERDES_V3_TX_INTERFACE_SELECT 0x034
+#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
+#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040
+#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
+#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
+#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
+#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c
+#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
+#define QSERDES_V3_TX_TX_POL_INV 0x064
+#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
+#define QSERDES_V3_TX_LANE_MODE_1 0x08c
+#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
+#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
+#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
+#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0
+
+/* Only for QMP V3 PHY - RX registers */
+#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
+#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
+#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
+#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
+#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
+#define QSERDES_V3_RX_RX_TERM_BW 0x07c
+#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
+#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
+#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
+#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
+#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
+#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
+#define QSERDES_V3_RX_SIGDET_ENABLES 0x100
+#define QSERDES_V3_RX_SIGDET_CNTRL 0x104
+#define QSERDES_V3_RX_SIGDET_LVL 0x108
+#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
+#define QSERDES_V3_RX_RX_BAND 0x110
+#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
+#define QSERDES_V3_RX_RX_MODE_00 0x164
+#define QSERDES_V3_RX_RX_MODE_01 0x168
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 6a24d61098e7..19bbe5aa9354 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -9,6 +9,9 @@
#include "phy-qcom-qmp-qserdes-com.h"
#include "phy-qcom-qmp-qserdes-txrx.h"
+#include "phy-qcom-qmp-qserdes-com-v3.h"
+#include "phy-qcom-qmp-qserdes-txrx-v3.h"
+
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
@@ -105,21 +108,7 @@
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
-/* Only for QMP V3 PHY - QSERDES COM registers */
-#define QSERDES_V3_COM_ATB_SEL1 0x000
-#define QSERDES_V3_COM_ATB_SEL2 0x004
-#define QSERDES_V3_COM_FREQ_UPDATE 0x008
-#define QSERDES_V3_COM_BG_TIMER 0x00c
-#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
-#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
-#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
-#define QSERDES_V3_COM_SSC_PER1 0x01c
-#define QSERDES_V3_COM_SSC_PER2 0x020
-#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
-#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
-#define QSERDES_V3_COM_POST_DIV 0x02c
-#define QSERDES_V3_COM_POST_DIV_MUX 0x030
-#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
+/* QSERDES V3 COM bits */
# define QSERDES_V3_COM_BIAS_EN 0x0001
# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
@@ -127,130 +116,13 @@
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
-#define QSERDES_V3_COM_CLK_ENABLE1 0x038
-#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
-#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
-#define QSERDES_V3_COM_PLL_EN 0x044
-#define QSERDES_V3_COM_PLL_IVCO 0x048
-#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
-#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
-#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
-#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
-#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
-#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
-#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
-#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
-#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
-#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
-#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
-#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
-#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
-#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
-#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
-#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
-#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
-#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
-#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
-#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
-#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
-#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
-#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
-#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
-#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
-#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
-#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
-#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
-#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
-#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
-#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
-#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
-#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
-#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
-#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
-#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
-#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
-#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
-#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
-#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
-#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
-#define QSERDES_V3_COM_CLK_SELECT 0x138
-#define QSERDES_V3_COM_HSCLK_SEL 0x13c
-#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
-#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
-#define QSERDES_V3_COM_CORE_CLK_EN 0x154
-#define QSERDES_V3_COM_C_READY_STATUS 0x158
-#define QSERDES_V3_COM_CMN_CONFIG 0x15c
-#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
-#define QSERDES_V3_COM_DEBUG_BUS0 0x168
-#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
-#define QSERDES_V3_COM_DEBUG_BUS2 0x170
-#define QSERDES_V3_COM_DEBUG_BUS3 0x174
-#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
-#define QSERDES_V3_COM_CMN_MODE 0x184
-/* Only for QMP V3 PHY - TX registers */
-#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
-#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
-#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
+/* QSERDES V3 TX bits */
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
-
-#define QSERDES_V3_TX_TX_DRV_LVL 0x01c
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
-#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
-#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
-
-#define QSERDES_V3_TX_TX_BAND 0x02c
-#define QSERDES_V3_TX_SLEW_CNTL 0x030
-#define QSERDES_V3_TX_INTERFACE_SELECT 0x034
-#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
-#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040
-#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
-#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
-#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
-#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c
-#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
-#define QSERDES_V3_TX_TX_POL_INV 0x064
-#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
-#define QSERDES_V3_TX_LANE_MODE_1 0x08c
-#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
-#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
-#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
-#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0
-
-/* Only for QMP V3 PHY - RX registers */
-#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
-#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
-#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
-#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
-#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
-#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
-#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
-#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
-#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
-#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
-#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
-#define QSERDES_V3_RX_RX_TERM_BW 0x07c
-#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
-#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
-#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
-#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
-#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
-#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
-#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
-#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
-#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
-#define QSERDES_V3_RX_SIGDET_ENABLES 0x100
-#define QSERDES_V3_RX_SIGDET_CNTRL 0x104
-#define QSERDES_V3_RX_SIGDET_LVL 0x108
-#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
-#define QSERDES_V3_RX_RX_BAND 0x110
-#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
-#define QSERDES_V3_RX_RX_MODE_00 0x164
-#define QSERDES_V3_RX_RX_MODE_01 0x168
-
/* Only for QMP V3 PHY - PCS registers */
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
#define QPHY_V3_PCS_TXMGN_V0 0x00c
--
2.35.1
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 10/28] phy: qcom-qmp: move QSERDES V4 registers to separate headers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES V4 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v4.h | 78 +++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h | 92 +++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 154 +-----------------
3 files changed, 173 insertions(+), 151 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
new file mode 100644
index 000000000000..af8662ca9ee0
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V4_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V4_H_
+
+/* Only for QMP V4 PHY - QSERDES COM registers */
+#define QSERDES_V4_COM_BG_TIMER 0x00c
+#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_V4_COM_SSC_PER1 0x01c
+#define QSERDES_V4_COM_SSC_PER2 0x020
+#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
+#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044
+#define QSERDES_V4_COM_CLK_ENABLE1 0x048
+#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c
+#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
+#define QSERDES_V4_COM_PLL_IVCO 0x058
+#define QSERDES_V4_COM_CMN_IPTRIM 0x060
+#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
+#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
+#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
+#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
+#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
+#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
+#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
+#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c
+#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
+#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8
+#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
+#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
+#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
+#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
+#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
+#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
+#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
+#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
+#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
+#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
+#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
+#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
+#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
+#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108
+#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
+#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
+#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
+#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
+#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
+#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V4_COM_CMN_STATUS 0x140
+#define QSERDES_V4_COM_CLK_SELECT 0x154
+#define QSERDES_V4_COM_HSCLK_SEL 0x158
+#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168
+#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
+#define QSERDES_V4_COM_CORE_CLK_EN 0x174
+#define QSERDES_V4_COM_C_READY_STATUS 0x178
+#define QSERDES_V4_COM_CMN_CONFIG 0x17c
+#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
+#define QSERDES_V4_COM_CMN_MISC1 0x19c
+#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0
+#define QSERDES_V4_COM_CMN_MODE 0x1a4
+#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
+#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
new file mode 100644
index 000000000000..1716932bdf1a
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
+
+/* Only for QMP V4 PHY - TX registers */
+#define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
+#define QSERDES_V4_TX_TX_DRV_LVL 0x014
+#define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
+#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
+#define QSERDES_V4_TX_TX_BAND 0x024
+#define QSERDES_V4_TX_INTERFACE_SELECT 0x02c
+#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034
+#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054
+#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058
+#define QSERDES_V4_TX_TX_POL_INV 0x05c
+#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
+#define QSERDES_V4_TX_LANE_MODE_1 0x084
+#define QSERDES_V4_TX_LANE_MODE_2 0x088
+#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c
+#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8
+#define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc
+#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8
+#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc
+#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0
+#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4
+#define QSERDES_V4_TX_VMODE_CTRL1 0x0e8
+#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
+
+/* Only for QMP V4 PHY - RX registers */
+#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
+#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
+#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
+#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
+#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
+#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c
+#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
+#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
+#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
+#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
+#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064
+#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
+#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
+#define QSERDES_V4_RX_RX_TERM_BW 0x080
+#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
+#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
+#define QSERDES_V4_RX_GM_CAL 0x0dc
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
+#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
+#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
+#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
+#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
+#define QSERDES_V4_RX_SIGDET_ENABLES 0x118
+#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
+#define QSERDES_V4_RX_SIGDET_LVL 0x120
+#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
+#define QSERDES_V4_RX_RX_BAND 0x128
+#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
+#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
+#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
+#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
+#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
+#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
+#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
+#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
+#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
+#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
+#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
+#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
+#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
+#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
+#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
+#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
+#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
+#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
+#define QSERDES_V4_RX_VTH_CODE 0x1c4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 19bbe5aa9354..6e890459b44e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -12,6 +12,9 @@
#include "phy-qcom-qmp-qserdes-com-v3.h"
#include "phy-qcom-qmp-qserdes-txrx-v3.h"
+#include "phy-qcom-qmp-qserdes-com-v4.h"
+#include "phy-qcom-qmp-qserdes-txrx-v4.h"
+
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
@@ -240,102 +243,6 @@
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
-/* Only for QMP V4 PHY - QSERDES COM registers */
-#define QSERDES_V4_COM_BG_TIMER 0x00c
-#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
-#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
-#define QSERDES_V4_COM_SSC_PER1 0x01c
-#define QSERDES_V4_COM_SSC_PER2 0x020
-#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
-#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
-#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
-#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
-#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044
-#define QSERDES_V4_COM_CLK_ENABLE1 0x048
-#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c
-#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
-#define QSERDES_V4_COM_PLL_IVCO 0x058
-#define QSERDES_V4_COM_CMN_IPTRIM 0x060
-#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
-#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
-#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
-#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
-#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
-#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
-#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
-#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c
-#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
-#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8
-#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
-#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
-#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
-#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
-#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
-#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
-#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
-#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
-#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
-#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
-#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
-#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
-#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
-#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
-#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
-#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
-#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108
-#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
-#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
-#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
-#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
-#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
-#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
-#define QSERDES_V4_COM_CMN_STATUS 0x140
-#define QSERDES_V4_COM_CLK_SELECT 0x154
-#define QSERDES_V4_COM_HSCLK_SEL 0x158
-#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
-#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168
-#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
-#define QSERDES_V4_COM_CORE_CLK_EN 0x174
-#define QSERDES_V4_COM_C_READY_STATUS 0x178
-#define QSERDES_V4_COM_CMN_CONFIG 0x17c
-#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
-#define QSERDES_V4_COM_CMN_MISC1 0x19c
-#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0
-#define QSERDES_V4_COM_CMN_MODE 0x1a4
-#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8
-#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
-#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
-#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
-#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
-#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
-
-/* Only for QMP V4 PHY - TX registers */
-#define QSERDES_V4_TX_CLKBUF_ENABLE 0x08
-#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c
-#define QSERDES_V4_TX_TX_DRV_LVL 0x14
-#define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c
-#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20
-#define QSERDES_V4_TX_TX_BAND 0x24
-#define QSERDES_V4_TX_INTERFACE_SELECT 0x2c
-#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34
-#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38
-#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c
-#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40
-#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54
-#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58
-#define QSERDES_V4_TX_TX_POL_INV 0x5c
-#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
-#define QSERDES_V4_TX_LANE_MODE_1 0x84
-#define QSERDES_V4_TX_LANE_MODE_2 0x88
-#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c
-#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
-#define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc
-#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
-#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdc
-#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0
-#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4
-#define QSERDES_V4_TX_VMODE_CTRL1 0xe8
-#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
/* Only for QMP V4_20 PHY - TX registers */
#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
@@ -344,61 +251,6 @@
#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
-/* Only for QMP V4 PHY - RX registers */
-#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
-#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
-#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
-#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
-#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
-#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
-#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
-#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
-#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c
-#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
-#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
-#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
-#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
-#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064
-#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
-#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
-#define QSERDES_V4_RX_RX_TERM_BW 0x080
-#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
-#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
-#define QSERDES_V4_RX_GM_CAL 0x0dc
-#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
-#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
-#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
-#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
-#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
-#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
-#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
-#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
-#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
-#define QSERDES_V4_RX_SIGDET_ENABLES 0x118
-#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
-#define QSERDES_V4_RX_SIGDET_LVL 0x120
-#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
-#define QSERDES_V4_RX_RX_BAND 0x128
-#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
-#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
-#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
-#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
-#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
-#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
-#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
-#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
-#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
-#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
-#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
-#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
-#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
-#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
-#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
-#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
-#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
-#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
-#define QSERDES_V4_RX_VTH_CODE 0x1c4
-
/* Only for QMP V4 PHY - DP PHY registers */
#define QSERDES_V4_DP_PHY_CFG_1 0x014
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 10/28] phy: qcom-qmp: move QSERDES V4 registers to separate headers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES V4 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v4.h | 78 +++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h | 92 +++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 154 +-----------------
3 files changed, 173 insertions(+), 151 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
new file mode 100644
index 000000000000..af8662ca9ee0
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V4_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V4_H_
+
+/* Only for QMP V4 PHY - QSERDES COM registers */
+#define QSERDES_V4_COM_BG_TIMER 0x00c
+#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_V4_COM_SSC_PER1 0x01c
+#define QSERDES_V4_COM_SSC_PER2 0x020
+#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
+#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044
+#define QSERDES_V4_COM_CLK_ENABLE1 0x048
+#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c
+#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
+#define QSERDES_V4_COM_PLL_IVCO 0x058
+#define QSERDES_V4_COM_CMN_IPTRIM 0x060
+#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
+#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
+#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
+#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
+#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
+#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
+#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
+#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c
+#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
+#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8
+#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
+#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
+#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
+#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
+#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
+#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
+#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
+#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
+#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
+#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
+#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
+#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
+#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
+#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108
+#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
+#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
+#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
+#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
+#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
+#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V4_COM_CMN_STATUS 0x140
+#define QSERDES_V4_COM_CLK_SELECT 0x154
+#define QSERDES_V4_COM_HSCLK_SEL 0x158
+#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168
+#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
+#define QSERDES_V4_COM_CORE_CLK_EN 0x174
+#define QSERDES_V4_COM_C_READY_STATUS 0x178
+#define QSERDES_V4_COM_CMN_CONFIG 0x17c
+#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
+#define QSERDES_V4_COM_CMN_MISC1 0x19c
+#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0
+#define QSERDES_V4_COM_CMN_MODE 0x1a4
+#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
+#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
new file mode 100644
index 000000000000..1716932bdf1a
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
+
+/* Only for QMP V4 PHY - TX registers */
+#define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
+#define QSERDES_V4_TX_TX_DRV_LVL 0x014
+#define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
+#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
+#define QSERDES_V4_TX_TX_BAND 0x024
+#define QSERDES_V4_TX_INTERFACE_SELECT 0x02c
+#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034
+#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054
+#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058
+#define QSERDES_V4_TX_TX_POL_INV 0x05c
+#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
+#define QSERDES_V4_TX_LANE_MODE_1 0x084
+#define QSERDES_V4_TX_LANE_MODE_2 0x088
+#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c
+#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8
+#define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc
+#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8
+#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc
+#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0
+#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4
+#define QSERDES_V4_TX_VMODE_CTRL1 0x0e8
+#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
+
+/* Only for QMP V4 PHY - RX registers */
+#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
+#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
+#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
+#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
+#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
+#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c
+#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
+#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
+#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
+#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
+#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064
+#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
+#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
+#define QSERDES_V4_RX_RX_TERM_BW 0x080
+#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
+#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
+#define QSERDES_V4_RX_GM_CAL 0x0dc
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
+#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
+#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
+#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
+#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
+#define QSERDES_V4_RX_SIGDET_ENABLES 0x118
+#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
+#define QSERDES_V4_RX_SIGDET_LVL 0x120
+#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
+#define QSERDES_V4_RX_RX_BAND 0x128
+#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
+#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
+#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
+#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
+#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
+#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
+#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
+#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
+#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
+#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
+#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
+#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
+#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
+#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
+#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
+#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
+#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
+#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
+#define QSERDES_V4_RX_VTH_CODE 0x1c4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 19bbe5aa9354..6e890459b44e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -12,6 +12,9 @@
#include "phy-qcom-qmp-qserdes-com-v3.h"
#include "phy-qcom-qmp-qserdes-txrx-v3.h"
+#include "phy-qcom-qmp-qserdes-com-v4.h"
+#include "phy-qcom-qmp-qserdes-txrx-v4.h"
+
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
@@ -240,102 +243,6 @@
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
-/* Only for QMP V4 PHY - QSERDES COM registers */
-#define QSERDES_V4_COM_BG_TIMER 0x00c
-#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
-#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
-#define QSERDES_V4_COM_SSC_PER1 0x01c
-#define QSERDES_V4_COM_SSC_PER2 0x020
-#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
-#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
-#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
-#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
-#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044
-#define QSERDES_V4_COM_CLK_ENABLE1 0x048
-#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c
-#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
-#define QSERDES_V4_COM_PLL_IVCO 0x058
-#define QSERDES_V4_COM_CMN_IPTRIM 0x060
-#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
-#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
-#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
-#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
-#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
-#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
-#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
-#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c
-#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
-#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8
-#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
-#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
-#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
-#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
-#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
-#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
-#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
-#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
-#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
-#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
-#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
-#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
-#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
-#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
-#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
-#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
-#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108
-#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
-#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
-#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
-#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
-#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
-#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
-#define QSERDES_V4_COM_CMN_STATUS 0x140
-#define QSERDES_V4_COM_CLK_SELECT 0x154
-#define QSERDES_V4_COM_HSCLK_SEL 0x158
-#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
-#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168
-#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
-#define QSERDES_V4_COM_CORE_CLK_EN 0x174
-#define QSERDES_V4_COM_C_READY_STATUS 0x178
-#define QSERDES_V4_COM_CMN_CONFIG 0x17c
-#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
-#define QSERDES_V4_COM_CMN_MISC1 0x19c
-#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0
-#define QSERDES_V4_COM_CMN_MODE 0x1a4
-#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8
-#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
-#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
-#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
-#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
-#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
-
-/* Only for QMP V4 PHY - TX registers */
-#define QSERDES_V4_TX_CLKBUF_ENABLE 0x08
-#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c
-#define QSERDES_V4_TX_TX_DRV_LVL 0x14
-#define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c
-#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20
-#define QSERDES_V4_TX_TX_BAND 0x24
-#define QSERDES_V4_TX_INTERFACE_SELECT 0x2c
-#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34
-#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38
-#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c
-#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40
-#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54
-#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58
-#define QSERDES_V4_TX_TX_POL_INV 0x5c
-#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
-#define QSERDES_V4_TX_LANE_MODE_1 0x84
-#define QSERDES_V4_TX_LANE_MODE_2 0x88
-#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c
-#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
-#define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc
-#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
-#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdc
-#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0
-#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4
-#define QSERDES_V4_TX_VMODE_CTRL1 0xe8
-#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
/* Only for QMP V4_20 PHY - TX registers */
#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
@@ -344,61 +251,6 @@
#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
-/* Only for QMP V4 PHY - RX registers */
-#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
-#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
-#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
-#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
-#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
-#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
-#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
-#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
-#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c
-#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
-#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
-#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
-#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
-#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064
-#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
-#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
-#define QSERDES_V4_RX_RX_TERM_BW 0x080
-#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
-#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
-#define QSERDES_V4_RX_GM_CAL 0x0dc
-#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
-#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
-#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
-#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
-#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
-#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
-#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
-#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
-#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
-#define QSERDES_V4_RX_SIGDET_ENABLES 0x118
-#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
-#define QSERDES_V4_RX_SIGDET_LVL 0x120
-#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
-#define QSERDES_V4_RX_RX_BAND 0x128
-#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
-#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
-#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
-#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
-#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
-#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
-#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
-#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
-#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
-#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
-#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
-#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
-#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
-#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
-#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
-#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
-#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
-#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
-#define QSERDES_V4_RX_VTH_CODE 0x1c4
-
/* Only for QMP V4 PHY - DP PHY registers */
#define QSERDES_V4_DP_PHY_CFG_1 0x014
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
--
2.35.1
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 11/28] phy: qcom-qmp: move QSERDES V5 registers to separate headers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES V5 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v5.h | 65 +++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h | 84 +++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 133 +-----------------
3 files changed, 152 insertions(+), 130 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
new file mode 100644
index 000000000000..8d2f9f012fed
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V5_H_
+
+/* Only for QMP V5 PHY - QSERDES COM registers */
+#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V5_COM_SSC_PER1 0x01c
+#define QSERDES_V5_COM_SSC_PER2 0x020
+#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
+#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044
+#define QSERDES_V5_COM_CLK_ENABLE1 0x048
+#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
+#define QSERDES_V5_COM_PLL_IVCO 0x058
+#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
+#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
+#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
+#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
+#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
+#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
+#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
+#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
+#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8
+#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
+#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
+#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
+#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
+#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
+#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
+#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
+#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
+#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
+#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
+#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
+#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
+#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
+#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
+#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
+#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V5_COM_CLK_SELECT 0x154
+#define QSERDES_V5_COM_HSCLK_SEL 0x158
+#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168
+#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
+#define QSERDES_V5_COM_CORE_CLK_EN 0x174
+#define QSERDES_V5_COM_CMN_CONFIG 0x17c
+#define QSERDES_V5_COM_CMN_MISC1 0x19c
+#define QSERDES_V5_COM_CMN_MODE 0x1a0
+#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
+#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
+#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
new file mode 100644
index 000000000000..6887c0cb3155
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
@@ -0,0 +1,84 @@
+
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
+
+/* Only for QMP V5 PHY - TX registers */
+#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034
+#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038
+#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c
+#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V5_TX_LANE_MODE_1 0x084
+#define QSERDES_V5_TX_LANE_MODE_2 0x088
+#define QSERDES_V5_TX_LANE_MODE_3 0x08c
+#define QSERDES_V5_TX_LANE_MODE_4 0x090
+#define QSERDES_V5_TX_LANE_MODE_5 0x094
+#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4
+#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0
+#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4
+#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
+#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
+#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
+#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
+
+/* Only for QMP V5 PHY - RX registers */
+#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
+#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
+#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
+#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
+#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048
+#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c
+#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
+#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
+#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
+#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
+#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
+#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
+#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
+#define QSERDES_V5_RX_RX_TERM_BW 0x080
+#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
+#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
+#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
+#define QSERDES_V5_RX_GM_CAL 0x0dc
+#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
+#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
+#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
+#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
+#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
+#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
+#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
+#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
+#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
+#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c
+#define QSERDES_V5_RX_SIGDET_LVL 0x120
+#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
+#define QSERDES_V5_RX_RX_BAND 0x128
+#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
+#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
+#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
+#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168
+#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c
+#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170
+#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174
+#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178
+#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c
+#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180
+#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184
+#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188
+#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
+#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
+#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
+#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
+#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
+#define QSERDES_V5_RX_VTH_CODE 0x1b0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 6e890459b44e..50a663bb0f2f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -15,6 +15,9 @@
#include "phy-qcom-qmp-qserdes-com-v4.h"
#include "phy-qcom-qmp-qserdes-txrx-v4.h"
+#include "phy-qcom-qmp-qserdes-com-v5.h"
+#include "phy-qcom-qmp-qserdes-txrx-v5.h"
+
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
@@ -612,142 +615,12 @@
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
-/* Only for QMP V5 PHY - QSERDES COM registers */
-#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
-#define QSERDES_V5_COM_SSC_PER1 0x01c
-#define QSERDES_V5_COM_SSC_PER2 0x020
-#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
-#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
-#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
-#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
-#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044
-#define QSERDES_V5_COM_CLK_ENABLE1 0x048
-#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
-#define QSERDES_V5_COM_PLL_IVCO 0x058
-#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
-#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
-#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
-#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
-#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
-#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
-#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
-#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
-#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8
-#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
-#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
-#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
-#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
-#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
-#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
-#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
-#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
-#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
-#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
-#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
-#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
-#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
-#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
-#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
-#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
-#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
-#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
-#define QSERDES_V5_COM_CLK_SELECT 0x154
-#define QSERDES_V5_COM_HSCLK_SEL 0x158
-#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
-#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168
-#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
-#define QSERDES_V5_COM_CORE_CLK_EN 0x174
-#define QSERDES_V5_COM_CMN_CONFIG 0x17c
-#define QSERDES_V5_COM_CMN_MISC1 0x19c
-#define QSERDES_V5_COM_CMN_MODE 0x1a0
-#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
-#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
-#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
-#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
-#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
-#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
-#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
-
-/* Only for QMP V5 PHY - TX registers */
-#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34
-#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38
-#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c
-#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40
-#define QSERDES_V5_TX_LANE_MODE_1 0x84
-#define QSERDES_V5_TX_LANE_MODE_2 0x88
-#define QSERDES_V5_TX_LANE_MODE_3 0x8c
-#define QSERDES_V5_TX_LANE_MODE_4 0x90
-#define QSERDES_V5_TX_LANE_MODE_5 0x94
-#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4
-#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0
-#define QSERDES_V5_TX_PI_QEC_CTRL 0xe4
-#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
-#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
-#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
-#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
-
/* Only for QMP V5_20 PHY - TX registers */
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
-/* Only for QMP V5 PHY - RX registers */
-#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
-#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
-#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
-#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
-#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
-#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
-#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
-#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048
-#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c
-#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
-#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
-#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
-#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
-#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
-#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
-#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
-#define QSERDES_V5_RX_RX_TERM_BW 0x080
-#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
-#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
-#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
-#define QSERDES_V5_RX_GM_CAL 0x0dc
-#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
-#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
-#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
-#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
-#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
-#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
-#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
-#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
-#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
-#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
-#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c
-#define QSERDES_V5_RX_SIGDET_LVL 0x120
-#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
-#define QSERDES_V5_RX_RX_BAND 0x128
-#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
-#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
-#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
-#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168
-#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c
-#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170
-#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174
-#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178
-#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c
-#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180
-#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184
-#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188
-#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
-#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
-#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
-#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
-#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
-#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
-#define QSERDES_V5_RX_VTH_CODE 0x1b0
-
/* Only for QMP V5_20 PHY - RX registers */
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 11/28] phy: qcom-qmp: move QSERDES V5 registers to separate headers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES V5 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v5.h | 65 +++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h | 84 +++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 133 +-----------------
3 files changed, 152 insertions(+), 130 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
new file mode 100644
index 000000000000..8d2f9f012fed
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V5_H_
+
+/* Only for QMP V5 PHY - QSERDES COM registers */
+#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V5_COM_SSC_PER1 0x01c
+#define QSERDES_V5_COM_SSC_PER2 0x020
+#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
+#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044
+#define QSERDES_V5_COM_CLK_ENABLE1 0x048
+#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
+#define QSERDES_V5_COM_PLL_IVCO 0x058
+#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
+#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
+#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
+#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
+#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
+#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
+#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
+#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
+#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8
+#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
+#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
+#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
+#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
+#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
+#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
+#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
+#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
+#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
+#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
+#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
+#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
+#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
+#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
+#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
+#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V5_COM_CLK_SELECT 0x154
+#define QSERDES_V5_COM_HSCLK_SEL 0x158
+#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168
+#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
+#define QSERDES_V5_COM_CORE_CLK_EN 0x174
+#define QSERDES_V5_COM_CMN_CONFIG 0x17c
+#define QSERDES_V5_COM_CMN_MISC1 0x19c
+#define QSERDES_V5_COM_CMN_MODE 0x1a0
+#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
+#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
+#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
+#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
new file mode 100644
index 000000000000..6887c0cb3155
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
@@ -0,0 +1,84 @@
+
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
+
+/* Only for QMP V5 PHY - TX registers */
+#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034
+#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038
+#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c
+#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V5_TX_LANE_MODE_1 0x084
+#define QSERDES_V5_TX_LANE_MODE_2 0x088
+#define QSERDES_V5_TX_LANE_MODE_3 0x08c
+#define QSERDES_V5_TX_LANE_MODE_4 0x090
+#define QSERDES_V5_TX_LANE_MODE_5 0x094
+#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4
+#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0
+#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4
+#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
+#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
+#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
+#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
+
+/* Only for QMP V5 PHY - RX registers */
+#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
+#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
+#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
+#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
+#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048
+#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c
+#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
+#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
+#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
+#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
+#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
+#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
+#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
+#define QSERDES_V5_RX_RX_TERM_BW 0x080
+#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
+#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
+#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
+#define QSERDES_V5_RX_GM_CAL 0x0dc
+#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
+#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
+#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
+#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
+#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
+#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
+#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
+#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
+#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
+#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c
+#define QSERDES_V5_RX_SIGDET_LVL 0x120
+#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
+#define QSERDES_V5_RX_RX_BAND 0x128
+#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
+#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
+#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
+#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168
+#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c
+#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170
+#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174
+#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178
+#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c
+#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180
+#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184
+#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188
+#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
+#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
+#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
+#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
+#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
+#define QSERDES_V5_RX_VTH_CODE 0x1b0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 6e890459b44e..50a663bb0f2f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -15,6 +15,9 @@
#include "phy-qcom-qmp-qserdes-com-v4.h"
#include "phy-qcom-qmp-qserdes-txrx-v4.h"
+#include "phy-qcom-qmp-qserdes-com-v5.h"
+#include "phy-qcom-qmp-qserdes-txrx-v5.h"
+
/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER 0x00c
@@ -612,142 +615,12 @@
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
-/* Only for QMP V5 PHY - QSERDES COM registers */
-#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
-#define QSERDES_V5_COM_SSC_PER1 0x01c
-#define QSERDES_V5_COM_SSC_PER2 0x020
-#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
-#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
-#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
-#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
-#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044
-#define QSERDES_V5_COM_CLK_ENABLE1 0x048
-#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
-#define QSERDES_V5_COM_PLL_IVCO 0x058
-#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
-#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
-#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
-#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
-#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
-#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
-#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
-#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
-#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8
-#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
-#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
-#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
-#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
-#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
-#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
-#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
-#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
-#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
-#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
-#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
-#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
-#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
-#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
-#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
-#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
-#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
-#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
-#define QSERDES_V5_COM_CLK_SELECT 0x154
-#define QSERDES_V5_COM_HSCLK_SEL 0x158
-#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
-#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168
-#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
-#define QSERDES_V5_COM_CORE_CLK_EN 0x174
-#define QSERDES_V5_COM_CMN_CONFIG 0x17c
-#define QSERDES_V5_COM_CMN_MISC1 0x19c
-#define QSERDES_V5_COM_CMN_MODE 0x1a0
-#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
-#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
-#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
-#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
-#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
-#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
-#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
-
-/* Only for QMP V5 PHY - TX registers */
-#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34
-#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38
-#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c
-#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40
-#define QSERDES_V5_TX_LANE_MODE_1 0x84
-#define QSERDES_V5_TX_LANE_MODE_2 0x88
-#define QSERDES_V5_TX_LANE_MODE_3 0x8c
-#define QSERDES_V5_TX_LANE_MODE_4 0x90
-#define QSERDES_V5_TX_LANE_MODE_5 0x94
-#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4
-#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0
-#define QSERDES_V5_TX_PI_QEC_CTRL 0xe4
-#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
-#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
-#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
-#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
-
/* Only for QMP V5_20 PHY - TX registers */
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
-/* Only for QMP V5 PHY - RX registers */
-#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
-#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
-#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
-#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
-#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
-#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
-#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
-#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048
-#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c
-#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
-#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
-#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
-#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
-#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
-#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
-#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
-#define QSERDES_V5_RX_RX_TERM_BW 0x080
-#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
-#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
-#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
-#define QSERDES_V5_RX_GM_CAL 0x0dc
-#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
-#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
-#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
-#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
-#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
-#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
-#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
-#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
-#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
-#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
-#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c
-#define QSERDES_V5_RX_SIGDET_LVL 0x120
-#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
-#define QSERDES_V5_RX_RX_BAND 0x128
-#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
-#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
-#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
-#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168
-#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c
-#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170
-#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174
-#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178
-#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c
-#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180
-#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184
-#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188
-#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
-#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
-#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
-#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
-#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
-#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
-#define QSERDES_V5_RX_VTH_CODE 0x1b0
-
/* Only for QMP V5_20 PHY - RX registers */
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 12/28] phy: qcom-qmp: move QSERDES PLL registers to separate header
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES PLL registers to the separate header. This register set is
unique for the IPQ PCIe Gen3 PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 66 +++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 58 +---------------
2 files changed, 67 insertions(+), 57 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
new file mode 100644
index 000000000000..ad326e301a3a
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_PLL_H_
+#define QCOM_PHY_QMP_QSERDES_PLL_H_
+
+/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
+#define QSERDES_PLL_BG_TIMER 0x00c
+#define QSERDES_PLL_SSC_PER1 0x01c
+#define QSERDES_PLL_SSC_PER2 0x020
+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
+#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
+#define QSERDES_PLL_CLK_ENABLE1 0x040
+#define QSERDES_PLL_SYS_CLK_CTRL 0x044
+#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
+#define QSERDES_PLL_PLL_IVCO 0x050
+#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
+#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
+#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
+#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
+#define QSERDES_PLL_BG_TRIM 0x074
+#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
+#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
+#define QSERDES_PLL_CP_CTRL_MODE0 0x080
+#define QSERDES_PLL_CP_CTRL_MODE1 0x084
+#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
+#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c
+#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
+#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
+#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
+#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
+#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
+#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
+#define QSERDES_PLL_DEC_START_MODE0 0x0cc
+#define QSERDES_PLL_DEC_START_MODE1 0x0d0
+#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
+#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
+#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
+#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
+#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
+#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec
+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
+#define QSERDES_PLL_VCO_TUNE_MAP 0x120
+#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
+#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
+#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
+#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
+#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
+#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
+#define QSERDES_PLL_CLK_SELECT 0x16c
+#define QSERDES_PLL_HSCLK_SEL 0x170
+#define QSERDES_PLL_CORECLK_DIV 0x17c
+#define QSERDES_PLL_CORE_CLK_EN 0x184
+#define QSERDES_PLL_CMN_CONFIG 0x18c
+#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
+#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 50a663bb0f2f..07e281c818b1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -18,63 +18,7 @@
#include "phy-qcom-qmp-qserdes-com-v5.h"
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
-/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
-
-#define QSERDES_PLL_BG_TIMER 0x00c
-#define QSERDES_PLL_SSC_PER1 0x01c
-#define QSERDES_PLL_SSC_PER2 0x020
-#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
-#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
-#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
-#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
-#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
-#define QSERDES_PLL_CLK_ENABLE1 0x040
-#define QSERDES_PLL_SYS_CLK_CTRL 0x044
-#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
-#define QSERDES_PLL_PLL_IVCO 0x050
-#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
-#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
-#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
-#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
-#define QSERDES_PLL_BG_TRIM 0x074
-#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
-#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
-#define QSERDES_PLL_CP_CTRL_MODE0 0x080
-#define QSERDES_PLL_CP_CTRL_MODE1 0x084
-#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
-#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c
-#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
-#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
-#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
-#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
-#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
-#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
-#define QSERDES_PLL_DEC_START_MODE0 0x0cc
-#define QSERDES_PLL_DEC_START_MODE1 0x0d0
-#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
-#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
-#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
-#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
-#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
-#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec
-#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
-#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
-#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
-#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
-#define QSERDES_PLL_VCO_TUNE_MAP 0x120
-#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
-#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
-#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
-#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
-#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
-#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
-#define QSERDES_PLL_CLK_SELECT 0x16c
-#define QSERDES_PLL_HSCLK_SEL 0x170
-#define QSERDES_PLL_CORECLK_DIV 0x17c
-#define QSERDES_PLL_CORE_CLK_EN 0x184
-#define QSERDES_PLL_CMN_CONFIG 0x18c
-#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
-#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
+#include "phy-qcom-qmp-qserdes-pll.h"
/* Only for QMP V2 PHY - PCS registers */
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 12/28] phy: qcom-qmp: move QSERDES PLL registers to separate header
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move QSERDES PLL registers to the separate header. This register set is
unique for the IPQ PCIe Gen3 PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 66 +++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 58 +---------------
2 files changed, 67 insertions(+), 57 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
new file mode 100644
index 000000000000..ad326e301a3a
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_PLL_H_
+#define QCOM_PHY_QMP_QSERDES_PLL_H_
+
+/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
+#define QSERDES_PLL_BG_TIMER 0x00c
+#define QSERDES_PLL_SSC_PER1 0x01c
+#define QSERDES_PLL_SSC_PER2 0x020
+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
+#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
+#define QSERDES_PLL_CLK_ENABLE1 0x040
+#define QSERDES_PLL_SYS_CLK_CTRL 0x044
+#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
+#define QSERDES_PLL_PLL_IVCO 0x050
+#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
+#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
+#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
+#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
+#define QSERDES_PLL_BG_TRIM 0x074
+#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
+#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
+#define QSERDES_PLL_CP_CTRL_MODE0 0x080
+#define QSERDES_PLL_CP_CTRL_MODE1 0x084
+#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
+#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c
+#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
+#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
+#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
+#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
+#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
+#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
+#define QSERDES_PLL_DEC_START_MODE0 0x0cc
+#define QSERDES_PLL_DEC_START_MODE1 0x0d0
+#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
+#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
+#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
+#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
+#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
+#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec
+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
+#define QSERDES_PLL_VCO_TUNE_MAP 0x120
+#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
+#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
+#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
+#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
+#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
+#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
+#define QSERDES_PLL_CLK_SELECT 0x16c
+#define QSERDES_PLL_HSCLK_SEL 0x170
+#define QSERDES_PLL_CORECLK_DIV 0x17c
+#define QSERDES_PLL_CORE_CLK_EN 0x184
+#define QSERDES_PLL_CMN_CONFIG 0x18c
+#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
+#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 50a663bb0f2f..07e281c818b1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -18,63 +18,7 @@
#include "phy-qcom-qmp-qserdes-com-v5.h"
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
-/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
-
-#define QSERDES_PLL_BG_TIMER 0x00c
-#define QSERDES_PLL_SSC_PER1 0x01c
-#define QSERDES_PLL_SSC_PER2 0x020
-#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
-#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
-#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
-#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
-#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
-#define QSERDES_PLL_CLK_ENABLE1 0x040
-#define QSERDES_PLL_SYS_CLK_CTRL 0x044
-#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
-#define QSERDES_PLL_PLL_IVCO 0x050
-#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
-#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
-#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
-#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
-#define QSERDES_PLL_BG_TRIM 0x074
-#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
-#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
-#define QSERDES_PLL_CP_CTRL_MODE0 0x080
-#define QSERDES_PLL_CP_CTRL_MODE1 0x084
-#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
-#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c
-#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
-#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
-#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
-#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
-#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
-#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
-#define QSERDES_PLL_DEC_START_MODE0 0x0cc
-#define QSERDES_PLL_DEC_START_MODE1 0x0d0
-#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
-#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
-#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
-#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
-#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
-#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec
-#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
-#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
-#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
-#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
-#define QSERDES_PLL_VCO_TUNE_MAP 0x120
-#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
-#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
-#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
-#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
-#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
-#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
-#define QSERDES_PLL_CLK_SELECT 0x16c
-#define QSERDES_PLL_HSCLK_SEL 0x170
-#define QSERDES_PLL_CORECLK_DIV 0x17c
-#define QSERDES_PLL_CORE_CLK_EN 0x184
-#define QSERDES_PLL_CMN_CONFIG 0x18c
-#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
-#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
+#include "phy-qcom-qmp-qserdes-pll.h"
/* Only for QMP V2 PHY - PCS registers */
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 13/28] phy: qcom-qmp: move PCS V2 registers to separate header
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCS V2 registers to the separate header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 38 ++++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 29 +----------------
2 files changed, 39 insertions(+), 28 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
new file mode 100644
index 000000000000..3fc3c0562d16
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V2_H_
+#define QCOM_PHY_QMP_PCS_V2_H_
+
+/* Only for QMP V2 PHY - PCS registers */
+#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
+#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
+#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
+#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
+#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
+#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
+#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
+#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
+#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
+#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
+#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
+#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
+#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
+#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
+#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
+#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
+#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
+#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
+#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
+#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 07e281c818b1..1bb57d1563c3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -20,34 +20,7 @@
#include "phy-qcom-qmp-qserdes-pll.h"
-/* Only for QMP V2 PHY - PCS registers */
-#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
-#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24
-#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28
-#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34
-#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38
-#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c
-#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40
-#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54
-#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58
-#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60
-#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64
-#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c
-#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80
-#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84
-#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88
-#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
-#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
-#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
-#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
-#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
-#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
-#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
-#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
-#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
-#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
-#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
-#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+#include "phy-qcom-qmp-pcs-v2.h"
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 13/28] phy: qcom-qmp: move PCS V2 registers to separate header
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCS V2 registers to the separate header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 38 ++++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 29 +----------------
2 files changed, 39 insertions(+), 28 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
new file mode 100644
index 000000000000..3fc3c0562d16
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V2_H_
+#define QCOM_PHY_QMP_PCS_V2_H_
+
+/* Only for QMP V2 PHY - PCS registers */
+#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
+#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
+#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
+#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
+#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
+#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
+#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
+#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
+#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
+#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
+#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084
+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
+#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
+#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
+#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
+#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
+#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
+#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
+#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
+#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
+#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 07e281c818b1..1bb57d1563c3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -20,34 +20,7 @@
#include "phy-qcom-qmp-qserdes-pll.h"
-/* Only for QMP V2 PHY - PCS registers */
-#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
-#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24
-#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28
-#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34
-#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38
-#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c
-#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40
-#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54
-#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58
-#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60
-#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64
-#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c
-#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80
-#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84
-#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88
-#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
-#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
-#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
-#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
-#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
-#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
-#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
-#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
-#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
-#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
-#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
-#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+#include "phy-qcom-qmp-pcs-v2.h"
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 14/28] phy: qcom-qmp: move PCS V3 registers to separate headers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCS V3 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h | 17 +++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 71 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 73 +------------------
3 files changed, 91 insertions(+), 70 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
new file mode 100644
index 000000000000..a45bd301bc9e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_
+#define QCOM_PHY_QMP_PCS_MISC_V3_H_
+
+/* Only for QMP V3 PHY - PCS_MISC registers */
+#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
+#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
new file mode 100644
index 000000000000..0b023df19126
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V3_H_
+#define QCOM_PHY_QMP_PCS_V3_H_
+
+/* Only for QMP V3 PHY - PCS registers */
+#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V3_PCS_TXMGN_V0 0x00c
+#define QPHY_V3_PCS_TXMGN_V1 0x010
+#define QPHY_V3_PCS_TXMGN_V2 0x014
+#define QPHY_V3_PCS_TXMGN_V3 0x018
+#define QPHY_V3_PCS_TXMGN_V4 0x01c
+#define QPHY_V3_PCS_TXMGN_LS 0x020
+#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
+#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
+#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
+#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
+#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
+#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
+#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
+#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
+#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
+#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
+#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
+#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
+#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
+#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
+#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
+#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
+#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
+#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
+#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
+#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
+#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
+#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
+#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
+#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
+#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
+#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
+#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1bb57d1563c3..1290c62a16fe 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -22,6 +22,9 @@
#include "phy-qcom-qmp-pcs-v2.h"
+#include "phy-qcom-qmp-pcs-v3.h"
+#include "phy-qcom-qmp-pcs-misc-v3.h"
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
@@ -46,76 +49,6 @@
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
-/* Only for QMP V3 PHY - PCS registers */
-#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
-#define QPHY_V3_PCS_TXMGN_V0 0x00c
-#define QPHY_V3_PCS_TXMGN_V1 0x010
-#define QPHY_V3_PCS_TXMGN_V2 0x014
-#define QPHY_V3_PCS_TXMGN_V3 0x018
-#define QPHY_V3_PCS_TXMGN_V4 0x01c
-#define QPHY_V3_PCS_TXMGN_LS 0x020
-#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
-#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
-#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
-#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
-#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
-#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
-#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
-#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
-#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
-#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
-#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
-#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
-#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
-#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
-#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
-#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
-#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
-#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
-#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
-#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
-#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
-#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
-#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
-#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
-#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
-#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
-#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
-#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
-#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
-#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
-#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
-#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
-#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
-#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
-
-/* Only for QMP V3 PHY - PCS_MISC registers */
-#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
-#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
-#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
-
/* QMP PHY - DP PHY registers */
#define QSERDES_DP_PHY_REVISION_ID0 0x000
#define QSERDES_DP_PHY_REVISION_ID1 0x004
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 14/28] phy: qcom-qmp: move PCS V3 registers to separate headers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCS V3 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h | 17 +++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 71 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 73 +------------------
3 files changed, 91 insertions(+), 70 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
new file mode 100644
index 000000000000..a45bd301bc9e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_
+#define QCOM_PHY_QMP_PCS_MISC_V3_H_
+
+/* Only for QMP V3 PHY - PCS_MISC registers */
+#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
+#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
new file mode 100644
index 000000000000..0b023df19126
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V3_H_
+#define QCOM_PHY_QMP_PCS_V3_H_
+
+/* Only for QMP V3 PHY - PCS registers */
+#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V3_PCS_TXMGN_V0 0x00c
+#define QPHY_V3_PCS_TXMGN_V1 0x010
+#define QPHY_V3_PCS_TXMGN_V2 0x014
+#define QPHY_V3_PCS_TXMGN_V3 0x018
+#define QPHY_V3_PCS_TXMGN_V4 0x01c
+#define QPHY_V3_PCS_TXMGN_LS 0x020
+#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
+#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
+#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
+#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
+#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
+#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
+#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
+#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
+#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
+#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
+#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
+#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
+#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
+#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
+#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
+#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
+#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
+#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
+#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
+#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
+#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
+#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
+#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
+#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
+#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
+#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
+#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
+#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
+#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1bb57d1563c3..1290c62a16fe 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -22,6 +22,9 @@
#include "phy-qcom-qmp-pcs-v2.h"
+#include "phy-qcom-qmp-pcs-v3.h"
+#include "phy-qcom-qmp-pcs-misc-v3.h"
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
@@ -46,76 +49,6 @@
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
-/* Only for QMP V3 PHY - PCS registers */
-#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
-#define QPHY_V3_PCS_TXMGN_V0 0x00c
-#define QPHY_V3_PCS_TXMGN_V1 0x010
-#define QPHY_V3_PCS_TXMGN_V2 0x014
-#define QPHY_V3_PCS_TXMGN_V3 0x018
-#define QPHY_V3_PCS_TXMGN_V4 0x01c
-#define QPHY_V3_PCS_TXMGN_LS 0x020
-#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
-#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
-#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
-#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
-#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
-#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
-#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
-#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
-#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
-#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
-#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
-#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
-#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
-#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
-#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
-#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
-#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
-#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
-#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
-#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
-#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
-#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
-#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
-#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
-#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
-#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
-#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
-#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
-#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
-#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
-#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
-#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
-#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
-#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
-#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
-#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
-#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
-#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
-
-/* Only for QMP V3 PHY - PCS_MISC registers */
-#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
-#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
-#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
-#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
-
/* QMP PHY - DP PHY registers */
#define QSERDES_DP_PHY_REVISION_ID0 0x000
#define QSERDES_DP_PHY_REVISION_ID1 0x004
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 15/28] phy: qcom-qmp: move PCS V4 registers to separate headers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCS V4 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h | 23 +++
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h | 31 +++
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h | 34 ++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h | 135 ++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 192 +-----------------
5 files changed, 228 insertions(+), 187 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
new file mode 100644
index 000000000000..5a97867c5ba6
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V4_H_
+
+/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
+#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
+#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
+#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
+#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
+#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
+#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
+#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
+#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
+#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
+#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
+#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h
new file mode 100644
index 000000000000..a1c7d3d17150
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_UFS_V4_H_
+#define QCOM_PHY_QMP_PCS_UFS_V4_H_
+
+/* Only for QMP V4 PHY - UFS PCS registers */
+#define QPHY_V4_PCS_UFS_PHY_START 0x000
+#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V4_PCS_UFS_SW_RESET 0x008
+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
+#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
+#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
+#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
+#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
+#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
+#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
+#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
+#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
+#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
+#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
+#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
+#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
+#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
+#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
+#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h
new file mode 100644
index 000000000000..d7fd4ac0fc55
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V4_H_
+#define QCOM_PHY_QMP_PCS_USB_V4_H_
+
+/* Only for QMP V4 PHY - USB3 PCS registers */
+#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
+#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
+#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
+#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
+#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
+#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
+#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
+#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
+#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h
new file mode 100644
index 000000000000..a2c1eba2b693
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V4_H_
+#define QCOM_PHY_QMP_PCS_V4_H_
+
+/* Only for QMP V4 PHY - USB/PCIe PCS registers */
+#define QPHY_V4_PCS_SW_RESET 0x000
+#define QPHY_V4_PCS_REVISION_ID0 0x004
+#define QPHY_V4_PCS_REVISION_ID1 0x008
+#define QPHY_V4_PCS_REVISION_ID2 0x00c
+#define QPHY_V4_PCS_REVISION_ID3 0x010
+#define QPHY_V4_PCS_PCS_STATUS1 0x014
+#define QPHY_V4_PCS_PCS_STATUS2 0x018
+#define QPHY_V4_PCS_PCS_STATUS3 0x01c
+#define QPHY_V4_PCS_PCS_STATUS4 0x020
+#define QPHY_V4_PCS_PCS_STATUS5 0x024
+#define QPHY_V4_PCS_PCS_STATUS6 0x028
+#define QPHY_V4_PCS_PCS_STATUS7 0x02c
+#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
+#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
+#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
+#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
+#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
+#define QPHY_V4_PCS_START_CONTROL 0x044
+#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
+#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
+#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
+#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
+#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
+#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
+#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
+#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
+#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
+#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
+#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
+#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
+#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
+#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
+#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
+#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
+#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
+#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
+#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
+#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
+#define QPHY_V4_PCS_FLL_CNTRL1 0x098
+#define QPHY_V4_PCS_FLL_CNTRL2 0x09c
+#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
+#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
+#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
+#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
+#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
+#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
+#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
+#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
+#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
+#define QPHY_V4_PCS_BIST_CTRL 0x0e8
+#define QPHY_V4_PCS_PRBS_POLY0 0x0ec
+#define QPHY_V4_PCS_PRBS_POLY1 0x0f0
+#define QPHY_V4_PCS_FIXED_PAT0 0x0f4
+#define QPHY_V4_PCS_FIXED_PAT1 0x0f8
+#define QPHY_V4_PCS_FIXED_PAT2 0x0fc
+#define QPHY_V4_PCS_FIXED_PAT3 0x100
+#define QPHY_V4_PCS_FIXED_PAT4 0x104
+#define QPHY_V4_PCS_FIXED_PAT5 0x108
+#define QPHY_V4_PCS_FIXED_PAT6 0x10c
+#define QPHY_V4_PCS_FIXED_PAT7 0x110
+#define QPHY_V4_PCS_FIXED_PAT8 0x114
+#define QPHY_V4_PCS_FIXED_PAT9 0x118
+#define QPHY_V4_PCS_FIXED_PAT10 0x11c
+#define QPHY_V4_PCS_FIXED_PAT11 0x120
+#define QPHY_V4_PCS_FIXED_PAT12 0x124
+#define QPHY_V4_PCS_FIXED_PAT13 0x128
+#define QPHY_V4_PCS_FIXED_PAT14 0x12c
+#define QPHY_V4_PCS_FIXED_PAT15 0x130
+#define QPHY_V4_PCS_TXMGN_CONFIG 0x134
+#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
+#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
+#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
+#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
+#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
+#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
+#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
+#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
+#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
+#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
+#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
+#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
+#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
+#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
+#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
+#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
+#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
+#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
+#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
+#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
+#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
+#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
+#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
+#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
+#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
+#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
+#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
+#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
+#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
+#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
+#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
+#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
+#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
+#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
+#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
+#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
+#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
+#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
+#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
+#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
+#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1290c62a16fe..05da0725df71 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -25,6 +25,11 @@
#include "phy-qcom-qmp-pcs-v3.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
+#include "phy-qcom-qmp-pcs-v4.h"
+#include "phy-qcom-qmp-pcs-pcie-v4.h"
+#include "phy-qcom-qmp-pcs-usb-v4.h"
+#include "phy-qcom-qmp-pcs-ufs-v4.h"
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
@@ -142,28 +147,6 @@
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
-/* Only for QMP V4 PHY - UFS PCS registers */
-#define QPHY_V4_PCS_UFS_PHY_START 0x000
-#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
-#define QPHY_V4_PCS_UFS_SW_RESET 0x008
-#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
-#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
-#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
-#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
-#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
-#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
-#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
-#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
-#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
-#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
-#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
-#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
-#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
-#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
-#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
-#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
-#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
-
/* PCIE GEN3 COM registers */
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
@@ -278,157 +261,6 @@
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
-/* Only for QMP V4 PHY - USB/PCIe PCS registers */
-#define QPHY_V4_PCS_SW_RESET 0x000
-#define QPHY_V4_PCS_REVISION_ID0 0x004
-#define QPHY_V4_PCS_REVISION_ID1 0x008
-#define QPHY_V4_PCS_REVISION_ID2 0x00c
-#define QPHY_V4_PCS_REVISION_ID3 0x010
-#define QPHY_V4_PCS_PCS_STATUS1 0x014
-#define QPHY_V4_PCS_PCS_STATUS2 0x018
-#define QPHY_V4_PCS_PCS_STATUS3 0x01c
-#define QPHY_V4_PCS_PCS_STATUS4 0x020
-#define QPHY_V4_PCS_PCS_STATUS5 0x024
-#define QPHY_V4_PCS_PCS_STATUS6 0x028
-#define QPHY_V4_PCS_PCS_STATUS7 0x02c
-#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
-#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
-#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
-#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
-#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
-#define QPHY_V4_PCS_START_CONTROL 0x044
-#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
-#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
-#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
-#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
-#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
-#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
-#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
-#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
-#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
-#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
-#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
-#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
-#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
-#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
-#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
-#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
-#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
-#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
-#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
-#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
-#define QPHY_V4_PCS_FLL_CNTRL1 0x098
-#define QPHY_V4_PCS_FLL_CNTRL2 0x09c
-#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
-#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
-#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
-#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
-#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
-#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
-#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
-#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
-#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
-#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
-#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
-#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
-#define QPHY_V4_PCS_BIST_CTRL 0x0e8
-#define QPHY_V4_PCS_PRBS_POLY0 0x0ec
-#define QPHY_V4_PCS_PRBS_POLY1 0x0f0
-#define QPHY_V4_PCS_FIXED_PAT0 0x0f4
-#define QPHY_V4_PCS_FIXED_PAT1 0x0f8
-#define QPHY_V4_PCS_FIXED_PAT2 0x0fc
-#define QPHY_V4_PCS_FIXED_PAT3 0x100
-#define QPHY_V4_PCS_FIXED_PAT4 0x104
-#define QPHY_V4_PCS_FIXED_PAT5 0x108
-#define QPHY_V4_PCS_FIXED_PAT6 0x10c
-#define QPHY_V4_PCS_FIXED_PAT7 0x110
-#define QPHY_V4_PCS_FIXED_PAT8 0x114
-#define QPHY_V4_PCS_FIXED_PAT9 0x118
-#define QPHY_V4_PCS_FIXED_PAT10 0x11c
-#define QPHY_V4_PCS_FIXED_PAT11 0x120
-#define QPHY_V4_PCS_FIXED_PAT12 0x124
-#define QPHY_V4_PCS_FIXED_PAT13 0x128
-#define QPHY_V4_PCS_FIXED_PAT14 0x12c
-#define QPHY_V4_PCS_FIXED_PAT15 0x130
-#define QPHY_V4_PCS_TXMGN_CONFIG 0x134
-#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
-#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
-#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
-#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
-#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
-#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
-#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
-#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
-#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
-#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
-#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
-#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
-#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
-#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
-#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
-#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
-#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
-#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
-#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
-#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
-#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
-#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
-#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
-#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
-#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
-#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
-#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
-#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
-#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
-#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
-#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
-#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
-#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
-#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
-#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
-#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
-#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
-#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
-#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
-#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
-#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
-#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
-#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
-#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
-#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
-#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
-
-/* Only for QMP V4 PHY - USB3 PCS registers */
-#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
-#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
-#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
-#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
-#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
-#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
-#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
-#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
-#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
-#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
-#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
-#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
-#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
-#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
-#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
-
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
@@ -443,20 +275,6 @@
#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
-/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
-#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
-#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
-#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
-#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
-#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
-#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
-#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
-#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
-#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
-#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
-#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
-#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
-
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 15/28] phy: qcom-qmp: move PCS V4 registers to separate headers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCS V4 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h | 23 +++
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h | 31 +++
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h | 34 ++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h | 135 ++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 192 +-----------------
5 files changed, 228 insertions(+), 187 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
new file mode 100644
index 000000000000..5a97867c5ba6
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V4_H_
+
+/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
+#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
+#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
+#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
+#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
+#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
+#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
+#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
+#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
+#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
+#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
+#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h
new file mode 100644
index 000000000000..a1c7d3d17150
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v4.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_UFS_V4_H_
+#define QCOM_PHY_QMP_PCS_UFS_V4_H_
+
+/* Only for QMP V4 PHY - UFS PCS registers */
+#define QPHY_V4_PCS_UFS_PHY_START 0x000
+#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V4_PCS_UFS_SW_RESET 0x008
+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
+#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
+#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
+#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
+#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
+#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
+#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
+#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
+#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
+#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
+#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
+#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
+#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
+#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
+#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
+#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h
new file mode 100644
index 000000000000..d7fd4ac0fc55
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v4.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V4_H_
+#define QCOM_PHY_QMP_PCS_USB_V4_H_
+
+/* Only for QMP V4 PHY - USB3 PCS registers */
+#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
+#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
+#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
+#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
+#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
+#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
+#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
+#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
+#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h
new file mode 100644
index 000000000000..a2c1eba2b693
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V4_H_
+#define QCOM_PHY_QMP_PCS_V4_H_
+
+/* Only for QMP V4 PHY - USB/PCIe PCS registers */
+#define QPHY_V4_PCS_SW_RESET 0x000
+#define QPHY_V4_PCS_REVISION_ID0 0x004
+#define QPHY_V4_PCS_REVISION_ID1 0x008
+#define QPHY_V4_PCS_REVISION_ID2 0x00c
+#define QPHY_V4_PCS_REVISION_ID3 0x010
+#define QPHY_V4_PCS_PCS_STATUS1 0x014
+#define QPHY_V4_PCS_PCS_STATUS2 0x018
+#define QPHY_V4_PCS_PCS_STATUS3 0x01c
+#define QPHY_V4_PCS_PCS_STATUS4 0x020
+#define QPHY_V4_PCS_PCS_STATUS5 0x024
+#define QPHY_V4_PCS_PCS_STATUS6 0x028
+#define QPHY_V4_PCS_PCS_STATUS7 0x02c
+#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
+#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
+#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
+#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
+#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
+#define QPHY_V4_PCS_START_CONTROL 0x044
+#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
+#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
+#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
+#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
+#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
+#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
+#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
+#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
+#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
+#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
+#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
+#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
+#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
+#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
+#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
+#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
+#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
+#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
+#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
+#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
+#define QPHY_V4_PCS_FLL_CNTRL1 0x098
+#define QPHY_V4_PCS_FLL_CNTRL2 0x09c
+#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
+#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
+#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
+#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
+#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
+#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
+#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
+#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
+#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
+#define QPHY_V4_PCS_BIST_CTRL 0x0e8
+#define QPHY_V4_PCS_PRBS_POLY0 0x0ec
+#define QPHY_V4_PCS_PRBS_POLY1 0x0f0
+#define QPHY_V4_PCS_FIXED_PAT0 0x0f4
+#define QPHY_V4_PCS_FIXED_PAT1 0x0f8
+#define QPHY_V4_PCS_FIXED_PAT2 0x0fc
+#define QPHY_V4_PCS_FIXED_PAT3 0x100
+#define QPHY_V4_PCS_FIXED_PAT4 0x104
+#define QPHY_V4_PCS_FIXED_PAT5 0x108
+#define QPHY_V4_PCS_FIXED_PAT6 0x10c
+#define QPHY_V4_PCS_FIXED_PAT7 0x110
+#define QPHY_V4_PCS_FIXED_PAT8 0x114
+#define QPHY_V4_PCS_FIXED_PAT9 0x118
+#define QPHY_V4_PCS_FIXED_PAT10 0x11c
+#define QPHY_V4_PCS_FIXED_PAT11 0x120
+#define QPHY_V4_PCS_FIXED_PAT12 0x124
+#define QPHY_V4_PCS_FIXED_PAT13 0x128
+#define QPHY_V4_PCS_FIXED_PAT14 0x12c
+#define QPHY_V4_PCS_FIXED_PAT15 0x130
+#define QPHY_V4_PCS_TXMGN_CONFIG 0x134
+#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
+#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
+#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
+#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
+#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
+#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
+#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
+#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
+#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
+#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
+#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
+#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
+#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
+#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
+#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
+#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
+#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
+#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
+#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
+#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
+#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
+#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
+#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
+#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
+#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
+#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
+#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
+#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
+#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
+#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
+#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
+#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
+#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
+#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
+#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
+#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
+#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
+#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
+#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
+#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
+#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1290c62a16fe..05da0725df71 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -25,6 +25,11 @@
#include "phy-qcom-qmp-pcs-v3.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
+#include "phy-qcom-qmp-pcs-v4.h"
+#include "phy-qcom-qmp-pcs-pcie-v4.h"
+#include "phy-qcom-qmp-pcs-usb-v4.h"
+#include "phy-qcom-qmp-pcs-ufs-v4.h"
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
@@ -142,28 +147,6 @@
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
-/* Only for QMP V4 PHY - UFS PCS registers */
-#define QPHY_V4_PCS_UFS_PHY_START 0x000
-#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
-#define QPHY_V4_PCS_UFS_SW_RESET 0x008
-#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
-#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
-#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
-#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
-#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
-#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
-#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
-#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
-#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
-#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
-#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
-#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
-#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
-#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
-#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
-#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
-#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
-
/* PCIE GEN3 COM registers */
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
@@ -278,157 +261,6 @@
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
-/* Only for QMP V4 PHY - USB/PCIe PCS registers */
-#define QPHY_V4_PCS_SW_RESET 0x000
-#define QPHY_V4_PCS_REVISION_ID0 0x004
-#define QPHY_V4_PCS_REVISION_ID1 0x008
-#define QPHY_V4_PCS_REVISION_ID2 0x00c
-#define QPHY_V4_PCS_REVISION_ID3 0x010
-#define QPHY_V4_PCS_PCS_STATUS1 0x014
-#define QPHY_V4_PCS_PCS_STATUS2 0x018
-#define QPHY_V4_PCS_PCS_STATUS3 0x01c
-#define QPHY_V4_PCS_PCS_STATUS4 0x020
-#define QPHY_V4_PCS_PCS_STATUS5 0x024
-#define QPHY_V4_PCS_PCS_STATUS6 0x028
-#define QPHY_V4_PCS_PCS_STATUS7 0x02c
-#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
-#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
-#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
-#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
-#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
-#define QPHY_V4_PCS_START_CONTROL 0x044
-#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
-#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
-#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
-#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
-#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
-#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
-#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
-#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
-#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
-#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
-#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
-#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
-#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
-#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
-#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
-#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
-#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
-#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
-#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
-#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
-#define QPHY_V4_PCS_FLL_CNTRL1 0x098
-#define QPHY_V4_PCS_FLL_CNTRL2 0x09c
-#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
-#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
-#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
-#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
-#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
-#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
-#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
-#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
-#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
-#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
-#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
-#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
-#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
-#define QPHY_V4_PCS_BIST_CTRL 0x0e8
-#define QPHY_V4_PCS_PRBS_POLY0 0x0ec
-#define QPHY_V4_PCS_PRBS_POLY1 0x0f0
-#define QPHY_V4_PCS_FIXED_PAT0 0x0f4
-#define QPHY_V4_PCS_FIXED_PAT1 0x0f8
-#define QPHY_V4_PCS_FIXED_PAT2 0x0fc
-#define QPHY_V4_PCS_FIXED_PAT3 0x100
-#define QPHY_V4_PCS_FIXED_PAT4 0x104
-#define QPHY_V4_PCS_FIXED_PAT5 0x108
-#define QPHY_V4_PCS_FIXED_PAT6 0x10c
-#define QPHY_V4_PCS_FIXED_PAT7 0x110
-#define QPHY_V4_PCS_FIXED_PAT8 0x114
-#define QPHY_V4_PCS_FIXED_PAT9 0x118
-#define QPHY_V4_PCS_FIXED_PAT10 0x11c
-#define QPHY_V4_PCS_FIXED_PAT11 0x120
-#define QPHY_V4_PCS_FIXED_PAT12 0x124
-#define QPHY_V4_PCS_FIXED_PAT13 0x128
-#define QPHY_V4_PCS_FIXED_PAT14 0x12c
-#define QPHY_V4_PCS_FIXED_PAT15 0x130
-#define QPHY_V4_PCS_TXMGN_CONFIG 0x134
-#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
-#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
-#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
-#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
-#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
-#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
-#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
-#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
-#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
-#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
-#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
-#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
-#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
-#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
-#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
-#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
-#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
-#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
-#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
-#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
-#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
-#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
-#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
-#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
-#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
-#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
-#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
-#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
-#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
-#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
-#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
-#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
-#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
-#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
-#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
-#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
-#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
-#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
-#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
-#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
-#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
-#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
-#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
-#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
-#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
-#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
-
-/* Only for QMP V4 PHY - USB3 PCS registers */
-#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
-#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
-#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
-#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
-#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
-#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
-#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
-#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034
-#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038
-#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c
-#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040
-#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044
-#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048
-#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c
-#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050
-#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054
-#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058
-
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
@@ -443,20 +275,6 @@
#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
-/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
-#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
-#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
-#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
-#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
-#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
-#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
-#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
-#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
-#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
-#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
-#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
-#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
-
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
--
2.35.1
--
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linux-phy@lists.infradead.org
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 16/28] phy: qcom-qmp: move PCS V5 registers to separate headers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCS V5 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 16 +++++
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 27 ++++++++
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h | 36 +++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 17 +++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 63 ++-----------------
5 files changed, 101 insertions(+), 58 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
new file mode 100644
index 000000000000..2e19fb3f051e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
@@ -0,0 +1,16 @@
+/* Only for QMP V5 PHY - PCS_PCIE registers */
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V5_H_
+
+/* Only for QMP V5 PHY - PCS_PCIE registers */
+#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
+#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
+#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
new file mode 100644
index 000000000000..bcca23493b7e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
@@ -0,0 +1,27 @@
+/* Only for QMP V5 PHY - UFS PCS registers */
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_
+#define QCOM_PHY_QMP_PCS_UFS_V5_H_
+
+/* Only for QMP V5 PHY - UFS PCS registers */
+#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
+#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
+#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
+#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
+#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
+#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
+#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
+#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
+#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
+#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
+#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
+#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
+#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
+#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
+#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h
new file mode 100644
index 000000000000..73de626223ed
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V5_H_
+#define QCOM_PHY_QMP_PCS_USB_V5_H_
+
+/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
+#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
+#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
+#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
+#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
+#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
+#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
+#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
+#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
+#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
+#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
+#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
new file mode 100644
index 000000000000..61a44519f969
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V5_H_
+#define QCOM_PHY_QMP_PCS_V5_H_
+
+/* Only for QMP V5 PHY - USB/PCIe PCS registers */
+#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
+#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
+#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
+#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 05da0725df71..9d93ae785b16 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -30,6 +30,11 @@
#include "phy-qcom-qmp-pcs-usb-v4.h"
#include "phy-qcom-qmp-pcs-ufs-v4.h"
+#include "phy-qcom-qmp-pcs-v5.h"
+#include "phy-qcom-qmp-pcs-pcie-v5.h"
+#include "phy-qcom-qmp-pcs-usb-v5.h"
+#include "phy-qcom-qmp-pcs-ufs-v5.h"
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
@@ -334,20 +339,6 @@
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
-/* Only for QMP V5 PHY - USB/PCIe PCS registers */
-#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
-#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
-#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
-#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
-#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
-#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
-
-/* Only for QMP V5 PHY - PCS_PCIE registers */
-#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
-#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
-#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
-#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
-
/* Only for QMP V5_20 PHY - PCIe PCS registers */
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
@@ -356,48 +347,4 @@
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
-/* Only for QMP V5 PHY - UFS PCS registers */
-#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
-#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
-#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
-#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
-#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
-#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
-#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
-#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
-#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
-#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
-#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
-#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
-#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
-#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
-#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
-
-/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
-#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
-#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
-#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
-#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
-#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
-#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
-#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
-#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
-#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
-#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
-#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
-
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 16/28] phy: qcom-qmp: move PCS V5 registers to separate headers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCS V5 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 16 +++++
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 27 ++++++++
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h | 36 +++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 17 +++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 63 ++-----------------
5 files changed, 101 insertions(+), 58 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
new file mode 100644
index 000000000000..2e19fb3f051e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
@@ -0,0 +1,16 @@
+/* Only for QMP V5 PHY - PCS_PCIE registers */
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V5_H_
+
+/* Only for QMP V5 PHY - PCS_PCIE registers */
+#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
+#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
+#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
new file mode 100644
index 000000000000..bcca23493b7e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
@@ -0,0 +1,27 @@
+/* Only for QMP V5 PHY - UFS PCS registers */
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_
+#define QCOM_PHY_QMP_PCS_UFS_V5_H_
+
+/* Only for QMP V5 PHY - UFS PCS registers */
+#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
+#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
+#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
+#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
+#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
+#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
+#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
+#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
+#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
+#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
+#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
+#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
+#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
+#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
+#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h
new file mode 100644
index 000000000000..73de626223ed
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V5_H_
+#define QCOM_PHY_QMP_PCS_USB_V5_H_
+
+/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
+#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
+#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
+#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
+#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
+#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
+#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
+#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
+#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
+#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
+#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
+#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
+#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
+#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
+#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
+#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
+#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
new file mode 100644
index 000000000000..61a44519f969
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V5_H_
+#define QCOM_PHY_QMP_PCS_V5_H_
+
+/* Only for QMP V5 PHY - USB/PCIe PCS registers */
+#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
+#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
+#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
+#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 05da0725df71..9d93ae785b16 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -30,6 +30,11 @@
#include "phy-qcom-qmp-pcs-usb-v4.h"
#include "phy-qcom-qmp-pcs-ufs-v4.h"
+#include "phy-qcom-qmp-pcs-v5.h"
+#include "phy-qcom-qmp-pcs-pcie-v5.h"
+#include "phy-qcom-qmp-pcs-usb-v5.h"
+#include "phy-qcom-qmp-pcs-ufs-v5.h"
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
@@ -334,20 +339,6 @@
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
-/* Only for QMP V5 PHY - USB/PCIe PCS registers */
-#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
-#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
-#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
-#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
-#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
-#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
-
-/* Only for QMP V5 PHY - PCS_PCIE registers */
-#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
-#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
-#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
-#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
-
/* Only for QMP V5_20 PHY - PCIe PCS registers */
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
@@ -356,48 +347,4 @@
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
-/* Only for QMP V5 PHY - UFS PCS registers */
-#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
-#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
-#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
-#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
-#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
-#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
-#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
-#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
-#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
-#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
-#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
-#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
-#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
-#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
-#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
-
-/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
-#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
-#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
-#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
-#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
-#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
-#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
-#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
-#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038
-#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040
-#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048
-#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c
-#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050
-#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054
-#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058
-#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c
-#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060
-
#endif
--
2.35.1
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 17/28] phy: qcom-qmp: move PCIE QHP registers to separate header
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCIE QHP registers to the separate header. QHP is a sepecial PHY
kind used on sdm845 to drive one of PCIe links.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h | 123 +++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 116 +----------------
2 files changed, 125 insertions(+), 114 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h
new file mode 100644
index 000000000000..e4a4d2cd85eb
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCIE_QHP_H_
+#define QCOM_PHY_QMP_PCIE_QHP_H_
+
+/* PCIE GEN3 COM registers */
+#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
+#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
+#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
+#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
+#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
+#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
+#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
+#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
+#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
+#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
+#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
+#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
+#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
+#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
+#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
+#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
+#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
+#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
+#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
+#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
+#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
+#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
+#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
+#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
+#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
+#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
+#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
+#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
+#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
+#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
+#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
+#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
+#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
+#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
+#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
+
+/* PCIE GEN3 QHP Lane registers */
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
+#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
+#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
+#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
+#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
+#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
+#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
+#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
+#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
+#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
+#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
+#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
+#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
+#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
+#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
+#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
+#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
+#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
+#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
+#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
+#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
+#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
+#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
+#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
+#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
+#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
+#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
+#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
+#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
+#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
+#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
+#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
+#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
+#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
+#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
+#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
+#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
+#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
+#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
+
+/* PCIE GEN3 PCS registers */
+#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
+#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
+#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
+#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
+#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
+#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
+#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 9d93ae785b16..59510d927fec 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -35,6 +35,8 @@
#include "phy-qcom-qmp-pcs-usb-v5.h"
#include "phy-qcom-qmp-pcs-ufs-v5.h"
+#include "phy-qcom-qmp-pcie-qhp.h"
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
@@ -152,120 +154,6 @@
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
-/* PCIE GEN3 COM registers */
-#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
-#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
-#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
-#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
-#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
-#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
-#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
-#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
-#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
-#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
-#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
-#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
-#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
-#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
-#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
-#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
-#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
-#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
-#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
-#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
-#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
-#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
-#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
-#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
-#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
-#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
-#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
-#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
-#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
-#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
-#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
-#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
-#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
-#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
-#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
-#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
-#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
-#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
-#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
-
-/* PCIE GEN3 QHP Lane registers */
-#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
-#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
-#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
-#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
-#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
-#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
-#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
-#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
-#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
-#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
-#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
-#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
-#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
-#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
-#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
-#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
-#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
-#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
-#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
-#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
-#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
-#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
-#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
-#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
-#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
-#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
-#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
-#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
-#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
-#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
-#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
-#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
-#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
-#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
-#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
-#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
-#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
-#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
-#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
-#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
-#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
-#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
-#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
-#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
-#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
-#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
-#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
-#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
-#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
-#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
-#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
-#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
-#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
-#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
-#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
-#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
-
-/* PCIE GEN3 PCS registers */
-#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
-#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
-#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
-#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
-#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
-#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
-#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
-
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 17/28] phy: qcom-qmp: move PCIE QHP registers to separate header
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Move PCIE QHP registers to the separate header. QHP is a sepecial PHY
kind used on sdm845 to drive one of PCIe links.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h | 123 +++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 116 +----------------
2 files changed, 125 insertions(+), 114 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h
new file mode 100644
index 000000000000..e4a4d2cd85eb
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-qhp.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCIE_QHP_H_
+#define QCOM_PHY_QMP_PCIE_QHP_H_
+
+/* PCIE GEN3 COM registers */
+#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
+#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
+#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
+#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
+#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
+#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
+#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
+#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
+#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
+#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
+#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
+#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
+#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
+#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
+#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
+#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
+#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
+#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
+#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
+#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
+#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
+#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
+#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
+#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
+#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
+#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
+#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
+#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
+#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
+#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
+#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
+#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
+#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
+#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
+#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
+
+/* PCIE GEN3 QHP Lane registers */
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
+#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
+#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
+#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
+#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
+#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
+#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
+#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
+#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
+#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
+#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
+#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
+#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
+#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
+#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
+#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
+#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
+#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
+#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
+#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
+#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
+#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
+#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
+#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
+#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
+#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
+#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
+#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
+#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
+#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
+#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
+#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
+#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
+#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
+#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
+#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
+#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
+#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
+#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
+
+/* PCIE GEN3 PCS registers */
+#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
+#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
+#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
+#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
+#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
+#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
+#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 9d93ae785b16..59510d927fec 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -35,6 +35,8 @@
#include "phy-qcom-qmp-pcs-usb-v5.h"
#include "phy-qcom-qmp-pcs-ufs-v5.h"
+#include "phy-qcom-qmp-pcie-qhp.h"
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
#define QPHY_V3_DP_COM_SW_RESET 0x04
@@ -152,120 +154,6 @@
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
-/* PCIE GEN3 COM registers */
-#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
-#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
-#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
-#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
-#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
-#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
-#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
-#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
-#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
-#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
-#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
-#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
-#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
-#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
-#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
-#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
-#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
-#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
-#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
-#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
-#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
-#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
-#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
-#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
-#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
-#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
-#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
-#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
-#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
-#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
-#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
-#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
-#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
-#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
-#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
-#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
-#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
-#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
-#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
-#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
-
-/* PCIE GEN3 QHP Lane registers */
-#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
-#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
-#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
-#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
-#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
-#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
-#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
-#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
-#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
-#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
-#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
-#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
-#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
-#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
-#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
-#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
-#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
-#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
-#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
-#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
-#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
-#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
-#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
-#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
-#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
-#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
-#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
-#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
-#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
-#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
-#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
-#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
-#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
-#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
-#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
-#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
-#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
-#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
-#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
-#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
-#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
-#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
-#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
-#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
-#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
-#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
-#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
-#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
-#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
-#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
-#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
-#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
-#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
-#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
-#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
-#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
-
-/* PCIE GEN3 PCS registers */
-#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
-#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
-#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
-#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
-#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
-#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
-#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
-
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
--
2.35.1
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 18/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy-qcom-qmp-qserdes-txrx-v4_20.h | 43 +++++++++
.../phy-qcom-qmp-qserdes-txrx-v5_20.h | 60 +++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 88 +------------------
3 files changed, 105 insertions(+), 86 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
new file mode 100644
index 000000000000..114570f3017f
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_
+
+/* Only for QMP V4_20 PHY - TX registers */
+#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
+#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
+#define QSERDES_V4_20_TX_LANE_MODE_3 0x90
+#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
+#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
+
+/* Only for QMP V4_20 PHY - RX registers */
+#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
+#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
+#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
+#define QSERDES_V4_20_RX_DFE_3 0x110
+#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
+#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138
+#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150
+#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178
+#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8
+#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc
+#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0
+#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc
+#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200
+#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
+#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
new file mode 100644
index 000000000000..86c01104799e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
+
+/* Only for QMP V5_20 PHY - TX registers */
+#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
+#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
+#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
+#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
+
+/* Only for QMP V5_20 PHY - RX registers */
+#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
+#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
+#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
+#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
+#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
+#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
+#define QSERDES_V5_20_RX_DFE_3 0x090
+#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
+#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
+#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
+#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
+#define QSERDES_V5_20_RX_GM_CAL 0x0ec
+#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
+#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
+#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 59510d927fec..1f8684c87c06 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -14,9 +14,11 @@
#include "phy-qcom-qmp-qserdes-com-v4.h"
#include "phy-qcom-qmp-qserdes-txrx-v4.h"
+#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
#include "phy-qcom-qmp-qserdes-com-v5.h"
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
+#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
#include "phy-qcom-qmp-qserdes-pll.h"
@@ -108,14 +110,6 @@
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
-
-/* Only for QMP V4_20 PHY - TX registers */
-#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
-#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
-#define QSERDES_V4_20_TX_LANE_MODE_3 0x90
-#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
-#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
-
/* Only for QMP V4 PHY - DP PHY registers */
#define QSERDES_V4_DP_PHY_CFG_1 0x014
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
@@ -127,33 +121,6 @@
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
-/* Only for QMP V4_20 PHY - RX registers */
-#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
-#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
-#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
-#define QSERDES_V4_20_RX_DFE_3 0x110
-#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
-#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138
-#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150
-#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178
-#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8
-#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc
-#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0
-#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc
-#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200
-#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
-#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
-
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
@@ -176,57 +143,6 @@
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
-/* Only for QMP V5_20 PHY - TX registers */
-#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
-#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
-#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
-#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
-
-/* Only for QMP V5_20 PHY - RX registers */
-#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
-#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
-#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
-#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
-#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
-#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
-#define QSERDES_V5_20_RX_DFE_3 0x090
-#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
-#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
-#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
-#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
-#define QSERDES_V5_20_RX_GM_CAL 0x0ec
-#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
-#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
-#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
-
/* Only for QMP V5_20 PHY - PCIe PCS registers */
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 18/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy-qcom-qmp-qserdes-txrx-v4_20.h | 43 +++++++++
.../phy-qcom-qmp-qserdes-txrx-v5_20.h | 60 +++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 88 +------------------
3 files changed, 105 insertions(+), 86 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
new file mode 100644
index 000000000000..114570f3017f
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_
+
+/* Only for QMP V4_20 PHY - TX registers */
+#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
+#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
+#define QSERDES_V4_20_TX_LANE_MODE_3 0x90
+#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
+#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
+
+/* Only for QMP V4_20 PHY - RX registers */
+#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
+#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
+#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
+#define QSERDES_V4_20_RX_DFE_3 0x110
+#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
+#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138
+#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150
+#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178
+#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8
+#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc
+#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0
+#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4
+#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8
+#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc
+#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200
+#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
+#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
new file mode 100644
index 000000000000..86c01104799e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
+
+/* Only for QMP V5_20 PHY - TX registers */
+#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
+#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
+#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
+#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
+
+/* Only for QMP V5_20 PHY - RX registers */
+#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
+#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
+#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
+#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
+#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
+#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
+#define QSERDES_V5_20_RX_DFE_3 0x090
+#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
+#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
+#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
+#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
+#define QSERDES_V5_20_RX_GM_CAL 0x0ec
+#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
+#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
+#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
+#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
+#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
+#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
+#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 59510d927fec..1f8684c87c06 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -14,9 +14,11 @@
#include "phy-qcom-qmp-qserdes-com-v4.h"
#include "phy-qcom-qmp-qserdes-txrx-v4.h"
+#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
#include "phy-qcom-qmp-qserdes-com-v5.h"
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
+#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
#include "phy-qcom-qmp-qserdes-pll.h"
@@ -108,14 +110,6 @@
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
-
-/* Only for QMP V4_20 PHY - TX registers */
-#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
-#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
-#define QSERDES_V4_20_TX_LANE_MODE_3 0x90
-#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
-#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
-
/* Only for QMP V4 PHY - DP PHY registers */
#define QSERDES_V4_DP_PHY_CFG_1 0x014
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
@@ -127,33 +121,6 @@
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
-/* Only for QMP V4_20 PHY - RX registers */
-#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
-#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
-#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
-#define QSERDES_V4_20_RX_DFE_3 0x110
-#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
-#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138
-#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150
-#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178
-#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8
-#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc
-#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0
-#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4
-#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8
-#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc
-#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200
-#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
-#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
-
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
@@ -176,57 +143,6 @@
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
-/* Only for QMP V5_20 PHY - TX registers */
-#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
-#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
-#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
-#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
-
-/* Only for QMP V5_20 PHY - RX registers */
-#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
-#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
-#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
-#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
-#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
-#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
-#define QSERDES_V5_20_RX_DFE_3 0x090
-#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
-#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
-#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
-#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
-#define QSERDES_V5_20_RX_GM_CAL 0x0ec
-#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
-#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
-#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
-#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
-#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
-#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
-#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
-
/* Only for QMP V5_20 PHY - PCIe PCS registers */
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 19/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 17 ++++++++++++
.../qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 17 ++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h | 15 +++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 27 ++++---------------
4 files changed, 54 insertions(+), 22 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
new file mode 100644
index 000000000000..af273602998e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+
+#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
+#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
+#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
+#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
+#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
+#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
+#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
new file mode 100644
index 000000000000..1eedf50cf9cb
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
+
+/* Only for QMP V5_20 PHY - PCIe PCS registers */
+#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
+#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
+#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
+#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
+#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
+#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
new file mode 100644
index 000000000000..08c3dd115488
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V4_20_H_
+#define QCOM_PHY_QMP_PCS_V4_20_H_
+
+/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
+#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
+#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
+#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1f8684c87c06..cdbbcf6b5686 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -32,11 +32,16 @@
#include "phy-qcom-qmp-pcs-usb-v4.h"
#include "phy-qcom-qmp-pcs-ufs-v4.h"
+#include "phy-qcom-qmp-pcs-v4_20.h"
+#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
+
#include "phy-qcom-qmp-pcs-v5.h"
#include "phy-qcom-qmp-pcs-pcie-v5.h"
#include "phy-qcom-qmp-pcs-usb-v5.h"
#include "phy-qcom-qmp-pcs-ufs-v5.h"
+#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
+
#include "phy-qcom-qmp-pcie-qhp.h"
/* Only for QMP V3 & V4 PHY - DP COM registers */
@@ -121,12 +126,6 @@
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
-/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
-#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
-#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
-#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
-#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
-
/* Only for QMP V4 PHY - PCS_MISC registers */
#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
@@ -135,20 +134,4 @@
#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
-#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
-#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
-#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
-#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
-#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
-#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
-#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
-
-/* Only for QMP V5_20 PHY - PCIe PCS registers */
-#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
-#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
-#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
-#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
-#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
-#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
-
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 19/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 17 ++++++++++++
.../qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 17 ++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h | 15 +++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 27 ++++---------------
4 files changed, 54 insertions(+), 22 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
new file mode 100644
index 000000000000..af273602998e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+
+#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
+#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
+#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
+#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
+#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
+#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
+#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
new file mode 100644
index 000000000000..1eedf50cf9cb
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
+
+/* Only for QMP V5_20 PHY - PCIe PCS registers */
+#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
+#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
+#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
+#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
+#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
+#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
new file mode 100644
index 000000000000..08c3dd115488
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V4_20_H_
+#define QCOM_PHY_QMP_PCS_V4_20_H_
+
+/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
+#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
+#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
+#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1f8684c87c06..cdbbcf6b5686 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -32,11 +32,16 @@
#include "phy-qcom-qmp-pcs-usb-v4.h"
#include "phy-qcom-qmp-pcs-ufs-v4.h"
+#include "phy-qcom-qmp-pcs-v4_20.h"
+#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
+
#include "phy-qcom-qmp-pcs-v5.h"
#include "phy-qcom-qmp-pcs-pcie-v5.h"
#include "phy-qcom-qmp-pcs-usb-v5.h"
#include "phy-qcom-qmp-pcs-ufs-v5.h"
+#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
+
#include "phy-qcom-qmp-pcie-qhp.h"
/* Only for QMP V3 & V4 PHY - DP COM registers */
@@ -121,12 +126,6 @@
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
-/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
-#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
-#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8
-#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0
-#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4
-
/* Only for QMP V4 PHY - PCS_MISC registers */
#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
@@ -135,20 +134,4 @@
#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
-#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
-#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
-#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
-#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
-#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
-#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
-#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
-
-/* Only for QMP V5_20 PHY - PCIe PCS registers */
-#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
-#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
-#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
-#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
-#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
-#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
-
#endif
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 20/28] phy: qcom-qmp: split PCS_UFS V3 symbols to separate header
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Several registers defined in the PCS V3 namespace in reality belong to
the PCS_UFS V3 register space. Move them to the separate header and
rename them to explicitly mention PCS_UFS. While we are at it, correct
one register in the msm8998_usb3_pcs_tbl table to use PCS register name.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h | 18 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 8 --------
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 16 ++++++++--------
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 2 +-
drivers/phy/qualcomm/phy-qcom-qmp.h | 1 +
5 files changed, 28 insertions(+), 17 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
new file mode 100644
index 000000000000..ba1ea29d2884
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
+#define QCOM_PHY_QMP_PCS_UFS_V3_H_
+
+#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
+#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
+#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
+#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
+#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
+#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
+#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
+#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
index 0b023df19126..ac13f2989a73 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
@@ -14,8 +14,6 @@
#define QPHY_V3_PCS_TXMGN_V3 0x018
#define QPHY_V3_PCS_TXMGN_V4 0x01c
#define QPHY_V3_PCS_TXMGN_LS 0x020
-#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
-#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
@@ -53,15 +51,9 @@
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
-#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
-#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
-#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
-#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
-#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
-#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index bfe5f562bcd0..701b03a13b17 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -389,14 +389,14 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
};
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index fd169daffb02..98c6b5c8e2fc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -634,7 +634,7 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index cdbbcf6b5686..b139c8af5e8b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -26,6 +26,7 @@
#include "phy-qcom-qmp-pcs-v3.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
+#include "phy-qcom-qmp-pcs-ufs-v3.h"
#include "phy-qcom-qmp-pcs-v4.h"
#include "phy-qcom-qmp-pcs-pcie-v4.h"
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 20/28] phy: qcom-qmp: split PCS_UFS V3 symbols to separate header
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Several registers defined in the PCS V3 namespace in reality belong to
the PCS_UFS V3 register space. Move them to the separate header and
rename them to explicitly mention PCS_UFS. While we are at it, correct
one register in the msm8998_usb3_pcs_tbl table to use PCS register name.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h | 18 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 8 --------
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 16 ++++++++--------
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 2 +-
drivers/phy/qualcomm/phy-qcom-qmp.h | 1 +
5 files changed, 28 insertions(+), 17 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
new file mode 100644
index 000000000000..ba1ea29d2884
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
+#define QCOM_PHY_QMP_PCS_UFS_V3_H_
+
+#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
+#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
+#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
+#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
+#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
+#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
+#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
+#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
index 0b023df19126..ac13f2989a73 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
@@ -14,8 +14,6 @@
#define QPHY_V3_PCS_TXMGN_V3 0x018
#define QPHY_V3_PCS_TXMGN_V4 0x01c
#define QPHY_V3_PCS_TXMGN_LS 0x020
-#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
-#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
@@ -53,15 +51,9 @@
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
-#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
-#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
-#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
-#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
-#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
-#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index bfe5f562bcd0..701b03a13b17 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -389,14 +389,14 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
};
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index fd169daffb02..98c6b5c8e2fc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -634,7 +634,7 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index cdbbcf6b5686..b139c8af5e8b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -26,6 +26,7 @@
#include "phy-qcom-qmp-pcs-v3.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
+#include "phy-qcom-qmp-pcs-ufs-v3.h"
#include "phy-qcom-qmp-pcs-v4.h"
#include "phy-qcom-qmp-pcs-pcie-v4.h"
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 21/28] phy: qcom-qmp: qserdes-com: add missing registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-3.18's phy-qcom-ufs-qmp-14nm.h
- msm-3.18's mdss-hdmi-pll-8996.c
- msm-5.4's ep_pcie_phy.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 +-
.../phy/qualcomm/phy-qcom-qmp-qserdes-com.h | 57 ++++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h | 163 +++++++++++++++++-
3 files changed, 220 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 2992ef6603f3..9e3889cbd645 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -423,7 +423,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
};
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
index 9dfa80263707..fbaf6ef467f8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
@@ -7,6 +7,9 @@
#define QCOM_PHY_QMP_QSERDES_COM_H_
/* Only for QMP V2 PHY - QSERDES COM registers */
+#define QSERDES_COM_ATB_SEL1 0x000
+#define QSERDES_COM_ATB_SEL2 0x004
+#define QSERDES_COM_FREQ_UPDATE 0x008
#define QSERDES_COM_BG_TIMER 0x00c
#define QSERDES_COM_SSC_EN_CENTER 0x010
#define QSERDES_COM_SSC_ADJ_PER1 0x014
@@ -15,10 +18,13 @@
#define QSERDES_COM_SSC_PER2 0x020
#define QSERDES_COM_SSC_STEP_SIZE1 0x024
#define QSERDES_COM_SSC_STEP_SIZE2 0x028
+#define QSERDES_COM_POST_DIV 0x02c
+#define QSERDES_COM_POST_DIV_MUX 0x030
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
#define QSERDES_COM_CLK_ENABLE1 0x038
#define QSERDES_COM_SYS_CLK_CTRL 0x03c
#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
+#define QSERDES_COM_PLL_EN 0x044
#define QSERDES_COM_PLL_IVCO 0x048
#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
@@ -26,58 +32,109 @@
#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
+#define QSERDES_COM_LOCK_CMP1_MODE2 0x064
+#define QSERDES_COM_CMN_RSVD0 0x064
+#define QSERDES_COM_LOCK_CMP2_MODE2 0x068
+#define QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x068
+#define QSERDES_COM_LOCK_CMP3_MODE2 0x06c
+#define QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x06c
#define QSERDES_COM_BG_TRIM 0x070
#define QSERDES_COM_CLK_EP_DIV 0x074
#define QSERDES_COM_CP_CTRL_MODE0 0x078
#define QSERDES_COM_CP_CTRL_MODE1 0x07c
+#define QSERDES_COM_CP_CTRL_MODE2 0x080
+#define QSERDES_COM_CMN_RSVD1 0x080
#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
+#define QSERDES_COM_PLL_RCTRL_MODE2 0x08c
+#define QSERDES_COM_CMN_RSVD2 0x08c
#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
+#define QSERDES_COM_PLL_CCTRL_MODE2 0x098
+#define QSERDES_COM_CMN_RSVD3 0x098
+#define QSERDES_COM_PLL_CNTRL 0x09c
+#define QSERDES_COM_PHASE_SEL_CTRL 0x0a0
+#define QSERDES_COM_PHASE_SEL_DC 0x0a4
+#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x0a8
#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
+#define QSERDES_COM_CML_SYSCLK_SEL 0x0b0
#define QSERDES_COM_RESETSM_CNTRL 0x0b4
#define QSERDES_COM_RESETSM_CNTRL2 0x0b8
#define QSERDES_COM_RESTRIM_CTRL 0x0bc
+#define QSERDES_COM_RESTRIM_CTRL2 0x0c0
#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
#define QSERDES_COM_LOCK_CMP_EN 0x0c8
#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
#define QSERDES_COM_DEC_START_MODE0 0x0d0
#define QSERDES_COM_DEC_START_MODE1 0x0d4
+#define QSERDES_COM_DEC_START_MODE2 0x0d8
+#define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0d8
#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
+#define QSERDES_COM_DIV_FRAC_START1_MODE2 0x0f4
+#define QSERDES_COM_VCO_TUNE_MINVAL1 0x0f4
+#define QSERDES_COM_DIV_FRAC_START2_MODE2 0x0f8
+#define QSERDES_COM_VCO_TUNE_MINVAL2 0x0f8
+#define QSERDES_COM_DIV_FRAC_START3_MODE2 0x0fc
+#define QSERDES_COM_CMN_RSVD4 0x0fc
#define QSERDES_COM_INTEGLOOP_INITVAL 0x100
+#define QSERDES_COM_INTEGLOOP_EN 0x104
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x118
+#define QSERDES_COM_VCO_TUNE_MAXVAL1 0x118
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x11c
+#define QSERDES_COM_VCO_TUNE_MAXVAL2 0x11c
+#define QSERDES_COM_RES_TRIM_CONTROL2 0x120
#define QSERDES_COM_VCO_TUNE_CTRL 0x124
#define QSERDES_COM_VCO_TUNE_MAP 0x128
#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
+#define QSERDES_COM_VCO_TUNE1_MODE2 0x13c
#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
+#define QSERDES_COM_VCO_TUNE2_MODE2 0x140
#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
+#define QSERDES_COM_SAR 0x14c
+#define QSERDES_COM_SAR_CLK 0x150
+#define QSERDES_COM_SAR_CODE_OUT_STATUS 0x154
+#define QSERDES_COM_SAR_CODE_READY_STATUS 0x158
+#define QSERDES_COM_CMN_STATUS 0x15c
+#define QSERDES_COM_RESET_SM_STATUS 0x160
+#define QSERDES_COM_RESTRIM_CODE_STATUS 0x164
+#define QSERDES_COM_PLLCAL_CODE1_STATUS 0x168
+#define QSERDES_COM_PLLCAL_CODE2_STATUS 0x16c
#define QSERDES_COM_BG_CTRL 0x170
#define QSERDES_COM_CLK_SELECT 0x174
#define QSERDES_COM_HSCLK_SEL 0x178
+#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x17c
+#define QSERDES_COM_PLL_ANALOG 0x180
#define QSERDES_COM_CORECLK_DIV 0x184
+#define QSERDES_COM_SW_RESET 0x188
#define QSERDES_COM_CORE_CLK_EN 0x18c
#define QSERDES_COM_C_READY_STATUS 0x190
#define QSERDES_COM_CMN_CONFIG 0x194
+#define QSERDES_COM_CMN_RATE_OVERRIDE 0x198
#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
#define QSERDES_COM_DEBUG_BUS0 0x1a0
#define QSERDES_COM_DEBUG_BUS1 0x1a4
#define QSERDES_COM_DEBUG_BUS2 0x1a8
#define QSERDES_COM_DEBUG_BUS3 0x1ac
#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
+#define QSERDES_COM_CMN_MISC1 0x1b4
+#define QSERDES_COM_CMN_MISC2 0x1b8
#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
+#define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0
+#define QSERDES_COM_CMN_RSVD5 0x1c0
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
index 583098a88b65..d20694513eb4 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
@@ -7,31 +7,143 @@
#define QCOM_PHY_QMP_QSERDES_TXRX_H_
/* Only for QMP V2 PHY - TX registers */
-#define QSERDES_TX_EMP_POST1_LVL 0x018
+#define QSERDES_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_TX_BIST_INVERT 0x004
+#define QSERDES_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_TX_CMN_CONTROL_ONE 0x00c
+#define QSERDES_TX_CMN_CONTROL_TWO 0x010
+#define QSERDES_TX_CMN_CONTROL_THREE 0x014
+#define QSERDES_TX_TX_EMP_POST1_LVL 0x018
+#define QSERDES_TX_TX_POST2_EMPH 0x01c
+#define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
+#define QSERDES_TX_HP_PD_ENABLES 0x024
+#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x028
+#define QSERDES_TX_TX_DRV_LVL 0x02c
+#define QSERDES_TX_TX_DRV_LVL_OFFSET 0x030
+#define QSERDES_TX_RESET_TSYNC_EN 0x034
+#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x038
+#define QSERDES_TX_TX_BAND 0x03c
#define QSERDES_TX_SLEW_CNTL 0x040
+#define QSERDES_TX_INTERFACE_SELECT 0x044
+#define QSERDES_TX_LPB_EN 0x048
+#define QSERDES_TX_RES_CODE_LANE_TX 0x04c
+#define QSERDES_TX_RES_CODE_LANE_RX 0x050
#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
+#define QSERDES_TX_PERL_LENGTH1 0x058
+#define QSERDES_TX_PERL_LENGTH2 0x05c
+#define QSERDES_TX_SERDES_BYP_EN_OUT 0x060
#define QSERDES_TX_DEBUG_BUS_SEL 0x064
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
+#define QSERDES_TX_TX_POL_INV 0x06c
+#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x070
+#define QSERDES_TX_BIST_PATTERN1 0x074
+#define QSERDES_TX_BIST_PATTERN2 0x078
+#define QSERDES_TX_BIST_PATTERN3 0x07c
+#define QSERDES_TX_BIST_PATTERN4 0x080
+#define QSERDES_TX_BIST_PATTERN5 0x084
+#define QSERDES_TX_BIST_PATTERN6 0x088
+#define QSERDES_TX_BIST_PATTERN7 0x08c
+#define QSERDES_TX_BIST_PATTERN8 0x090
#define QSERDES_TX_LANE_MODE 0x094
+#define QSERDES_TX_IDAC_CAL_LANE_MODE 0x098
+#define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x09c
+#define QSERDES_TX_ATB_SEL1 0x0a0
+#define QSERDES_TX_ATB_SEL2 0x0a4
+#define QSERDES_TX_RCV_DETECT_LVL 0x0a8
#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
+#define QSERDES_TX_PRBS_SEED1 0x0b0
+#define QSERDES_TX_PRBS_SEED2 0x0b4
+#define QSERDES_TX_PRBS_SEED3 0x0b8
+#define QSERDES_TX_PRBS_SEED4 0x0bc
+#define QSERDES_TX_RESET_GEN 0x0c0
+#define QSERDES_TX_RESET_GEN_MUXES 0x0c4
+#define QSERDES_TX_TRAN_DRVR_EMP_EN 0x0c8
+#define QSERDES_TX_TX_INTERFACE_MODE 0x0cc
+#define QSERDES_TX_PWM_CTRL 0x0d0
+#define QSERDES_TX_PWM_ENCODED_OR_DATA 0x0d4
+#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0d8
+#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0dc
+#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0e0
+#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0e4
+#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0e8
+#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0ec
+#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0f0
+#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0f4
+#define QSERDES_TX_VMODE_CTRL1 0x0f8
+#define QSERDES_TX_VMODE_CTRL2 0x0fc
+#define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL 0x100
+#define QSERDES_TX_BIST_STATUS 0x104
+#define QSERDES_TX_BIST_ERROR_COUNT1 0x108
+#define QSERDES_TX_BIST_ERROR_COUNT2 0x10c
+#define QSERDES_TX_TX_ALOG_INTF_OBSV 0x110
/* Only for QMP V2 PHY - RX registers */
+#define QSERDES_RX_UCDR_FO_GAIN_HALF 0x000
+#define QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x004
+#define QSERDES_RX_UCDR_FO_GAIN_EIGHTH 0x008
+#define QSERDES_RX_UCDR_FO_GAIN 0x00c
#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
+#define QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x014
+#define QSERDES_RX_UCDR_SO_GAIN_EIGHTH 0x018
#define QSERDES_RX_UCDR_SO_GAIN 0x01c
+#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x020
+#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x024
+#define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH 0x028
+#define QSERDES_RX_UCDR_SVS_FO_GAIN 0x02c
#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
+#define QSERDES_RX_UCDR_FD_GAIN 0x044
#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
+#define QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x04c
+#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x050
+#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x054
+#define QSERDES_RX_UCDR_MODULATE 0x058
+#define QSERDES_RX_UCDR_PI_CONTROLS 0x05c
+#define QSERDES_RX_RBIST_CONTROL 0x060
+#define QSERDES_RX_AUX_CONTROL 0x064
+#define QSERDES_RX_AUX_DATA_TCOARSE 0x068
+#define QSERDES_RX_AUX_DATA_TFINE_LSB 0x06c
+#define QSERDES_RX_AUX_DATA_TFINE_MSB 0x070
+#define QSERDES_RX_RCLK_AUXDATA_SEL 0x074
+#define QSERDES_RX_AC_JTAG_ENABLE 0x078
+#define QSERDES_RX_AC_JTAG_INITP 0x07c
+#define QSERDES_RX_AC_JTAG_INITN 0x080
+#define QSERDES_RX_AC_JTAG_LVL 0x084
+#define QSERDES_RX_AC_JTAG_MODE 0x088
+#define QSERDES_RX_AC_JTAG_RESET 0x08c
#define QSERDES_RX_RX_TERM_BW 0x090
+#define QSERDES_RX_RX_RCVR_IQ_EN 0x094
+#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x098
+#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x09c
+#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0a0
+#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0a4
+#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0a8
+#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x0ac
+#define QSERDES_RX_RX_IDAC_EN 0x0b0
+#define QSERDES_RX_RX_IDAC_ENABLES 0x0b4
+#define QSERDES_RX_RX_IDAC_SIGN 0x0b8
+#define QSERDES_RX_RX_HIGHZ_HIGHRATE 0x0bc
+#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0c0
#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d4
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
+#define QSERDES_RX_RX_IDAC_CAL_CONFIGURATION 0x0e4
+#define QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x0e8
+#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x0ec
+#define QSERDES_RX_RX_IDAC_ENDSAMP_LOW 0x0f0
+#define QSERDES_RX_RX_IDAC_ENDSAMP_HIGH 0x0f4
+#define QSERDES_RX_RX_IDAC_MIDPOINT_LOW 0x0f8
+#define QSERDES_RX_RX_IDAC_MIDPOINT_HIGH 0x0fc
+#define QSERDES_RX_RX_EQ_OFFSET_LSB 0x100
+#define QSERDES_RX_RX_EQ_OFFSET_MSB 0x104
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
#define QSERDES_RX_SIGDET_ENABLES 0x110
@@ -39,6 +151,55 @@
#define QSERDES_RX_SIGDET_LVL 0x118
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
#define QSERDES_RX_RX_BAND 0x120
+#define QSERDES_RX_CDR_FREEZE_UP_DN 0x124
+#define QSERDES_RX_CDR_RESET_OVERRIDE 0x128
#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
+#define QSERDES_RX_JITTER_GEN_MODE 0x130
+#define QSERDES_RX_BUJ_AMP 0x134
+#define QSERDES_RX_SJ_AMP1 0x138
+#define QSERDES_RX_SJ_AMP2 0x13c
+#define QSERDES_RX_SJ_PER1 0x140
+#define QSERDES_RX_SJ_PER2 0x144
+#define QSERDES_RX_BUJ_STEP_FREQ1 0x148
+#define QSERDES_RX_BUJ_STEP_FREQ2 0x14c
+#define QSERDES_RX_PPM_OFFSET1 0x150
+#define QSERDES_RX_PPM_OFFSET2 0x154
+#define QSERDES_RX_SIGN_PPM_PERIOD1 0x158
+#define QSERDES_RX_SIGN_PPM_PERIOD2 0x15c
+#define QSERDES_RX_SSC_CTRL 0x160
+#define QSERDES_RX_SSC_COUNT1 0x164
+#define QSERDES_RX_SSC_COUNT2 0x168
+#define QSERDES_RX_RX_ALOG_INTF_OBSV_CNTL 0x16c
+#define QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x170
+#define QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x174
+#define QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x178
+#define QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x17c
+#define QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x180
+#define QSERDES_RX_PI_CTRL1 0x184
+#define QSERDES_RX_PI_CTRL2 0x188
+#define QSERDES_RX_PI_QUAD 0x18c
+#define QSERDES_RX_IDATA1 0x190
+#define QSERDES_RX_IDATA2 0x194
+#define QSERDES_RX_AUX_DATA1 0x198
+#define QSERDES_RX_AUX_DATA2 0x19c
+#define QSERDES_RX_AC_JTAG_OUTP 0x1a0
+#define QSERDES_RX_AC_JTAG_OUTN 0x1a4
+#define QSERDES_RX_RX_SIGDET 0x1a8
+#define QSERDES_RX_RX_VDCOFF 0x1ac
+#define QSERDES_RX_IDAC_CAL_ON 0x1b0
+#define QSERDES_RX_IDAC_STATUS_I 0x1b4
+#define QSERDES_RX_IDAC_STATUS_IBAR 0x1b8
+#define QSERDES_RX_IDAC_STATUS_Q 0x1bc
+#define QSERDES_RX_IDAC_STATUS_QBAR 0x1c0
+#define QSERDES_RX_IDAC_STATUS_A 0x1c4
+#define QSERDES_RX_IDAC_STATUS_ABAR 0x1c8
+#define QSERDES_RX_CALST_STATUS_I 0x1cc
+#define QSERDES_RX_CALST_STATUS_Q 0x1d0
+#define QSERDES_RX_CALST_STATUS_A 0x1d4
+#define QSERDES_RX_RX_ALOG_INTF_OBSV 0x1d8
+#define QSERDES_RX_READ_EQCODE 0x1dc
+#define QSERDES_RX_READ_OFFSETCODE 0x1e0
+#define QSERDES_RX_IA_ERROR_COUNTER_LOW 0x1e4
+#define QSERDES_RX_IA_ERROR_COUNTER_HIGH 0x1e8
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 21/28] phy: qcom-qmp: qserdes-com: add missing registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-3.18's phy-qcom-ufs-qmp-14nm.h
- msm-3.18's mdss-hdmi-pll-8996.c
- msm-5.4's ep_pcie_phy.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 +-
.../phy/qualcomm/phy-qcom-qmp-qserdes-com.h | 57 ++++++
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h | 163 +++++++++++++++++-
3 files changed, 220 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 2992ef6603f3..9e3889cbd645 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -423,7 +423,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
};
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
index 9dfa80263707..fbaf6ef467f8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h
@@ -7,6 +7,9 @@
#define QCOM_PHY_QMP_QSERDES_COM_H_
/* Only for QMP V2 PHY - QSERDES COM registers */
+#define QSERDES_COM_ATB_SEL1 0x000
+#define QSERDES_COM_ATB_SEL2 0x004
+#define QSERDES_COM_FREQ_UPDATE 0x008
#define QSERDES_COM_BG_TIMER 0x00c
#define QSERDES_COM_SSC_EN_CENTER 0x010
#define QSERDES_COM_SSC_ADJ_PER1 0x014
@@ -15,10 +18,13 @@
#define QSERDES_COM_SSC_PER2 0x020
#define QSERDES_COM_SSC_STEP_SIZE1 0x024
#define QSERDES_COM_SSC_STEP_SIZE2 0x028
+#define QSERDES_COM_POST_DIV 0x02c
+#define QSERDES_COM_POST_DIV_MUX 0x030
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
#define QSERDES_COM_CLK_ENABLE1 0x038
#define QSERDES_COM_SYS_CLK_CTRL 0x03c
#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
+#define QSERDES_COM_PLL_EN 0x044
#define QSERDES_COM_PLL_IVCO 0x048
#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
@@ -26,58 +32,109 @@
#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
+#define QSERDES_COM_LOCK_CMP1_MODE2 0x064
+#define QSERDES_COM_CMN_RSVD0 0x064
+#define QSERDES_COM_LOCK_CMP2_MODE2 0x068
+#define QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x068
+#define QSERDES_COM_LOCK_CMP3_MODE2 0x06c
+#define QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x06c
#define QSERDES_COM_BG_TRIM 0x070
#define QSERDES_COM_CLK_EP_DIV 0x074
#define QSERDES_COM_CP_CTRL_MODE0 0x078
#define QSERDES_COM_CP_CTRL_MODE1 0x07c
+#define QSERDES_COM_CP_CTRL_MODE2 0x080
+#define QSERDES_COM_CMN_RSVD1 0x080
#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
+#define QSERDES_COM_PLL_RCTRL_MODE2 0x08c
+#define QSERDES_COM_CMN_RSVD2 0x08c
#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
+#define QSERDES_COM_PLL_CCTRL_MODE2 0x098
+#define QSERDES_COM_CMN_RSVD3 0x098
+#define QSERDES_COM_PLL_CNTRL 0x09c
+#define QSERDES_COM_PHASE_SEL_CTRL 0x0a0
+#define QSERDES_COM_PHASE_SEL_DC 0x0a4
+#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x0a8
#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
+#define QSERDES_COM_CML_SYSCLK_SEL 0x0b0
#define QSERDES_COM_RESETSM_CNTRL 0x0b4
#define QSERDES_COM_RESETSM_CNTRL2 0x0b8
#define QSERDES_COM_RESTRIM_CTRL 0x0bc
+#define QSERDES_COM_RESTRIM_CTRL2 0x0c0
#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
#define QSERDES_COM_LOCK_CMP_EN 0x0c8
#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
#define QSERDES_COM_DEC_START_MODE0 0x0d0
#define QSERDES_COM_DEC_START_MODE1 0x0d4
+#define QSERDES_COM_DEC_START_MODE2 0x0d8
+#define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0d8
#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
+#define QSERDES_COM_DIV_FRAC_START1_MODE2 0x0f4
+#define QSERDES_COM_VCO_TUNE_MINVAL1 0x0f4
+#define QSERDES_COM_DIV_FRAC_START2_MODE2 0x0f8
+#define QSERDES_COM_VCO_TUNE_MINVAL2 0x0f8
+#define QSERDES_COM_DIV_FRAC_START3_MODE2 0x0fc
+#define QSERDES_COM_CMN_RSVD4 0x0fc
#define QSERDES_COM_INTEGLOOP_INITVAL 0x100
+#define QSERDES_COM_INTEGLOOP_EN 0x104
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x118
+#define QSERDES_COM_VCO_TUNE_MAXVAL1 0x118
+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x11c
+#define QSERDES_COM_VCO_TUNE_MAXVAL2 0x11c
+#define QSERDES_COM_RES_TRIM_CONTROL2 0x120
#define QSERDES_COM_VCO_TUNE_CTRL 0x124
#define QSERDES_COM_VCO_TUNE_MAP 0x128
#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
+#define QSERDES_COM_VCO_TUNE1_MODE2 0x13c
#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c
+#define QSERDES_COM_VCO_TUNE2_MODE2 0x140
#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140
#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
+#define QSERDES_COM_SAR 0x14c
+#define QSERDES_COM_SAR_CLK 0x150
+#define QSERDES_COM_SAR_CODE_OUT_STATUS 0x154
+#define QSERDES_COM_SAR_CODE_READY_STATUS 0x158
+#define QSERDES_COM_CMN_STATUS 0x15c
+#define QSERDES_COM_RESET_SM_STATUS 0x160
+#define QSERDES_COM_RESTRIM_CODE_STATUS 0x164
+#define QSERDES_COM_PLLCAL_CODE1_STATUS 0x168
+#define QSERDES_COM_PLLCAL_CODE2_STATUS 0x16c
#define QSERDES_COM_BG_CTRL 0x170
#define QSERDES_COM_CLK_SELECT 0x174
#define QSERDES_COM_HSCLK_SEL 0x178
+#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x17c
+#define QSERDES_COM_PLL_ANALOG 0x180
#define QSERDES_COM_CORECLK_DIV 0x184
+#define QSERDES_COM_SW_RESET 0x188
#define QSERDES_COM_CORE_CLK_EN 0x18c
#define QSERDES_COM_C_READY_STATUS 0x190
#define QSERDES_COM_CMN_CONFIG 0x194
+#define QSERDES_COM_CMN_RATE_OVERRIDE 0x198
#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
#define QSERDES_COM_DEBUG_BUS0 0x1a0
#define QSERDES_COM_DEBUG_BUS1 0x1a4
#define QSERDES_COM_DEBUG_BUS2 0x1a8
#define QSERDES_COM_DEBUG_BUS3 0x1ac
#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
+#define QSERDES_COM_CMN_MISC1 0x1b4
+#define QSERDES_COM_CMN_MISC2 0x1b8
#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
+#define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0
+#define QSERDES_COM_CMN_RSVD5 0x1c0
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
index 583098a88b65..d20694513eb4 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
@@ -7,31 +7,143 @@
#define QCOM_PHY_QMP_QSERDES_TXRX_H_
/* Only for QMP V2 PHY - TX registers */
-#define QSERDES_TX_EMP_POST1_LVL 0x018
+#define QSERDES_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_TX_BIST_INVERT 0x004
+#define QSERDES_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_TX_CMN_CONTROL_ONE 0x00c
+#define QSERDES_TX_CMN_CONTROL_TWO 0x010
+#define QSERDES_TX_CMN_CONTROL_THREE 0x014
+#define QSERDES_TX_TX_EMP_POST1_LVL 0x018
+#define QSERDES_TX_TX_POST2_EMPH 0x01c
+#define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
+#define QSERDES_TX_HP_PD_ENABLES 0x024
+#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x028
+#define QSERDES_TX_TX_DRV_LVL 0x02c
+#define QSERDES_TX_TX_DRV_LVL_OFFSET 0x030
+#define QSERDES_TX_RESET_TSYNC_EN 0x034
+#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x038
+#define QSERDES_TX_TX_BAND 0x03c
#define QSERDES_TX_SLEW_CNTL 0x040
+#define QSERDES_TX_INTERFACE_SELECT 0x044
+#define QSERDES_TX_LPB_EN 0x048
+#define QSERDES_TX_RES_CODE_LANE_TX 0x04c
+#define QSERDES_TX_RES_CODE_LANE_RX 0x050
#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
+#define QSERDES_TX_PERL_LENGTH1 0x058
+#define QSERDES_TX_PERL_LENGTH2 0x05c
+#define QSERDES_TX_SERDES_BYP_EN_OUT 0x060
#define QSERDES_TX_DEBUG_BUS_SEL 0x064
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
+#define QSERDES_TX_TX_POL_INV 0x06c
+#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x070
+#define QSERDES_TX_BIST_PATTERN1 0x074
+#define QSERDES_TX_BIST_PATTERN2 0x078
+#define QSERDES_TX_BIST_PATTERN3 0x07c
+#define QSERDES_TX_BIST_PATTERN4 0x080
+#define QSERDES_TX_BIST_PATTERN5 0x084
+#define QSERDES_TX_BIST_PATTERN6 0x088
+#define QSERDES_TX_BIST_PATTERN7 0x08c
+#define QSERDES_TX_BIST_PATTERN8 0x090
#define QSERDES_TX_LANE_MODE 0x094
+#define QSERDES_TX_IDAC_CAL_LANE_MODE 0x098
+#define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x09c
+#define QSERDES_TX_ATB_SEL1 0x0a0
+#define QSERDES_TX_ATB_SEL2 0x0a4
+#define QSERDES_TX_RCV_DETECT_LVL 0x0a8
#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
+#define QSERDES_TX_PRBS_SEED1 0x0b0
+#define QSERDES_TX_PRBS_SEED2 0x0b4
+#define QSERDES_TX_PRBS_SEED3 0x0b8
+#define QSERDES_TX_PRBS_SEED4 0x0bc
+#define QSERDES_TX_RESET_GEN 0x0c0
+#define QSERDES_TX_RESET_GEN_MUXES 0x0c4
+#define QSERDES_TX_TRAN_DRVR_EMP_EN 0x0c8
+#define QSERDES_TX_TX_INTERFACE_MODE 0x0cc
+#define QSERDES_TX_PWM_CTRL 0x0d0
+#define QSERDES_TX_PWM_ENCODED_OR_DATA 0x0d4
+#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0d8
+#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0dc
+#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0e0
+#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0e4
+#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0e8
+#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0ec
+#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0f0
+#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0f4
+#define QSERDES_TX_VMODE_CTRL1 0x0f8
+#define QSERDES_TX_VMODE_CTRL2 0x0fc
+#define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL 0x100
+#define QSERDES_TX_BIST_STATUS 0x104
+#define QSERDES_TX_BIST_ERROR_COUNT1 0x108
+#define QSERDES_TX_BIST_ERROR_COUNT2 0x10c
+#define QSERDES_TX_TX_ALOG_INTF_OBSV 0x110
/* Only for QMP V2 PHY - RX registers */
+#define QSERDES_RX_UCDR_FO_GAIN_HALF 0x000
+#define QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x004
+#define QSERDES_RX_UCDR_FO_GAIN_EIGHTH 0x008
+#define QSERDES_RX_UCDR_FO_GAIN 0x00c
#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
+#define QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x014
+#define QSERDES_RX_UCDR_SO_GAIN_EIGHTH 0x018
#define QSERDES_RX_UCDR_SO_GAIN 0x01c
+#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x020
+#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x024
+#define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH 0x028
+#define QSERDES_RX_UCDR_SVS_FO_GAIN 0x02c
#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030
#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034
#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038
#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
+#define QSERDES_RX_UCDR_FD_GAIN 0x044
#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
+#define QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x04c
+#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x050
+#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x054
+#define QSERDES_RX_UCDR_MODULATE 0x058
+#define QSERDES_RX_UCDR_PI_CONTROLS 0x05c
+#define QSERDES_RX_RBIST_CONTROL 0x060
+#define QSERDES_RX_AUX_CONTROL 0x064
+#define QSERDES_RX_AUX_DATA_TCOARSE 0x068
+#define QSERDES_RX_AUX_DATA_TFINE_LSB 0x06c
+#define QSERDES_RX_AUX_DATA_TFINE_MSB 0x070
+#define QSERDES_RX_RCLK_AUXDATA_SEL 0x074
+#define QSERDES_RX_AC_JTAG_ENABLE 0x078
+#define QSERDES_RX_AC_JTAG_INITP 0x07c
+#define QSERDES_RX_AC_JTAG_INITN 0x080
+#define QSERDES_RX_AC_JTAG_LVL 0x084
+#define QSERDES_RX_AC_JTAG_MODE 0x088
+#define QSERDES_RX_AC_JTAG_RESET 0x08c
#define QSERDES_RX_RX_TERM_BW 0x090
+#define QSERDES_RX_RX_RCVR_IQ_EN 0x094
+#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x098
+#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x09c
+#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0a0
+#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0a4
+#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0a8
+#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x0ac
+#define QSERDES_RX_RX_IDAC_EN 0x0b0
+#define QSERDES_RX_RX_IDAC_ENABLES 0x0b4
+#define QSERDES_RX_RX_IDAC_SIGN 0x0b8
+#define QSERDES_RX_RX_HIGHZ_HIGHRATE 0x0bc
+#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0c0
#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d4
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
+#define QSERDES_RX_RX_IDAC_CAL_CONFIGURATION 0x0e4
+#define QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x0e8
+#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x0ec
+#define QSERDES_RX_RX_IDAC_ENDSAMP_LOW 0x0f0
+#define QSERDES_RX_RX_IDAC_ENDSAMP_HIGH 0x0f4
+#define QSERDES_RX_RX_IDAC_MIDPOINT_LOW 0x0f8
+#define QSERDES_RX_RX_IDAC_MIDPOINT_HIGH 0x0fc
+#define QSERDES_RX_RX_EQ_OFFSET_LSB 0x100
+#define QSERDES_RX_RX_EQ_OFFSET_MSB 0x104
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
#define QSERDES_RX_SIGDET_ENABLES 0x110
@@ -39,6 +151,55 @@
#define QSERDES_RX_SIGDET_LVL 0x118
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
#define QSERDES_RX_RX_BAND 0x120
+#define QSERDES_RX_CDR_FREEZE_UP_DN 0x124
+#define QSERDES_RX_CDR_RESET_OVERRIDE 0x128
#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
+#define QSERDES_RX_JITTER_GEN_MODE 0x130
+#define QSERDES_RX_BUJ_AMP 0x134
+#define QSERDES_RX_SJ_AMP1 0x138
+#define QSERDES_RX_SJ_AMP2 0x13c
+#define QSERDES_RX_SJ_PER1 0x140
+#define QSERDES_RX_SJ_PER2 0x144
+#define QSERDES_RX_BUJ_STEP_FREQ1 0x148
+#define QSERDES_RX_BUJ_STEP_FREQ2 0x14c
+#define QSERDES_RX_PPM_OFFSET1 0x150
+#define QSERDES_RX_PPM_OFFSET2 0x154
+#define QSERDES_RX_SIGN_PPM_PERIOD1 0x158
+#define QSERDES_RX_SIGN_PPM_PERIOD2 0x15c
+#define QSERDES_RX_SSC_CTRL 0x160
+#define QSERDES_RX_SSC_COUNT1 0x164
+#define QSERDES_RX_SSC_COUNT2 0x168
+#define QSERDES_RX_RX_ALOG_INTF_OBSV_CNTL 0x16c
+#define QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x170
+#define QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x174
+#define QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x178
+#define QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x17c
+#define QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x180
+#define QSERDES_RX_PI_CTRL1 0x184
+#define QSERDES_RX_PI_CTRL2 0x188
+#define QSERDES_RX_PI_QUAD 0x18c
+#define QSERDES_RX_IDATA1 0x190
+#define QSERDES_RX_IDATA2 0x194
+#define QSERDES_RX_AUX_DATA1 0x198
+#define QSERDES_RX_AUX_DATA2 0x19c
+#define QSERDES_RX_AC_JTAG_OUTP 0x1a0
+#define QSERDES_RX_AC_JTAG_OUTN 0x1a4
+#define QSERDES_RX_RX_SIGDET 0x1a8
+#define QSERDES_RX_RX_VDCOFF 0x1ac
+#define QSERDES_RX_IDAC_CAL_ON 0x1b0
+#define QSERDES_RX_IDAC_STATUS_I 0x1b4
+#define QSERDES_RX_IDAC_STATUS_IBAR 0x1b8
+#define QSERDES_RX_IDAC_STATUS_Q 0x1bc
+#define QSERDES_RX_IDAC_STATUS_QBAR 0x1c0
+#define QSERDES_RX_IDAC_STATUS_A 0x1c4
+#define QSERDES_RX_IDAC_STATUS_ABAR 0x1c8
+#define QSERDES_RX_CALST_STATUS_I 0x1cc
+#define QSERDES_RX_CALST_STATUS_Q 0x1d0
+#define QSERDES_RX_CALST_STATUS_A 0x1d4
+#define QSERDES_RX_RX_ALOG_INTF_OBSV 0x1d8
+#define QSERDES_RX_READ_EQCODE 0x1dc
+#define QSERDES_RX_READ_OFFSETCODE 0x1e0
+#define QSERDES_RX_IA_ERROR_COUNTER_LOW 0x1e4
+#define QSERDES_RX_IA_ERROR_COUNTER_HIGH 0x1e8
#endif
--
2.35.1
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 22/28] phy: qcom-qmp: qserdes-com-v3: add missing registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-4.4's phy-qcom-ufs-qmp-v3.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v3.h | 25 +++++++++++++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h | 3 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
index a61f8d36d01e..c0bd54e0e7b6 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
@@ -27,6 +27,10 @@
#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
#define QSERDES_V3_COM_PLL_EN 0x044
#define QSERDES_V3_COM_PLL_IVCO 0x048
+#define QSERDES_V3_COM_CMN_IETRIM 0x04c
+#define QSERDES_V3_COM_CMN_IPTRIM 0x050
+#define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR 0x054
+#define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS 0x058
#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
@@ -34,7 +38,10 @@
#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
+#define QSERDES_V3_COM_PLL_CNTRL 0x078
+#define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM 0x07c
#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
+#define QSERDES_V3_COM_CML_SYSCLK_SEL 0x084
#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
@@ -54,10 +61,12 @@
#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
+#define QSERDES_V3_COM_INTEGLOOP_EN 0x0d4
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
+#define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL 0x0e8
#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
@@ -66,21 +75,37 @@
#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
+#define QSERDES_V3_COM_VCO_TUNE_MINVAL1 0x10c
+#define QSERDES_V3_COM_VCO_TUNE_MINVAL2 0x110
+#define QSERDES_V3_COM_VCO_TUNE_MAXVAL1 0x114
+#define QSERDES_V3_COM_VCO_TUNE_MAXVAL2 0x118
#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
+#define QSERDES_V3_COM_CMN_STATUS 0x124
+#define QSERDES_V3_COM_RESET_SM_STATUS 0x128
+#define QSERDES_V3_COM_RESTRIM_CODE_STATUS 0x12c
+#define QSERDES_V3_COM_PLLCAL_CODE1_STATUS 0x130
+#define QSERDES_V3_COM_PLLCAL_CODE2_STATUS 0x134
#define QSERDES_V3_COM_CLK_SELECT 0x138
#define QSERDES_V3_COM_HSCLK_SEL 0x13c
+#define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS 0x140
+#define QSERDES_V3_COM_PLL_ANALOG 0x144
#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
+#define QSERDES_V3_COM_SW_RESET 0x150
#define QSERDES_V3_COM_CORE_CLK_EN 0x154
#define QSERDES_V3_COM_C_READY_STATUS 0x158
#define QSERDES_V3_COM_CMN_CONFIG 0x15c
+#define QSERDES_V3_COM_CMN_RATE_OVERRIDE 0x160
#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
#define QSERDES_V3_COM_DEBUG_BUS0 0x168
#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
#define QSERDES_V3_COM_DEBUG_BUS2 0x170
#define QSERDES_V3_COM_DEBUG_BUS3 0x174
#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
+#define QSERDES_V3_COM_CMN_MISC1 0x17c
+#define QSERDES_V3_COM_CMN_MISC2 0x180
#define QSERDES_V3_COM_CMN_MODE 0x184
+#define QSERDES_V3_COM_CMN_VREG_SEL 0x188
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
index 2c7238df38d7..161e6df30ea8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
@@ -26,6 +26,8 @@
#define QSERDES_V3_TX_TX_POL_INV 0x064
#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
#define QSERDES_V3_TX_LANE_MODE_1 0x08c
+#define QSERDES_V3_TX_LANE_MODE_2 0x090
+#define QSERDES_V3_TX_LANE_MODE_3 0x094
#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
@@ -48,6 +50,7 @@
#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 22/28] phy: qcom-qmp: qserdes-com-v3: add missing registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-4.4's phy-qcom-ufs-qmp-v3.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v3.h | 25 +++++++++++++++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h | 3 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
index a61f8d36d01e..c0bd54e0e7b6 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h
@@ -27,6 +27,10 @@
#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
#define QSERDES_V3_COM_PLL_EN 0x044
#define QSERDES_V3_COM_PLL_IVCO 0x048
+#define QSERDES_V3_COM_CMN_IETRIM 0x04c
+#define QSERDES_V3_COM_CMN_IPTRIM 0x050
+#define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR 0x054
+#define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS 0x058
#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
@@ -34,7 +38,10 @@
#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
+#define QSERDES_V3_COM_PLL_CNTRL 0x078
+#define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM 0x07c
#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
+#define QSERDES_V3_COM_CML_SYSCLK_SEL 0x084
#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
@@ -54,10 +61,12 @@
#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
+#define QSERDES_V3_COM_INTEGLOOP_EN 0x0d4
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
+#define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL 0x0e8
#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
@@ -66,21 +75,37 @@
#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
+#define QSERDES_V3_COM_VCO_TUNE_MINVAL1 0x10c
+#define QSERDES_V3_COM_VCO_TUNE_MINVAL2 0x110
+#define QSERDES_V3_COM_VCO_TUNE_MAXVAL1 0x114
+#define QSERDES_V3_COM_VCO_TUNE_MAXVAL2 0x118
#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
+#define QSERDES_V3_COM_CMN_STATUS 0x124
+#define QSERDES_V3_COM_RESET_SM_STATUS 0x128
+#define QSERDES_V3_COM_RESTRIM_CODE_STATUS 0x12c
+#define QSERDES_V3_COM_PLLCAL_CODE1_STATUS 0x130
+#define QSERDES_V3_COM_PLLCAL_CODE2_STATUS 0x134
#define QSERDES_V3_COM_CLK_SELECT 0x138
#define QSERDES_V3_COM_HSCLK_SEL 0x13c
+#define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS 0x140
+#define QSERDES_V3_COM_PLL_ANALOG 0x144
#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
+#define QSERDES_V3_COM_SW_RESET 0x150
#define QSERDES_V3_COM_CORE_CLK_EN 0x154
#define QSERDES_V3_COM_C_READY_STATUS 0x158
#define QSERDES_V3_COM_CMN_CONFIG 0x15c
+#define QSERDES_V3_COM_CMN_RATE_OVERRIDE 0x160
#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
#define QSERDES_V3_COM_DEBUG_BUS0 0x168
#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
#define QSERDES_V3_COM_DEBUG_BUS2 0x170
#define QSERDES_V3_COM_DEBUG_BUS3 0x174
#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
+#define QSERDES_V3_COM_CMN_MISC1 0x17c
+#define QSERDES_V3_COM_CMN_MISC2 0x180
#define QSERDES_V3_COM_CMN_MODE 0x184
+#define QSERDES_V3_COM_CMN_VREG_SEL 0x188
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
index 2c7238df38d7..161e6df30ea8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h
@@ -26,6 +26,8 @@
#define QSERDES_V3_TX_TX_POL_INV 0x064
#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
#define QSERDES_V3_TX_LANE_MODE_1 0x08c
+#define QSERDES_V3_TX_LANE_MODE_2 0x090
+#define QSERDES_V3_TX_LANE_MODE_3 0x094
#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
@@ -48,6 +50,7 @@
#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 23/28] phy: qcom-qmp: qserdes-com-v4: add missing registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-4.19's qcom,kona-qmp-usb3.h
The 0x1a0 register name was corrected, verified via msm-4.14's
qcom,sdxprairie-qmp-usb3.h.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 +-
.../qualcomm/phy-qcom-qmp-qserdes-com-v4.h | 47 +++++-
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h | 141 ++++++++++++++++++
3 files changed, 188 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 9e3889cbd645..5b3f612d1c2c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -958,7 +958,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
index af8662ca9ee0..b0e3298d990d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
@@ -7,29 +7,47 @@
#define QCOM_PHY_QMP_QSERDES_COM_V4_H_
/* Only for QMP V4 PHY - QSERDES COM registers */
+#define QSERDES_V4_COM_ATB_SEL1 0x000
+#define QSERDES_V4_COM_ATB_SEL2 0x004
+#define QSERDES_V4_COM_FREQ_UPDATE 0x008
#define QSERDES_V4_COM_BG_TIMER 0x00c
#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
#define QSERDES_V4_COM_SSC_PER1 0x01c
#define QSERDES_V4_COM_SSC_PER2 0x020
#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE0 0x02c
#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE1 0x038
+#define QSERDES_V4_COM_POST_DIV 0x03c
+#define QSERDES_V4_COM_POST_DIV_MUX 0x040
#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044
#define QSERDES_V4_COM_CLK_ENABLE1 0x048
#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c
#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
+#define QSERDES_V4_COM_PLL_EN 0x054
#define QSERDES_V4_COM_PLL_IVCO 0x058
+#define QSERDES_V4_COM_CMN_IETRIM 0x05c
#define QSERDES_V4_COM_CMN_IPTRIM 0x060
+#define QSERDES_V4_COM_EP_CLOCK_DETECT_CTRL 0x064
+#define QSERDES_V4_COM_SYSCLK_DET_COMP_STATUS 0x068
+#define QSERDES_V4_COM_CLK_EP_DIV_MODE0 0x06c
+#define QSERDES_V4_COM_CLK_EP_DIV_MODE1 0x070
#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
+#define QSERDES_V4_COM_PLL_CNTRL 0x08c
+#define QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM 0x090
#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
+#define QSERDES_V4_COM_CML_SYSCLK_SEL 0x098
#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c
+#define QSERDES_V4_COM_RESETSM_CNTRL2 0x0a0
#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8
#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
@@ -37,36 +55,63 @@
#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
+#define QSERDES_V4_COM_DEC_START_MSB_MODE0 0x0c0
#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V4_COM_DEC_START_MSB_MODE1 0x0c8
#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define QSERDES_V4_COM_INTEGLOOP_INITVAL 0x0e4
+#define QSERDES_V4_COM_INTEGLOOP_EN 0x0e8
#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
+#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN1 0x100
+#define QSERDES_V4_COM_VCOCAL_DEADMAN_CTRL 0x104
#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108
#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
+#define QSERDES_V4_COM_VCO_TUNE_INITVAL1 0x120
#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V4_COM_VCO_TUNE_MINVAL1 0x128
+#define QSERDES_V4_COM_VCO_TUNE_MINVAL2 0x12c
+#define QSERDES_V4_COM_VCO_TUNE_MAXVAL1 0x130
+#define QSERDES_V4_COM_VCO_TUNE_MAXVAL2 0x134
+#define QSERDES_V4_COM_VCO_TUNE_TIMER1 0x138
+#define QSERDES_V4_COM_VCO_TUNE_TIMER2 0x13c
#define QSERDES_V4_COM_CMN_STATUS 0x140
+#define QSERDES_V4_COM_RESET_SM_STATUS 0x144
+#define QSERDES_V4_COM_RESTRIM_CODE_STATUS 0x148
+#define QSERDES_V4_COM_PLLCAL_CODE1_STATUS 0x14c
+#define QSERDES_V4_COM_PLLCAL_CODE2_STATUS 0x150
#define QSERDES_V4_COM_CLK_SELECT 0x154
#define QSERDES_V4_COM_HSCLK_SEL 0x158
#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V4_COM_INTEGLOOP_BINCODE_STATUS 0x160
+#define QSERDES_V4_COM_PLL_ANALOG 0x164
#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168
#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
+#define QSERDES_V4_COM_SW_RESET 0x170
#define QSERDES_V4_COM_CORE_CLK_EN 0x174
#define QSERDES_V4_COM_C_READY_STATUS 0x178
#define QSERDES_V4_COM_CMN_CONFIG 0x17c
+#define QSERDES_V4_COM_CMN_RATE_OVERRIDE 0x180
#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
+#define QSERDES_V4_COM_DEBUG_BUS0 0x188
+#define QSERDES_V4_COM_DEBUG_BUS1 0x18c
+#define QSERDES_V4_COM_DEBUG_BUS2 0x190
+#define QSERDES_V4_COM_DEBUG_BUS3 0x194
+#define QSERDES_V4_COM_DEBUG_BUS_SEL 0x198
#define QSERDES_V4_COM_CMN_MISC1 0x19c
-#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0
+#define QSERDES_V4_COM_CMN_MISC2 0x1a0
#define QSERDES_V4_COM_CMN_MODE 0x1a4
#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
index 1716932bdf1a..6ee3bec9ac4a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
@@ -7,38 +7,115 @@
#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
/* Only for QMP V4 PHY - TX registers */
+#define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_V4_TX_BIST_INVERT 0x004
#define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
+#define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
#define QSERDES_V4_TX_TX_DRV_LVL 0x014
+#define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
#define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
#define QSERDES_V4_TX_TX_BAND 0x024
+#define QSERDES_V4_TX_SLEW_CNTL 0x028
#define QSERDES_V4_TX_INTERFACE_SELECT 0x02c
+#define QSERDES_V4_TX_LPB_EN 0x030
#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034
#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V4_TX_PERL_LENGTH1 0x044
+#define QSERDES_V4_TX_PERL_LENGTH2 0x048
+#define QSERDES_V4_TX_SERDES_BYP_EN_OUT 0x04c
+#define QSERDES_V4_TX_DEBUG_BUS_SEL 0x050
#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054
#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058
#define QSERDES_V4_TX_TX_POL_INV 0x05c
#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
+#define QSERDES_V4_TX_BIST_PATTERN1 0x064
+#define QSERDES_V4_TX_BIST_PATTERN2 0x068
+#define QSERDES_V4_TX_BIST_PATTERN3 0x06c
+#define QSERDES_V4_TX_BIST_PATTERN4 0x070
+#define QSERDES_V4_TX_BIST_PATTERN5 0x074
+#define QSERDES_V4_TX_BIST_PATTERN6 0x078
+#define QSERDES_V4_TX_BIST_PATTERN7 0x07c
+#define QSERDES_V4_TX_BIST_PATTERN8 0x080
#define QSERDES_V4_TX_LANE_MODE_1 0x084
#define QSERDES_V4_TX_LANE_MODE_2 0x088
+#define QSERDES_V4_TX_LANE_MODE_3 0x08c
+#define QSERDES_V4_TX_ATB_SEL1 0x090
+#define QSERDES_V4_TX_ATB_SEL2 0x094
+#define QSERDES_V4_TX_RCV_DETECT_LVL 0x098
#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c
+#define QSERDES_V4_TX_PRBS_SEED1 0x0a0
+#define QSERDES_V4_TX_PRBS_SEED2 0x0a4
+#define QSERDES_V4_TX_PRBS_SEED3 0x0a8
+#define QSERDES_V4_TX_PRBS_SEED4 0x0ac
+#define QSERDES_V4_TX_RESET_GEN 0x0b0
+#define QSERDES_V4_TX_RESET_GEN_MUXES 0x0b4
#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8
#define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc
+#define QSERDES_V4_TX_PWM_CTRL 0x0c0
+#define QSERDES_V4_TX_PWM_ENCODED_OR_DATA 0x0c4
+#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0c8
+#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0cc
+#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0d0
+#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0d4
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc
#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0
#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4
#define QSERDES_V4_TX_VMODE_CTRL1 0x0e8
+#define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1 0x0ec
+#define QSERDES_V4_TX_BIST_STATUS 0x0f0
+#define QSERDES_V4_TX_BIST_ERROR_COUNT1 0x0f4
+#define QSERDES_V4_TX_BIST_ERROR_COUNT2 0x0f8
+#define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1 0x0fc
+#define QSERDES_V4_TX_LANE_DIG_CONFIG 0x100
#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
+#define QSERDES_V4_TX_PRE_EMPH 0x108
+#define QSERDES_V4_TX_SW_RESET 0x10c
+#define QSERDES_V4_TX_DCC_OFFSET 0x110
+#define QSERDES_V4_TX_DIG_BKUP_CTRL 0x114
+#define QSERDES_V4_TX_DEBUG_BUS0 0x118
+#define QSERDES_V4_TX_DEBUG_BUS1 0x11c
+#define QSERDES_V4_TX_DEBUG_BUS2 0x120
+#define QSERDES_V4_TX_DEBUG_BUS3 0x124
+#define QSERDES_V4_TX_READ_EQCODE 0x128
+#define QSERDES_V4_TX_READ_OFFSETCODE 0x12c
+#define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW 0x130
+#define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH 0x134
+#define QSERDES_V4_TX_VGA_READ_CODE 0x138
+#define QSERDES_V4_TX_VTH_READ_CODE 0x13c
+#define QSERDES_V4_TX_DFE_TAP1_READ_CODE 0x140
+#define QSERDES_V4_TX_DFE_TAP2_READ_CODE 0x144
+#define QSERDES_V4_TX_IDAC_STATUS_I 0x148
+#define QSERDES_V4_TX_IDAC_STATUS_IBAR 0x14c
+#define QSERDES_V4_TX_IDAC_STATUS_Q 0x150
+#define QSERDES_V4_TX_IDAC_STATUS_QBAR 0x154
+#define QSERDES_V4_TX_IDAC_STATUS_A 0x158
+#define QSERDES_V4_TX_IDAC_STATUS_ABAR 0x15c
+#define QSERDES_V4_TX_IDAC_STATUS_SM_ON 0x160
+#define QSERDES_V4_TX_IDAC_STATUS_CAL_DONE 0x164
+#define QSERDES_V4_TX_IDAC_STATUS_SIGNERROR 0x168
+#define QSERDES_V4_TX_DCC_CAL_STATUS 0x16c
/* Only for QMP V4 PHY - RX registers */
+#define QSERDES_V4_RX_UCDR_FO_GAIN_HALF 0x000
+#define QSERDES_V4_RX_UCDR_FO_GAIN_QUARTER 0x004
#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V4_RX_UCDR_SO_GAIN_HALF 0x00c
+#define QSERDES_V4_RX_UCDR_SO_GAIN_QUARTER 0x010
#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_HALF 0x018
+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN 0x020
+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_HALF 0x024
+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN 0x02c
#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V4_RX_UCDR_FO_TO_SO_DELAY 0x038
#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
@@ -47,14 +124,41 @@
#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
+#define QSERDES_V4_RX_AUX_CONTROL 0x05c
#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064
#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
+#define QSERDES_V4_RX_AC_JTAG_INITP 0x06c
+#define QSERDES_V4_RX_AC_JTAG_INITN 0x070
+#define QSERDES_V4_RX_AC_JTAG_LVL 0x074
#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
+#define QSERDES_V4_RX_AC_JTAG_RESET 0x07c
#define QSERDES_V4_RX_RX_TERM_BW 0x080
+#define QSERDES_V4_RX_RX_RCVR_IQ_EN 0x084
+#define QSERDES_V4_RX_RX_IDAC_I_DC_OFFSETS 0x088
+#define QSERDES_V4_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
+#define QSERDES_V4_RX_RX_IDAC_Q_DC_OFFSETS 0x090
+#define QSERDES_V4_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
+#define QSERDES_V4_RX_RX_IDAC_A_DC_OFFSETS 0x098
+#define QSERDES_V4_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
+#define QSERDES_V4_RX_RX_IDAC_EN 0x0a0
+#define QSERDES_V4_RX_RX_IDAC_ENABLES 0x0a4
+#define QSERDES_V4_RX_RX_IDAC_SIGN 0x0a8
+#define QSERDES_V4_RX_RX_HIGHZ_HIGHRATE 0x0ac
+#define QSERDES_V4_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
+#define QSERDES_V4_RX_DFE_1 0x0b4
+#define QSERDES_V4_RX_DFE_2 0x0b8
+#define QSERDES_V4_RX_DFE_3 0x0bc
+#define QSERDES_V4_RX_DFE_4 0x0c0
+#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1 0x0c4
+#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2 0x0c8
+#define QSERDES_V4_RX_TX_ADAPT_POST_THRESH 0x0cc
+#define QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH 0x0d0
#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
#define QSERDES_V4_RX_GM_CAL 0x0dc
+#define QSERDES_V4_RX_RX_VGA_GAIN2_LSB 0x0e0
+#define QSERDES_V4_RX_RX_VGA_GAIN2_MSB 0x0e4
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
@@ -62,6 +166,9 @@
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
+#define QSERDES_V4_RX_RX_IDAC_ACCUMULATOR 0x104
+#define QSERDES_V4_RX_RX_EQ_OFFSET_LSB 0x108
+#define QSERDES_V4_RX_RX_EQ_OFFSET_MSB 0x10c
#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
#define QSERDES_V4_RX_SIGDET_ENABLES 0x118
@@ -69,6 +176,23 @@
#define QSERDES_V4_RX_SIGDET_LVL 0x120
#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
#define QSERDES_V4_RX_RX_BAND 0x128
+#define QSERDES_V4_RX_CDR_FREEZE_UP_DN 0x12c
+#define QSERDES_V4_RX_CDR_RESET_OVERRIDE 0x130
+#define QSERDES_V4_RX_RX_INTERFACE_MODE 0x134
+#define QSERDES_V4_RX_JITTER_GEN_MODE 0x138
+#define QSERDES_V4_RX_SJ_AMP1 0x13c
+#define QSERDES_V4_RX_SJ_AMP2 0x140
+#define QSERDES_V4_RX_SJ_PER1 0x144
+#define QSERDES_V4_RX_SJ_PER2 0x148
+#define QSERDES_V4_RX_PPM_OFFSET1 0x14c
+#define QSERDES_V4_RX_PPM_OFFSET2 0x150
+#define QSERDES_V4_RX_SIGN_PPM_PERIOD1 0x154
+#define QSERDES_V4_RX_SIGN_PPM_PERIOD2 0x158
+#define QSERDES_V4_RX_RX_PWM_ENABLE_AND_DATA 0x15c
+#define QSERDES_V4_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x160
+#define QSERDES_V4_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x164
+#define QSERDES_V4_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x168
+#define QSERDES_V4_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x16c
#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
@@ -84,9 +208,26 @@
#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
+#define QSERDES_V4_RX_PHPRE_CTRL 0x1ac
+#define QSERDES_V4_RX_PHPRE_INITVAL 0x1b0
#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
+#define QSERDES_V4_RX_DCC_CTRL2 0x1c0
#define QSERDES_V4_RX_VTH_CODE 0x1c4
+#define QSERDES_V4_RX_VTH_MIN_THRESH 0x1c8
+#define QSERDES_V4_RX_VTH_MAX_THRESH 0x1cc
+#define QSERDES_V4_RX_ALOG_OBSV_BUS_CTRL_1 0x1d0
+#define QSERDES_V4_RX_PI_CTRL1 0x1d4
+#define QSERDES_V4_RX_PI_CTRL2 0x1d8
+#define QSERDES_V4_RX_PI_QUAD 0x1dc
+#define QSERDES_V4_RX_IDATA1 0x1e0
+#define QSERDES_V4_RX_IDATA2 0x1e4
+#define QSERDES_V4_RX_AUX_DATA1 0x1e8
+#define QSERDES_V4_RX_AUX_DATA2 0x1ec
+#define QSERDES_V4_RX_AC_JTAG_OUTP 0x1f0
+#define QSERDES_V4_RX_AC_JTAG_OUTN 0x1f4
+#define QSERDES_V4_RX_RX_SIGDET 0x1f8
+#define QSERDES_V4_RX_ALOG_OBSV_BUS_STATUS_1 0x1fc
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 23/28] phy: qcom-qmp: qserdes-com-v4: add missing registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-4.19's qcom,kona-qmp-usb3.h
The 0x1a0 register name was corrected, verified via msm-4.14's
qcom,sdxprairie-qmp-usb3.h.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 +-
.../qualcomm/phy-qcom-qmp-qserdes-com-v4.h | 47 +++++-
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h | 141 ++++++++++++++++++
3 files changed, 188 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 9e3889cbd645..5b3f612d1c2c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -958,7 +958,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
index af8662ca9ee0..b0e3298d990d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h
@@ -7,29 +7,47 @@
#define QCOM_PHY_QMP_QSERDES_COM_V4_H_
/* Only for QMP V4 PHY - QSERDES COM registers */
+#define QSERDES_V4_COM_ATB_SEL1 0x000
+#define QSERDES_V4_COM_ATB_SEL2 0x004
+#define QSERDES_V4_COM_FREQ_UPDATE 0x008
#define QSERDES_V4_COM_BG_TIMER 0x00c
#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
#define QSERDES_V4_COM_SSC_PER1 0x01c
#define QSERDES_V4_COM_SSC_PER2 0x020
#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE0 0x02c
#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE1 0x038
+#define QSERDES_V4_COM_POST_DIV 0x03c
+#define QSERDES_V4_COM_POST_DIV_MUX 0x040
#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044
#define QSERDES_V4_COM_CLK_ENABLE1 0x048
#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c
#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
+#define QSERDES_V4_COM_PLL_EN 0x054
#define QSERDES_V4_COM_PLL_IVCO 0x058
+#define QSERDES_V4_COM_CMN_IETRIM 0x05c
#define QSERDES_V4_COM_CMN_IPTRIM 0x060
+#define QSERDES_V4_COM_EP_CLOCK_DETECT_CTRL 0x064
+#define QSERDES_V4_COM_SYSCLK_DET_COMP_STATUS 0x068
+#define QSERDES_V4_COM_CLK_EP_DIV_MODE0 0x06c
+#define QSERDES_V4_COM_CLK_EP_DIV_MODE1 0x070
#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
+#define QSERDES_V4_COM_PLL_CNTRL 0x08c
+#define QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM 0x090
#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
+#define QSERDES_V4_COM_CML_SYSCLK_SEL 0x098
#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c
+#define QSERDES_V4_COM_RESETSM_CNTRL2 0x0a0
#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8
#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
@@ -37,36 +55,63 @@
#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
+#define QSERDES_V4_COM_DEC_START_MSB_MODE0 0x0c0
#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V4_COM_DEC_START_MSB_MODE1 0x0c8
#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define QSERDES_V4_COM_INTEGLOOP_INITVAL 0x0e4
+#define QSERDES_V4_COM_INTEGLOOP_EN 0x0e8
#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
+#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN1 0x100
+#define QSERDES_V4_COM_VCOCAL_DEADMAN_CTRL 0x104
#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108
#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
+#define QSERDES_V4_COM_VCO_TUNE_INITVAL1 0x120
#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V4_COM_VCO_TUNE_MINVAL1 0x128
+#define QSERDES_V4_COM_VCO_TUNE_MINVAL2 0x12c
+#define QSERDES_V4_COM_VCO_TUNE_MAXVAL1 0x130
+#define QSERDES_V4_COM_VCO_TUNE_MAXVAL2 0x134
+#define QSERDES_V4_COM_VCO_TUNE_TIMER1 0x138
+#define QSERDES_V4_COM_VCO_TUNE_TIMER2 0x13c
#define QSERDES_V4_COM_CMN_STATUS 0x140
+#define QSERDES_V4_COM_RESET_SM_STATUS 0x144
+#define QSERDES_V4_COM_RESTRIM_CODE_STATUS 0x148
+#define QSERDES_V4_COM_PLLCAL_CODE1_STATUS 0x14c
+#define QSERDES_V4_COM_PLLCAL_CODE2_STATUS 0x150
#define QSERDES_V4_COM_CLK_SELECT 0x154
#define QSERDES_V4_COM_HSCLK_SEL 0x158
#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V4_COM_INTEGLOOP_BINCODE_STATUS 0x160
+#define QSERDES_V4_COM_PLL_ANALOG 0x164
#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168
#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
+#define QSERDES_V4_COM_SW_RESET 0x170
#define QSERDES_V4_COM_CORE_CLK_EN 0x174
#define QSERDES_V4_COM_C_READY_STATUS 0x178
#define QSERDES_V4_COM_CMN_CONFIG 0x17c
+#define QSERDES_V4_COM_CMN_RATE_OVERRIDE 0x180
#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
+#define QSERDES_V4_COM_DEBUG_BUS0 0x188
+#define QSERDES_V4_COM_DEBUG_BUS1 0x18c
+#define QSERDES_V4_COM_DEBUG_BUS2 0x190
+#define QSERDES_V4_COM_DEBUG_BUS3 0x194
+#define QSERDES_V4_COM_DEBUG_BUS_SEL 0x198
#define QSERDES_V4_COM_CMN_MISC1 0x19c
-#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0
+#define QSERDES_V4_COM_CMN_MISC2 0x1a0
#define QSERDES_V4_COM_CMN_MODE 0x1a4
#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8
#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
index 1716932bdf1a..6ee3bec9ac4a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
@@ -7,38 +7,115 @@
#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
/* Only for QMP V4 PHY - TX registers */
+#define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_V4_TX_BIST_INVERT 0x004
#define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
+#define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
#define QSERDES_V4_TX_TX_DRV_LVL 0x014
+#define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
#define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
#define QSERDES_V4_TX_TX_BAND 0x024
+#define QSERDES_V4_TX_SLEW_CNTL 0x028
#define QSERDES_V4_TX_INTERFACE_SELECT 0x02c
+#define QSERDES_V4_TX_LPB_EN 0x030
#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034
#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V4_TX_PERL_LENGTH1 0x044
+#define QSERDES_V4_TX_PERL_LENGTH2 0x048
+#define QSERDES_V4_TX_SERDES_BYP_EN_OUT 0x04c
+#define QSERDES_V4_TX_DEBUG_BUS_SEL 0x050
#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054
#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058
#define QSERDES_V4_TX_TX_POL_INV 0x05c
#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
+#define QSERDES_V4_TX_BIST_PATTERN1 0x064
+#define QSERDES_V4_TX_BIST_PATTERN2 0x068
+#define QSERDES_V4_TX_BIST_PATTERN3 0x06c
+#define QSERDES_V4_TX_BIST_PATTERN4 0x070
+#define QSERDES_V4_TX_BIST_PATTERN5 0x074
+#define QSERDES_V4_TX_BIST_PATTERN6 0x078
+#define QSERDES_V4_TX_BIST_PATTERN7 0x07c
+#define QSERDES_V4_TX_BIST_PATTERN8 0x080
#define QSERDES_V4_TX_LANE_MODE_1 0x084
#define QSERDES_V4_TX_LANE_MODE_2 0x088
+#define QSERDES_V4_TX_LANE_MODE_3 0x08c
+#define QSERDES_V4_TX_ATB_SEL1 0x090
+#define QSERDES_V4_TX_ATB_SEL2 0x094
+#define QSERDES_V4_TX_RCV_DETECT_LVL 0x098
#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c
+#define QSERDES_V4_TX_PRBS_SEED1 0x0a0
+#define QSERDES_V4_TX_PRBS_SEED2 0x0a4
+#define QSERDES_V4_TX_PRBS_SEED3 0x0a8
+#define QSERDES_V4_TX_PRBS_SEED4 0x0ac
+#define QSERDES_V4_TX_RESET_GEN 0x0b0
+#define QSERDES_V4_TX_RESET_GEN_MUXES 0x0b4
#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8
#define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc
+#define QSERDES_V4_TX_PWM_CTRL 0x0c0
+#define QSERDES_V4_TX_PWM_ENCODED_OR_DATA 0x0c4
+#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0c8
+#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0cc
+#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0d0
+#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0d4
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc
#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0
#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4
#define QSERDES_V4_TX_VMODE_CTRL1 0x0e8
+#define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1 0x0ec
+#define QSERDES_V4_TX_BIST_STATUS 0x0f0
+#define QSERDES_V4_TX_BIST_ERROR_COUNT1 0x0f4
+#define QSERDES_V4_TX_BIST_ERROR_COUNT2 0x0f8
+#define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1 0x0fc
+#define QSERDES_V4_TX_LANE_DIG_CONFIG 0x100
#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
+#define QSERDES_V4_TX_PRE_EMPH 0x108
+#define QSERDES_V4_TX_SW_RESET 0x10c
+#define QSERDES_V4_TX_DCC_OFFSET 0x110
+#define QSERDES_V4_TX_DIG_BKUP_CTRL 0x114
+#define QSERDES_V4_TX_DEBUG_BUS0 0x118
+#define QSERDES_V4_TX_DEBUG_BUS1 0x11c
+#define QSERDES_V4_TX_DEBUG_BUS2 0x120
+#define QSERDES_V4_TX_DEBUG_BUS3 0x124
+#define QSERDES_V4_TX_READ_EQCODE 0x128
+#define QSERDES_V4_TX_READ_OFFSETCODE 0x12c
+#define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW 0x130
+#define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH 0x134
+#define QSERDES_V4_TX_VGA_READ_CODE 0x138
+#define QSERDES_V4_TX_VTH_READ_CODE 0x13c
+#define QSERDES_V4_TX_DFE_TAP1_READ_CODE 0x140
+#define QSERDES_V4_TX_DFE_TAP2_READ_CODE 0x144
+#define QSERDES_V4_TX_IDAC_STATUS_I 0x148
+#define QSERDES_V4_TX_IDAC_STATUS_IBAR 0x14c
+#define QSERDES_V4_TX_IDAC_STATUS_Q 0x150
+#define QSERDES_V4_TX_IDAC_STATUS_QBAR 0x154
+#define QSERDES_V4_TX_IDAC_STATUS_A 0x158
+#define QSERDES_V4_TX_IDAC_STATUS_ABAR 0x15c
+#define QSERDES_V4_TX_IDAC_STATUS_SM_ON 0x160
+#define QSERDES_V4_TX_IDAC_STATUS_CAL_DONE 0x164
+#define QSERDES_V4_TX_IDAC_STATUS_SIGNERROR 0x168
+#define QSERDES_V4_TX_DCC_CAL_STATUS 0x16c
/* Only for QMP V4 PHY - RX registers */
+#define QSERDES_V4_RX_UCDR_FO_GAIN_HALF 0x000
+#define QSERDES_V4_RX_UCDR_FO_GAIN_QUARTER 0x004
#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V4_RX_UCDR_SO_GAIN_HALF 0x00c
+#define QSERDES_V4_RX_UCDR_SO_GAIN_QUARTER 0x010
#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_HALF 0x018
+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN 0x020
+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_HALF 0x024
+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN 0x02c
#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V4_RX_UCDR_FO_TO_SO_DELAY 0x038
#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
@@ -47,14 +124,41 @@
#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
+#define QSERDES_V4_RX_AUX_CONTROL 0x05c
#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064
#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
+#define QSERDES_V4_RX_AC_JTAG_INITP 0x06c
+#define QSERDES_V4_RX_AC_JTAG_INITN 0x070
+#define QSERDES_V4_RX_AC_JTAG_LVL 0x074
#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
+#define QSERDES_V4_RX_AC_JTAG_RESET 0x07c
#define QSERDES_V4_RX_RX_TERM_BW 0x080
+#define QSERDES_V4_RX_RX_RCVR_IQ_EN 0x084
+#define QSERDES_V4_RX_RX_IDAC_I_DC_OFFSETS 0x088
+#define QSERDES_V4_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
+#define QSERDES_V4_RX_RX_IDAC_Q_DC_OFFSETS 0x090
+#define QSERDES_V4_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
+#define QSERDES_V4_RX_RX_IDAC_A_DC_OFFSETS 0x098
+#define QSERDES_V4_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
+#define QSERDES_V4_RX_RX_IDAC_EN 0x0a0
+#define QSERDES_V4_RX_RX_IDAC_ENABLES 0x0a4
+#define QSERDES_V4_RX_RX_IDAC_SIGN 0x0a8
+#define QSERDES_V4_RX_RX_HIGHZ_HIGHRATE 0x0ac
+#define QSERDES_V4_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
+#define QSERDES_V4_RX_DFE_1 0x0b4
+#define QSERDES_V4_RX_DFE_2 0x0b8
+#define QSERDES_V4_RX_DFE_3 0x0bc
+#define QSERDES_V4_RX_DFE_4 0x0c0
+#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1 0x0c4
+#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2 0x0c8
+#define QSERDES_V4_RX_TX_ADAPT_POST_THRESH 0x0cc
+#define QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH 0x0d0
#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
#define QSERDES_V4_RX_GM_CAL 0x0dc
+#define QSERDES_V4_RX_RX_VGA_GAIN2_LSB 0x0e0
+#define QSERDES_V4_RX_RX_VGA_GAIN2_MSB 0x0e4
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
@@ -62,6 +166,9 @@
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
+#define QSERDES_V4_RX_RX_IDAC_ACCUMULATOR 0x104
+#define QSERDES_V4_RX_RX_EQ_OFFSET_LSB 0x108
+#define QSERDES_V4_RX_RX_EQ_OFFSET_MSB 0x10c
#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
#define QSERDES_V4_RX_SIGDET_ENABLES 0x118
@@ -69,6 +176,23 @@
#define QSERDES_V4_RX_SIGDET_LVL 0x120
#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
#define QSERDES_V4_RX_RX_BAND 0x128
+#define QSERDES_V4_RX_CDR_FREEZE_UP_DN 0x12c
+#define QSERDES_V4_RX_CDR_RESET_OVERRIDE 0x130
+#define QSERDES_V4_RX_RX_INTERFACE_MODE 0x134
+#define QSERDES_V4_RX_JITTER_GEN_MODE 0x138
+#define QSERDES_V4_RX_SJ_AMP1 0x13c
+#define QSERDES_V4_RX_SJ_AMP2 0x140
+#define QSERDES_V4_RX_SJ_PER1 0x144
+#define QSERDES_V4_RX_SJ_PER2 0x148
+#define QSERDES_V4_RX_PPM_OFFSET1 0x14c
+#define QSERDES_V4_RX_PPM_OFFSET2 0x150
+#define QSERDES_V4_RX_SIGN_PPM_PERIOD1 0x154
+#define QSERDES_V4_RX_SIGN_PPM_PERIOD2 0x158
+#define QSERDES_V4_RX_RX_PWM_ENABLE_AND_DATA 0x15c
+#define QSERDES_V4_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x160
+#define QSERDES_V4_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x164
+#define QSERDES_V4_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x168
+#define QSERDES_V4_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x16c
#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
@@ -84,9 +208,26 @@
#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
+#define QSERDES_V4_RX_PHPRE_CTRL 0x1ac
+#define QSERDES_V4_RX_PHPRE_INITVAL 0x1b0
#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
+#define QSERDES_V4_RX_DCC_CTRL2 0x1c0
#define QSERDES_V4_RX_VTH_CODE 0x1c4
+#define QSERDES_V4_RX_VTH_MIN_THRESH 0x1c8
+#define QSERDES_V4_RX_VTH_MAX_THRESH 0x1cc
+#define QSERDES_V4_RX_ALOG_OBSV_BUS_CTRL_1 0x1d0
+#define QSERDES_V4_RX_PI_CTRL1 0x1d4
+#define QSERDES_V4_RX_PI_CTRL2 0x1d8
+#define QSERDES_V4_RX_PI_QUAD 0x1dc
+#define QSERDES_V4_RX_IDATA1 0x1e0
+#define QSERDES_V4_RX_IDATA2 0x1e4
+#define QSERDES_V4_RX_AUX_DATA1 0x1e8
+#define QSERDES_V4_RX_AUX_DATA2 0x1ec
+#define QSERDES_V4_RX_AC_JTAG_OUTP 0x1f0
+#define QSERDES_V4_RX_AC_JTAG_OUTN 0x1f4
+#define QSERDES_V4_RX_RX_SIGDET 0x1f8
+#define QSERDES_V4_RX_ALOG_OBSV_BUS_STATUS_1 0x1fc
#endif
--
2.35.1
--
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^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 24/28] phy: qcom-qmp: qserdes-com-v5: add missing registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-5.4's qcom,usb3-5nm-qmp-uni.h
- msm-5.4's qcom,usb3-5nm-qmp-combo.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v5.h | 59 +++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h | 155 +++++++++++++++++-
2 files changed, 210 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
index 8d2f9f012fed..c8afdf7bc1ee 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
@@ -7,24 +7,47 @@
#define QCOM_PHY_QMP_QSERDES_COM_V5_H_
/* Only for QMP V5 PHY - QSERDES COM registers */
+#define QSERDES_V5_COM_ATB_SEL1 0x000
+#define QSERDES_V5_COM_ATB_SEL2 0x004
+#define QSERDES_V5_COM_FREQ_UPDATE 0x008
+#define QSERDES_V5_COM_BG_TIMER 0x00c
#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
#define QSERDES_V5_COM_SSC_PER1 0x01c
#define QSERDES_V5_COM_SSC_PER2 0x020
#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c
#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038
+#define QSERDES_V5_COM_POST_DIV 0x03c
+#define QSERDES_V5_COM_POST_DIV_MUX 0x040
#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044
#define QSERDES_V5_COM_CLK_ENABLE1 0x048
+#define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c
#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
+#define QSERDES_V5_COM_PLL_EN 0x054
#define QSERDES_V5_COM_PLL_IVCO 0x058
+#define QSERDES_V5_COM_CMN_IETRIM 0x05c
+#define QSERDES_V5_COM_CMN_IPTRIM 0x060
+#define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064
+#define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068
+#define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c
+#define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070
#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
+#define QSERDES_V5_COM_PLL_CNTRL 0x08c
+#define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090
#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
+#define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098
+#define QSERDES_V5_COM_RESETSM_CNTRL 0x09c
+#define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0
#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8
#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
@@ -32,26 +55,61 @@
#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
+#define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0
#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4
+#define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8
+#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
+#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
+#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
+#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
+#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100
+#define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104
+#define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108
#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
+#define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120
#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128
+#define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c
+#define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130
+#define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134
+#define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138
+#define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c
+#define QSERDES_V5_COM_CMN_STATUS 0x140
+#define QSERDES_V5_COM_RESET_SM_STATUS 0x144
+#define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148
+#define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c
+#define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150
#define QSERDES_V5_COM_CLK_SELECT 0x154
#define QSERDES_V5_COM_HSCLK_SEL 0x158
#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160
+#define QSERDES_V5_COM_PLL_ANALOG 0x164
#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168
#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
+#define QSERDES_V5_COM_SW_RESET 0x170
#define QSERDES_V5_COM_CORE_CLK_EN 0x174
+#define QSERDES_V5_COM_C_READY_STATUS 0x178
#define QSERDES_V5_COM_CMN_CONFIG 0x17c
+#define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180
+#define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184
+#define QSERDES_V5_COM_DEBUG_BUS0 0x188
+#define QSERDES_V5_COM_DEBUG_BUS1 0x18c
+#define QSERDES_V5_COM_DEBUG_BUS2 0x190
+#define QSERDES_V5_COM_DEBUG_BUS3 0x194
+#define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198
#define QSERDES_V5_COM_CMN_MISC1 0x19c
#define QSERDES_V5_COM_CMN_MODE 0x1a0
#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
@@ -61,5 +119,6 @@
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
+#define QSERDES_V5_COM_RESERVED_1 0x1c0
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
index 6887c0cb3155..fe8f3e330d09 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
@@ -8,28 +8,111 @@
#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
/* Only for QMP V5 PHY - TX registers */
+#define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_V5_TX_BIST_INVERT 0x004
+#define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
+#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
+#define QSERDES_V5_TX_TX_DRV_LVL 0x014
+#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
+#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
+#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
+#define QSERDES_V5_TX_TX_BAND 0x024
+#define QSERDES_V5_TX_SLEW_CNTL 0x028
+#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c
+#define QSERDES_V5_TX_LPB_EN 0x030
#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034
#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V5_TX_PERL_LENGTH1 0x044
+#define QSERDES_V5_TX_PERL_LENGTH2 0x048
+#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c
+#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050
+#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054
+#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058
+#define QSERDES_V5_TX_TX_POL_INV 0x05c
+#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
+#define QSERDES_V5_TX_BIST_PATTERN1 0x064
+#define QSERDES_V5_TX_BIST_PATTERN2 0x068
+#define QSERDES_V5_TX_BIST_PATTERN3 0x06c
+#define QSERDES_V5_TX_BIST_PATTERN4 0x070
+#define QSERDES_V5_TX_BIST_PATTERN5 0x074
+#define QSERDES_V5_TX_BIST_PATTERN6 0x078
+#define QSERDES_V5_TX_BIST_PATTERN7 0x07c
+#define QSERDES_V5_TX_BIST_PATTERN8 0x080
#define QSERDES_V5_TX_LANE_MODE_1 0x084
#define QSERDES_V5_TX_LANE_MODE_2 0x088
#define QSERDES_V5_TX_LANE_MODE_3 0x08c
#define QSERDES_V5_TX_LANE_MODE_4 0x090
#define QSERDES_V5_TX_LANE_MODE_5 0x094
+#define QSERDES_V5_TX_ATB_SEL1 0x098
+#define QSERDES_V5_TX_ATB_SEL2 0x09c
+#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0
#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4
+#define QSERDES_V5_TX_PRBS_SEED1 0x0a8
+#define QSERDES_V5_TX_PRBS_SEED2 0x0ac
+#define QSERDES_V5_TX_PRBS_SEED3 0x0b0
+#define QSERDES_V5_TX_PRBS_SEED4 0x0b4
+#define QSERDES_V5_TX_RESET_GEN 0x0b8
+#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc
#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0
+#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4
+#define QSERDES_V5_TX_VMODE_CTRL1 0x0c8
+#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc
+#define QSERDES_V5_TX_BIST_STATUS 0x0d0
+#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4
+#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8
+#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc
+#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0
#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4
-#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
-#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
-#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
-#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
+#define QSERDES_V5_TX_PRE_EMPH 0x0e8
+#define QSERDES_V5_TX_SW_RESET 0x0ec
+#define QSERDES_V5_TX_DCC_OFFSET 0x0f0
+#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4
+#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8
+#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc
+#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100
+#define QSERDES_V5_TX_DEBUG_BUS0 0x104
+#define QSERDES_V5_TX_DEBUG_BUS1 0x108
+#define QSERDES_V5_TX_DEBUG_BUS2 0x10c
+#define QSERDES_V5_TX_DEBUG_BUS3 0x110
+#define QSERDES_V5_TX_READ_EQCODE 0x114
+#define QSERDES_V5_TX_READ_OFFSETCODE 0x118
+#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c
+#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120
+#define QSERDES_V5_TX_VGA_READ_CODE 0x124
+#define QSERDES_V5_TX_VTH_READ_CODE 0x128
+#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c
+#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130
+#define QSERDES_V5_TX_IDAC_STATUS_I 0x134
+#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138
+#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c
+#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140
+#define QSERDES_V5_TX_IDAC_STATUS_A 0x144
+#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148
+#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c
+#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150
+#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154
+#define QSERDES_V5_TX_DCC_CAL_STATUS 0x158
+#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c
/* Only for QMP V5 PHY - RX registers */
+#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000
+#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004
#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c
+#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010
#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018
+#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
+#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020
+#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024
+#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
+#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c
#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
@@ -38,15 +121,41 @@
#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
+#define QSERDES_V5_RX_AUX_CONTROL 0x05c
#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
+#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c
+#define QSERDES_V5_RX_AC_JTAG_INITN 0x070
+#define QSERDES_V5_RX_AC_JTAG_LVL 0x074
#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
+#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c
#define QSERDES_V5_RX_RX_TERM_BW 0x080
+#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084
+#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088
+#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
+#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090
+#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
+#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098
+#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
+#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0
+#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4
+#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8
+#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac
+#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
+#define QSERDES_V5_RX_DFE_1 0x0b4
+#define QSERDES_V5_RX_DFE_2 0x0b8
+#define QSERDES_V5_RX_DFE_3 0x0bc
+#define QSERDES_V5_RX_DFE_4 0x0c0
+#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4
+#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8
#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
+#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0
#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
#define QSERDES_V5_RX_GM_CAL 0x0dc
+#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0
+#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
@@ -54,6 +163,9 @@
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
+#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104
+#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108
+#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c
#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
@@ -61,6 +173,18 @@
#define QSERDES_V5_RX_SIGDET_LVL 0x120
#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
#define QSERDES_V5_RX_RX_BAND 0x128
+#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c
+#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130
+#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134
+#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138
+#define QSERDES_V5_RX_SJ_AMP1 0x13c
+#define QSERDES_V5_RX_SJ_AMP2 0x140
+#define QSERDES_V5_RX_SJ_PER1 0x144
+#define QSERDES_V5_RX_SJ_PER2 0x148
+#define QSERDES_V5_RX_PPM_OFFSET1 0x14c
+#define QSERDES_V5_RX_PPM_OFFSET2 0x150
+#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154
+#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158
#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
@@ -76,9 +200,32 @@
#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_V5_RX_PHPRE_CTRL 0x198
+#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c
#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
+#define QSERDES_V5_RX_DCC_CTRL2 0x1ac
#define QSERDES_V5_RX_VTH_CODE 0x1b0
+#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4
+#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8
+#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc
+#define QSERDES_V5_RX_PI_CTRL1 0x1c0
+#define QSERDES_V5_RX_PI_CTRL2 0x1c4
+#define QSERDES_V5_RX_PI_QUAD 0x1c8
+#define QSERDES_V5_RX_IDATA1 0x1cc
+#define QSERDES_V5_RX_IDATA2 0x1d0
+#define QSERDES_V5_RX_AUX_DATA1 0x1d4
+#define QSERDES_V5_RX_AUX_DATA2 0x1d8
+#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc
+#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0
+#define QSERDES_V5_RX_RX_SIGDET 0x1e4
+#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8
+
+/* Only for QMP V5 UFS ? */
+#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
+#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
+#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
+#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 24/28] phy: qcom-qmp: qserdes-com-v5: add missing registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-5.4's qcom,usb3-5nm-qmp-uni.h
- msm-5.4's qcom,usb3-5nm-qmp-combo.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../qualcomm/phy-qcom-qmp-qserdes-com-v5.h | 59 +++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h | 155 +++++++++++++++++-
2 files changed, 210 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
index 8d2f9f012fed..c8afdf7bc1ee 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v5.h
@@ -7,24 +7,47 @@
#define QCOM_PHY_QMP_QSERDES_COM_V5_H_
/* Only for QMP V5 PHY - QSERDES COM registers */
+#define QSERDES_V5_COM_ATB_SEL1 0x000
+#define QSERDES_V5_COM_ATB_SEL2 0x004
+#define QSERDES_V5_COM_FREQ_UPDATE 0x008
+#define QSERDES_V5_COM_BG_TIMER 0x00c
#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
+#define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
#define QSERDES_V5_COM_SSC_PER1 0x01c
#define QSERDES_V5_COM_SSC_PER2 0x020
#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c
#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038
+#define QSERDES_V5_COM_POST_DIV 0x03c
+#define QSERDES_V5_COM_POST_DIV_MUX 0x040
#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044
#define QSERDES_V5_COM_CLK_ENABLE1 0x048
+#define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c
#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
+#define QSERDES_V5_COM_PLL_EN 0x054
#define QSERDES_V5_COM_PLL_IVCO 0x058
+#define QSERDES_V5_COM_CMN_IETRIM 0x05c
+#define QSERDES_V5_COM_CMN_IPTRIM 0x060
+#define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064
+#define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068
+#define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c
+#define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070
#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
+#define QSERDES_V5_COM_PLL_CNTRL 0x08c
+#define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090
#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
+#define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098
+#define QSERDES_V5_COM_RESETSM_CNTRL 0x09c
+#define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0
#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8
#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
@@ -32,26 +55,61 @@
#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
+#define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0
#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
+#define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4
+#define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8
+#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
+#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
+#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4
+#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8
+#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc
+#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100
+#define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104
+#define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108
#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
+#define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120
#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128
+#define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c
+#define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130
+#define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134
+#define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138
+#define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c
+#define QSERDES_V5_COM_CMN_STATUS 0x140
+#define QSERDES_V5_COM_RESET_SM_STATUS 0x144
+#define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148
+#define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c
+#define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150
#define QSERDES_V5_COM_CLK_SELECT 0x154
#define QSERDES_V5_COM_HSCLK_SEL 0x158
#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160
+#define QSERDES_V5_COM_PLL_ANALOG 0x164
#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168
#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
+#define QSERDES_V5_COM_SW_RESET 0x170
#define QSERDES_V5_COM_CORE_CLK_EN 0x174
+#define QSERDES_V5_COM_C_READY_STATUS 0x178
#define QSERDES_V5_COM_CMN_CONFIG 0x17c
+#define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180
+#define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184
+#define QSERDES_V5_COM_DEBUG_BUS0 0x188
+#define QSERDES_V5_COM_DEBUG_BUS1 0x18c
+#define QSERDES_V5_COM_DEBUG_BUS2 0x190
+#define QSERDES_V5_COM_DEBUG_BUS3 0x194
+#define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198
#define QSERDES_V5_COM_CMN_MISC1 0x19c
#define QSERDES_V5_COM_CMN_MODE 0x1a0
#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
@@ -61,5 +119,6 @@
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
+#define QSERDES_V5_COM_RESERVED_1 0x1c0
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
index 6887c0cb3155..fe8f3e330d09 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5.h
@@ -8,28 +8,111 @@
#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_
/* Only for QMP V5 PHY - TX registers */
+#define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_V5_TX_BIST_INVERT 0x004
+#define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
+#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
+#define QSERDES_V5_TX_TX_DRV_LVL 0x014
+#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
+#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
+#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
+#define QSERDES_V5_TX_TX_BAND 0x024
+#define QSERDES_V5_TX_SLEW_CNTL 0x028
+#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c
+#define QSERDES_V5_TX_LPB_EN 0x030
#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034
#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c
#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040
+#define QSERDES_V5_TX_PERL_LENGTH1 0x044
+#define QSERDES_V5_TX_PERL_LENGTH2 0x048
+#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c
+#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050
+#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054
+#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058
+#define QSERDES_V5_TX_TX_POL_INV 0x05c
+#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060
+#define QSERDES_V5_TX_BIST_PATTERN1 0x064
+#define QSERDES_V5_TX_BIST_PATTERN2 0x068
+#define QSERDES_V5_TX_BIST_PATTERN3 0x06c
+#define QSERDES_V5_TX_BIST_PATTERN4 0x070
+#define QSERDES_V5_TX_BIST_PATTERN5 0x074
+#define QSERDES_V5_TX_BIST_PATTERN6 0x078
+#define QSERDES_V5_TX_BIST_PATTERN7 0x07c
+#define QSERDES_V5_TX_BIST_PATTERN8 0x080
#define QSERDES_V5_TX_LANE_MODE_1 0x084
#define QSERDES_V5_TX_LANE_MODE_2 0x088
#define QSERDES_V5_TX_LANE_MODE_3 0x08c
#define QSERDES_V5_TX_LANE_MODE_4 0x090
#define QSERDES_V5_TX_LANE_MODE_5 0x094
+#define QSERDES_V5_TX_ATB_SEL1 0x098
+#define QSERDES_V5_TX_ATB_SEL2 0x09c
+#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0
#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4
+#define QSERDES_V5_TX_PRBS_SEED1 0x0a8
+#define QSERDES_V5_TX_PRBS_SEED2 0x0ac
+#define QSERDES_V5_TX_PRBS_SEED3 0x0b0
+#define QSERDES_V5_TX_PRBS_SEED4 0x0b4
+#define QSERDES_V5_TX_RESET_GEN 0x0b8
+#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc
#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0
+#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4
+#define QSERDES_V5_TX_VMODE_CTRL1 0x0c8
+#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc
+#define QSERDES_V5_TX_BIST_STATUS 0x0d0
+#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4
+#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8
+#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc
+#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0
#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4
-#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
-#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
-#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
-#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
+#define QSERDES_V5_TX_PRE_EMPH 0x0e8
+#define QSERDES_V5_TX_SW_RESET 0x0ec
+#define QSERDES_V5_TX_DCC_OFFSET 0x0f0
+#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4
+#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8
+#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc
+#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100
+#define QSERDES_V5_TX_DEBUG_BUS0 0x104
+#define QSERDES_V5_TX_DEBUG_BUS1 0x108
+#define QSERDES_V5_TX_DEBUG_BUS2 0x10c
+#define QSERDES_V5_TX_DEBUG_BUS3 0x110
+#define QSERDES_V5_TX_READ_EQCODE 0x114
+#define QSERDES_V5_TX_READ_OFFSETCODE 0x118
+#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c
+#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120
+#define QSERDES_V5_TX_VGA_READ_CODE 0x124
+#define QSERDES_V5_TX_VTH_READ_CODE 0x128
+#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c
+#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130
+#define QSERDES_V5_TX_IDAC_STATUS_I 0x134
+#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138
+#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c
+#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140
+#define QSERDES_V5_TX_IDAC_STATUS_A 0x144
+#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148
+#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c
+#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150
+#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154
+#define QSERDES_V5_TX_DCC_CAL_STATUS 0x158
+#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c
/* Only for QMP V5 PHY - RX registers */
+#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000
+#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004
#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
+#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c
+#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010
#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
+#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018
+#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c
+#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020
+#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024
+#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
+#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c
#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
@@ -38,15 +121,41 @@
#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
+#define QSERDES_V5_RX_AUX_CONTROL 0x05c
#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
+#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c
+#define QSERDES_V5_RX_AC_JTAG_INITN 0x070
+#define QSERDES_V5_RX_AC_JTAG_LVL 0x074
#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
+#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c
#define QSERDES_V5_RX_RX_TERM_BW 0x080
+#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084
+#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088
+#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c
+#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090
+#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094
+#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098
+#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c
+#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0
+#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4
+#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8
+#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac
+#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0
+#define QSERDES_V5_RX_DFE_1 0x0b4
+#define QSERDES_V5_RX_DFE_2 0x0b8
+#define QSERDES_V5_RX_DFE_3 0x0bc
+#define QSERDES_V5_RX_DFE_4 0x0c0
+#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4
+#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8
#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
+#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0
#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
#define QSERDES_V5_RX_GM_CAL 0x0dc
+#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0
+#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
@@ -54,6 +163,9 @@
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
+#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104
+#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108
+#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c
#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
#define QSERDES_V5_RX_SIGDET_ENABLES 0x118
@@ -61,6 +173,18 @@
#define QSERDES_V5_RX_SIGDET_LVL 0x120
#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
#define QSERDES_V5_RX_RX_BAND 0x128
+#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c
+#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130
+#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134
+#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138
+#define QSERDES_V5_RX_SJ_AMP1 0x13c
+#define QSERDES_V5_RX_SJ_AMP2 0x140
+#define QSERDES_V5_RX_SJ_PER1 0x144
+#define QSERDES_V5_RX_SJ_PER2 0x148
+#define QSERDES_V5_RX_PPM_OFFSET1 0x14c
+#define QSERDES_V5_RX_PPM_OFFSET2 0x150
+#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154
+#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158
#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
@@ -76,9 +200,32 @@
#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_V5_RX_PHPRE_CTRL 0x198
+#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c
#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
+#define QSERDES_V5_RX_DCC_CTRL2 0x1ac
#define QSERDES_V5_RX_VTH_CODE 0x1b0
+#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4
+#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8
+#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc
+#define QSERDES_V5_RX_PI_CTRL1 0x1c0
+#define QSERDES_V5_RX_PI_CTRL2 0x1c4
+#define QSERDES_V5_RX_PI_QUAD 0x1c8
+#define QSERDES_V5_RX_IDATA1 0x1cc
+#define QSERDES_V5_RX_IDATA2 0x1d0
+#define QSERDES_V5_RX_AUX_DATA1 0x1d4
+#define QSERDES_V5_RX_AUX_DATA2 0x1d8
+#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc
+#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0
+#define QSERDES_V5_RX_RX_SIGDET 0x1e4
+#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8
+
+/* Only for QMP V5 UFS ? */
+#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
+#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
+#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
+#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
#endif
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 25/28] phy: qcom-qmp: pcs-v3: add missing registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-4.19's qcom,usb3-11nm-qmp-combo.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 82 ++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
index ac13f2989a73..10dbbb006201 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
@@ -7,7 +7,9 @@
#define QCOM_PHY_QMP_PCS_V3_H_
/* Only for QMP V3 PHY - PCS registers */
+#define QPHY_V3_PCS_SW_RESET 0x000
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V3_PCS_START_CONTROL 0x008
#define QPHY_V3_PCS_TXMGN_V0 0x00c
#define QPHY_V3_PCS_TXMGN_V1 0x010
#define QPHY_V3_PCS_TXMGN_V2 0x014
@@ -31,6 +33,7 @@
#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
+#define QPHY_V3_PCS_POWER_STATE_CONFIG3 0x068
#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
@@ -40,24 +43,103 @@
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
+#define QPHY_V3_PCS_SIGDET_LOW_2_IDLE_TIME 0x090
+#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_L 0x094
+#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_H 0x098
+#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_SYSCLK 0x09c
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
+#define QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL 0x0ac
#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
+#define QPHY_V3_PCS_LFPS_TX_END_CNT_P2U3_START 0x0b4
#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
+#define QPHY_V3_PCS_TXONESZEROS_RUN_LENGTH 0x0c0
#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
+#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL 0x0d8
+#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0dc
+#define QPHY_V3_PCS_ARCVR_DTCT_EN_PERIOD 0x0e0
+#define QPHY_V3_PCS_ARCVR_DTCT_CM_DLY 0x0e4
+#define QPHY_V3_PCS_ALFPS_DEGLITCH_VAL 0x0e8
+#define QPHY_V3_PCS_INSIG_SW_CTRL1 0x0ec
+#define QPHY_V3_PCS_INSIG_SW_CTRL2 0x0f0
+#define QPHY_V3_PCS_INSIG_SW_CTRL3 0x0f4
+#define QPHY_V3_PCS_INSIG_MX_CTRL1 0x0f8
+#define QPHY_V3_PCS_INSIG_MX_CTRL2 0x0fc
+#define QPHY_V3_PCS_INSIG_MX_CTRL3 0x100
+#define QPHY_V3_PCS_OUTSIG_SW_CTRL1 0x104
+#define QPHY_V3_PCS_OUTSIG_MX_CTRL1 0x108
+#define QPHY_V3_PCS_CLK_DEBUG_BYPASS_CTRL 0x10c
+#define QPHY_V3_PCS_TEST_CONTROL 0x110
+#define QPHY_V3_PCS_TEST_CONTROL2 0x114
+#define QPHY_V3_PCS_TEST_CONTROL3 0x118
+#define QPHY_V3_PCS_TEST_CONTROL4 0x11c
+#define QPHY_V3_PCS_TEST_CONTROL5 0x120
+#define QPHY_V3_PCS_TEST_CONTROL6 0x124
+#define QPHY_V3_PCS_TEST_CONTROL7 0x128
+#define QPHY_V3_PCS_COM_RESET_CONTROL 0x12c
+#define QPHY_V3_PCS_BIST_CTRL 0x130
+#define QPHY_V3_PCS_PRBS_POLY0 0x134
+#define QPHY_V3_PCS_PRBS_POLY1 0x138
+#define QPHY_V3_PCS_PRBS_SEED0 0x13c
+#define QPHY_V3_PCS_PRBS_SEED1 0x140
+#define QPHY_V3_PCS_FIXED_PAT_CTRL 0x144
+#define QPHY_V3_PCS_FIXED_PAT0 0x148
+#define QPHY_V3_PCS_FIXED_PAT1 0x14c
+#define QPHY_V3_PCS_FIXED_PAT2 0x150
+#define QPHY_V3_PCS_FIXED_PAT3 0x154
+#define QPHY_V3_PCS_COM_CLK_SWITCH_CTRL 0x158
+#define QPHY_V3_PCS_ELECIDLE_DLY_SEL 0x15c
+#define QPHY_V3_PCS_SPARE1 0x160
+#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_L_STATUS 0x164
+#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_H_STATUS 0x168
+#define QPHY_V3_PCS_BIST_CHK_STATUS 0x16c
+#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x170
+#define QPHY_V3_PCS_PCS_STATUS 0x174
+#define QPHY_V3_PCS_PCS_STATUS2 0x178
+#define QPHY_V3_PCS_PCS_STATUS3 0x17c
+#define QPHY_V3_PCS_COM_RESET_STATUS 0x180
+#define QPHY_V3_PCS_OSC_DTCT_STATUS 0x184
+#define QPHY_V3_PCS_REVISION_ID0 0x188
+#define QPHY_V3_PCS_REVISION_ID1 0x18c
+#define QPHY_V3_PCS_REVISION_ID2 0x190
+#define QPHY_V3_PCS_REVISION_ID3 0x194
+#define QPHY_V3_PCS_DEBUG_BUS_0_STATUS 0x198
+#define QPHY_V3_PCS_DEBUG_BUS_1_STATUS 0x19c
+#define QPHY_V3_PCS_DEBUG_BUS_2_STATUS 0x1a0
+#define QPHY_V3_PCS_DEBUG_BUS_3_STATUS 0x1a4
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
+#define QPHY_V3_PCS_IDAC_CAL_CNTRL 0x1b4
+#define QPHY_V3_PCS_CMN_ACK_OUT_SEL 0x1b8
+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME_SYSCLK 0x1bc
+#define QPHY_V3_PCS_AUTONOMOUS_MODE_STATUS 0x1c0
+#define QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL 0x1c4
+#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_SYSCLK 0x1c8
+#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x1cc
+#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_L 0x1d0
+#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_H 0x1d4
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL2 0x1e4
+#define QPHY_V3_PCS_RXTERMINATION_DLY_SEL 0x1e8
+#define QPHY_V3_PCS_LFPS_PER_TIMER_VAL 0x1ec
+#define QPHY_V3_PCS_SIGDET_STARTUP_TIMER_VAL 0x1f0
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG4 0x1f4
+#define QPHY_V3_PCS_RX_SIGDET_DTCT_CNTRL 0x1f8
+#define QPHY_V3_PCS_PCS_STATUS4 0x1fc
+#define QPHY_V3_PCS_PCS_STATUS4_CLEAR 0x200
+#define QPHY_V3_PCS_DEC_ERROR_COUNT_STATUS 0x204
+#define QPHY_V3_PCS_COMMA_POS_STATUS 0x208
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG3 0x214
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 25/28] phy: qcom-qmp: pcs-v3: add missing registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-4.19's qcom,usb3-11nm-qmp-combo.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h | 82 ++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
index ac13f2989a73..10dbbb006201 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
@@ -7,7 +7,9 @@
#define QCOM_PHY_QMP_PCS_V3_H_
/* Only for QMP V3 PHY - PCS registers */
+#define QPHY_V3_PCS_SW_RESET 0x000
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
+#define QPHY_V3_PCS_START_CONTROL 0x008
#define QPHY_V3_PCS_TXMGN_V0 0x00c
#define QPHY_V3_PCS_TXMGN_V1 0x010
#define QPHY_V3_PCS_TXMGN_V2 0x014
@@ -31,6 +33,7 @@
#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
+#define QPHY_V3_PCS_POWER_STATE_CONFIG3 0x068
#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
@@ -40,24 +43,103 @@
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
+#define QPHY_V3_PCS_SIGDET_LOW_2_IDLE_TIME 0x090
+#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_L 0x094
+#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_H 0x098
+#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_SYSCLK 0x09c
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
+#define QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL 0x0ac
#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
+#define QPHY_V3_PCS_LFPS_TX_END_CNT_P2U3_START 0x0b4
#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
+#define QPHY_V3_PCS_TXONESZEROS_RUN_LENGTH 0x0c0
#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
+#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL 0x0d8
+#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0dc
+#define QPHY_V3_PCS_ARCVR_DTCT_EN_PERIOD 0x0e0
+#define QPHY_V3_PCS_ARCVR_DTCT_CM_DLY 0x0e4
+#define QPHY_V3_PCS_ALFPS_DEGLITCH_VAL 0x0e8
+#define QPHY_V3_PCS_INSIG_SW_CTRL1 0x0ec
+#define QPHY_V3_PCS_INSIG_SW_CTRL2 0x0f0
+#define QPHY_V3_PCS_INSIG_SW_CTRL3 0x0f4
+#define QPHY_V3_PCS_INSIG_MX_CTRL1 0x0f8
+#define QPHY_V3_PCS_INSIG_MX_CTRL2 0x0fc
+#define QPHY_V3_PCS_INSIG_MX_CTRL3 0x100
+#define QPHY_V3_PCS_OUTSIG_SW_CTRL1 0x104
+#define QPHY_V3_PCS_OUTSIG_MX_CTRL1 0x108
+#define QPHY_V3_PCS_CLK_DEBUG_BYPASS_CTRL 0x10c
+#define QPHY_V3_PCS_TEST_CONTROL 0x110
+#define QPHY_V3_PCS_TEST_CONTROL2 0x114
+#define QPHY_V3_PCS_TEST_CONTROL3 0x118
+#define QPHY_V3_PCS_TEST_CONTROL4 0x11c
+#define QPHY_V3_PCS_TEST_CONTROL5 0x120
+#define QPHY_V3_PCS_TEST_CONTROL6 0x124
+#define QPHY_V3_PCS_TEST_CONTROL7 0x128
+#define QPHY_V3_PCS_COM_RESET_CONTROL 0x12c
+#define QPHY_V3_PCS_BIST_CTRL 0x130
+#define QPHY_V3_PCS_PRBS_POLY0 0x134
+#define QPHY_V3_PCS_PRBS_POLY1 0x138
+#define QPHY_V3_PCS_PRBS_SEED0 0x13c
+#define QPHY_V3_PCS_PRBS_SEED1 0x140
+#define QPHY_V3_PCS_FIXED_PAT_CTRL 0x144
+#define QPHY_V3_PCS_FIXED_PAT0 0x148
+#define QPHY_V3_PCS_FIXED_PAT1 0x14c
+#define QPHY_V3_PCS_FIXED_PAT2 0x150
+#define QPHY_V3_PCS_FIXED_PAT3 0x154
+#define QPHY_V3_PCS_COM_CLK_SWITCH_CTRL 0x158
+#define QPHY_V3_PCS_ELECIDLE_DLY_SEL 0x15c
+#define QPHY_V3_PCS_SPARE1 0x160
+#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_L_STATUS 0x164
+#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_H_STATUS 0x168
+#define QPHY_V3_PCS_BIST_CHK_STATUS 0x16c
+#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x170
+#define QPHY_V3_PCS_PCS_STATUS 0x174
+#define QPHY_V3_PCS_PCS_STATUS2 0x178
+#define QPHY_V3_PCS_PCS_STATUS3 0x17c
+#define QPHY_V3_PCS_COM_RESET_STATUS 0x180
+#define QPHY_V3_PCS_OSC_DTCT_STATUS 0x184
+#define QPHY_V3_PCS_REVISION_ID0 0x188
+#define QPHY_V3_PCS_REVISION_ID1 0x18c
+#define QPHY_V3_PCS_REVISION_ID2 0x190
+#define QPHY_V3_PCS_REVISION_ID3 0x194
+#define QPHY_V3_PCS_DEBUG_BUS_0_STATUS 0x198
+#define QPHY_V3_PCS_DEBUG_BUS_1_STATUS 0x19c
+#define QPHY_V3_PCS_DEBUG_BUS_2_STATUS 0x1a0
+#define QPHY_V3_PCS_DEBUG_BUS_3_STATUS 0x1a4
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
+#define QPHY_V3_PCS_IDAC_CAL_CNTRL 0x1b4
+#define QPHY_V3_PCS_CMN_ACK_OUT_SEL 0x1b8
+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME_SYSCLK 0x1bc
+#define QPHY_V3_PCS_AUTONOMOUS_MODE_STATUS 0x1c0
+#define QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL 0x1c4
+#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_SYSCLK 0x1c8
+#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x1cc
+#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_L 0x1d0
+#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_H 0x1d4
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
+#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL2 0x1e4
+#define QPHY_V3_PCS_RXTERMINATION_DLY_SEL 0x1e8
+#define QPHY_V3_PCS_LFPS_PER_TIMER_VAL 0x1ec
+#define QPHY_V3_PCS_SIGDET_STARTUP_TIMER_VAL 0x1f0
+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG4 0x1f4
+#define QPHY_V3_PCS_RX_SIGDET_DTCT_CNTRL 0x1f8
+#define QPHY_V3_PCS_PCS_STATUS4 0x1fc
+#define QPHY_V3_PCS_PCS_STATUS4_CLEAR 0x200
+#define QPHY_V3_PCS_DEC_ERROR_COUNT_STATUS 0x204
+#define QPHY_V3_PCS_COMMA_POS_STATUS 0x208
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG3 0x214
#endif
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 26/28] phy: qcom-qmp: pcs-pcie-v4: add missing registers
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-4.19's qcom,kona-qmp-usb3.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
index 5a97867c5ba6..4cc02288d418 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
@@ -7,17 +7,66 @@
#define QCOM_PHY_QMP_PCS_PCIE_V4_H_
/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
+#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04
+#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
+#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
+#define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
+#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20
+#define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24
+#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28
+#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c
+#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30
+#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34
+#define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38
+#define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
+#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
+#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
+#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c
#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
+#define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94
+#define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98
+#define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c
#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
+#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8
+#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac
+#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
+#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
+#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0
+#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4
+#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8
+#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc
+#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0
+#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4
+#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8
+#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc
#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
+#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4
+#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8
+#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec
+#define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 26/28] phy: qcom-qmp: pcs-pcie-v4: add missing registers
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Add missing registers, verified against:
- msm-4.19's qcom,kona-qmp-usb3.h
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
index 5a97867c5ba6..4cc02288d418 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4.h
@@ -7,17 +7,66 @@
#define QCOM_PHY_QMP_PCS_PCIE_V4_H_
/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
+#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04
+#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
+#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
+#define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
+#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20
+#define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24
+#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28
+#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c
+#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30
+#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34
+#define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38
+#define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
+#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
+#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
+#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88
+#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c
#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
+#define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94
+#define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98
+#define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c
#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0
#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
+#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8
+#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac
+#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
+#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
+#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0
+#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4
+#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8
+#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc
+#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0
+#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4
+#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8
+#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc
#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
+#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4
+#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8
+#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec
+#define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0
#endif
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 27/28] phy: qcom-qmp-usb: replace FLL layout writes for msm8996
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Other PHYs tables directly reference FLL registers without using
reglayout. Define corresponding registers to be used by msm8996 PHY
tables and use them directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 5 -----
.../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 10 ----------
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 10 ----------
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 7 +++++++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 5 -----
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++--------------
6 files changed, 12 insertions(+), 45 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 2335658affdb..3f2c89ffee21 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 90a4bb8e86a4..5bbdf5675974 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -147,11 +142,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448,
[QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
- [QPHY_FLL_CNTRL1] = 0xc4,
- [QPHY_FLL_CNTRL2] = 0xc8,
- [QPHY_FLL_CNT_VAL_L] = 0xcc,
- [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
- [QPHY_FLL_MAN_CODE] = 0xd4,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x174,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 5b3f612d1c2c..4d17169c5eb0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -154,11 +149,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448,
[QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
- [QPHY_FLL_CNTRL1] = 0xc4,
- [QPHY_FLL_CNTRL2] = 0xc8,
- [QPHY_FLL_CNT_VAL_L] = 0xcc,
- [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
- [QPHY_FLL_MAN_CODE] = 0xd4,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x174,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
index 3fc3c0562d16..9593277cbd3a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
@@ -24,6 +24,13 @@
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
+#define QPHY_V2_PCS_FLL_CNTRL1 0x0c0
+#define QPHY_V2_PCS_FLL_CNTRL2 0x0c4
+#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
+#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc
+#define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0
+
+/* UFS only ? */
#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 701b03a13b17..7ab129cd739b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index 98c6b5c8e2fc..da2e6fe1336f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -142,11 +137,6 @@ enum qphy_reg_layout {
};
static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_FLL_CNTRL1] = 0xc0,
- [QPHY_FLL_CNTRL2] = 0xc4,
- [QPHY_FLL_CNT_VAL_L] = 0xc8,
- [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
- [QPHY_FLL_MAN_CODE] = 0xd0,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x17c,
@@ -318,11 +308,11 @@ static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
/* FLL settings */
- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
- QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
/* Lock Det settings */
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 27/28] phy: qcom-qmp-usb: replace FLL layout writes for msm8996
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Other PHYs tables directly reference FLL registers without using
reglayout. Define corresponding registers to be used by msm8996 PHY
tables and use them directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 5 -----
.../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 10 ----------
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 10 ----------
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 7 +++++++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 5 -----
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++--------------
6 files changed, 12 insertions(+), 45 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 2335658affdb..3f2c89ffee21 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 90a4bb8e86a4..5bbdf5675974 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -147,11 +142,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448,
[QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
- [QPHY_FLL_CNTRL1] = 0xc4,
- [QPHY_FLL_CNTRL2] = 0xc8,
- [QPHY_FLL_CNT_VAL_L] = 0xcc,
- [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
- [QPHY_FLL_MAN_CODE] = 0xd4,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x174,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 5b3f612d1c2c..4d17169c5eb0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -154,11 +149,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448,
[QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
- [QPHY_FLL_CNTRL1] = 0xc4,
- [QPHY_FLL_CNTRL2] = 0xc8,
- [QPHY_FLL_CNT_VAL_L] = 0xcc,
- [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
- [QPHY_FLL_MAN_CODE] = 0xd4,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x174,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
index 3fc3c0562d16..9593277cbd3a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
@@ -24,6 +24,13 @@
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
+#define QPHY_V2_PCS_FLL_CNTRL1 0x0c0
+#define QPHY_V2_PCS_FLL_CNTRL2 0x0c4
+#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
+#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc
+#define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0
+
+/* UFS only ? */
#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 701b03a13b17..7ab129cd739b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index 98c6b5c8e2fc..da2e6fe1336f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -122,11 +122,6 @@ enum qphy_reg_layout {
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
QPHY_PLL_LOCK_CHK_DLY_TIME,
- QPHY_FLL_CNTRL1,
- QPHY_FLL_CNTRL2,
- QPHY_FLL_CNT_VAL_L,
- QPHY_FLL_CNT_VAL_H_TOL,
- QPHY_FLL_MAN_CODE,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -142,11 +137,6 @@ enum qphy_reg_layout {
};
static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_FLL_CNTRL1] = 0xc0,
- [QPHY_FLL_CNTRL2] = 0xc4,
- [QPHY_FLL_CNT_VAL_L] = 0xc8,
- [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
- [QPHY_FLL_MAN_CODE] = 0xd0,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x17c,
@@ -318,11 +308,11 @@ static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
/* FLL settings */
- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
- QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
/* Lock Det settings */
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-06-10 19:09 ` Dmitry Baryshkov
-1 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Other PHYs tables directly reference QPHY_PLL_LOCK_CHK_DLY_TIME register
without using reglayout. Define corresponding register to be used by
msm8996 PHY tables and use it directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 -
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 4 +---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 1 -
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 1 -
6 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 3f2c89ffee21..01e1d3f7538b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 5bbdf5675974..76afe55db7cc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -141,7 +140,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
[QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448,
- [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x174,
@@ -216,7 +214,7 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 4d17169c5eb0..5b222bd17611 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -148,7 +147,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
[QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448,
- [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x174,
@@ -435,7 +433,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
index 9593277cbd3a..c8515f506872 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
@@ -24,6 +24,7 @@
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
#define QPHY_V2_PCS_FLL_CNTRL1 0x0c0
#define QPHY_V2_PCS_FLL_CNTRL2 0x0c4
#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 7ab129cd739b..c8583f5a54bd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index da2e6fe1336f..c54df83637b1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
--
2.35.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC PATCH 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register
@ 2022-06-10 19:09 ` Dmitry Baryshkov
0 siblings, 0 replies; 60+ messages in thread
From: Dmitry Baryshkov @ 2022-06-10 19:09 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
Other PHYs tables directly reference QPHY_PLL_LOCK_CHK_DLY_TIME register
without using reglayout. Define corresponding register to be used by
msm8996 PHY tables and use it directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 -
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 4 +---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 1 -
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 1 -
6 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 3f2c89ffee21..01e1d3f7538b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 5bbdf5675974..76afe55db7cc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -141,7 +140,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
[QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448,
- [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x174,
@@ -216,7 +214,7 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 4d17169c5eb0..5b222bd17611 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
@@ -148,7 +147,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
[QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448,
- [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x08,
[QPHY_PCS_STATUS] = 0x174,
@@ -435,7 +433,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
+ QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
index 9593277cbd3a..c8515f506872 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
@@ -24,6 +24,7 @@
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
#define QPHY_V2_PCS_FLL_CNTRL1 0x0c0
#define QPHY_V2_PCS_FLL_CNTRL2 0x0c4
#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 7ab129cd739b..c8583f5a54bd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index da2e6fe1336f..c54df83637b1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -121,7 +121,6 @@ enum qphy_reg_layout {
QPHY_COM_START_CONTROL,
QPHY_COM_PCS_READY_STATUS,
/* PCS registers */
- QPHY_PLL_LOCK_CHK_DLY_TIME,
QPHY_SW_RESET,
QPHY_START_CTRL,
QPHY_PCS_READY_STATUS,
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [RFC PATCH 00/28] phy: qcom-qmp: split register tables
2022-06-10 19:08 ` Dmitry Baryshkov
@ 2022-07-05 7:05 ` Vinod Koul
-1 siblings, 0 replies; 60+ messages in thread
From: Vinod Koul @ 2022-07-05 7:05 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I,
Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
On 10-06-22, 22:08, Dmitry Baryshkov wrote:
> As discussed during sc8280xp PHY review, rework and split QMP register
> tables. Create separate files for most of QMP register kinds. The only
> things left are various DP registers, which will be handled separately.
This fails for me on patch 2, can you please rebase on my next later
today and resend. I would like to merge this for current cycle..
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC PATCH 00/28] phy: qcom-qmp: split register tables
@ 2022-07-05 7:05 ` Vinod Koul
0 siblings, 0 replies; 60+ messages in thread
From: Vinod Koul @ 2022-07-05 7:05 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I,
Philipp Zabel, linux-arm-msm, linux-phy, Johan Hovold
On 10-06-22, 22:08, Dmitry Baryshkov wrote:
> As discussed during sc8280xp PHY review, rework and split QMP register
> tables. Create separate files for most of QMP register kinds. The only
> things left are various DP registers, which will be handled separately.
This fails for me on patch 2, can you please rebase on my next later
today and resend. I would like to merge this for current cycle..
--
~Vinod
^ permalink raw reply [flat|nested] 60+ messages in thread
end of thread, other threads:[~2022-07-05 7:06 UTC | newest]
Thread overview: 60+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-10 19:08 [RFC PATCH 00/28] phy: qcom-qmp: split register tables Dmitry Baryshkov
2022-06-10 19:08 ` Dmitry Baryshkov
2022-06-10 19:08 ` [RFC PATCH 01/28] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register Dmitry Baryshkov
2022-06-10 19:08 ` Dmitry Baryshkov
2022-06-10 19:08 ` [RFC PATCH 02/28] phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table Dmitry Baryshkov
2022-06-10 19:08 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 03/28] phy: qcom-qmp-combo,usb: add support for separate PCS_USB region Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 04/28] phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3 Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 05/28] phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 06/28] phy: qcom-qmp: rename QMP V2 PCS registers Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 07/28] phy: qcom-qmp: use QPHY_V4_PCS for ipq6018 PCIe gen3 Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 08/28] phy: qcom-qmp: move QSERDES registers to separate header Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 09/28] phy: qcom-qmp: move QSERDES V3 registers to separate headers Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 10/28] phy: qcom-qmp: move QSERDES V4 " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 11/28] phy: qcom-qmp: move QSERDES V5 " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 12/28] phy: qcom-qmp: move QSERDES PLL registers to separate header Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 13/28] phy: qcom-qmp: move PCS V2 " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 14/28] phy: qcom-qmp: move PCS V3 registers to separate headers Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 15/28] phy: qcom-qmp: move PCS V4 " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 16/28] phy: qcom-qmp: move PCS V5 " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 17/28] phy: qcom-qmp: move PCIE QHP registers to separate header Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 18/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 19/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 20/28] phy: qcom-qmp: split PCS_UFS V3 symbols to separate header Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 21/28] phy: qcom-qmp: qserdes-com: add missing registers Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 22/28] phy: qcom-qmp: qserdes-com-v3: " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 23/28] phy: qcom-qmp: qserdes-com-v4: " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 24/28] phy: qcom-qmp: qserdes-com-v5: " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 25/28] phy: qcom-qmp: pcs-v3: " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 26/28] phy: qcom-qmp: pcs-pcie-v4: " Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 27/28] phy: qcom-qmp-usb: replace FLL layout writes for msm8996 Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-06-10 19:09 ` [RFC PATCH 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register Dmitry Baryshkov
2022-06-10 19:09 ` Dmitry Baryshkov
2022-07-05 7:05 ` [RFC PATCH 00/28] phy: qcom-qmp: split register tables Vinod Koul
2022-07-05 7:05 ` Vinod Koul
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