* [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
@ 2022-07-14 18:58 Shenwei Wang
2022-07-19 10:25 ` Ilpo Järvinen
2022-07-28 8:35 ` Greg KH
0 siblings, 2 replies; 6+ messages in thread
From: Shenwei Wang @ 2022-07-14 18:58 UTC (permalink / raw)
To: gregkh; +Cc: linux-serial, stable, Shenwei Wang
The LPUART hardware doesn't zero out the parity bit on the received
characters. This behavior won't impact the use cases of CS8 because
the parity bit is the 9th bit which is not currently used by software.
But the parity bit for CS7 must be zeroed out by software in order to
get the correct raw data.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
---
changes in v2
- remove the "inline" keyword from the function of lpuart_tty_insert_flip_string;
changes in v1
- fix the code indent and whitespace issue;
drivers/tty/serial/fsl_lpuart.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index fc7d235a1e270..afa0f941c862f 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -274,6 +274,8 @@ struct lpuart_port {
int rx_dma_rng_buf_len;
unsigned int dma_tx_nents;
wait_queue_head_t dma_wait;
+ bool is_cs7; /* Set to true when character size is 7 */
+ /* and the parity is enabled */
};
struct lpuart_soc_data {
@@ -1022,6 +1024,9 @@ static void lpuart32_rxint(struct lpuart_port *sport)
flg = TTY_OVERRUN;
}
+ if (sport->is_cs7)
+ rx &= 0x7F;
+
if (tty_insert_flip_char(port, rx, flg) == 0)
sport->port.icount.buf_overrun++;
}
@@ -1107,6 +1112,17 @@ static void lpuart_handle_sysrq(struct lpuart_port *sport)
}
}
+static int lpuart_tty_insert_flip_string(struct tty_port *port,
+ unsigned char *chars, size_t size, bool is_cs7)
+{
+ int i;
+
+ if (is_cs7)
+ for (i = 0; i < size; i++)
+ chars[i] &= 0x7F;
+ return tty_insert_flip_string(port, chars, size);
+}
+
static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
{
struct tty_port *port = &sport->port.state->port;
@@ -1217,7 +1233,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
if (ring->head < ring->tail) {
count = sport->rx_sgl.length - ring->tail;
- copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
+ copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
+ count, sport->is_cs7);
if (copied != count)
sport->port.icount.buf_overrun++;
ring->tail = 0;
@@ -1227,7 +1244,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
/* Finally we read data from tail to head */
if (ring->tail < ring->head) {
count = ring->head - ring->tail;
- copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
+ copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
+ count, sport->is_cs7);
if (copied != count)
sport->port.icount.buf_overrun++;
/* Wrap ring->head if needed */
@@ -2066,6 +2084,7 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
bd = lpuart32_read(&sport->port, UARTBAUD);
modem = lpuart32_read(&sport->port, UARTMODIR);
+ sport->is_cs7 = false;
/*
* only support CS8 and CS7, and for CS7 must enable PE.
* supported mode:
@@ -2184,6 +2203,9 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
lpuart32_write(&sport->port, ctrl, UARTCTRL);
/* restore control register */
+ if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
+ sport->is_cs7 = true;
+
if (old && sport->lpuart_dma_rx_use) {
if (!lpuart_start_rx_dma(sport))
rx_dma_timer_init(sport);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
2022-07-14 18:58 [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode Shenwei Wang
@ 2022-07-19 10:25 ` Ilpo Järvinen
2022-07-19 23:33 ` [EXT] " Shenwei Wang
2022-07-28 8:35 ` Greg KH
1 sibling, 1 reply; 6+ messages in thread
From: Ilpo Järvinen @ 2022-07-19 10:25 UTC (permalink / raw)
To: Shenwei Wang; +Cc: Greg Kroah-Hartman, linux-serial, stable
On Thu, 14 Jul 2022, Shenwei Wang wrote:
> The LPUART hardware doesn't zero out the parity bit on the received
> characters. This behavior won't impact the use cases of CS8 because
> the parity bit is the 9th bit which is not currently used by software.
> But the parity bit for CS7 must be zeroed out by software in order to
> get the correct raw data.
This problem only occurs with the lpuart32 variant? Or should the other
functions be changed as well?
--
i.
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> ---
> changes in v2
> - remove the "inline" keyword from the function of lpuart_tty_insert_flip_string;
>
> changes in v1
> - fix the code indent and whitespace issue;
>
> drivers/tty/serial/fsl_lpuart.c | 26 ++++++++++++++++++++++++--
> 1 file changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
> index fc7d235a1e270..afa0f941c862f 100644
> --- a/drivers/tty/serial/fsl_lpuart.c
> +++ b/drivers/tty/serial/fsl_lpuart.c
> @@ -274,6 +274,8 @@ struct lpuart_port {
> int rx_dma_rng_buf_len;
> unsigned int dma_tx_nents;
> wait_queue_head_t dma_wait;
> + bool is_cs7; /* Set to true when character size is 7 */
> + /* and the parity is enabled */
> };
>
> struct lpuart_soc_data {
> @@ -1022,6 +1024,9 @@ static void lpuart32_rxint(struct lpuart_port *sport)
> flg = TTY_OVERRUN;
> }
>
> + if (sport->is_cs7)
> + rx &= 0x7F;
> +
> if (tty_insert_flip_char(port, rx, flg) == 0)
> sport->port.icount.buf_overrun++;
> }
> @@ -1107,6 +1112,17 @@ static void lpuart_handle_sysrq(struct lpuart_port *sport)
> }
> }
>
> +static int lpuart_tty_insert_flip_string(struct tty_port *port,
> + unsigned char *chars, size_t size, bool is_cs7)
> +{
> + int i;
> +
> + if (is_cs7)
> + for (i = 0; i < size; i++)
> + chars[i] &= 0x7F;
> + return tty_insert_flip_string(port, chars, size);
> +}
> +
> static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
> {
> struct tty_port *port = &sport->port.state->port;
> @@ -1217,7 +1233,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
> if (ring->head < ring->tail) {
> count = sport->rx_sgl.length - ring->tail;
>
> - copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
> + copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
> + count, sport->is_cs7);
> if (copied != count)
> sport->port.icount.buf_overrun++;
> ring->tail = 0;
> @@ -1227,7 +1244,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
> /* Finally we read data from tail to head */
> if (ring->tail < ring->head) {
> count = ring->head - ring->tail;
> - copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
> + copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
> + count, sport->is_cs7);
> if (copied != count)
> sport->port.icount.buf_overrun++;
> /* Wrap ring->head if needed */
> @@ -2066,6 +2084,7 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
> ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
> bd = lpuart32_read(&sport->port, UARTBAUD);
> modem = lpuart32_read(&sport->port, UARTMODIR);
> + sport->is_cs7 = false;
> /*
> * only support CS8 and CS7, and for CS7 must enable PE.
> * supported mode:
> @@ -2184,6 +2203,9 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
> lpuart32_write(&sport->port, ctrl, UARTCTRL);
> /* restore control register */
>
> + if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
> + sport->is_cs7 = true;
> +
> if (old && sport->lpuart_dma_rx_use) {
> if (!lpuart_start_rx_dma(sport))
> rx_dma_timer_init(sport);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [EXT] Re: [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
2022-07-19 10:25 ` Ilpo Järvinen
@ 2022-07-19 23:33 ` Shenwei Wang
0 siblings, 0 replies; 6+ messages in thread
From: Shenwei Wang @ 2022-07-19 23:33 UTC (permalink / raw)
To: Ilpo Järvinen; +Cc: Greg Kroah-Hartman, linux-serial, stable
> -----Original Message-----
> From: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> Sent: Tuesday, July 19, 2022 5:26 AM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; linux-serial <linux-
> serial@vger.kernel.org>; stable@vger.kernel.org
> Subject: [EXT] Re: [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> mode
>
> Caution: EXT Email
>
> On Thu, 14 Jul 2022, Shenwei Wang wrote:
>
> > The LPUART hardware doesn't zero out the parity bit on the received
> > characters. This behavior won't impact the use cases of CS8 because
> > the parity bit is the 9th bit which is not currently used by software.
> > But the parity bit for CS7 must be zeroed out by software in order to
> > get the correct raw data.
>
> This problem only occurs with the lpuart32 variant? Or should the other
> functions be changed as well?
In theory this problem should occur with the non lpuart32 variant too, because LPUART32 was derived from the non lpuart32 IP module. However, I don't have a platform to confirm it.
Thanks,
Shenwei
>
> --
> i.
>
>
> > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > ---
> > changes in v2
> > - remove the "inline" keyword from the function of
> > lpuart_tty_insert_flip_string;
> >
> > changes in v1
> > - fix the code indent and whitespace issue;
> >
> > drivers/tty/serial/fsl_lpuart.c | 26 ++++++++++++++++++++++++--
> > 1 file changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/tty/serial/fsl_lpuart.c
> > b/drivers/tty/serial/fsl_lpuart.c index fc7d235a1e270..afa0f941c862f
> > 100644
> > --- a/drivers/tty/serial/fsl_lpuart.c
> > +++ b/drivers/tty/serial/fsl_lpuart.c
> > @@ -274,6 +274,8 @@ struct lpuart_port {
> > int rx_dma_rng_buf_len;
> > unsigned int dma_tx_nents;
> > wait_queue_head_t dma_wait;
> > + bool is_cs7; /* Set to true when character size is 7 */
> > + /* and the parity is enabled */
> > };
> >
> > struct lpuart_soc_data {
> > @@ -1022,6 +1024,9 @@ static void lpuart32_rxint(struct lpuart_port *sport)
> > flg = TTY_OVERRUN;
> > }
> >
> > + if (sport->is_cs7)
> > + rx &= 0x7F;
> > +
> > if (tty_insert_flip_char(port, rx, flg) == 0)
> > sport->port.icount.buf_overrun++;
> > }
> > @@ -1107,6 +1112,17 @@ static void lpuart_handle_sysrq(struct lpuart_port
> *sport)
> > }
> > }
> >
> > +static int lpuart_tty_insert_flip_string(struct tty_port *port,
> > + unsigned char *chars, size_t size, bool is_cs7) {
> > + int i;
> > +
> > + if (is_cs7)
> > + for (i = 0; i < size; i++)
> > + chars[i] &= 0x7F;
> > + return tty_insert_flip_string(port, chars, size); }
> > +
> > static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) {
> > struct tty_port *port = &sport->port.state->port; @@ -1217,7
> > +1233,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
> > if (ring->head < ring->tail) {
> > count = sport->rx_sgl.length - ring->tail;
> >
> > - copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
> > + copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
> > + count, sport->is_cs7);
> > if (copied != count)
> > sport->port.icount.buf_overrun++;
> > ring->tail = 0;
> > @@ -1227,7 +1244,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port
> *sport)
> > /* Finally we read data from tail to head */
> > if (ring->tail < ring->head) {
> > count = ring->head - ring->tail;
> > - copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
> > + copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
> > + count, sport->is_cs7);
> > if (copied != count)
> > sport->port.icount.buf_overrun++;
> > /* Wrap ring->head if needed */ @@ -2066,6 +2084,7 @@
> > lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
> > ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
> > bd = lpuart32_read(&sport->port, UARTBAUD);
> > modem = lpuart32_read(&sport->port, UARTMODIR);
> > + sport->is_cs7 = false;
> > /*
> > * only support CS8 and CS7, and for CS7 must enable PE.
> > * supported mode:
> > @@ -2184,6 +2203,9 @@ lpuart32_set_termios(struct uart_port *port, struct
> ktermios *termios,
> > lpuart32_write(&sport->port, ctrl, UARTCTRL);
> > /* restore control register */
> >
> > + if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
> > + sport->is_cs7 = true;
> > +
> > if (old && sport->lpuart_dma_rx_use) {
> > if (!lpuart_start_rx_dma(sport))
> > rx_dma_timer_init(sport);
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
2022-07-14 18:58 [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode Shenwei Wang
2022-07-19 10:25 ` Ilpo Järvinen
@ 2022-07-28 8:35 ` Greg KH
2022-07-28 18:15 ` [EXT] " Shenwei Wang
1 sibling, 1 reply; 6+ messages in thread
From: Greg KH @ 2022-07-28 8:35 UTC (permalink / raw)
To: Shenwei Wang; +Cc: linux-serial, stable
On Thu, Jul 14, 2022 at 01:58:58PM -0500, Shenwei Wang wrote:
> The LPUART hardware doesn't zero out the parity bit on the received
> characters. This behavior won't impact the use cases of CS8 because
> the parity bit is the 9th bit which is not currently used by software.
> But the parity bit for CS7 must be zeroed out by software in order to
> get the correct raw data.
>
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> ---
> changes in v2
> - remove the "inline" keyword from the function of lpuart_tty_insert_flip_string;
>
> changes in v1
> - fix the code indent and whitespace issue;
Please work with your email admins to fix up your systems as it is
showing this is an invalid signature when validating it:
✗ BADSIG: DKIM/nxp.com
Soon I will just reject patches like this as you don't want people to
impersonate your domain, right?
thanks,
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [EXT] Re: [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
2022-07-28 8:35 ` Greg KH
@ 2022-07-28 18:15 ` Shenwei Wang
2022-07-29 7:52 ` Greg KH
0 siblings, 1 reply; 6+ messages in thread
From: Shenwei Wang @ 2022-07-28 18:15 UTC (permalink / raw)
To: Greg KH; +Cc: linux-serial, stable
Hi Greg,
I tried to send an email again to check this DKIM badsig issue, but everything looked fine here. Can you please let me know how you validated the signature? The following is my DKIM validating info:
----
DKIM Information:
DKIM Signature
Message contains this DKIM Signature:
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=HY2pC5xqaOLmE689KAZnKl30J3TnLONOqLYxM4y08r0=;
b=M7qxUAWtDowVzPZs0eTTdrStj3bo9DDxO3rsxhBiCGs1PMAjGv1JGOwEzz/UQ/qgQ14O+l6OXybJojrpmh1zVophUphTVy2sNaW5oK5s5oU1ZXeMTu0jtm3ajPIRPlTRV8JeyV0Rq8qgPdhA59Gqb/1UYhW0Aq5gO0ImjVwj2Fc=
Signature Information:
v= Version: 1
a= Algorithm: rsa-sha256
c= Method: relaxed/relaxed
d= Domain: nxp.com
s= Selector: selector2
q= Protocol:
bh= HY2pC5xqaOLmE689KAZnKl30J3TnLONOqLYxM4y08r0=
h= Signed Headers: From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck
b= Data: M7qxUAWtDowVzPZs0eTTdrStj3bo9DDxO3rsxhBiCGs1PMAjGv1JGOwEzz/UQ/qgQ14O+l6OXybJojrpmh1zVophUphTVy2sNaW5oK5s5oU1ZXeMTu0jtm3ajPIRPlTRV8JeyV0Rq8qgPdhA59Gqb/1UYhW0Aq5gO0ImjVwj2Fc=
Public Key DNS Lookup
Building DNS Query for selector2._domainkey.nxp.com
Retrieved this publickey from DNS: v=DKIM1; k=rsa; p=MIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQC0SigNOw1Kjk6b0883ph4IRUjfgLfp8yL2J8RwU9J9mMTkKxyFQYMtqUR0C0HmGtDjzdKT3DUHe06GjP9Hq6Jbiga0JKKVp3iy6lyLFmvcy64odjUrvOhKgOjgnRpeEV2t98a/idhL3sRxH1JkjqkLmUy4k7k4EY105oYA31IpOwIDAQAB;
Validating Signature
result = pass
Details:
Regards,
Shenwei
> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Thursday, July 28, 2022 3:35 AM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: linux-serial@vger.kernel.org; stable@vger.kernel.org
> Subject: [EXT] Re: [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> mode
>
> Caution: EXT Email
>
> On Thu, Jul 14, 2022 at 01:58:58PM -0500, Shenwei Wang wrote:
> > The LPUART hardware doesn't zero out the parity bit on the received
> > characters. This behavior won't impact the use cases of CS8 because
> > the parity bit is the 9th bit which is not currently used by software.
> > But the parity bit for CS7 must be zeroed out by software in order to
> > get the correct raw data.
> >
> > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > ---
> > changes in v2
> > - remove the "inline" keyword from the function of
> > lpuart_tty_insert_flip_string;
> >
> > changes in v1
> > - fix the code indent and whitespace issue;
>
> Please work with your email admins to fix up your systems as it is showing this is
> an invalid signature when validating it:
> ✗ BADSIG: DKIM/nxp.com
>
> Soon I will just reject patches like this as you don't want people to impersonate
> your domain, right?
>
> thanks,
>
> greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [EXT] Re: [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
2022-07-28 18:15 ` [EXT] " Shenwei Wang
@ 2022-07-29 7:52 ` Greg KH
0 siblings, 0 replies; 6+ messages in thread
From: Greg KH @ 2022-07-29 7:52 UTC (permalink / raw)
To: Shenwei Wang; +Cc: linux-serial, stable
A: http://en.wikipedia.org/wiki/Top_post
Q: Were do I find info about this thing called top-posting?
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
A: No.
Q: Should I include quotations after my reply?
http://daringfireball.net/2007/07/on_top
On Thu, Jul 28, 2022 at 06:15:09PM +0000, Shenwei Wang wrote:
> Hi Greg,
>
> I tried to send an email again to check this DKIM badsig issue, but everything looked fine here. Can you please let me know how you validated the signature? The following is my DKIM validating info:
I use b4, and here's what I used and you should be able to duplicate it
yourself:
$ b4 am -t https://lore.kernel.org/r/20220714185858.615373-1-shenwei.wang@nxp.com
Grabbing thread from lore.kernel.org/all/20220714185858.615373-1-shenwei.wang%40nxp.com/t.mbox.gz
Analyzing 5 messages in the thread
Checking attestation on all messages, may take a moment...
---
✗ [PATCH v2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
---
✗ BADSIG: DKIM/nxp.com
---
Total patches: 1
---
Link: https://lore.kernel.org/r/20220714185858.615373-1-shenwei.wang@nxp.com
Base: not specified
git am ./v2_20220714_shenwei_wang_serial_fsl_lpuart_zero_out_parity_bit_in_cs7_mode.mbx
thanks,
greg k-h
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-07-29 7:52 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-14 18:58 [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode Shenwei Wang
2022-07-19 10:25 ` Ilpo Järvinen
2022-07-19 23:33 ` [EXT] " Shenwei Wang
2022-07-28 8:35 ` Greg KH
2022-07-28 18:15 ` [EXT] " Shenwei Wang
2022-07-29 7:52 ` Greg KH
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