* [Qemu-devel] [PATCH v2 1/7] elf: Fix PT_MIPS_XXX constants
2018-10-05 15:19 [Qemu-devel] [PATCH v2 0/7] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
@ 2018-10-05 15:19 ` Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 2/7] elf: Add MIPS_ABI_FP_XXX constants Aleksandar Markovic
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-05 15:19 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Fix existing and add missing PT_MIPS_XXX constants in elf.h.
This is copied from kernel header arch/mips/include/asm/elf.h.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
include/elf.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/include/elf.h b/include/elf.h
index 312f68a..decf210 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -28,8 +28,11 @@ typedef int64_t Elf64_Sxword;
#define PT_PHDR 6
#define PT_LOPROC 0x70000000
#define PT_HIPROC 0x7fffffff
-#define PT_MIPS_REGINFO 0x70000000
-#define PT_MIPS_OPTIONS 0x70000001
+
+#define PT_MIPS_REGINFO 0x70000000
+#define PT_MIPS_RTPROC 0x70000001
+#define PT_MIPS_OPTIONS 0x70000002
+#define PT_MIPS_ABIFLAGS 0x70000003
/* Flags in the e_flags field of the header */
/* MIPS architecture level. */
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v2 2/7] elf: Add MIPS_ABI_FP_XXX constants
2018-10-05 15:19 [Qemu-devel] [PATCH v2 0/7] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 1/7] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
@ 2018-10-05 15:19 ` Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 3/7] elf: Add Mips_elf_abiflags_v0 structure Aleksandar Markovic
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-05 15:19 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Add MIPS_ABI_FP_XXX constants to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
include/elf.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index decf210..eb5958d 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -87,6 +87,14 @@ typedef int64_t Elf64_Sxword;
#define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */
#define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */
+#define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */
+#define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float */
+#define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float */
+#define MIPS_ABI_FP_SOFT 0x3 /* -msoft-float */
+#define MIPS_ABI_FP_OLD_64 0x4 /* -mips32r2 -mfp64 */
+#define MIPS_ABI_FP_XX 0x5 /* -mfpxx */
+#define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */
+#define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */
/* These constants define the different elf file types */
#define ET_NONE 0
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v2 3/7] elf: Add Mips_elf_abiflags_v0 structure
2018-10-05 15:19 [Qemu-devel] [PATCH v2 0/7] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 1/7] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 2/7] elf: Add MIPS_ABI_FP_XXX constants Aleksandar Markovic
@ 2018-10-05 15:19 ` Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 4/7] target/mips: Add bit definitions for DSP R3 ASE Aleksandar Markovic
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-05 15:19 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Add Mips_elf_abiflags_v0 structure to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
include/elf.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index eb5958d..75c60cc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -96,6 +96,21 @@ typedef int64_t Elf64_Sxword;
#define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */
#define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */
+typedef struct mips_elf_abiflags_v0 {
+ uint16_t version; /* Version of flags structure */
+ uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */
+ uint8_t isa_rev; /* The revision of ISA: 0 for MIPS V and below,*/
+ /* 1-n otherwise */
+ uint8_t gpr_size; /* The size of general purpose registers */
+ uint8_t cpr1_size; /* The size of co-processor 1 registers */
+ uint8_t cpr2_size; /* The size of co-processor 2 registers */
+ uint8_t fp_abi; /* The floating-point ABI */
+ uint32_t isa_ext; /* Mask of processor-specific extensions */
+ uint32_t ases; /* Mask of ASEs used */
+ uint32_t flags1; /* Mask of general flags */
+ uint32_t flags2;
+} Mips_elf_abiflags_v0;
+
/* These constants define the different elf file types */
#define ET_NONE 0
#define ET_REL 1
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v2 4/7] target/mips: Add bit definitions for DSP R3 ASE
2018-10-05 15:19 [Qemu-devel] [PATCH v2 0/7] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (2 preceding siblings ...)
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 3/7] elf: Add Mips_elf_abiflags_v0 structure Aleksandar Markovic
@ 2018-10-05 15:19 ` Aleksandar Markovic
2018-10-08 14:03 ` Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 5/7] target/mips: Add availability control " Aleksandar Markovic
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-05 15:19 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Add DSP R3 ASE related bit definition for insn_flags and hflags.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/mips-defs.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d1..4160699 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -598,6 +598,7 @@ struct CPUMIPSState {
/* MIPS DSP resources access. */
#define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
+#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/
/* Extra flag about HWREna register. */
#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index c8e9979..b27b7ae 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -47,6 +47,7 @@
#define ASE_MDMX 0x00040000
#define ASE_DSP 0x00080000
#define ASE_DSPR2 0x00100000
+#define ASE_DSPR3 0x02000000
#define ASE_MT 0x00200000
#define ASE_SMARTMIPS 0x00400000
#define ASE_MICROMIPS 0x00800000
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/7] target/mips: Add bit definitions for DSP R3 ASE
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 4/7] target/mips: Add bit definitions for DSP R3 ASE Aleksandar Markovic
@ 2018-10-08 14:03 ` Aleksandar Markovic
0 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-08 14:03 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Stefan Markovic <smarkovic@wavecomp.com>
>
> Add DSP R3 ASE related bit definition for insn_flags and hflags.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This should be integrated with other pending insn_flags cleanups.
hflags need cleaning too, but this is not planned this year. Any such
cleanup should be beyond the scope of this patch. So:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v2 5/7] target/mips: Add availability control for DSP R3 ASE
2018-10-05 15:19 [Qemu-devel] [PATCH v2 0/7] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (3 preceding siblings ...)
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 4/7] target/mips: Add bit definitions for DSP R3 ASE Aleksandar Markovic
@ 2018-10-05 15:19 ` Aleksandar Markovic
2018-10-08 14:05 ` Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 7/7] target/mips: Implement emulation of " Aleksandar Markovic
6 siblings, 1 reply; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-05 15:19 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/internal.h | 11 ++++++++---
target/mips/translate.c | 13 ++++++++++++-
target/mips/translate_init.inc.c | 3 ++-
3 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e41051f..3c5867e 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -307,8 +307,8 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
- MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
- MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
+ MIPS_HFLAG_DSPR3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
+ MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
if (env->CP0_Status & (1 << CP0St_ERL)) {
env->hflags |= MIPS_HFLAG_ERL;
}
@@ -355,7 +355,12 @@ static inline void compute_hflags(CPUMIPSState *env)
(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
env->hflags |= MIPS_HFLAG_SBRI;
}
- if (env->insn_flags & ASE_DSPR2) {
+ if (env->insn_flags & ASE_DSPR3) {
+ if (env->CP0_Status & (1 << CP0St_MX)) {
+ env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
+ MIPS_HFLAG_DSPR3;
+ }
+ } else if (env->insn_flags & ASE_DSPR2) {
/* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
so enable to access DSPR2 resources. */
if (env->CP0_Status & (1 << CP0St_MX)) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb..d64a1da 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1868,6 +1868,17 @@ static inline void check_dspr2(DisasContext *ctx)
}
}
+static inline void check_dspr3(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) {
+ if (ctx->insn_flags & ASE_DSP) {
+ generate_exception_end(ctx, EXCP_DSPDIS);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ }
+}
+
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
static inline void check_insn(DisasContext *ctx, int flags)
@@ -20098,7 +20109,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
break;
case NM_BPOSGE32C:
- check_dspr2(ctx);
+ check_dspr3(ctx);
{
int32_t imm = extract32(ctx->opcode, 1, 13) |
extract32(ctx->opcode, 0, 1) << 13;
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index b3320b9..d7cd4ee 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -485,7 +485,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,
+ .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
+ ASE_MT,
.mmu_type = MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/7] target/mips: Add availability control for DSP R3 ASE
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 5/7] target/mips: Add availability control " Aleksandar Markovic
@ 2018-10-08 14:05 ` Aleksandar Markovic
0 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-08 14:05 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Stefan Markovic <smarkovic@wavecomp.com>
>
> Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
I think check_dspr3() should be check_dsp_r3(), but this will be then
inconsistent with check_dspr3(). Consider a separate patch for refactoring
dsp r2/r3-related constant and function names. But that is beyond the scope
of this patch, so:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions
2018-10-05 15:19 [Qemu-devel] [PATCH v2 0/7] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (4 preceding siblings ...)
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 5/7] target/mips: Add availability control " Aleksandar Markovic
@ 2018-10-05 15:19 ` Aleksandar Markovic
2018-10-05 17:16 ` Philippe Mathieu-Daudé
2018-10-08 14:07 ` Aleksandar Markovic
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 7/7] target/mips: Implement emulation of " Aleksandar Markovic
6 siblings, 2 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-05 15:19 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d64a1da..b0b2f40 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16499,6 +16499,22 @@ enum {
NM_P_SC = 0x0b,
};
+/* P.LS.E0 instruction pool */
+enum {
+ NM_LBE = 0x00,
+ NM_SBE = 0x01,
+ NM_LBUE = 0x02,
+ NM_P_PREFE = 0x03,
+ NM_LHE = 0x04,
+ NM_SHE = 0x05,
+ NM_LHUE = 0x06,
+ NM_CACHEE = 0x07,
+ NM_LWE = 0x08,
+ NM_SWE = 0x09,
+ NM_P_LLE = 0x0a,
+ NM_P_SCE = 0x0b,
+};
+
/* P.LS.WM instruction pool */
enum {
NM_LWM = 0x00,
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
@ 2018-10-05 17:16 ` Philippe Mathieu-Daudé
2018-10-08 14:07 ` Aleksandar Markovic
1 sibling, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-05 17:16 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: smarkovic, riku.voipio, richard.henderson, laurent, amarkovic,
pjovanovic, aurelien
On 05/10/2018 17:19, Aleksandar Markovic wrote:
> From: Dimitrije Nikolic <dnikolic@wavecomp.com>
>
> Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
> LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
B.44 of "nanoMIPS32 Instruction Set Technical Reference Manual"
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/mips/translate.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index d64a1da..b0b2f40 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -16499,6 +16499,22 @@ enum {
> NM_P_SC = 0x0b,
> };
>
> +/* P.LS.E0 instruction pool */
> +enum {
> + NM_LBE = 0x00,
> + NM_SBE = 0x01,
> + NM_LBUE = 0x02,
> + NM_P_PREFE = 0x03,
> + NM_LHE = 0x04,
> + NM_SHE = 0x05,
> + NM_LHUE = 0x06,
> + NM_CACHEE = 0x07,
> + NM_LWE = 0x08,
> + NM_SWE = 0x09,
> + NM_P_LLE = 0x0a,
> + NM_P_SCE = 0x0b,
> +};
> +
> /* P.LS.WM instruction pool */
> enum {
> NM_LWM = 0x00,
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
2018-10-05 17:16 ` Philippe Mathieu-Daudé
@ 2018-10-08 14:07 ` Aleksandar Markovic
1 sibling, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-08 14:07 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Dimitrije Nikolic <dnikolic@wavecomp.com>
>
> Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This patch is incomplete. The pool P.LS.E0 has three subpools, and, for each of them,
corresponding opcodes should be created.
Thanks,
Aleksandar
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v2 7/7] target/mips: Implement emulation of nanoMIPS EVA instructions
2018-10-05 15:19 [Qemu-devel] [PATCH v2 0/7] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (5 preceding siblings ...)
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
@ 2018-10-05 15:19 ` Aleksandar Markovic
2018-10-05 17:27 ` Philippe Mathieu-Daudé
6 siblings, 1 reply; 13+ messages in thread
From: Aleksandar Markovic @ 2018-10-05 15:19 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b0b2f40..3adf31f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1979,6 +1979,17 @@ static inline void check_nms(DisasContext *ctx)
}
}
+/*
+ * This code generates a "reserved instruction" exception if the
+ * Config5 EVA bit is NOT set.
+ */
+static inline void check_eva(DisasContext *ctx)
+{
+ if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+}
+
/* Define small wrappers for gen_load_fpr* so that we have a uniform
calling interface for 32 and 64-bit FPRs. No sense in changing
@@ -20011,6 +20022,74 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case NM_P_LS_E0:
+ check_eva(ctx);
+ switch (extract32(ctx->opcode, 11, 4)) {
+ case NM_LBE:
+ gen_ld(ctx, OPC_LBE, rt, rs, s);
+ break;
+ case NM_SBE:
+ gen_st(ctx, OPC_SBE, rt, rs, s);
+ break;
+ case NM_LBUE:
+ gen_ld(ctx, OPC_LBUE, rt, rs, s);
+ break;
+ case NM_P_PREFE:
+ if (rt == 31) {
+ /* SYNCIE */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->base.is_jmp = DISAS_STOP;
+ } else {
+ /* PREF */
+ /* Treat as NOP. */
+ }
+ break;
+ case NM_LHE:
+ gen_ld(ctx, OPC_LHE, rt, rs, s);
+ break;
+ case NM_SHE:
+ gen_st(ctx, OPC_SHE, rt, rs, s);
+ break;
+ case NM_LHUE:
+ gen_ld(ctx, OPC_LHUE, rt, rs, s);
+ break;
+ case NM_CACHEE:
+ /* Treat as no-op */
+ if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
+ gen_cache_operation(ctx, rt, rs, s);
+ }
+ break;
+ case NM_LWE:
+ gen_ld(ctx, OPC_LWE, rt, rs, s);
+ break;
+ case NM_SWE:
+ gen_st(ctx, OPC_SWE, rt, rs, s);
+ break;
+ case NM_P_LLE:
+ switch (extract32(ctx->opcode, 2, 2)) {
+ case NM_LL:
+ gen_ld(ctx, OPC_LLE, rt, rs, s);
+ break;
+ case NM_LLWP:
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P_SCE:
+ switch (extract32(ctx->opcode, 2, 2)) {
+ case NM_SC:
+ gen_st_cond(ctx, OPC_SCE, rt, rs, s);
+ break;
+ case NM_SCWP:
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ }
+ break;
case NM_P_LS_WM:
case NM_P_LS_UAWM:
check_nms(ctx);
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v2 7/7] target/mips: Implement emulation of nanoMIPS EVA instructions
2018-10-05 15:19 ` [Qemu-devel] [PATCH v2 7/7] target/mips: Implement emulation of " Aleksandar Markovic
@ 2018-10-05 17:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-05 17:27 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: smarkovic, riku.voipio, richard.henderson, laurent, amarkovic,
pjovanovic, aurelien
Hi Aleksandar,
On 05/10/2018 17:19, Aleksandar Markovic wrote:
> From: Dimitrije Nikolic <dnikolic@wavecomp.com>
>
> Implement emulation of nanoMIPS EVA instructions. They are all
> part of P.LS.E0 instruction pool, or one of its subpools.
>
Shouldn't this be signed off by Dimitrije Nikolic too?
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index b0b2f40..3adf31f 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1979,6 +1979,17 @@ static inline void check_nms(DisasContext *ctx)
> }
> }
>
> +/*
> + * This code generates a "reserved instruction" exception if the
> + * Config5 EVA bit is NOT set.
> + */
> +static inline void check_eva(DisasContext *ctx)
> +{
> + if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) {
> + generate_exception_end(ctx, EXCP_RI);
> + }
> +}
> +
>
> /* Define small wrappers for gen_load_fpr* so that we have a uniform
> calling interface for 32 and 64-bit FPRs. No sense in changing
> @@ -20011,6 +20022,74 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
> break;
> }
> break;
> + case NM_P_LS_E0:
> + check_eva(ctx);
> + switch (extract32(ctx->opcode, 11, 4)) {
> + case NM_LBE:
> + gen_ld(ctx, OPC_LBE, rt, rs, s);
> + break;
> + case NM_SBE:
> + gen_st(ctx, OPC_SBE, rt, rs, s);
> + break;
> + case NM_LBUE:
> + gen_ld(ctx, OPC_LBUE, rt, rs, s);
> + break;
> + case NM_P_PREFE:
> + if (rt == 31) {
> + /* SYNCIE */
> + /* Break the TB to be able to sync copied instructions
> + immediately */
> + ctx->base.is_jmp = DISAS_STOP;
> + } else {
> + /* PREF */
> + /* Treat as NOP. */
> + }
> + break;
> + case NM_LHE:
> + gen_ld(ctx, OPC_LHE, rt, rs, s);
> + break;
> + case NM_SHE:
> + gen_st(ctx, OPC_SHE, rt, rs, s);
> + break;
> + case NM_LHUE:
> + gen_ld(ctx, OPC_LHUE, rt, rs, s);
> + break;
> + case NM_CACHEE:
> + /* Treat as no-op */
What about NMS core without caches? Shouldn't we use:
check_nms(ctx);
> + if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
> + gen_cache_operation(ctx, rt, rs, s);
> + }
> + break;
> + case NM_LWE:
> + gen_ld(ctx, OPC_LWE, rt, rs, s);
> + break;
> + case NM_SWE:
> + gen_st(ctx, OPC_SWE, rt, rs, s);
> + break;
> + case NM_P_LLE:
> + switch (extract32(ctx->opcode, 2, 2)) {
> + case NM_LL:
> + gen_ld(ctx, OPC_LLE, rt, rs, s);
> + break;
> + case NM_LLWP:
> + default:
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + }
> + break;
> + case NM_P_SCE:
> + switch (extract32(ctx->opcode, 2, 2)) {
> + case NM_SC:
> + gen_st_cond(ctx, OPC_SCE, rt, rs, s);
> + break;
> + case NM_SCWP:
> + default:
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + }
> + break;
> + }
> + break;
> case NM_P_LS_WM:
> case NM_P_LS_UAWM:
> check_nms(ctx);
>
The rest of this patch is OK.
Regards,
Phil.
^ permalink raw reply [flat|nested] 13+ messages in thread