[PATCH 0/6] Add i.MX8MM support

[PATCH 0/6] Add i.MX8MM support

[Bryan O'Donoghue]

This set adds support for the i.MX8MM.

When adding support for this processor there are two interesting gotchas to
watch for.

#1 We current do not preserve the WAIT field for i.MX6 and since we are
   reusing the i.MX6 set_timing() values, this would also affect i.MX8.
   On the face of it, it appears to be an inocuous error with no real side
   effects.

#2 Secondly the i.MX8MM will calculate a zero value for the RELAX bit-field
   when programming up OTP fuses.
   This is fine for programming the fuses but, it introduces a strange
   failure state with reloading the shadow registers subsequent to blowing
   an OTP fuse.
   The second important patch here then is ensuring the RELAX field is
   non-zero to avoid the failure state.

Bryan O'Donoghue (6):
  nvmem: imx-ocotp: Allow selection of OCOTP for imx8 processors
  nvmem: imx-ocotp: Fix i.MX OC-OTP naming prompt
  nvmem: imx-ocotp: Add i.MX8MM support
  nvmem: imx-ocotp: Ensure WAIT bits are preserved when setting timing
  nvmem: imx-ocotp: Ensure the RELAX field is non-zero
  dt-bindings: imx-ocotp: Add i.MX8MM support

 .../devicetree/bindings/nvmem/imx-ocotp.txt     |  1 +
 drivers/nvmem/Kconfig                           |  4 ++--
 drivers/nvmem/imx-ocotp.c                       | 17 ++++++++++++++++-
 3 files changed, 19 insertions(+), 3 deletions(-)

-- 
2.20.1


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[PATCH 1/6] nvmem: imx-ocotp: Allow selection of OCOTP for imx8 processors

[Bryan O'Donoghue]

This patch allows switching on of the i.MX OCTOP driver when building for
i.MX8 processors.

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
 drivers/nvmem/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 530d570724c9..4d1c8778c064 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -26,7 +26,7 @@ config NVMEM_IMX_IIM
 
 config NVMEM_IMX_OCOTP
 	tristate "i.MX6 On-Chip OTP Controller support"
-	depends on SOC_IMX6 || SOC_IMX7D || COMPILE_TEST
+	depends on SOC_IMX6 || SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
 	depends on HAS_IOMEM
 	help
 	  This is a driver for the On-Chip OTP Controller (OCOTP) available on
-- 
2.20.1


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[PATCH 2/6] nvmem: imx-ocotp: Fix i.MX OC-OTP naming prompt

[Bryan O'Donoghue]

The imx-ocotp driver supports i.MX6, i.MX7 and i.MX8 but, the Kconfig
prompt only specifies i.MX6, which is pretty confusing.

Add the two absent processor types to the prompt to make driver selection
easier to understand.

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
 drivers/nvmem/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 4d1c8778c064..ebd1ba649aad 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -25,7 +25,7 @@ config NVMEM_IMX_IIM
 	  will be called nvmem-imx-iim.
 
 config NVMEM_IMX_OCOTP
-	tristate "i.MX6 On-Chip OTP Controller support"
+	tristate "i.MX6/i.MX7/i.MX8 On-Chip OTP Controller support"
 	depends on SOC_IMX6 || SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
 	depends on HAS_IOMEM
 	help
-- 
2.20.1


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[PATCH 3/6] nvmem: imx-ocotp: Add i.MX8MM support

[Bryan O'Donoghue]

This patch adds support to burn the fuses on the i.MX8MM.
https://www.nxp.com/webapp/Download?colCode=IMX8MMRM

The i.MX8MM is similar to i.MX6 processors in terms of addressing and clock
setup.

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
 drivers/nvmem/imx-ocotp.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 08a9b1ef8ae4..b6e71c34a393 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -45,7 +45,12 @@
 #define IMX_OCOTP_ADDR_DATA2		0x0040
 #define IMX_OCOTP_ADDR_DATA3		0x0050
 
+#if defined(CONFIG_ARCH_MXC)
+#define IMX_OCOTP_BM_CTRL_ADDR		0x000000FF
+#else
 #define IMX_OCOTP_BM_CTRL_ADDR		0x0000007F
+#endif	/* ARCH_MXC */
+
 #define IMX_OCOTP_BM_CTRL_BUSY		0x00000100
 #define IMX_OCOTP_BM_CTRL_ERROR		0x00000200
 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS	0x00000400
@@ -444,6 +449,12 @@ static const struct ocotp_params imx7ulp_params = {
 	.bank_address_words = 0,
 };
 
+static const struct ocotp_params imx8mm_params = {
+	.nregs = 64,
+	.bank_address_words = 0,
+	.set_timing = imx_ocotp_set_imx6_timing,
+};
+
 static const struct of_device_id imx_ocotp_dt_ids[] = {
 	{ .compatible = "fsl,imx6q-ocotp",  .data = &imx6q_params },
 	{ .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
@@ -453,6 +464,7 @@ static const struct of_device_id imx_ocotp_dt_ids[] = {
 	{ .compatible = "fsl,imx7d-ocotp",  .data = &imx7d_params },
 	{ .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
 	{ .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
+	{ .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
-- 
2.20.1


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[PATCH 4/6] nvmem: imx-ocotp: Ensure WAIT bits are preserved when setting timing

[Bryan O'Donoghue]

The i.MX6 and i.MX8 both have a bit-field spanning bits 27:22 called the
WAIT field.

The WAIT field according to the documentation for both parts "specifies
time interval between auto read and write access in one time program. It is
given in number of ipg_clk periods."

This patch ensures that the relevant field is read and written back to the
timing register.

Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support")

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
 drivers/nvmem/imx-ocotp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index b6e71c34a393..840d939f792b 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -194,7 +194,8 @@ static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
 	strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
 	strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
 
-	timing = strobe_prog & 0x00000FFF;
+	timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
+	timing |= strobe_prog & 0x00000FFF;
 	timing |= (relax       << 12) & 0x0000F000;
 	timing |= (strobe_read << 16) & 0x003F0000;
 
-- 
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[PATCH 5/6] nvmem: imx-ocotp: Ensure the RELAX field is non-zero

[Bryan O'Donoghue]

The RELAX field of the OCOTP block quote "specifies the time to add to all
default timing parameters other than the Tpgm and Trd. It is given in
number of ipg_clk periods".

On the i.MX8MM the calculation for the RELAX value is turning out to be
zero which is not a problem for programming OTP values but, does
subsequently mess up reloading the OTP shadow registers.

This patch ensures the RELAX field is at least one ipg_clk cycle, which
seems like a pretty obvious floor to place on a value such as this.

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
 drivers/nvmem/imx-ocotp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 840d939f792b..458586295518 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -191,6 +191,8 @@ static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
 	clk_rate = clk_get_rate(priv->clk);
 
 	relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
+	if (!relax)
+		relax = 1;
 	strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
 	strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
 
-- 
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[PATCH 6/6] dt-bindings: imx-ocotp: Add i.MX8MM support

[Bryan O'Donoghue]

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
---
 Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
index 7a999a135e56..f3aa5935fe6d 100644
--- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
+++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
@@ -13,6 +13,7 @@ Required properties:
 	"fsl,imx7d-ocotp" (i.MX7D/S),
 	"fsl,imx6sll-ocotp" (i.MX6SLL),
 	"fsl,imx7ulp-ocotp" (i.MX7ULP),
+	"fsl,imx8mm-ocotp" (i.MX8MM),
 	followed by "syscon".
 - #address-cells : Should be 1
 - #size-cells : Should be 1
-- 
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Re: [PATCH 3/6] nvmem: imx-ocotp: Add i.MX8MM support

[Leonard Crestez]

On 19.04.2019 13:03, Bryan O'Donoghue wrote:
> This patch adds support to burn the fuses on the i.MX8MM.
>   
> +#if defined(CONFIG_ARCH_MXC)
> +#define IMX_OCOTP_BM_CTRL_ADDR		0x000000FF
> +#else
>   #define IMX_OCOTP_BM_CTRL_ADDR		0x0000007F
> +#endif	/* ARCH_MXC */

You're on an older tree; in upstream ARCH_MXC is defined on all imx6/7/8 
so can't be used to distinguish. Maybe move to ocotp_params instead?
The number of valid ADDR bits in OCOTP_CTRL also seems to vary between 
some imx6 variants.

As far as I can tell high ADDR bits are RSVD0 based on total number of 
fuses in the chip. Reading that zero from hardware and writing it back 
should be harmless.

Maybe enlarge to 0xFF, maximum of all current parts?

> +static const struct ocotp_params imx8mm_params = {
> +	.nregs = 64,

Why nregs=64? fusemap in RM documents fuses from 0x400 and 0x13f0 so 256 
in total. But most of those are reserved anyway.

--
Regards,
Leonard

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Re: [PATCH 3/6] nvmem: imx-ocotp: Add i.MX8MM support

[Bryan O'Donoghue]

On 19/04/2019 11:32, Leonard Crestez wrote:
> On 19.04.2019 13:03, Bryan O'Donoghue wrote:
>> This patch adds support to burn the fuses on the i.MX8MM.
>>    
>> +#if defined(CONFIG_ARCH_MXC)
>> +#define IMX_OCOTP_BM_CTRL_ADDR		0x000000FF
>> +#else
>>    #define IMX_OCOTP_BM_CTRL_ADDR		0x0000007F
>> +#endif	/* ARCH_MXC */
> 
> You're on an older tree; in upstream ARCH_MXC is defined on all imx6/7/8
> so can't be used to distinguish. Maybe move to ocotp_params instead?
> The number of valid ADDR bits in OCOTP_CTRL also seems to vary between
> some imx6 variants.
> 
> As far as I can tell high ADDR bits are RSVD0 based on total number of
> fuses in the chip. Reading that zero from hardware and writing it back
> should be harmless.
> 
> Maybe enlarge to 0xFF, maximum of all current parts?

putative yes..

> 
>> +static const struct ocotp_params imx8mm_params = {
>> +	.nregs = 64,
> 
> Why nregs=64? fusemap in RM documents fuses from 0x400 and 0x13f0 so 256
> in total. But most of those are reserved anyway.

Hrmm.

I did print out all of the address offsets all the way up to what is 
documented @ 3035_07B0h but, now that you ask the question I will check 
that again.

I'll rebase this against linux-next/master.

---
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Re: [PATCH 3/6] nvmem: imx-ocotp: Add i.MX8MM support

[Bryan O'Donoghue]

On 19/04/2019 12:48, Bryan O'Donoghue wrote:
> On 19/04/2019 11:32, Leonard Crestez wrote:
>> On 19.04.2019 13:03, Bryan O'Donoghue wrote:
>>> This patch adds support to burn the fuses on the i.MX8MM.
>>> +static const struct ocotp_params imx8mm_params = {
>>> +    .nregs = 64,
>>
>> Why nregs=64? fusemap in RM documents fuses from 0x400 and 0x13f0 so 256
>> in total. But most of those are reserved anyway.

That should be 60, not 64 the address range for i.M8XMM is from 0x400 - 
0x7b0 unlike i.MX7S/D 0x400 - 0x7F0.

i.MX 8M Mini Applications Processor Reference Manual, Rev. 1, 03/2019
page 834

True enough the 8MQ has 256 regs but, 8mm is much smaller.

---
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